Pixel circuit, control method thereof and display device

Abstract

The invention discloses a pixel circuit, a control method thereof and a display device. The display device includes: a display panel on which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are disposed, the display panel being configured to operate in a display mode for displaying an image and a sensing mode for sensing degradation of the pixels; a gate driver configured to supply a scan signal and a light emission control signal to the plurality of gate lines; a data driver configured to supply data signals to the plurality of data lines; a power supply configured to apply an initialization voltage to the pixels in a sensing mode; and a sensing unit configured to sense degradation of the pixels in a sensing mode.

Description

Technical Field

[0001] The present disclosure relates to a display device, and in particular, for example but not limited to, a display device configured to enhance image quality by compensating for degradation of its light-emitting elements. Background Art

[0002] An image display device that renders various information on a screen is a core technology in the information and communication era, and is evolving towards thinner, lighter, greater portability, and higher performance. Therefore, there is a need for a display device that can be manufactured with a light and thin structure.

[0003] Such a display device is self-luminous, and thus is advantageous not only in terms of power consumption according to low-voltage driving, but also has a fast response time, high luminous efficiency, wide viewing angle, and high contrast. In this regard, such a display device is highlighted as a next-generation display device, and research is being conducted on it. This display device renders an image through a plurality of sub-pixels arranged in a matrix. Each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit including a plurality of transistors configured to independently drive the light-emitting element.

[0004] As a specific example of such a display device, there are liquid crystal display (LCD) devices, quantum dot display (QD) devices, field emission display (FED) devices, organic light-emitting display (OLED) devices, and the like.

[0005] Among these display devices, the OLED device, which is highlighted as a device that achieves compactness and high-definition color display without the need for a separate light source, has advantages such as fast response time, high contrast, high luminous efficiency, high brightness, and wide viewing angle by using an organic light-emitting diode (OLED) configured to emit light in a self-luminous manner.

[0006] Among the above display devices, the OLED device including an OLED has various advantages because an image is displayed based on light emitted from the light-emitting element in the pixel.

[0007] The descriptions provided in the description of the background art section should not be assumed to be prior art merely because they are mentioned in the description of the background art section or are associated with the description of the background art section. The description of the background art section may include information describing one or more aspects of the subject technology, and the description in this section does not limit the present disclosure. Summary of the Invention

[0008] The inventors have recognized that in OLED devices in the related art, during driving, image quality degradation phenomena such as color coordinate changes often occur. This may lead to a reduction in the basic satisfaction of high image quality in a display device including OLED elements. Therefore, the present disclosure aims to provide a pixel circuit and a display device including the pixel circuit that substantially eliminate one or more problems caused by the limitations and disadvantages of the related art.

[0009] The present disclosure relates to a display device including a pixel circuit including a transistor configured to receive a sensing signal and configured to compensate for degradation of a light-emitting element by sensing degradation, thereby enhancing image quality.

[0010] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as implemented and broadly described herein, a display device includes: a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels disposed thereon, the display panel being configured to operate in a display mode for displaying an image and a sensing mode for sensing degradation of the pixels; a gate driver configured to supply a scan signal and a light-emitting control signal to the plurality of gate lines; a data driver configured to supply a data signal to the plurality of data lines; a power supply configured to apply an initialization voltage to the pixels in the sensing mode; and a sensing unit configured to sense degradation of the pixels in the sensing mode.

[0011] In another aspect of the present disclosure, a pixel circuit includes: a light-emitting element; a capacitor connected between a first node and a second node; a first transistor including a first electrode connected to a reference voltage line and a second electrode connected to the first node, the first transistor being configured to supply a reference voltage to the first node in response to a light-emitting control signal of the (n + 1)-th pixel row; a second transistor including a first electrode connected to the reference voltage line and a second electrode connected to the second node, the second transistor being configured to supply a reference voltage to the second node in response to a scan signal of the (n - 1)-th pixel row; a driving transistor including a gate electrode connected to the second node, a first electrode configured to receive a high-level driving voltage, and a second electrode connected to a third node; a third transistor including a first electrode connected to an initialization voltage line and a second electrode connected to a fourth node, the third transistor being configured to supply an initialization voltage to the fourth node in response to a scan signal of the n-th pixel row; and a fourth transistor including a first electrode connected to the initialization voltage line and a second electrode connected to the fourth node, the fourth transistor being configured to conduct in response to a sensing signal.

[0012] In another aspect of the present disclosure, a control method of a pixel circuit according to an exemplary embodiment of the present disclosure may include: supplying a reference voltage to a first node via a first transistor in response to a light emission control signal of the (n + 1)-th pixel row, the first transistor including a first electrode connected to a reference voltage line and a second electrode connected to the first node; supplying a reference voltage to a second node via a second transistor in response to a scan signal of the (n - 1)-th pixel row, the second transistor including a first electrode connected to the reference voltage line and a second electrode connected to the second node; receiving a high-level driving voltage via a driving transistor, the driving transistor including a first electrode receiving the high-level driving voltage, a second electrode connected to a third node, and a gate electrode connected to the second node; supplying an initialization voltage to a fourth node via a third transistor in response to a scan signal of the n-th pixel row, the third transistor including a first electrode connected to an initialization voltage line and a second electrode connected to the fourth node; and turning on a fourth transistor in response to a sensing signal, the fourth transistor including a first electrode connected to the initialization voltage line and a second electrode connected to the fourth node, wherein a first capacitor is connected between the first node and the second node.

[0013] The object of the present disclosure is not limited to the above object, and other objects of the present disclosure that have not been described will be more clearly understood by those skilled in the art from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0015] In the drawings:

[0016] Figure 1 is a block diagram of a display device according to an exemplary embodiment of the present disclosure;

[0017] Figure 2 is a cross-sectional view showing a stacked structure of a display device according to an exemplary embodiment of the present disclosure;

[0018] Figure 3 is a block diagram showing a configuration of a gate driver in a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 4 is a circuit diagram showing a pixel circuit in a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 5 is a diagram depicting the Figure 4 operation waveform of the pixel circuit shown in the display mode of a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 6 is a diagram depicting operation waveforms during an active period of a display mode operation and a blanking period of a sensing mode operation in one frame in a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 7A and Figure 7B is a diagram showing the configuration of a controller including a sensing unit in a display device according to an exemplary embodiment of the present disclosure; and

[0023] Figure 8 is a diagram depicting the lifetime brightness in a display device according to an exemplary embodiment of the present disclosure.

[0024] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Embodiments

[0025] Now, embodiments of the present disclosure will be described in detail, and examples thereof may be shown in the drawings. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to that described herein and may be changed as known in the art, except for steps and / or operations that must occur in a specific order. The names of the respective elements used in the following explanations may be selected only for the convenience of writing the specification and may thus be different from the names used in actual products.

[0026] Advantages and features of the present disclosure and methods for achieving them will become clear from the embodiments described in detail below with reference to the drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Here, the embodiments of the present disclosure are provided so that the present disclosure may be thorough and complete, to help those skilled in the art fully understand the scope of the present disclosure, and the present disclosure is limited only by the scope of the appended claims.

[0027] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for illustrating the embodiments of the present disclosure are for illustration only and are not limited to the content shown in the drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. In the following description, detailed descriptions of technologies or configurations related to the present disclosure may be omitted so as not to unnecessarily obscure the subject matter of the present disclosure.

[0028] When terms such as "comprising", "having", "including", "containing", "constituting", "made of", "formed by", "consisting of" are used throughout the specification, additional components may be present, unless "only" is used. Components described in the singular form cover components in the plural form, unless otherwise specifically stated.

[0029] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc. of the elements shown in the drawings used to describe the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements.

[0030] The dimensions, including the size and thickness, of the respective components shown in the drawings are shown for ease of description, and the present disclosure is not limited to the size and thickness of the components shown. However, it should be noted that the relative dimensions, including the relative size, position, and thickness, of the components shown in the respective drawings submitted here are part of the present disclosure.

[0031] It should be noted that the components included in the exemplary embodiments of the present disclosure include an error range, although no additional specific description thereof is provided.

[0032] When describing the various embodiments of the present disclosure, when using terms for positional relationships such as "on", "above", "over", "under", "below", "beside", "beneath", "near", "close to", "adjacent to", "on the side of", "close", at least one intermediate element may be present between two elements, unless "immediately" or "directly" is used.

[0033] Spatially relative terms, such as "under", "below", "beneath", "lower", "above", "upper", etc., may be used herein to facilitate the description of the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of the element during use or operation. For example, if the element in the figure is inverted, the element described as "under" or "below" other elements or features will be oriented "above" other elements or features. Thus, the exemplary term "below" may include both below and above orientations. Similarly, the exemplary terms "above" or "over" may include both "above" and "below" orientations.

[0034] When an element or layer is disposed "on" another element or layer, yet another layer or yet another element may be directly interposed on the other element or between the two elements or layers.

[0035] When describing temporal relationships, for example, when using terms for temporal relationships of events such as "after", "subsequently", "next", and "before", there may also be cases where the events are not continuous, unless "immediately" or "directly" is used.

[0036] In addition, although terms including serial numbers such as first or second may be used to describe various constituent elements, the constituent elements are not limited to these terms, and these terms are only for the purpose of differentiating one constituent element from other constituent elements. Thus, within the scope of the present disclosure, the first constituent element may represent the second constituent element.

[0037] The term "at least one" should be understood to include all possible combinations that can be proposed from one or more related items. For example, the meaning of "at least one of the first item, the second item, or the third item" can be each of the first item, the second item, or the third item, and can also be all possible combinations that can be proposed from two or more of the first item, the second item, and the third item.

[0038] The term "device" as used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of the display device may include a light-emitting element, etc. Additionally, examples of the device may include a laptop computer, a television, a computer monitor, a vehicle device, a wearable device, and a vehicle equipment device, and complete product or final product sets of electronic devices (or equipment) or sets of devices (or equipment) respectively including a light-emitting element, etc., such as a mobile electronic device such as a smartphone or a tablet computer, but the embodiments of the present disclosure are not limited thereto.

[0039] The respective features of the various embodiments according to the present disclosure may be partially or completely joined or combined and are technically related or operate in various ways, and the embodiments may be implemented independently or in combination.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0041] In aspects of the present disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode may be used interchangeably. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. In addition, the source electrode in any aspect of the present disclosure may be the drain electrode in another aspect of the present disclosure, and the drain electrode in any aspect of the present disclosure may be the source electrode in another aspect of the present disclosure.

[0042] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the specification, when adding reference numerals to elements in each drawing, it should be noted that whenever possible, the same reference numerals that have been used to denote elements in other drawings are used for that element. In addition, for ease of description, the dimensional ratios of the constituent elements shown in the drawings may be different from the actual dimensional ratios. That is, the dimensional ratios of the constituent elements shown in the drawings should not be construed as being the same as the dimensional ratios shown in the drawings.

[0043] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 is a block diagram of a display device according to an exemplary embodiment of the present disclosure.

[0045] Refer to Figure 1 , a display device denoted by reference numeral "10" according to an exemplary embodiment of the present disclosure includes: a display panel 100 including a plurality of pixels P; a controller 200; a gate driver 300 configured to supply a gate signal to each of the plurality of pixels P; a data driver 400 configured to supply a data signal to each of the plurality of pixels P; a power supply 500 configured to supply power to each of the plurality of pixels P for driving each of the plurality of pixels P; a level shifter 600 configured to adjust the potential of the gate signal applied to the gate driver 300; and a sensing unit 700 configured to sense the deterioration of the plurality of pixels P.

[0046] Here, the controller 200, the gate driver 300, the data driver 400, and the sensing unit 700 may be collectively referred to as a "control unit".

[0047] The display panel 100 includes a display area (AA) in which pixels P are provided (see Figure 2 ) and a non-display area (NA) provided around the display area (AA) (see Figures 2 to 4 ). In the non-display area (NA), the gate driver 300 and the data driver 400 are provided.

[0048] A plurality of gate lines GL and a plurality of data lines DL cross each other at the display panel 100, and each of the plurality of pixels P is connected to a corresponding one of the gate line GL and the data line DL. Specifically, each pixel P receives a gate signal from the gate driver 300 through a corresponding gate line GL, receives a data signal from the data driver 400 through a corresponding data line DL, and receives a high-level driving voltage EVDD and a low-level driving voltage EVSS from the power supply 500 through the driving voltage line PL.

[0049] Each gate line GL supplies a scan signal SC and a light emission control signal EM, and each data line DL supplies a data voltage Vdata. According to various embodiments, each gate line GL may include a plurality of scan lines SCL for supplying the scan signal SC and a plurality of light emission control signal lines EML for supplying the light emission control signal EM. In addition, the plurality of pixels P further include a power line VL, and thus can receive a reference voltage Vref and an initialization voltage Vini.

[0050] In addition, as Figure 2 and Figure 4 shown, each pixel P includes a light emitting element EL and a pixel circuit configured to control the driving of the light emitting element EL. In this case, the light emitting element EL is composed of an anode 171, a cathode 173, and a light emitting layer 172 disposed between the anode 171 and the cathode 173.

[0051] The pixel circuit includes a plurality of switching elements, driving elements, and capacitors. In this case, each of the switching elements and the driving elements may be composed of a thin film transistor.

[0052] The active layer of the thin film transistor TFT may be formed of a semiconductor material, such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0053] The oxide semiconductor material may have an excellent effect of preventing leakage current and a relatively low manufacturing cost. The oxide semiconductor may be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. Specifically, the oxide semiconductor may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto.

[0054] Polycrystalline semiconductor materials have fast carrier mobilities such as electrons and holes, and thus have high mobilities, low power consumption, and excellent reliability. Polycrystalline semiconductors can be made of polysilicon (poly-Si), but are not limited thereto.

[0055] Amorphous semiconductor materials can be made of amorphous silicon (a-Si), but are not limited thereto.

[0056] In the pixel circuit, the driving element adjusts the light emission amount of the light emitting element EL by controlling the amount of current supplied to the light emitting element EL according to the data voltage Vdata.

[0057] In addition, multiple switching elements receive the corresponding scan signal SC supplied through multiple scan lines SCL and the light emission control signal EM supplied through the light emission control signal line EML, thereby operating the pixel circuit.

[0058] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device, where an image is displayed on the screen and the actual background is visible through the transparent display device. The display panel 100 can be implemented as a flexible display panel. The flexible display panel can be implemented as an organic light emitting display panel using a plastic substrate. For example, the substrate can include a flexible polymer film. For example, the flexible polymer film can be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cycloolefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS), and the present disclosure is not limited thereto.

[0059] Multiple sub-pixels SP are the smallest units that make up the display area, and n sub-pixels SP form one pixel. Each of the multiple sub-pixels SP can emit light with different wavelengths from each other. The multiple sub-pixels can include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors from each other. Each pixel P can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color rendering. Each pixel P can also include a white sub-pixel. The multiple sub-pixels SP can be variously modified in color and configuration as needed. However, the present disclosure is not limited thereto.

[0060] For example, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, where the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in a repeating manner. Alternatively, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, where the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a repeating manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be sequentially arranged along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be sequentially arranged along the row direction. However, in the embodiments of the present disclosure, the color type, the arrangement type, and the arrangement order of the sub-pixels are not limited and may be configured in various forms according to the light-emitting characteristics, the device lifetime, and the device specifications.

[0061] In addition, according to the light-emitting characteristics, the sub-pixels may have different light-emitting areas. For example, a sub-pixel that emits light of a color different from that of the blue sub-pixel may have a light-emitting area different from that of the blue sub-pixel. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel or the red sub-pixel, the blue sub-pixel, the white sub-pixel, and the green sub-pixel may each have a different light-emitting area.

[0062] Each pixel P may include a pixel circuit. For example, the pixel circuit of each of the plurality of sub-pixels may include a capacitor, at least one thin-film transistor, and a light-emitting element. For example, the at least one thin-film transistor may include a driving transistor, a first switching transistor, and a second switching transistor. In addition, the light-emitting element may include a first electrode (or an anode electrode, a pixel electrode), a light-emitting layer (or an organic light-emitting layer), and a second electrode (or a cathode electrode, a common electrode). However, the pixel circuit of each of the plurality of sub-pixels is not limited thereto, and each of the plurality of sub-pixels may further include a compensation circuit. In this case, each of the plurality of sub-pixels may have various structures such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0063] A touch sensor may be provided on the display panel 100. Touch input may be sensed using a separate touch sensor, or may be sensed through the pixel P. The touch sensor may be provided on the screen of the display panel 100 in an on-cell type or an additional type, or may be implemented as an in-cell type touch sensor built into the display panel 100.

[0064] The controller 200 processes the image data RGB input from the outside thereof to match the size and resolution of the display panel 100, and then supplies the processed image data RGB to the data driver 400.

[0065] The controller 200 generates a gate control signal GCS and a data control signal DCS by using timing signals CS input from the outside thereof, such as a dot clock signal CLK, a data enable signal DE, a horizontal sync signal Hsync, and a vertical sync signal Vsync. Here, the horizontal sync signal is a signal indicating the time for one horizontal line of a display screen, and the vertical sync signal is a signal indicating the time for displaying one frame of a screen. The data enable signal may correspond to a signal indicating a period for supplying a data voltage to a pixel. The controller 200 supplies the generated gate control signal GCS and data control signal DCS to a gate driver 300 and a data driver 400, respectively, thereby controlling the gate driver 300 and the data driver 400.

[0066] The controller 200 may be configured to be coupled to various processors such as a microprocessor, a mobile processor, an application processor, etc. according to a device installed therein.

[0067] The host system to which the controller 200 is applied may be one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system.

[0068] The controller 200 may multiply an input frame frequency by i times, thereby controlling an operation timing of a display panel driver at a frame frequency corresponding to “input frame frequency × i” Hz (i is a positive integer greater than 0). The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the Phase Alternating Line (PAL) system.

[0069] The controller 200 may generate signals so that each pixel P can be driven at various refresh rates. That is, the controller 200 may generate signals associated with driving each pixel P so that the pixel P can be driven in a variable refresh rate (VRR) mode or switched between a first refresh rate and a second refresh rate. For example, the controller 200 may drive each pixel P at various refresh rates by simply changing a rate of a clock signal, generating a sync signal for generating a horizontal blanking or a vertical blanking, or driving the gate driver 300 in a masked manner.

[0070] The controller 200 generates a gate control signal GCS for controlling an operation timing of the gate driver 300 and a data control signal DCS for controlling an operation timing of the data driver 400 based on the timing signal CS received from the host system. The controller 200 synchronizes the gate driver 300 and the data driver 400 with each other by controlling an operation timing of the display panel driver.

[0071] The data driver 400 receives image data DATA and a data control signal DCS from the controller 200. The data driver 400 converts the image data DATA into a gamma-compensated voltage in response to the data control signal DCS from the controller 200, thereby generating a data voltage Vdata, and then supplies the data voltage Vdata to the data lines DL of the display panel 100 in synchronization with the scan signal SC. The data driver 400 may be connected to the data lines of the display panel 100 through a chip on glass (COG) process or a tape automated bonding (TAB) process.

[0072] The gate driver 300 operates according to a gate control signal GCS input thereto from the level shifter 600, thereby generating a gate signal. In addition, the gate driver 300 sequentially supplies the gate signal to the gate lines GL. The gate driver 300 may be directly formed on the lower substrate of the display panel 100 in a gate in panel (GIP) manner.

[0073] The gate driver 300 may be formed in a non-display area NA outside a display area AA on which a display screen is displayed of the display panel 100. The non-display area NA may be an area adjacent to the display area AA. Further, the non-display area NA may be an area adjacent to and configured to surround the display area AA. However, the present disclosure is not limited thereto.

[0074] For example, the non-display area NA may include a first non-display area located outside the display area AA in a first direction, a second non-display area located outside the display area AA in a second direction intersecting the first direction, a third non-display area located outside the display area AA in a direction opposite to the first direction, and a fourth non-display area located outside the display area AA in a direction opposite to the second direction.

[0075] As another example, a boundary area between the display area AA and the non-display area NA may be curved such that the non-display area NA may be located below the display area. In this case, when a user views the display device from the front, little or no non-display area NA may be visible to the user.

[0076] The non-display area NA may include a border area BZ or may be the same as the border area BZ. In the GIP structure, the level shifter 600 may be mounted on a printed circuit board (PCB) together with the controller 200.

[0077] The power supply 500 uses a DC-DC converter to generate the DC power required to drive the pixel array of the display panel 100 and the display panel driver. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 500 may receive a DC input voltage applied from a host system (not shown) to generate DC voltages such as a gate-on voltage VGL / VEL, a gate-off voltage VGH / VEH, a high-level drive voltage EVDD, a low-level drive voltage EVSS, etc. The gate-on voltage VGL / VEL and the gate-off voltage VGH / VEH are supplied to the level shifter 600 and the gate driver 300. The high-level drive voltage EVDD and the low-level drive voltage EVSS are commonly supplied to the pixel P.

[0078] The level shifter 600 boosts the transistor-transistor-logic (TTL) level voltage of the gate control signal GCS input thereto from the controller 200 to a gate high voltage VGH or a gate low voltage VGL capable of driving the thin film transistor (TFT) formed at the display panel 100, and then supplies the boosted voltage to the gate driver 300. The gate control signal GCS includes a start signal, a clock signal, etc.

[0079] Figure 2 is a cross-sectional view showing a stacked structure of a display device according to an exemplary embodiment of the present disclosure.

[0080] Referring to Figure 2 , a thin film transistor TFT configured to drive the light emitting element EL may be disposed on the substrate 101 in the display area AA. In Figure 2 , among the various thin film transistors that may be included in the display device 10, for ease of description, only the driving transistor DT ( Figure 7A and Figure 7B ) is shown. However, Figure 2 the shown thin film transistor TFT is not limited to the above conditions. Although the thin film transistor TFT will be described below in conjunction with an example in which the thin film transistor TFT has a coplanar structure, in the following description, the thin film transistor TFT may be implemented with various structures such as a staggered structure.

[0081] The driving transistor DT may control the current supplied to the light emitting element EL based on the high-level drive voltage EVDD corresponding to the data voltage Vdata supplied to its gate electrode 125. According to this current control, the driving transistor DT may adjust the light emission amount of the light emitting element EL. In this case, a constant amount of current is supplied to the light emitting element EL through the voltage charged in the storage capacitor Cst until the data voltage Vdata of the next frame is supplied, and thus, the light emission state of the light emitting element EL may be maintained.

[0082] The high-level driving voltage line PL1 configured to supply a high-level driving voltage EVDD may be formed in parallel with the data line DL. The high-level driving voltage line PL1 and / or the data line DL may be formed of the same material as the source electrode or the drain electrode 140 of the thin-film transistor TFT and on the same layer as the source electrode or the drain electrode 140 of the thin-film transistor TFT. However, the present disclosure is not limited thereto. For example, the high-level driving voltage line PL1 and / or the data line DL may be formed of a material different from that of the source electrode or the drain electrode 140 of the thin-film transistor TFT, and the high-level driving voltage line PL1 and / or the data line DL may also be formed on a layer different from that of the source electrode or the drain electrode 140 of the thin-film transistor TFT.

[0083] The thin-film transistor TFT may include a semiconductor layer 115 disposed on the first insulating layer 110, a gate electrode 125 overlapping the semiconductor layer 115 with a second insulating layer 120 interposed therebetween, and source and drain electrodes 140 formed on the third insulating layer 135 to contact the semiconductor layer 115.

[0084] The semiconductor layer 115 may be a region where a channel is formed during the driving of the thin-film transistor TFT. The semiconductor layer 115 may be formed of an oxide semiconductor or may be formed of various organic semiconductors such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), pentacene, etc., but is not limited thereto.

[0085] The semiconductor layer 115 may be formed on the first insulating layer 110. The semiconductor layer 115 may include a channel region, a source region, and a drain region. The semiconductor layer 115 may overlap the gate electrode 125 with a second insulating layer 120 interposed therebetween, thereby forming a channel region between the source electrode and the drain electrode 140. The source region is electrically connected to the source electrode 140 through a contact hole extending through the second insulating layer 120 and the third insulating layer 135. The drain region is electrically connected to the drain electrode 140 through a contact hole extending through the second insulating layer 120 and the third insulating layer 135.

[0086] The buffer layer 105 and the first insulating layer 110 may be disposed between the semiconductor layer 115 and the substrate 101. The buffer layer 105 may delay the diffusion of moisture and / or oxygen permeating the substrate 101. The first insulating layer 110 may protect the semiconductor layer 115 and may block various defects introduced from the substrate 101.

[0087] The uppermost layer of the buffer layer 105 contacting the first insulating layer 110 may be formed of a material having an etching characteristic different from those of the remaining layer of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135. The uppermost layer of the buffer layer 105 contacting the first insulating layer 110 may be formed of silicon nitride (SiN x ) and silicon oxide (SiO x) and formed by the remaining one of silicon nitride (SiN x ) and silicon oxide (SiO x ). For example, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be formed of silicon nitride (SiN x ), while the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be formed of silicon oxide (SiO x ). For example, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be formed of silicon oxide (SiO x ), while the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be formed of silicon nitride (SiN x ). Of course, the present disclosure is not limited to the above conditions.

[0088] The gate electrode 125 may be formed on the second insulating layer 120 and may overlap with the channel region of the semiconductor layer 115 with the second insulating layer 120 interposed therebetween. The gate electrode 125 may be formed of a first conductive material composed of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and may have a single-layer structure or a multi-layer structure, but is not limited thereto.

[0089] The source electrode 140 may be connected to a source region of the semiconductor layer 115 exposed through a contact hole extending through the second insulating layer 120 and the third insulating layer 135. The drain electrode 140 may face the source electrode 140 and may be connected to a drain region of the semiconductor layer 115 through a contact hole extending through the second insulating layer 120 and the third insulating layer 135. The source electrode and the drain electrode 140 as described above may be formed of a second conductive material made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but is not limited thereto. The second conductive material may be the same as or different from the first conductive material. For example, the first conductive material includes one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, and the second conductive material is the same as the first conductive material. For example, the first conductive material includes one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, while the second conductive material includes another one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) different from the one or an alloy thereof. However, the present disclosure is not limited thereto.

[0090] The connection electrode 155 may be disposed between the first intermediate layer 150 and the second intermediate layer 160. The connection electrode 155 may be exposed through a connection electrode contact hole 156 extending through the protective layer 145 and the first intermediate layer 150, and thus, may be connected to the drain electrode 140. The connection electrode 155 may be made of a material having a low resistivity and be the same as or similar to the drain electrode 150, but is not limited thereto.

[0091] The light-emitting element EL including the light-emitting layer 172 may be disposed on the second intermediate layer 160 and the bank layer 165. The light-emitting element EL may include an anode 171, at least one light-emitting layer 172 formed on the anode 171, and a cathode 173 formed on the light-emitting layer 172.

[0092] The anode 171 may be disposed on the first intermediate layer 150 through a contact hole extending through the second intermediate layer 160 and may be electrically connected to the upwardly exposed connection electrode 155 of the second intermediate layer 160.

[0093] The anode 171 may be formed of a metal material having a high reflectivity, such as a stacked structure of aluminum and titanium Ti / Al / Ti, a stacked structure of aluminum and ITO ITO / Al / ITO, an Ag alloy, a stacked structure of an Ag alloy and ITO ITO / Ag alloy / ITO, a MoTi alloy, and a stacked structure of a MoTi alloy and ITO ITO / MoTi alloy / ITO. The Ag alloy may be an alloy of silver Ag, palladium Pd, and copper Cu. The MoTi alloy may be an alloy of molybdenum Mo and titanium Ti. However, the present disclosure is not limited thereto.

[0094] In each pixel, the anode 171 is formed to be exposed by the bank layer 165. The bank layer 165 may be formed of an opaque material (e.g., black) to prevent light interference between adjacent pixels. In this case, the bank layer 165 may include a light-shielding material composed of at least one of a color pigment, an organic black, or carbon, but is not limited thereto.

[0095] For example, the bank layer 165 may be formed of an organic layer such as an acrylic-based material, an epoxy-based material, a phenolic-based material, a polyamide-based material, or a polyimide-based material. In addition, the bank layer 165 may include an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or the bank layer 165 may be formed of a black resin. However, the present disclosure is not limited thereto.

[0096] The bank layer 165 may cover the edges of each of the anodes 171 and may be formed to expose a part of each of the anodes 171. Therefore, the bank layer 165 can prevent current concentration at the ends of each of the anodes 171, thereby preventing deterioration of the light-emitting efficiency.

[0097] At least one light-emitting layer 172 may be formed on the anode 171 in a light-emitting region provided by the bank layer 165. At least one light-emitting layer 172 may include a hole transport layer, a hole injection layer, a hole blocking layer, a light-emitting layer 172, an electron injection layer, an electron blocking layer, an electron transport layer, etc. on the anode 171, and these layers may be sequentially stacked in their normal order or reverse order according to the light-emitting direction. In addition, under the condition that a charge generation layer is interposed therebetween, the light-emitting layer 172 may be provided at first and second light-emitting stacks facing each other. In this case, the light-emitting layer 172 of one of the first and second light-emitting stacks may generate blue light, and the light-emitting layer 172 of the remaining one of the first and second light-emitting stacks may generate yellow-green light. Therefore, white light may be generated by the first and second light-emitting stacks. The white light generated from the light-emitting stack may be incident on a color filter provided above or below the light-emitting layer 172, and thus, a color image may be rendered.

[0098] In another example, a color image can be rendered to generate color light corresponding to each sub-pixel in each light-emitting layer 172 without providing a separate color filter. For example, the light-emitting layer 172 of the red sub-pixel can generate red light, the light-emitting layer 172 of the green sub-pixel can generate green light, and the light-emitting layer 172 of the blue sub-pixel can generate blue light. However, the present disclosure is not limited thereto.

[0099] The cathode 173 can be formed to face the anode 171 with the light-emitting layer 172 interposed therebetween, and can receive a high-level driving voltage EVDD.

[0100] The cathode 173 can be formed of a transparent conductive material TCO such as indium tin oxide ITO and indium zinc oxide IZO that can transmit light, or can be formed of a semi-transmissive conductive material such as magnesium Mg, silver Ag, or an alloy of magnesium Mg and silver Ag. However, the present disclosure is not limited thereto. When the cathode 173 is formed of a semi-transmissive metal material, the light-emitting efficiency can be improved by a microcavity.

[0101] The encapsulation layer 180 can prevent external moisture or oxygen from penetrating into the light-emitting element EL that is vulnerable to external moisture or oxygen. To this end, the encapsulation layer 180 can include an inorganic encapsulation layer composed of at least one layer and an organic encapsulation layer composed of at least one layer, but is not limited thereto. In the following description, the encapsulation layer 180 will be described in conjunction with a structure in which, for example, the first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 are sequentially stacked.

[0102] The first encapsulation layer 181 is formed on the substrate 101 on which the cathode 173 is formed. The third encapsulation layer 183 is formed on the substrate 101 on which the second encapsulation layer 182 is formed. The third encapsulation layer 183 can be formed together with the first encapsulation layer 181 to surround the upper surface, lower surface, and side surfaces of the second encapsulation layer 182. The first encapsulation layer 181 and the third encapsulation layer 183 as described above can minimize or reduce the penetration of external moisture or oxygen into the light-emitting element EL. The first encapsulation layer 181 and the third encapsulation layer 183 can be formed of an inorganic insulating material that can be deposited at a low temperature, such as silicon nitride (SiN x )), silicon oxide (SiO x ), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 ). Since the first encapsulation layer 181 and the third encapsulation layer 183 are deposited in a low-temperature atmosphere, damage to the light-emitting element EL that is vulnerable to a high-temperature atmosphere can be prevented during the deposition process of the first encapsulation layer 181 and the third encapsulation layer 183.

[0103] The second encapsulation layer 182 may have a buffer function for reducing stress between layers caused by bending of the display device 10, and may flatten the steps between layers. The second encapsulation layer 182 may be formed on the substrate 101 on which the first encapsulation layer 181 is formed using a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon oxycarbide (SiOC), or a photosensitive organic insulating material such as photoacryl, but is not limited thereto.

[0104] When the second encapsulation layer is formed by an inkjet method, a dam DAM may be provided to prevent the second encapsulation layer 182 having a liquid phase from spreading to the edge of the substrate 101. The dam DAM may be provided closer to the edge of the substrate 101 than the second encapsulation layer 182. By means of the dam DAM as described above, it is possible to prevent the second encapsulation layer 182 from spreading to the pad region of the conductive pad at the outermost portion where the substrate 101 is provided.

[0105] Although the dam DAM is designed to prevent the spread of the second encapsulation layer 182, when the second encapsulation layer 182 as an organic layer is formed to overflow the height of the dam DAM during the execution of the associated process, the second encapsulation layer 182 may be exposed outward, and thus, moisture or the like can easily penetrate the light-emitting element. Therefore, in order to prevent such a phenomenon, the dam DAM may be formed so as to form at least ten dams in an overlapping manner.

[0106] The dam DAM may be provided on the protective layer 145 in the non-display area NA. In addition, the dam DAM may be formed simultaneously with the first intermediate layer 150 and the second intermediate layer 160. When the first intermediate layer 150 is formed, the lower layer of the dam DAM may be formed together with the first intermediate layer 150, and when the second intermediate layer 160 is formed, the upper layer of the dam DAM may be formed together with the second intermediate layer 160. Therefore, the dam DAM may be formed to have a double-layered structure.

[0107] Therefore, the dam DAM may be made of the same material as the materials of the first intermediate layer 150 and the second intermediate layer 160, but is not limited thereto. For example, the dam DAM may be formed separately. The dam DAM may be made of a material different from the materials of the first intermediate layer 150 and the second intermediate layer 160.

[0108] The dam DAM may be formed to overlap with the low-level driving voltage line PL2. For example, the low-level driving voltage line PL2 may be formed at a lower layer in the region where the dam DAM is provided in the non-display area NA.

[0109] Alternatively, the encapsulation layer 180 may include a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer stacked in sequence.

[0110] The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer can be used to block the penetration of moisture or oxygen. The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer can be made of inorganic materials, such as inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlOx). However, the present disclosure is not limited thereto.

[0111] The first organic encapsulation layer is disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the second organic encapsulation layer is disposed between the second inorganic encapsulation layer and the third inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer can each have a greater thickness than each of the first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer, so as to adsorb or block particles that may be generated during the manufacturing process of the display device. The first organic encapsulation layer and the second organic encapsulation layer can fill cracks that may form in the first inorganic encapsulation layer and the second inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer can flatten the upper portions of the first inorganic encapsulation layer and the second inorganic encapsulation layer by covering the particles on the first inorganic encapsulation layer and the second inorganic encapsulation layer, respectively. For example, the first organic encapsulation layer can flatten the upper portion of the first inorganic encapsulation layer by covering the particles on the first inorganic encapsulation layer. For example, the second organic encapsulation layer can flatten the upper portion of the second inorganic encapsulation layer by covering the particles on the second inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer can be made of organic materials, and for example, epoxy polymers, acrylic polymers, etc. can be used. However, the present disclosure is not limited thereto.

[0112] In addition, the encapsulation layer 180 is not limited to three layers or five layers. For example, it can include n layers (where n is an integer greater than 3) in which inorganic encapsulation layers and organic encapsulation layers are alternately stacked.

[0113] The low-level driving voltage line PL2 configured as a GIP type and the gate driver 300 are formed to surround the periphery of the display panel. The low-level driving voltage line PL2 can be disposed outside the gate driver 300. In addition, the low-level driving voltage line PL2 can be connected to the anode 171, and thus, a common voltage can be applied to the anode 171. Although the gate driver 300 is simply shown in the plan view and the cross-sectional view, the gate driver 300 can be configured using thin film transistors TFT having the same structure as the thin film transistors TFT in the display area AA, and the present disclosure is not limited thereto.

[0114] The low-level driving voltage line PL2 is disposed outside the gate driver 300. The low-level driving voltage line PL2 disposed outside the gate driver 300 surrounds the display area AA. The low-level driving voltage line PL2 can be made of the same material as the source and drain electrodes 140 of the thin film transistor TFT, but is not limited thereto. For example, the low-level driving voltage line PL2 can be made of the same material as the gate electrode 125.

[0115] In addition, the low-level driving voltage line PL2 can be electrically connected to the anode 171. The low-level driving voltage line PL2 can supply a low-level driving voltage EVSS to a plurality of pixels in the display area AA.

[0116] The touch layer 190 can be disposed on the encapsulation layer 180. In the touch layer 190, the touch buffer layer 191 can be disposed between the touch sensor metal including the touch electrode connection lines 192 and the touch electrodes 194, 195, and 196 and the cathode 173 of the light emitting element EL.

[0117] The touch buffer layer 191 can prevent chemical solutions (developer, etching solution, etc.), external moisture, etc. used in the process of manufacturing the touch sensor metal disposed on the touch buffer layer 191 from penetrating the light emitting layer 172 including an organic material. Therefore, the touch buffer layer 191 can prevent damage to the light emitting layer 172 that is weak against chemical solutions or moisture.

[0118] In order to prevent damage to the light emitting layer 172 including an organic material that is weak against high temperatures, the touch buffer layer 191 is formed of an organic insulating material that can be formed at a low temperature not higher than a predetermined temperature (e.g., 100 °C) and has a low dielectric constant of 1 to 3. For example, the touch buffer layer 191 can be formed of an acrylic-based material, an epoxy-based material, or a siloxane-based material. The touch buffer layer 191 formed of an organic insulating material and having a planarization property can prevent the breakage of the touch sensor metal formed on the touch buffer layer 191 and the damage to the encapsulation layer 180 due to the bending of the display device that can be an organic light emitting display device.

[0119] According to the mutual capacitance-based touch sensor structure, the touch electrodes 195 and 196 are disposed on the touch buffer layer 191. In this case, the touch electrodes 195 and 196 can be disposed to cross each other.

[0120] The touch electrode connection lines 192 can electrically interconnect the touch electrodes 194, 195, and 196. The touch electrode connection lines 192 and the touch electrodes 195 and 196 can be disposed on different layers with a touch insulating layer 193 interposed therebetween. The touch electrode connection lines 1924 can be disposed to overlap the bank layer 165, and thus, a reduction in the aperture ratio can be prevented.

[0121] In addition, a part of the touch electrode connection line 192 can be electrically connected to a touch driving circuit (not shown) through the touch pad 198, and extends along the upper and side surfaces of the encapsulation layer 180 and the upper and side surfaces of the DAM.

[0122] This part of the touch electrode connection line 192 can receive a touch driving signal from the touch driving circuit, then can transmit the touch driving signal to the touch electrodes 195 and 196, and can also transmit the touch sensing signals from the touch electrodes 195 and 196 to the touch driving circuit.

[0123] A touch protection layer 197 can be disposed on the touch electrodes 195 and 196. Although the touch protection layer 197 is shown in the figure as being disposed only on the touch electrodes 195 and 196 in the figure, the present disclosure is not limited thereto, and the touch protection layer 197 can also extend to an area close to or beyond the DAM, such that the touch protection layer 197 is also disposed on the touch electrode connection line 192.

[0124] In addition, a color filter (not shown) can also be disposed on the encapsulation layer 180. The color filter can be disposed on the touch layer 190, or can be disposed between the encapsulation layer 180 and the touch layer 190.

[0125] Figure 3 is a block diagram showing the configuration of a gate driver in a display device according to an exemplary embodiment of the present disclosure.

[0126] Referring to Figure 3 , the display panel 100 can include a display area AA for displaying an image and a non-display area NA for not displaying an image. The non-display area NA is disposed around the display area AA. For example, the non-display area NA can include a first non-display area located outside the display area AA along a first direction, a second non-display area located outside the display area AA along a second direction intersecting the first direction, a third non-display area located outside the display area AA along a direction opposite to the first direction, and a fourth non-display area located outside the display area AA along a direction opposite to the second direction.

[0127] An array of pixels P is disposed in the display area AA. In the non-display area NA, at least a part of the driver can be installed or its connection can be implemented. For example, in the non-display area NA, the gate driver 300 can be disposed on one side of the display area AA, or can be disposed on the opposite side (e.g., left and right sides) of the display area AA, as Figure 3As shown. When the gate drivers 300 are respectively disposed on opposite sides of the non-display area NA, the gate drivers 300 are configured to have a horizontally symmetric structure (mirror structure). Thus, signal distortion caused by load deviation of the gate lines GL can be minimized or reduced. Each gate driver 300 includes a scan driver 310 configured to generate a scan signal SC and a light emission control driver 320 configured to generate a light emission control signal EM.

[0128] The scan driver 310 can supply the scan signal SC to the scan lines SCL in a sequential manner. The light emission control driver 320 can supply the light emission control signal EM to the light emission control signal lines EML in a sequential manner. The scan driver 310 can be implemented by a shift register composed of multiple stages.

[0129] On one side of the display area AA, the scan driver 310 can be disposed adjacent to the display area AA, and the light emission control driver 320 can be disposed outside the scan driver 310. However, the present disclosure is not limited thereto.

[0130] The scan driver 310 and the light emission control driver 320 are driven by receiving respective separate start signals VST and EVST and respective separate clock signals CLK and ECLK via respective different start signal lines VSTL and respective different clock signal lines CLKL. Here, each of the start signals VST and EVST and / or the clock signals CLK and ECLK can be provided individually or in multiple ways.

[0131] Although the respective start signal lines VSTL and the respective clock signal lines CLKL of the scan driver 310 and the light emission control driver 320 are shown in Figure 3 as being disposed adjacent to or connected to the scan driver 310 or the light emission control driver 320, the present disclosure is not limited thereto. For example, each start signal line VSTL and each clock signal line CLKL can be disposed adjacent to each other in an area outside the area where the associated scan driver 310 or the associated light emission control driver 320 is disposed.

[0132] As described above, by simplifying the configuration of the gate drivers disposed on opposite sides of the display area, an effect of reducing the bezel can be provided.

[0133] Figure 4 is a circuit diagram showing a pixel circuit in a display device according to an exemplary embodiment of the present disclosure. In Figure 4 for ease of description, pixels connected to the nth pixel row (n is an integer greater than 0) are shown as an example.

[0134] Referring to Figure 4, the pixel P in the n-th pixel row may include a driving transistor DT, a light-emitting element EL connected to the driving transistor DT, and a control circuit configured to control the amount of driving current to be applied to the light-emitting element EL through the driving transistor DT. For example, the control circuit may include a first transistor T1 to a seventh transistor T7 and a first capacitor C1 and a second capacitor C2. Here, N is a natural number equal to or greater than 2. In addition, the structure of the control circuit is not limited thereto, and the control circuit may include one or more transistors and one or more capacitors. For example, the control circuit may have various structures such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0135] In the driving transistor DT, its first electrode is configured to receive a high-level driving voltage EVDD, and its second electrode is connected to the third node N3. The gate electrode of the driving transistor DT is connected to the second node N2. The driving transistor DT is turned on according to the voltage applied to the second node N2, thereby controlling the amount of driving current flowing through the light-emitting element EL.

[0136] In the first transistor T1, its first electrode is connected to the data line DL, and its second electrode is connected to the first node N1. The gate electrode of the first transistor T1 is connected to the scan line SCL of the n-th pixel row, so that the n-th scan signal SC(n) can be received. The first transistor T1 is turned on according to the n-th scan signal SC(n), thereby transmitting the data voltage Vdata to the first node N1. The first transistor T1 as described above may be a first switching transistor.

[0137] The first capacitor C1 is connected between the first node N1 and the second node N2. The first capacitor C1 can store a voltage corresponding to the voltage difference between the first node N1 and the second node N2. For example, the first capacitor C1 can store a voltage corresponding to the voltage difference between the data voltage Vdata applied to the data line DL and the voltage of the second node N2, and can hold the stored voltage for one frame period, thereby stabilizing the voltage of the gate electrode of the driving transistor DT (i.e., the voltage of the second node N2). The first capacitor C1 as described above may be a storage capacitor Cst.

[0138] The second transistor T2 is connected between the second node N2 and the third node N3. The gate electrode of the second transistor T2 is connected to the scan line SCL of the n-th pixel row, so that the n-th scan signal SC(n) can be received. The second transistor T2 can be turned on according to the n-th scan signal SC(n), thereby electrically interconnecting the gate electrode (second node N2) of the driving transistor DT and the second electrode (third node N3) of the driving transistor DT. Therefore, the second transistor T2 may be configured to have a diode-connected structure for connecting the second node N2 and the third node N3.

[0139] In another embodiment, the second transistor T2 may be composed of a plurality of sub-transistors connected in series to suppress current leakage when the second transistor T2 is turned off. In such a double-gate structure, the two gate electrodes are connected to each other to have the same potential, and the channel length of the double-gate structure is longer than that of the single-gate structure. When the channel length increases, the resistance increases. Therefore, the leakage current decreases in the off state of the second transistor T2. Thus, the operation stability can be ensured. The second transistor T2 as described above may be a second switching transistor.

[0140] In the third transistor T3, its first electrode is configured to receive a reference voltage Vref (connected to the reference voltage line VrefL), and its second electrode is connected to the first node N1. The gate electrode of the third transistor T3 is connected to the light-emitting line (light-emitting element) EL of the (n + 1)-th pixel row, so that the (n + 1)-th light-emitting control signal EM(n + 1) can be received. The third transistor T3 is turned on according to the (n + 1)-th light-emitting control signal EM(n + 1), thereby transmitting the reference voltage Vref to the first node N1. The third transistor T3 as described above may be a third switching transistor.

[0141] The fourth transistor T4 is connected between the third node N3 and the fourth node N4. The gate node of the fourth transistor T4 is connected to the light-emitting line (light-emitting element) EL of the n-th pixel row, so that the n-th light-emitting control signal EM(n) can be received. The fourth transistor T4 is turned on according to the n-th light-emitting control signal EM(n), thereby electrically interconnecting the driving transistor DT (third node N3) and the light-emitting element EL (fourth node N4). The fourth transistor T4 as described above may be a light-emitting transistor.

[0142] In the fifth transistor T5, its first electrode is configured to receive an initialization voltage Vini (connected to the initialization voltage line ViniL), and its second electrode is connected to the fourth node N4. The gate electrode of the fifth transistor T5 is connected to the scan line SCL of the n-th pixel row, so that the n-th scan signal SC(n) can be received. The fifth transistor T5 is turned on according to the n-th scan signal SC(n), thereby applying the initialization voltage Vini to the anode 171 (fourth node N4) of the light-emitting element EL. The fifth transistor T5 as described above may be a first initialization transistor.

[0143] In the sixth transistor T6, its first electrode is configured to receive a reference voltage Vref, and its second electrode is connected to the second node N2. The gate electrode of the sixth transistor T6 is connected to the scan line SCL of the (n-1)th pixel row, and thus, can receive the (n-1)th scan signal SC(n-1). The sixth transistor T6 is turned on according to the (n-1)th scan signal SC(n-1), thereby applying the reference voltage Vref to the gate electrode (the second node N2) of the driving transistor DT. The sixth transistor T6 as described above may be a second initialization transistor.

[0144] The second capacitor C2 is connected between the fourth node N4 and the low-level driving voltage line PL2 to which a low-level driving voltage EVSS is applied. The second capacitor C2 may be configured to form a capacitance between the anode 171 and the cathode 173 of the light-emitting element EL. The second capacitor C2 as described above may be a parasitic capacitor Coled of the light-emitting element EL. Since the second capacitor C2 is a parasitic capacitor Coled and the first capacitor C1 is a storage capacitor Cst, the first capacitor C1 may have a larger capacitance than the second capacitor C2.

[0145] In the seventh transistor T7, its first electrode is connected to the fourth node N4, and its second electrode is connected to the initialization voltage line ViniL. The gate electrode of the seventh transistor T7 is connected to the sense signal line SL, and thus, can receive the sense signal Sen. The seventh transistor T7 is turned on according to the sense signal Sen, thereby forming a current path between the sensing unit 700 and the second capacitor C2. Therefore, the sensing unit 700 can sense the amount of electric charge stored in the second capacitor C2. The seventh transistor T7 as described above may be a sensing transistor.

[0146] In the light-emitting element EL, its anode 171 may be connected to the fourth node N4, and its cathode 173 may be connected to the low-level driving voltage EVSS. When the driving transistor DT and the fourth transistor T4 are turned on, a current path is formed between the high-level driving voltage EVDD and the low-level driving voltage EVSS, and thus, a driving current can flow through the light-emitting element EL. The light-emitting element EL can emit light with a brightness corresponding to the amount of the driving current applied thereto.

[0147] In Figure 4 In the exemplary embodiment shown, the pixel P includes a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The LTPS thin-film transistor includes a gate electrode, a source electrode, and a drain electrode. The LTPS thin-film transistor includes an active layer formed of polycrystalline silicon. Such an LTPS thin-film transistor may be composed of a P-type thin-film transistor. The LTPS thin-film transistor has a high electron mobility, and thus, has fast driving characteristics. However, the exemplary embodiment is not limited to the above conditions.

[0148] In another embodiment, at least one of the transistors DT, T1 to T5, or T6 may be formed of an oxide semiconductor thin film transistor. The oxide semiconductor thin film transistor includes a gate electrode, a source electrode, and a drain electrode. The oxide semiconductor thin film transistor includes an active layer formed of an oxide semiconductor. Here, the oxide semiconductor may be an amorphous or crystalline oxide semiconductor. The oxide semiconductor thin film transistor may be formed of an N-type transistor. Compared with the LTPS thin film transistor, the oxide semiconductor thin film transistor can be manufactured by a low-temperature process and has a low charge mobility. The oxide semiconductor thin film transistor as described above exhibits excellent off-current characteristics.

[0149] The reference voltage line VrefL may be formed of the same material as the source electrode or the drain electrode 140 of the transistor TFT at the same layer as the source electrode or the drain electrode 140. However, the present disclosure is not limited to the above conditions, and at least a part of the reference voltage line VrefL may be formed of the same material as the gate electrode 125 at the same layer as the gate electrode 125, may be formed of the same material as the touch electrodes 194, 195, and 196 at the same layer as the touch electrodes 194, 195, and 196, or may be formed of the same material as the semiconductor layer 115 at the same layer as the semiconductor layer 115. In addition, at least a part of the reference voltage line VrefL may be formed of the same material as a shield metal layer not shown in the figure at the same layer as the shield metal layer.

[0150] As described above, it is possible to prevent a failure caused by a short circuit that may occur in a pixel during driving, and to enhance image quality by sensing and compensating for the deterioration of the light-emitting element.

[0151] Figure 5 is a diagram depicting the operation waveforms of the pixel circuit shown in Figure 4 the display mode of a display device according to an exemplary embodiment of the present disclosure.

[0152] Refer to Figure 5 , each of the plurality of pixels P may perform an initialization operation, a programming operation, and a light-emitting operation according to the scan signal SC and the light-emitting control signal EM.

[0153] During the initialization period ① when performing the initialization operation, the pixel circuit may initialize a specific node therein to the reference voltage Vref to stabilize the operation.

[0154] During the programming period ② when performing the programming operation, the pixel circuit may program the gate-source voltage of the driving transistor DT based on the data voltage Vdata. During the programming period ②, the threshold voltage of the driving transistor DT may be sampled and compensated.

[0155] During the light emission period ③ when the light emission operation is performed, a driving current corresponding to the gate-source voltage flows between the source electrode and the drain electrode of the driving transistor DT, and the light emitting element EL emits light through the driving current. According to the light emission control signal EM, the light emitting transistor can be turned on during the initialization period ① and the light emission period ③, and turned off during the programming period ②.

[0156] In an exemplary embodiment of the present disclosure, the driving mode in which the pixel P performs the initialization operation, the programming operation, and the light emission operation is referred to as the "display mode".

[0157] In addition to the display mode, the pixel P according to an exemplary embodiment of the present disclosure also performs a sensing mode for sensing the degradation of the light emitting element EL. The operation of the pixel P in the sensing mode will be described in detail later with reference to Figure 6 the detailed description of the operation of the pixel P in the sensing mode.

[0158] First, with reference to Figure 5 , one frame may include an initialization period ①, a programming period ②, and a light emission period ③.

[0159] In the initialization period ①, the (n + 1)-th light emission control signal EM(n + 1) of a conductive level is applied to turn on the third transistor T3, and the (n - 1)-th scan signal SC(n - 1) of a conductive level is applied to turn on the sixth transistor T6. Therefore, during the initialization period ①, the reference voltage Vref is applied to the first node N1 and the second node N2. In this case, when the reference voltage Vref is applied to the second node N2 connected to the gate electrode of the driving transistor DT, the driving transistor DT can be turned on. However, the fourth transistor T4 is in the off state. Therefore, the second electrode of the driving transistor DT connected to the third node N3 can be in a floating state during the initialization period ①. Therefore, both ends of the first capacitor C1 can be initialized to the reference voltage Vref during the initialization period ①.

[0160] In the programming period ②, the (n + 1)-th light emission control signal EM(n + 1) and the (n - 1)-th scan signal SC(n - 1) transition to the cut-off level. Therefore, the third transistor T3 and the sixth transistor T6 are turned off, while the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on according to the n-th scan signal SC(n) to which a conductive level is applied. Therefore, during the programming period ②, the data voltage Vdata applied to the data line DL is applied to the first node N1, and the initialization voltage Vini applied to the initialization voltage line ViniL is applied to the fourth node N4.

[0161] In addition, the charging voltage of the first capacitor C1 can gradually reach a voltage corresponding to the difference between the data voltage Vdata and the reference voltage Vref. When the charging voltage of the first capacitor C1 is transmitted to the gate electrode of the driving transistor DT, the source-gate voltage of the driving transistor DT becomes greater than the threshold voltage Vth of the driving transistor DT. Therefore, the driving transistor DT can be turned on. In this case, the source-drain current of the driving transistor DT can be determined based on the data voltage Vdata, the reference voltage Vref, and the threshold voltage Vth of the driving transistor DT. The driving transistor DT can supply the source-drain current to the third node N3 until the source-gate voltage of the driving transistor DT reaches the threshold voltage Vth of the driving transistor DT. In addition, the second transistor T2 can supply the voltage of the third node N3 to the second node N2.

[0162] During the on-period of the driving transistor DT, the voltage of the second node N2 and the source-drain current of the driving transistor DT can change in the above-described manner, and the voltage of the second node N2 can converge to a differential voltage between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT.

[0163] In addition, during the programming period ②, since the initialization voltage Vini is applied to the fourth node N4 through the fifth transistor T5, the anode 171 of the light-emitting element EL can be initialized to the initialization voltage Vini corresponding to the voltage of the fourth node N4. Therefore, during the programming period ②, the second capacitor C2 can be initialized to the initialization voltage Vini.

[0164] A holding period may also be included between the programming period ② and the light-emitting period ③. During the holding period, the n-th scan signal SC(n) transitions to the cut-off level. Therefore, the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off. During the holding period, the voltage of the second node N2 can be stably held by the first capacitor C1.

[0165] In the light-emitting period ③, the n-th light-emitting control signal EM(n) and the (n + 1)-th light-emitting control signal EM(n + 1) at the conduction level are applied. Therefore, the third transistor T3 and the fourth transistor T4 are turned on, and a current path extending from the high-level driving voltage EVDD through the driving transistor DT to the light-emitting element EL is formed. During the light-emitting period ③, the reference voltage Vref is applied to the first node N1 through the turned-on third transistor T3. In this case, both ends of the first capacitor C1 are coupled to each other. Therefore, the voltage of the second node N2 can be [Vref - Data + VDD + Vth]. Therefore, a drive current amount corresponding to the programming voltage flows along the current path through the driving transistor DT. Therefore, the driving transistor DT can cause the light-emitting element EL to emit light with a brightness corresponding to the drive current amount.

[0166] Figure 6 It is a diagram depicting the operation waveforms during the active period of the display mode operation and the blanking period of the sensing mode operation in one frame in a display device according to an exemplary embodiment of the present disclosure.

[0167] Reference Figure 6 , in the display mode operating during the active period V_Active, the scan signal SC and the emission control signal EM are sequentially applied to a plurality of pixels. Accordingly, the plurality of pixels operate to display an image on the display panel 100.

[0168] The sensing signal Sen may be applied at a cut-off level during the active period V_Active of the display mode operation.

[0169] In the sensing mode operating during the blanking period V_Blank, a sensing signal Sen at a conductive level is applied through the sensing signal line SL. Accordingly, the seventh transistor T7 may be turned on. Thus, the sensing unit 700 may sense the amount of charge stored in the second capacitor C2 through a current path formed by means of the initialization voltage line ViniL.

[0170] In other words, the second capacitor C2 forms a capacitance between the anode 171 and the cathode 173 of the light-emitting element EL, and the amount of charge stored in the second capacitor C2 may vary according to the degree of deterioration of the light-emitting element EL. Accordingly, the degree of deterioration of the light-emitting element EL may be sensed by sensing the amount of charge of the second capacitor C2.

[0171] In addition, during the blanking period V_Blank, the scan signal SC and the emission control signal EM of all pixel rows operate at a cut-off level, and the sensing signal Sen may have a phase inverted with respect to the phase of the emission control signal EM.

[0172] Figure 7A and Figure 7B is a diagram showing the configuration of a controller including a sensing unit in a display device according to an exemplary embodiment of the present disclosure.

[0173] Reference Figure 7A and Figure 7B , each of the initialization voltage line ViniL and the sensing signal line SL in the display panel 100 may be configured to include horizontal lines and vertical lines. Accordingly, they may be connected to a plurality of pixels P. In this case, the initialization voltage line ViniL may operate to initialize the light-emitting element EL in the display mode by applying the initialization voltage Vini to the fourth node N4 via the power supply 500, while the initialization voltage line ViniL may operate in the sensing mode to sense the amount of charge of the second capacitor C2 through the sensing unit 700, thereby sensing the deterioration state of the light-emitting element EL.

[0174] The initialization voltage line ViniL and / or the sensing signal line SL branch into vertical lines from a horizontal line formed on one side of the display panel 100, and all the initialization voltage lines ViniL in the display panel 100 can be electrically interconnected. Thus, in the sensing mode, the sensing unit 700 can obtain an analog sensing voltage Vsen by directly sensing the current flowing through all the light-emitting elements EL.

[0175] The initialization voltage line ViniL and / or the sensing signal line SL can be formed in the same layer as the source electrode or drain electrode 140 of the transistor TFT using the same material as the source electrode or drain electrode 140 of the transistor TFT. Of course, the present disclosure is not limited to the above conditions, and at least a part of the initialization voltage line ViniL and / or the sensing signal line SL can be formed in the same layer as the gate electrode 125 using the same material as the gate electrode 125, can be formed in the same layer as the touch electrodes 194, 195, and 196 using the same material as the touch electrodes 194, 195, and 196, or can be formed in the same layer as the semiconductor layer 115 using the same material as the semiconductor layer 115. In addition, at least a part of the initialization voltage line ViniL and / or the sensing signal line SL can be formed in the same layer as a shielding metal layer (not shown in the figure) using the same material as the shielding metal layer.

[0176] The sensing unit 700 can be configured to include a current integrator 710 and an analog-to-digital converter (hereinafter referred to as "ADC") 720. The current integrator 710 includes: an amplifier AMP, the amplifier AMP includes: an inverting input terminal (-) configured to receive the pixel current of the light-emitting element EL from the initialization voltage line ViniL; a non-inverting input terminal (+) configured to receive an initialization voltage Vpre; and an output terminal; an integration capacitor Cfb connected between the inverting input terminal (-) and the output terminal of the amplifier AMP; and a reset switch RST connected to both ends of the integration capacitor Cfb. The current integrator 710 is connected to the ADC 720, and thus, the analog sensing voltage Vsen output from the amplifier AMP of the current integrator 710 is supplied to the ADC 720.

[0177] In Figure 7A an exemplary embodiment, the sensing unit 700 can be provided on a printed circuit board (PCB) together with the controller 200, and thus, the current flowing through all the light-emitting elements EL provided in the display panel 100 can be sensed at one time. Alternatively, as in Figure 7BIn an exemplary embodiment, the sensing unit 700 may be configured in each of a plurality of driver integrated circuits (D-ICs) included in the data driver 400. In this case, the plurality of sensing units 700 may be configured to be equal in number to the D-ICs. Each sensing unit 700 senses only the area of the display panel 100 driven by one D-IC, and thus, the deterioration degree of the light-emitting element EL can be sensed more intensively.

[0178] In addition, the sensing unit 700 may simultaneously process a plurality of analog sensing voltages Vsen in parallel using a plurality of ADCs, or may sequentially process a plurality of analog sensing voltages Vsen serially using one ADC. Compared with the ADC in serial processing, the advantage of the ADC in parallel processing is that the sensing accuracy is improved. Such an ADC may be implemented by a flash-type ADC, an ADC using a tracking technique, a successive approximation register (SART)-type ADC, or the like. The ADC 720 converts the analog sensing voltage Vsen supplied from the current integrator 710 into digital sensing data, and then transmits the digital sensing data to the controller 200.

[0179] The controller 200 may analyze the digital sensing data, and thus, may output compensation data according to the cumulative deterioration degree of the light-emitting element EL. In this case, one of a plurality of look-up tables (LUTs) stored in the memory may be used to determine the compensation data. In other words, the controller 200 may compensate for the deterioration of the light-emitting element EL by selecting a suitable one in the LTU according to the deterioration level of the light-emitting element EL. Therefore, the compensation error can be minimized or reduced by sensing the deterioration of the light-emitting element EL and compensating for the sensed deterioration using a plurality of LUTs.

[0180] Figure 8 is a diagram depicting the lifetime luminance in a display device according to an exemplary embodiment of the present disclosure.

[0181] As described above, the sensing mode may operate in each blanking period V_Blank of all frames. Of course, the sensing mode is not limited to the above conditions, and may be executed to be activated at a specific time.

[0182] In other words, in the sensing mode, the sensing signal Sen transitions to the conductive level after a previously set time when the display device 10 is driven, and transitions back to the cutoff level again after the sensing and compensation of the light-emitting element EL are completed. These processes may be repeated for all frames. That is, the sensing mode may be activated only at a previously set time, and may operate to sense the deterioration of the light-emitting element EL by applying a conductive-level sensing signal Sen during the blanking period V_Blank to turn on the seventh transistor T7 and thus form a current path.

[0183] In this case, the controller 200 may further include a data counter (not shown). The data counter may accumulate data such as an image signal, a synchronization signal, etc., thereby counting the driving time of the display panel 100, and may be operated to output a sensing signal Sen at a specific time.

[0184] In other words, the display device 10 may drive the light-emitting element EL at a luminance intensity corresponding to the first lifetime luminance B1 at an initial driving time. Then, the display device 10 may apply a sensing signal Sen of a conduction level at a first sensing time t1 to sense the deterioration of the light-emitting element EL and compensate for the sensed deterioration, and thus, may drive the light-emitting element EL at a second lifetime luminance B2. Similarly, the display device 10 may drive the light-emitting element EL at a third lifetime luminance B3 at a second sensing time t2. In this case, the first sensing time t1 may be a time after at least 2,000 hours have elapsed.

[0185] For example, as Figure 8 shown, before the first sensing time t1, the display device 10 may drive the light-emitting element EL at a luminance intensity corresponding to the first lifetime luminance B1, between the first sensing time t1 and the second sensing time t2, the display device 10 may drive the light-emitting element EL at a second lifetime luminance B2 lower than the first lifetime luminance B1, and from the second sensing time t2, the display device 10 may drive the light-emitting element EL at a third lifetime luminance B3 lower than the second lifetime luminance B2. However, the present disclosure is not limited thereto.

[0186] From the above description, it can be seen that, through the pixel circuit according to the exemplary embodiment of the present disclosure, a failure due to a short circuit that may occur during driving can be prevented, the lifetime reliability can be enhanced by using the deterioration sensing and compensation of the initialization voltage line ViniL, and non-uniform defects such as horizontal stripes due to the luminance difference between the active period V_Active and the blanking period V_Blank can be avoided.

[0187] In addition, each of the gate drivers 300 provided on the opposite sides of the display area AA is configured by including a scan driver 310 and a light-emitting control driver 320, and thus, the bezel area BZ including the non-display area NA can be designed to have a small area.

[0188] A display device according to an exemplary embodiment of the present disclosure will be described below.

[0189] A display device according to an exemplary embodiment of the present disclosure may include: a display panel on which a plurality of data lines, a plurality of gate lines, and a plurality of sub-pixels are disposed, the display panel being configured to operate in a display mode for displaying an image and a sensing mode for sensing degradation of pixels; a gate driver configured to supply a scan signal and a light emission control signal to the plurality of gate lines; a data driver configured to supply a data signal to the plurality of data lines; a power supply configured to apply an initialization voltage to the pixels in the sensing mode; and a sensing unit configured to sense degradation of the pixels in the sensing mode.

[0190] A display device according to an exemplary embodiment of the present disclosure may include a light-emitting element; a capacitor connected between a first node and a second node; a first transistor including a first electrode connected to a reference voltage line and a second electrode connected to the first node, the first transistor being configured to supply a reference voltage to the first node in response to a light emission control signal of the (n + 1)-th pixel row; a second transistor including a first electrode connected to the reference voltage line and a second electrode connected to the second node, the second transistor being configured to supply a reference voltage to the second node in response to a scan signal of the (n - 1)-th pixel row; and a driving transistor connected to the second node at its gate electrode, the driving transistor including a first electrode configured to receive a high-level driving voltage and a second electrode connected to a third node.

[0191] A display device according to an exemplary embodiment of the present disclosure may further include: a third transistor including a first electrode connected to an initialization voltage line and a second electrode connected to a fourth node, the third transistor being configured to supply an initialization voltage to the fourth node in response to a scan signal of the n-th pixel row; and a second capacitor having one end connected to the fourth node and the other end connected to a low-level driving voltage line.

[0192] A display device according to an exemplary embodiment of the present disclosure may further include a fourth transistor including a first electrode connected to the initialization voltage line and a second electrode connected to one end of the second capacitor, the fourth transistor being configured to conduct in response to a sensing signal.

[0193] In a display device according to an exemplary embodiment of the present disclosure, the first capacitor may have a larger capacitance than the second capacitor.

[0194] A display device according to an exemplary embodiment of the present disclosure may further include a fifth transistor including a first electrode connected to a data line and a second electrode connected to the first node, the fifth transistor being configured to conduct in response to a scan signal of the n-th pixel row to transfer a data voltage to the first node.

[0195] The display device according to an exemplary embodiment of the present disclosure may further include a sixth transistor connected between the second node and the third node, and the sixth transistor is configured to be turned on in response to a scan signal of the nth pixel row to electrically interconnect the gate electrode of the driving transistor and the second electrode of the driving transistor.

[0196] The display device according to an exemplary embodiment of the present disclosure may further include a seventh transistor connected between the third node and the fourth node, and the seventh transistor is configured to be turned on in response to a light emission control signal of the nth pixel row to interconnect the driving transistor and the light emitting element.

[0197] In the display device according to an exemplary embodiment of the present disclosure, the fourth transistor may operate only in a sensing mode.

[0198] In the display device according to an exemplary embodiment of the present disclosure, the gate driver may include one scan driver and one light emission control driver respectively disposed on opposite sides of the display area.

[0199] In the display device according to an exemplary embodiment of the present disclosure, the gate driver may receive a gate control signal through a level shifter.

[0200] In the display device according to an exemplary embodiment of the present disclosure, the sensing unit may be disposed on a printed circuit board.

[0201] In the display device according to an exemplary embodiment of the present disclosure, the data driver may include a plurality of driver integrated circuits (D-ICs), and the sensing unit may be configured to be included in each of the plurality of D-ICs to sense the display panel on a block basis.

[0202] In the display device according to an exemplary embodiment of the present disclosure, at least one of a reference voltage line, an initialization voltage line, or a sensing signal line may be disposed on the same layer as a high-level driving voltage line or a data line.

[0203] In the display device according to an exemplary embodiment of the present disclosure, at least one of a reference voltage line, an initialization voltage line, or a sensing signal line may be formed of the same material as the first electrode and the second electrode of the driving transistor.

[0204] In the display device according to an exemplary embodiment of the present disclosure, at least two of a reference voltage line, an initialization voltage line, and a sensing signal line may be parallel.

[0205] In a display device according to an exemplary embodiment of the present disclosure, one frame may be configured to include an active period for displaying an image and a blanking period other than the active period. A display mode may operate during the active period, and a sensing mode may operate during the blanking period.

[0206] In a display device according to an exemplary embodiment of the present disclosure, a sensing unit may sense pixel degradation through a sensing signal output at a previously set time.

[0207] In a display device according to an exemplary embodiment of the present disclosure, a controller may count the driving time of a display panel by accumulating data and may output a sensing signal at a previously set time.

[0208] A display device according to an exemplary embodiment of the present disclosure may include: a light-emitting element; a capacitor connected between a first node and a second node; a first transistor including a first electrode connected to a reference voltage line and a second electrode connected to the first node, the first transistor being configured to supply a reference voltage to the first node in response to a light-emitting control signal of the (n + 1)-th pixel row; a second transistor including a first electrode connected to the reference voltage line and a second electrode connected to the second node, the second transistor being configured to provide the reference voltage to the second node in response to a scanning signal of the (n - 1)-th pixel row; a driving transistor having its gate electrode connected to the second node, the driving transistor including a first electrode configured to receive a high-level driving voltage and a second electrode connected to a third node; a third transistor including a first electrode connected to an initialization voltage line and a second electrode connected to a fourth node, the third transistor being configured to provide an initialization voltage to the fourth node in response to a scanning signal of the n-th pixel row; and a fourth transistor including a first electrode connected to the initialization voltage line and a second electrode connected to the fourth node, the fourth transistor being configured to conduct in response to a sensing signal.

[0209] A control method of a pixel circuit according to an exemplary embodiment of the present disclosure is provided. The pixel circuit includes a first transistor, a second transistor, a driving transistor, a third transistor, a fourth transistor, and a first capacitor. The control method may include: supplying a reference voltage to a first node via the first transistor in response to a light emission control signal of the (n + 1)-th pixel row, where the first transistor includes a first electrode connected to a reference voltage line and a second electrode connected to the first node; supplying a reference voltage to a second node via the second transistor in response to a scan signal of the (n - 1)-th pixel row, where the second transistor includes a first electrode connected to the reference voltage line and a second electrode connected to the second node; receiving a high-level driving voltage via the driving transistor, where the driving transistor includes a first electrode receiving the high-level driving voltage, a second electrode connected to a third node, and a gate electrode connected to the second node; supplying an initialization voltage to a fourth node via the third transistor in response to a scan signal of the n-th pixel row, where the third transistor includes a first electrode connected to an initialization voltage line and a second electrode connected to the fourth node; and turning on the fourth transistor in response to a sensing signal, where the fourth transistor includes a first electrode connected to the initialization voltage line and a second electrode connected to the fourth node, and wherein the first capacitor is connected between the first node and the second node.

[0210] As can be seen from the above description, according to an exemplary embodiment of the present disclosure, failures caused by short circuits that may occur in pixels during driving can be prevented, and image quality enhancement can be achieved by sensing and compensating for the degradation of light-emitting elements.

[0211] In addition, an effect of reducing the bezel can be provided by simplifying the configuration of a gate driver provided on the opposite side of the display area.

[0212] The effects according to the exemplary embodiments of the present disclosure are not limited to the above, and various broader effects may be included in the description.

[0213] The features, structures, or effects described in the foregoing exemplary embodiments are included in at least one exemplary embodiment of the present disclosure and are not necessarily limited to one exemplary embodiment thereof. In addition, the features, structures, or effects illustrated in each exemplary embodiment can be combined or modified by those skilled in the art and implemented in other embodiments thereof. Therefore, the description related to such combinations and modifications will be construed as being included within the scope of the present disclosure.

[0214] Obviously, the present disclosure described above is not limited to the above-described embodiments and the accompanying drawings, and those skilled in the art will understand that various modifications, changes, and substitutions are possible without departing from the scope and spirit of the present disclosure. Accordingly, the scope of the present disclosure is defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present disclosure.

[0215] Cross-reference to Related Applications

[0216] This application claims the benefit of priority of Korean Patent Application No. 10-2023-0180885, filed on Dec. 13, 2023, the entire contents of which are hereby expressly incorporated herein for all purposes.

Claims

1. A display device, comprising: A display panel, on which a plurality of data lines, a plurality of gate lines and a plurality of pixels are arranged, and the display panel is configured to operate in a display mode and a sensing mode; a gate driver configured to supply a scan signal and a light emitting control signal to the plurality of gate lines; a data driver configured to supply data signals to the plurality of data lines; a power supply configured to apply an initialization voltage to the plurality of pixels in the sensing mode; as well as A sensing unit is configured to sense degradation of the plurality of pixels in the sensing mode.

2. The display device according to claim 1, wherein: Among the plurality of pixels, each pixel of the nth pixel row includes: Light emitting element; a first capacitor connected between the first node and the second node; a first transistor including a first electrode connected to a reference voltage line and a second electrode connected to the first node, the first transistor being configured to supply a reference voltage to the first node in response to a light emission control signal of an n+1th pixel row; a second transistor including a first electrode connected to the reference voltage line and a second electrode connected to the second node, the second transistor being configured to supply the reference voltage to the second node in response to a scan signal of an n-1th pixel row; and a driving transistor including a gate electrode connected to the second node, a first electrode configured to receive a high-level driving voltage, and a second electrode connected to a third node, Here, n is an integer greater than 1.

3. The display device according to claim 2, wherein: The pixel also includes: a third transistor including a first electrode connected to the initialization voltage line and a second electrode connected to a fourth node, the third transistor being configured to supply the initialization voltage to the fourth node in response to a scan signal of an n-th pixel row; and A second capacitor is connected between the fourth node and a low-level driving voltage line.

4. The display device according to claim 3, wherein: The pixel also includes: A fourth transistor includes a first electrode connected to the initialization voltage line and a second electrode connected to one end of the second capacitor, the fourth transistor being configured to be turned on in response to a sensing signal.

5. The display device according to claim 4, wherein: The first capacitor has a capacitance greater than that of the second capacitor.

6. The display device according to claim 4, wherein: The pixel also includes: A fifth transistor includes a first electrode connected to the data line and a second electrode connected to the first node, and is configured to be turned on in response to the scan signal of the n-th pixel row to transmit a data voltage to the first node.

7. The display device according to claim 6, wherein: The pixel also includes: A sixth transistor is connected between the second node and the third node, and is configured to be turned on in response to the scan signal of the n-th pixel row to electrically interconnect the gate electrode of the driving transistor and the second electrode of the driving transistor.

8. The display device according to claim 7, wherein: The pixel also includes: A seventh transistor is connected between the third node and the fourth node, and is configured to be turned on in response to a light emission control signal of an n-th pixel row to interconnect the driving transistor and the light emitting element.

9. The display device according to claim 4, wherein: The fourth transistor operates only in the sensing mode.

10. The display device according to claim 4, wherein: At least one of the reference voltage line, the initialization voltage line, or a sensing signal line for supplying the sensing signal is disposed at the same layer as a high-level driving voltage line for supplying the high-level driving voltage or the data line.

11. The display device according to claim 4, wherein: At least one of the reference voltage line, the initialization voltage line, or a sensing signal line for supplying the sensing signal is formed of the same material as that of the first electrode and the second electrode of the driving transistor.

12. The display device according to claim 4, wherein: At least two of the reference voltage line, the initialization voltage line, and a sensing signal line for supplying the sensing signal are parallel.

13. The display device according to claim 1, wherein: The gate driver includes a scan driver and a light emission control driver respectively disposed at opposite sides of the display area.

14. The display device according to claim 13, wherein: The light emitting control driver is arranged outside the scanning driver.

15. The display device according to claim 1, wherein: The gate driver receives a gate control signal through a level shifter.

16. The display device according to claim 1, wherein: The sensing unit is arranged on a printed circuit board.

17. The display device according to claim 1, wherein: The data driver includes a plurality of driver integrated circuits, and The sensing unit is included in each of the plurality of driver integrated circuits to sense the display panel on a block basis.

18. The display device according to claim 1, wherein: One frame of the display device includes an active period for displaying an image and a blanking period other than the active period. The display mode operates during the active period, and The sensing mode operates in the blanking period.

19. The display device according to claim 1, wherein: The sensing unit senses pixel degradation through a sensing signal output at a previously set time.

20. The display device according to claim 19, further comprising: A controller is provided for counting the driving time of the display panel through accumulation of data and outputting the sensing signal at the previously set time.

21. A pixel circuit, the pixel circuit comprising: Light emitting element; a first capacitor connected between the first node and the second node; a first transistor including a first electrode connected to a reference voltage line and a second electrode connected to the first node, the first transistor being configured to supply a reference voltage to the first node in response to a light emission control signal of an n+1th pixel row; a second transistor including a first electrode connected to the reference voltage line and a second electrode connected to the second node, the second transistor being configured to supply the reference voltage to the second node in response to a scan signal of an n-1th pixel row; a driving transistor including a gate electrode connected to the second node, a first electrode configured to receive a high-level driving voltage, and a second electrode connected to a third node; a third transistor including a first electrode connected to the initialization voltage line and a second electrode connected to a fourth node, the third transistor being configured to supply an initialization voltage to the fourth node in response to a scan signal of an n-th pixel row; as well as A fourth transistor includes a first electrode connected to the initialization voltage line and a second electrode connected to the fourth node, the fourth transistor being configured to be turned on in response to a sensing signal.

22. The pixel circuit according to claim 21, wherein: The fourth transistor operates only in the sensing mode.

23. The pixel circuit according to claim 21, further comprising: A second capacitor is connected between the fourth node and the low level driving voltage line.

24. The pixel circuit according to claim 23, wherein: The first capacitor has a capacitance greater than that of the second capacitor.

25. A control method for a pixel circuit, the pixel circuit comprising a first transistor, a second transistor, a driving transistor, a third transistor, a fourth transistor and a first capacitor, the control method comprising: supplying a reference voltage to a first node via the first transistor in response to a light emitting control signal of an n+1-th pixel row, the first transistor including a first electrode connected to a reference voltage line and a second electrode connected to the first node; supplying the reference voltage to a second node via the second transistor in response to a scan signal of an n-1th pixel row, the second transistor comprising a first electrode connected to the reference voltage line and a second electrode connected to the second node; receiving a high-level driving voltage via the driving transistor, the driving transistor comprising a first electrode receiving the high-level driving voltage, a second electrode connected to a third node, and a gate electrode connected to the second node; supplying an initialization voltage to a fourth node via the third transistor in response to a scan signal of an n-th pixel row, the third transistor including a first electrode connected to an initialization voltage line and a second electrode connected to the fourth node; and turning on the fourth transistor in response to a sensing signal, the fourth transistor comprising a first electrode connected to the initialization voltage line and a second electrode connected to the fourth node, The first capacitor is connected between the first node and the second node.

26. The method for controlling a pixel circuit according to claim 25, wherein: The fourth transistor operates only in the sensing mode.

27. The method for controlling a pixel circuit according to claim 25, wherein: The second capacitor is connected between the fourth node and the low-level driving voltage line.

28. The method for controlling a pixel circuit according to claim 27, wherein: The first capacitor has a capacitance greater than that of the second capacitor.

Images