Display panel, driving method and display device

Abstract

The invention provides a display panel and a driving method thereof, a bias transistor in a pixel circuit of the display panel biases a second end of a driving transistor to solve the problem of threshold drift of the driving transistor, a first reset transistor resets a grid electrode of the driving transistor, and a second reset transistor resets the grid electrode of the driving transistor to solve the problem of threshold drift of the driving transistor. The bias transistor in the pixel circuit only needs to receive a signal for biasing the second end of the driving transistor, and obviously, the signal for biasing can be a fixed signal, so that an independent shift register circuit does not need to be arranged to control the signal; the data writing transistor and the first reset transistor have the same transistor type, so that the data writing transistor and the first reset transistor can be controlled at the same time through a group of shift register circuits, and the number of the shift register circuits is further reduced, so that the narrow frame design of the display panel is realized; and the performance of the driving transistor can be ensured, so that the display effect of the display panel is ensured.

Description

[0001] This application is a divisional application of the application with the application number 202211103061.1, the application date of September 9, 2022, and the invention title "A display panel and its driving method". Technical Field

[0002] The present invention relates to the field of display technologies, and more particularly, to a display panel, a driving method, and a display device. Background Art

[0003] Organic light-emitting display devices have the advantages of self-luminescence, low driving voltage, high luminous efficiency, fast response speed, light weight, high contrast, etc., and are considered to be the most promising display devices for the next generation.

[0004] Pixels in an organic light-emitting display device include a pixel circuit and a light-emitting element. A driving transistor in the pixel circuit can generate a driving current, and the light-emitting element emits light in response to the driving current.

[0005] However, the current circuit structure of the pixel circuit requires multiple groups of shift register circuits to control it, resulting in the display panel being not conducive to narrow bezel design. Summary of the Invention

[0006] In view of this, to solve the above problems, the present invention provides a display panel and its driving method, and the technical solutions are as follows:

[0007] A display panel, comprising: a pixel circuit and a light-emitting element;

[0008] The pixel circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor, a first reset transistor, a bias transistor, and a light-emitting control module;

[0009] The data writing transistor is electrically connected to the first end of the driving transistor;

[0010] The threshold compensation transistor is connected in series between the gate of the driving transistor and the second end of the driving transistor, and is used to detect and self-compensate for the deviation of the threshold voltage of the driving transistor;

[0011] The first reset transistor is electrically connected to the second end of the driving transistor;

[0012] The bias transistor is electrically connected to the second end of the driving transistor;

[0013] The light-emitting control module is respectively connected in series with the driving transistor and the light-emitting element, and is used to control whether the driving current flows through the light-emitting element;

[0014] The transistor type of the data writing transistor is the same as that of the first reset transistor.

[0015] A display panel, comprising: a pixel circuit and a light-emitting element;

[0016] The pixel circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor, a first reset transistor, a bias transistor, and a light-emitting control module;

[0017] The data writing transistor is electrically connected to a first end of the driving transistor;

[0018] The threshold compensation transistor is connected in series between the gate of the driving transistor and a second end of the driving transistor, and is used to detect and self-compensate for a deviation of the threshold voltage of the driving transistor;

[0019] The first reset transistor is electrically connected to the gate of the driving transistor;

[0020] The bias transistor is electrically connected to a second end of the driving transistor;

[0021] The light-emitting control module is respectively connected in series with the driving transistor and the light-emitting element, and is used to control whether a driving current flows through the light-emitting element;

[0022] The transistor type of the first reset transistor is the same as the transistor type of the bias transistor.

[0023] A driving method for a display panel, applicable to the display panel described above;

[0024] The working process of the pixel circuit includes a first biasing stage, a reset stage, a data writing stage, and a light-emitting stage;

[0025] In the first biasing stage, the bias transistor is turned on to provide a bias voltage to a second end of the driving transistor;

[0026] In the reset stage, the first reset transistor and the threshold compensation transistor are turned on to provide a first reference voltage to the gate of the driving transistor;

[0027] In the data writing stage, the data writing transistor and the threshold compensation transistor are turned on to provide a data signal to the gate of the driving transistor;

[0028] In the light-emitting stage, the light-emitting control module is turned on to control a driving current to flow through the light-emitting element.

[0029] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0030] In the pixel circuit of the display panel provided by the present invention, the bias transistor is used to bias the second end of the driving transistor to solve the problem of threshold drift of the driving transistor. The gate of the driving transistor is reset through the first reset transistor. That is to say, at this time, the bias transistor in the pixel circuit only needs to receive a signal that can bias the second end of the driving transistor. Obviously, the signal for biasing the second end of the driving transistor can be a fixed signal. Then, there is no need to set up an independent shift register circuit to control the signal. Further, since the transistor type of the data writing transistor in the pixel circuit is the same as that of the first reset transistor, obviously, a group of shift register circuits can be used to control the data writing transistor and the first reset transistor simultaneously, thereby reducing the number of shift register circuits, achieving the narrow bezel design of the display panel, and ensuring the performance of the driving transistor, and further ensuring the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to the provided drawings.

[0032] Figure 1 It is a schematic structural diagram of a pixel circuit in the prior art;

[0033] Figure 2 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0034] Figure 3 It is a schematic structural diagram of a pixel provided by an embodiment of the present invention;

[0035] Figure 4 It is a schematic structural diagram of another pixel provided by an embodiment of the present invention;

[0036] Figure 5 It is a schematic structural diagram of yet another pixel provided by an embodiment of the present invention;

[0037] Figure 6 It is a schematic structural diagram of yet another pixel provided by an embodiment of the present invention;

[0038] Figure 7 It is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0039] Figure 8 It is a schematic timing diagram provided by an embodiment of the present invention;

[0040] Figure 9 Another timing diagram provided by an embodiment of the present invention;

[0041] Figure 10 Another structural diagram of a pixel provided by an embodiment of the present invention;

[0042] Figure 11 A flowchart of a driving method for a display panel provided by an embodiment of the present invention;

[0043] Figure 12 A flowchart of another driving method for a display panel provided by an embodiment of the present invention;

[0044] Figure 13 A structural diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0045] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0046] Based on the content recorded in the background art, refer to Figure 1 , Figure 1 FIG. Figure 1 is a structural diagram of a pixel circuit in the prior art. If the driving transistor T3 is in the same bias state for a long time, its threshold is likely to drift, which affects the generated driving current and further affects the light-emitting effect of the display panel. To solve this technical problem, in the prior art, by controlling

[0047] the transistor T5 in

[0048] receives different signals in different working stages of the pixel circuit, so as to control the driving transistor T3, and further weaken the problem of threshold drift of the driving transistor T3, thereby improving the display effect of the display panel.

[0049] To make the above objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] Refer to Figure 2 , Figure 2 which is a schematic structural diagram of a display panel provided by an embodiment of the present invention. The display panel includes a plurality of pixels 11. To achieve full-color display of the display panel, optionally, the plurality of pixels 11 may include pixels for emitting green light, pixels for emitting blue light, and pixels for emitting red light.

[0051] Refer to Figure 3 , Figure 3 which is a schematic structural diagram of a pixel provided by an embodiment of the present invention. The pixel includes: a light-emitting element Q, and a pixel circuit 12 electrically connected to the light-emitting element Q. The pixel circuit 12 includes a driving transistor T3, a data writing transistor T2, a threshold compensation transistor T4, a first reset transistor T8, a bias transistor T5, and a light-emitting control module 13.

[0052] As Figure 3 shown, the data writing transistor T2 is electrically connected to the first end of the driving transistor T3.

[0053] The threshold compensation transistor T4 is connected in series between the gate of the driving transistor T3 and the second end of the driving transistor T3, and is used to detect and self-compensate the deviation of the threshold voltage of the driving transistor T3.

[0054] The first reset transistor T8 is electrically connected to the second end of the driving transistor T3.

[0055] The bias transistor T5 is electrically connected to the second end of the driving transistor T3.

[0056] The light-emitting control module 13 is connected in series with the driving transistor T3 and the light-emitting element Q respectively, and is used to control whether the driving current flows through the light-emitting element Q.

[0057] The transistor type of the data writing transistor T2 is the same as that of the first reset transistor T8.

[0058] Specifically, in the embodiment of the present invention, the data writing transistor T2 writes a data signal V data to the driving transistor T3, and the driving transistor T3 generates a driving current according to the data signal V data , and the light-emitting control module 13 controls whether the driving current flows through the light-emitting element Q, thereby controlling the display state of the light-emitting element Q.

[0059] AsFigure 3 As shown, in the pixel circuit 12, the bias transistor T5 is used to bias the second end of the driving transistor T3 to solve the problem of threshold drift of the driving transistor T3. The gate of the driving transistor T3 is reset by the first reset transistor T8. That is to say, at this time, the bias transistor T5 in the pixel circuit 12 only needs to receive a signal that can bias the second end of the driving transistor T3. The signal for biasing the second end of the driving transistor T3 can be a fixed signal. Then, there is no need to set up an independent shift register circuit to provide this bias signal to the bias transistor T5. It should be noted that in the embodiment of the present invention, the fixed signal is taken as the high-level signal DVH existing in the display panel as an example for illustration, and this high-level signal is a signal with a constant voltage.

[0060] Furthermore, the transistor type of the data writing transistor T2 in the pixel circuit 12 is the same as that of the first reset transistor T8. For example, if both the data writing transistor T2 and the first reset transistor T8 are P-type transistors, then the enable level for controlling the conduction of the data writing transistor T2 and the enable level for controlling the conduction of the first reset transistor T8 are both low levels. Or, if both the data writing transistor T2 and the first reset transistor T8 are N-type transistors, then the enable level for controlling the conduction of the data writing transistor T2 and the enable level for controlling the conduction of the first reset transistor T8 are both high levels. The first reset transistor T8 and the data writing transistor T2 in the pixel circuit 12 are turned on in a time-sharing manner. The signals provided by two adjacent stages of shift registers in the same group of shift register circuits can be used to control the first reset transistor T8 and the data writing transistor T2 respectively. Obviously, the control of the data writing transistor T2 and the first reset transistor T8 can be achieved simultaneously through a group of shift register circuits, thereby reducing the number of shift register circuits, realizing the narrow bezel design of the display panel, and ensuring the performance of the driving transistor T3, and further ensuring the display effect of the display panel.

[0061] Figure 4 Another structural schematic diagram of a pixel provided by an embodiment of the present invention is shown in Figure 4 as shown

[0062] The gate of the data writing transistor T2 is electrically connected to the first scan signal terminal SC_P(n); the gate of the first reset transistor T8 is electrically connected to the second scan signal terminal SC_P(n - 1).

[0063] For pixel circuits 12 located in adjacent rows, the signal of the second scan signal terminal SC_P(n - 1) electrically connected to the gate of the first reset transistor T8 of the pixel circuit 12 located in the current row (e.g., the nth row) is the same as the signal of the first scan signal terminal SC_P(n - 1) electrically connected to the gate of the data writing transistor T2 of the pixel circuit 12 located in the previous row (e.g., the (n - 1)th row).

[0064] Specifically, in the embodiment of the present invention, the gate of the data writing transistor T2 is electrically connected to the first scan signal terminal SC_P(n), and the first scan signal terminal SC_P(n) is used to output a first control signal for controlling the data writing transistor T2. The first control signal is a pulse signal, and the effective pulse of the first control signal controls the data writing transistor T2 to be in an on state to write the data signal V data to the first end (the second node N2) of the driving transistor T3; the ineffective pulse of the first control signal controls the data writing transistor T2 to be in an off state, that is, under the control of the first control signal, the data writing transistor T2 provides the data signal V data to the first end of the driving transistor T3.

[0065] It should be noted that the data writing transistor T2 cooperates with the threshold compensation transistor T4 to write the data signal V data to the gate of the driving transistor T3. At this time, both the data writing transistor T2 and the threshold compensation transistor T4 are in an on state.

[0066] The gate of the first reset transistor T8 is electrically connected to the second scan signal terminal SC_P(n - 1), and the second scan signal terminal SC_P(n - 1) is used to output a second control signal for controlling the first reset transistor T8. The second control signal is a pulse signal, and the effective pulse of the second control signal controls the first reset transistor T8 to be in an on state to provide a reference voltage to the second end of the driving transistor T3; the ineffective pulse of the second control signal controls the first reset transistor T8 to be in an off state.

[0067] It should be noted that the first reset transistor T8 cooperates with the threshold compensation transistor T4 to reset the gate of the driving transistor T3. At this time, both the first reset transistor T8 and the threshold compensation transistor T4 are in an on state.

[0068] The display panel includes a shift register circuit. A shift register circuit includes multiple stages of shift registers arranged in cascade. Each stage of the shift register is correspondingly arranged with a row of pixel circuits. For example, the nth stage of the shift register provides a control signal for the nth row of pixel circuits. The signal provided by the second scan signal terminal SC_P(n - 1) electrically connected to the gate of the first reset transistor T8 in the pixel circuit 12 can be provided by the (n - 1)th stage of the cascade shift register, that is, borrowing the control signal provided by the shift register corresponding to the (n - 1)th row of pixel circuits. The signal provided by the first scan signal terminal SC_P(n) electrically connected to the gate of the data writing transistor T2 can be provided by the nth stage of the cascade shift register. And the transistor type of the data writing transistor T2 in the pixel circuit 12 is the same as that of the first reset transistor T8. The signal provided by the second scan signal terminal SC_P(n - 1) electrically connected to the gate of the first reset transistor T8 in the nth row of pixel circuits, and the signal provided by the first scan signal terminal SC_P(n - 1) electrically connected to the gate of the data writing transistor T2 in the (n - 1)th row of pixel circuits can be provided by the same stage of the shift register (such as the (n - 1)th stage). That is to say, the data writing transistor T2 and the first reset transistor T8 in the pixel circuit can be provided with control signals by the same shift register circuit. That is to say, the display panel provided by the embodiment of the present invention reduces the number of shift register circuits in the border area of the display panel by improving the pixel circuit 12, so as to achieve the narrow border design of the display panel.

[0069] Continue to refer to Figure 3 , the gate of the bias transistor T5 is electrically connected to the third scan signal terminal SC_P1; the pixel circuit 12 further includes a second reset transistor T7. The first end of the second reset transistor T7 is electrically connected to the second reference voltage terminal Vref2. The second end of the second reset transistor T7 is electrically connected to the light-emitting element Q, and the two are electrically connected at the fourth node N4. The gate of the second reset transistor T7 is electrically connected to the fourth scan signal terminal SC_P2. The signals provided by the third scan signal terminal SC_P1 and the fourth scan signal terminal SC_P2 connected to the same pixel circuit 12 are the same. For example, the same scan signal line can be used to provide signals to the third scan signal terminal SC_P1 and the fourth scan signal terminal SC_P2 respectively.

[0070] Specifically, in the embodiment of the present invention, the gate of the bias transistor T5 is electrically connected to the third scan signal terminal SC_P1, and the gate of the second reset transistor T7 is electrically connected to the fourth scan signal terminal SC_P2. The third scan signal terminal SC_P1 for outputting a signal to control the bias transistor T5 and the fourth scan signal terminal SC_P2 for outputting a signal to control the second reset transistor T7 are both third control signals. The third control signal is a pulse signal. The effective pulse of the third control signal controls the bias transistor T5 to be in an on state to bias the second terminal of the driving transistor T3, and controls the second reset transistor T7 to be in an on state to reset the anode of the light-emitting element Q. The ineffective pulse of the third control signal controls the bias transistor T5 and the second reset transistor T7 to be in an off state.

[0071] In the embodiment of the present invention, the bias transistor T5 and the second reset transistor T7 use the same signal to control whether they are in an on state or an off state. The same stage of the shift register in the same shift register circuit can be used to provide control signals for the bias transistor T5 and the second reset transistor T7, thereby reducing the number of shift register circuits configured for each transistor.

[0072] Figure 5 Another structural schematic diagram of a pixel provided by the embodiment of the present invention is shown in Figure 5 As shown, the gate of the bias transistor T5 is electrically connected to the third scan signal terminal SC_P1. The pixel circuit 12 further includes a second reset transistor T7. The first terminal of the second reset transistor T7 is electrically connected to the second reference voltage terminal Vref2. The second terminal of the second reset transistor T7 is electrically connected to the light-emitting element Q. The gate of the second reset transistor T7 is electrically connected to the fourth scan signal terminal SC_P2.

[0073] For the pixel circuits in two adjacent groups, the signal of the third scan signal terminal SC_P1 to which the gate of the bias transistor T5 of the pixel circuit 12 in the current group is electrically connected is the same as the signal of the fourth scan signal terminal SC_P2 to which the gate of the second reset transistor T7 of the pixel circuit 12 in the previous group is electrically connected. Herein, one group includes pixel circuits 12 in two adjacent rows.

[0074] Specifically, in the embodiment of the present invention, since the display panel is provided with pixel arrays 11 arranged in an array, each pixel 11 includes a light-emitting element Q and a pixel circuit 12 electrically connected to the light-emitting element Q. In each driving cycle, the pixel circuits 12 in each row can be driven by a line-by-line scanning method; as Figure 5As shown, to reduce the number of signal lines in the display panel, the third scan signal terminal SC_P1 in the pixel circuit 12 of the nth pixel row can be electrically connected to the fourth scan signal terminal SC_P2 of the pixel circuit 12 of the (n - 1)th pixel row; when the pixel circuit 12 of the (n - 1)th pixel row resets the anode of the light-emitting element Q, the biasing process of the second terminal of the driving transistor T3 in the pixel circuit 12 of the nth pixel row is simultaneously achieved, so as to improve the biasing effect on the driving transistor T3, solve the threshold drift problem of the driving transistor T3 to the greatest extent, improve the stability of the driving current generated by the driving transistor T3, and further improve the display effect of the display panel.

[0075] The shift register circuit of the display panel can be set such that one-level shift registers are correspondingly arranged with two rows of pixel circuits. For example, one-level shift registers respectively provide signals for the third scan signal terminals SC_P1 of the bias transistors in two adjacent rows of pixel circuits. Two rows of pixel circuits corresponding to the same-level shift register form a group. For pixel circuits located in two adjacent groups, the signal of the third scan signal terminal electrically connected to the gate of the bias transistor T5 in the current group (such as the nth row and the (n + 1)th row) of pixel circuits is the same as the signal of the fourth scan signal terminal SC_P2 electrically connected to the gate of the second reset transistor T7 in the previous group (such as the (n - 2)th row and the (n - 1)th row) of pixel circuits, and is provided by the same-level shift register.

[0076] The active layer of the threshold compensation transistor T4 may include metal oxide.

[0077] Specifically, in the embodiments of the present invention, the threshold compensation transistor T4 may adopt a metal oxide transistor with a low leakage current level, that is, the active layer of the threshold compensation transistor T4 adopts metal oxide. First, the gate of the driving transistor T3 can be maintained at a stable potential during the light-emitting stage, avoiding the problem of brightness reduction during the light-emitting stage caused by the leakage current of the threshold compensation transistor T4.

[0078] Optionally, the active layer of the threshold compensation transistor T4 may adopt indium gallium zinc oxide (Indium Gallium Zinc Oxide, abbreviated as IGZO).

[0079] Among them, IGZO is composed of In 2 O 3 、Ga 2 O 3 and ZnO, and the band gap is about 3.5 eV, which is an N-type semiconductor material; that is, in the embodiments of the present invention, the threshold compensation transistor T4 is taken as an N-type transistor for illustration.

[0080] Based on the characteristic of low leakage current of the threshold compensation transistor T4, the data writing transistor T2 and the first reset transistor T8 can be LTPS (Low Temperature Poly Silicon) transistors, and it will not affect the stability of the data signal V written by the data writing transistor T2 data to the gate of the driving transistor T3, nor will it affect the reset effect of the first reset transistor T8 on resetting the gate of the driving transistor T3, and the leakage current problem of the first reset transistor T8 will not affect the gate potential of the driving transistor T3.

[0081] In the embodiment of the present invention, the active layers of the transistors in the driving transistor T3, the data writing transistor T2, the bias transistor T5, the first reset transistor T8, the second reset transistor T7, and the light emitting control module 13 may include polycrystalline silicon materials.

[0082] As Figures 3 - 5 shown, the pixel circuit further includes a second reset transistor T7.

[0083] The gate of the driving transistor T3 is electrically connected to the first node N1, the first end of the driving transistor T3 is electrically connected to the second node N2, and the second end of the driving transistor T3 is electrically connected to the third node N3;

[0084] The gate of the data writing transistor T2 is electrically connected to the first scan signal terminal SC_P(n), the first end of the data writing transistor T2 is electrically connected to the data signal terminal Vdata, and the second end of the data writing transistor T2 is electrically connected to the second node N2.

[0085] The gate of the first reset transistor T8 is electrically connected to the second scan signal terminal SC_P(n - 1), the first end of the first reset transistor T8 is electrically connected to the first reference voltage terminal Vref1, and the second end of the first reset transistor T8 is electrically connected to the third node N3.

[0086] The gate of the bias transistor T5 is electrically connected to the third scan signal terminal SC_P1, the first end of the bias transistor T5 is electrically connected to the bias voltage terminal DVH, and the second end of the bias transistor T5 is electrically connected to the third node N3.

[0087] The gate of the threshold compensation transistor T4 is electrically connected to the fifth scan signal terminal SC_N(n), the first end of the threshold compensation transistor T4 is electrically connected to the third node N3, and the second end of the threshold compensation transistor T4 is electrically connected to the first node N1.

[0088] The gate of the second reset transistor T7 is electrically connected to the fourth scan signal terminal SC_P2, the first end of the second reset transistor T7 is electrically connected to the second reference voltage terminal Vref2, and the second end of the second reset transistor T7 is electrically connected to the fourth node N4.

[0089] The light-emitting control module 13 includes a first light-emitting control transistor T1 and a second light-emitting control transistor T6. The first light-emitting control transistor T1 is electrically connected to the second node N2. The first end of the second light-emitting control transistor T6 is electrically connected to the third node N3, the second end of the second light-emitting control transistor T6 is electrically connected to the fourth node N4, and the gates of the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are both electrically connected to the light-emitting control signal terminal EM.

[0090] The light-emitting element Q is electrically connected to the fourth node N4.

[0091] Specifically, in the embodiment of the present invention, the gate of the data writing transistor T2 is electrically connected to the first scan signal terminal SC_P(n), the first end of the data writing transistor T2 is electrically connected to the data signal terminal Vdata, and the second end of the data writing transistor T2 is electrically connected to the second node N2. The data signal terminal Vdata is used to output a data signal V data , and the first scan signal terminal SC_P(n) is used to output a first control signal for controlling the data writing transistor T2. The first control signal is a pulse signal, and the effective pulse of the first control signal controls the data writing transistor T2 to be in an on state to write the data signal V data into the gate of the driving transistor T3; the invalid pulse of the first control signal controls the data writing transistor T2 to be in an off state; therefore, under the control of the first control signal, the data writing transistor T2 selectively writes the data signal V required by the pixel data .

[0092] The gate of the first reset transistor T8 is electrically connected to the second scan signal terminal SC_P(n - 1), the first end of the first reset transistor T8 is electrically connected to the first reference voltage terminal Vref1, the second end of the first reset transistor is electrically connected to the third node N3. The first reference voltage terminal Vref1 is used to output a first reset signal for resetting the gate of the driving transistor T3, and the second scan signal terminal SC_P(n - 1) is used to output a second control signal for controlling the first reset transistor T8. The second control signal is a pulse signal, and the effective pulse of the second control signal controls the first reset transistor T8 to be in an on state to reset the gate of the driving transistor T3; the invalid pulse of the second control signal controls the first reset transistor T8 to be in an off state.

[0093] The gate of the bias transistor T5 is electrically connected to the third scan signal terminal SC_P1. The first end of the bias transistor T5 is electrically connected to the bias voltage terminal DVH. The second end of the bias transistor T5 is electrically connected to the third node N3. The bias voltage terminal DVH is used to output a bias signal for biasing the second end of the driving transistor T3. The third scan signal terminal SC_P1 is used to output a third control signal for controlling the bias transistor T5. The third control signal is a pulse signal. The effective pulse of the third control signal controls the bias transistor T5 to be in an on state to bias the second end of the driving transistor T3. The ineffective pulse of the third control signal controls the bias transistor T5 to be in an off state.

[0094] The gate of the second reset transistor T7 is electrically connected to the fourth scan signal terminal SC_P2. The first end of the second reset transistor T7 is electrically connected to the second reference voltage terminal Vref2. The second end of the second reset transistor T7 is electrically connected to the fourth node N4. The second reference voltage terminal Vref2 is used to output a second reset signal for resetting the anode of the light-emitting element Q. The fourth scan signal terminal SC_P2 is used to output a fourth control signal for controlling the second reset transistor T7. The fourth control signal is a pulse signal. The effective pulse of the fourth control signal controls the second reset transistor T7 to be in an on state to reset the anode of the light-emitting element Q. The ineffective pulse of the fourth control signal controls the second reset transistor T7 to be in an off state.

[0095] The gate of the threshold compensation transistor T4 is electrically connected to the fifth scan signal terminal SC_N(n). The first end of the threshold compensation transistor T4 is electrically connected to the third node N3. The second end of the threshold compensation transistor T4 is electrically connected to the first node N1. The fifth scan signal terminal SC_N(n) is used to output a fifth control signal for controlling the threshold compensation transistor T4. The fifth control signal is a pulse signal. The effective pulse of the fifth control signal controls the threshold compensation transistor T4 to be in an on state to detect and self-compensate for the deviation of the threshold voltage of the driving transistor T3. The ineffective pulse of the fifth control signal controls the threshold compensation transistor T4 to be in an off state.

[0096] The first light-emitting control transistor T1 is electrically connected to the second node N2. The first end of the second light-emitting control transistor T6 is electrically connected to the third node N3, and the second end of the second light-emitting control transistor T6 is electrically connected to the fourth node N4. The gates of the first light-emitting control transistor T1 and the second light-emitting control transistor T2 are both electrically connected to the light-emitting control signal terminal EM. The light-emitting control signal terminal EM is used to output a light-emitting control signal for controlling the first light-emitting control transistor T1 and the second light-emitting control transistor T6. The light-emitting control signal is a pulse signal. The effective pulse of the light-emitting control signal controls the first light-emitting control transistor T1 and the second light-emitting control transistor T6 to be in the on state. At this time, the drive current flows through the light-emitting element Q, and the light-emitting element Q emits light in response to the drive current. The invalid pulse of the light-emitting control signal controls the first light-emitting control transistor T1 and the second light-emitting control transistor T6 to be in the off state.

[0097] It should be noted that the first end of the first light-emitting control transistor T1 is electrically connected to the first power supply voltage terminal PVDD, the second end of the first light-emitting control transistor T1 is electrically connected to the second node N2, the anode of the light-emitting element Q is electrically connected to the fourth node N4, and the cathode of the light-emitting element Q is electrically connected to the second power supply voltage terminal PVEE.

[0098] It should be noted that the data writing transistor T2 writes the data signal V data to the gate of the drive transistor T3. At this time, both the data writing transistor T2 and the threshold compensation transistor T4 are in the on state. When the first reset transistor T8 resets the gate of the drive transistor T3, both the first reset transistor T8 and the threshold compensation transistor T4 are in the on state.

[0099] It should be noted that the pixel circuit 12 further includes a capacitor C1. The first plate of the capacitor C1 is electrically connected to the first power supply voltage terminal PVDD, and the second plate of the capacitor C1 is electrically connected to the first node N1.

[0100] Figure 6 This is a schematic structural diagram of another pixel provided by an embodiment of the present invention. As Figure 6 shown, the control signals SC_P(n - 1) of the first reset transistor T8 and the control signals SC_P(n - 1) of the second reset transistor T7 are the same.

[0101] Specifically, in the embodiment of the present invention, the first reset transistor T8 is used to reset the gate of the drive transistor T3, and the second reset transistor T7 is used to reset the anode of the light-emitting element Q. In the embodiment of the present invention, if the control signals of the first reset transistor T8 and the second reset transistor T7 are the same, the same set of shift register circuits can be used to control the two, and the wiring quantity of the display panel can also be simplified.

[0102] That is to say, the gates of the first reset transistor T8 and the second reset transistor T7 are connected to the same scan signal terminal. In the embodiment of the present invention, the gates of the first reset transistor T8 and the second reset transistor T7 are commonly connected to the second scan signal terminal SC_P(n-1) as an example for illustration.

[0103] Figure 7 It is a schematic diagram of a display panel provided by an embodiment of the present invention. As Figure 7 shown, the display panel includes N rows of pixel circuits, such as the first row of pixel circuit P1 - the Nth row of pixel circuit PN shown in the figure. The display panel further includes a first scan circuit SC C, a second scan circuit SCN C, a third scan circuit SCP C, and a light emission control circuit Emit C. The first scan circuit SC C, the second scan circuit SCN C, the third scan circuit SCP C, and the light emission control circuit Emit C all include cascaded shift registers at multiple levels.

[0104] The first scan circuit SC C includes N + 1 levels of shift registers, namely SC 0 - SC N, and each level of shift register is correspondingly arranged with one row of pixel circuits.

[0105] The second scan circuit SCN C includes M levels of shift registers, namely SCN 1 - SCN M, and each level of shift register is correspondingly arranged with two rows of pixel circuits.

[0106] The third scan circuit SCP C includes M levels of shift registers, namely SCP 1 - SCP M, and each level of shift register is correspondingly arranged with two rows of pixel circuits.

[0107] The light emission control circuit Emit C includes M levels of shift registers, namely Emit 1 - Emit M, and each level of shift register is correspondingly arranged with two rows of pixel circuits

[0108] Wherein, M can be 1 / 2 of N.

[0109] The meaning that each level of shift register is correspondingly arranged with one row of pixel circuits is that each level of shift register only provides signals to the transistors with the same function in one row, rather than providing signals to the transistors with the same function in other rows. The meaning that each level of shift register is correspondingly arranged with two rows of pixel circuits is that each level of shift register provides the same signals to the transistors with the same function in two rows, rather than providing signals to the transistors with the same function in other rows.

[0110] Figure 7It is shown in the figure that the first scanning circuit SCC and the second scanning circuit SCNC are respectively bilaterally driven, that is, two sets of circuits are respectively arranged at opposite ends of the pixel circuit row, and the third scanning circuit SCPC and the light emission control circuit EmitC are respectively unidirectionally driven, that is, they are respectively arranged at one end of the pixel circuit row.

[0111] The control signal of the data writing transistor T2 and the control signal of the first reset transistor T8 are provided by the first scanning circuit SCC.

[0112] The control signal of the threshold compensation transistor T4 is provided by the second scanning circuit SCNC.

[0113] The control signal of the bias transistor T5 is provided by the third scanning circuit SCPC.

[0114] The light emission control module 13 includes a first light emission control transistor T1 and a second light emission control transistor T6, and the control signals of the first light emission control transistor T1 and the second light emission control transistor T6 are provided by the light emission control circuit EmitC.

[0115] Specifically, in the embodiment of the present invention, the first control signal for controlling the data writing transistor T2 and the second control signal for controlling the first reset transistor T8 are both provided by the first scanning circuit SCC; the third control signal for controlling the bias transistor T5 is provided by the second scanning circuit SCNC; the fifth control signal for controlling the threshold compensation transistor T4 is provided by the third scanning circuit SCPC; the light emission control signals for controlling the first light emission control transistor T1 and the second light emission control transistor T6 are provided by the light emission control circuit EmitC.

[0116] Optionally, the shift register included in the first scanning circuit is a first shift register, and one stage of the first shift register provides a control signal for the data writing transistor T2 of the pixel circuit 12 in the current row and a control signal for the first reset transistor T8 of the pixel circuit 12 in the next row. That is, while writing the data signal V data to the pixel circuit 12 in the current row, the gate of the driving transistor T3 in the pixel circuit 12 in the next row is reset to fully reset the gate of the driving transistor T3 in the pixel circuit 12 in the next row, improve the reset effect of the gate of the driving transistor T3 in the pixel circuit 12 in the next row, and further ensure the signal stability of writing the data signal V data to the gate of the driving transistor T3 in the pixel circuit 12 in the next row.

[0117] The shift register included in the second scanning circuit is a second shift register, and one stage of the second shift register provides a control signal for the threshold compensation transistor T4 of the pixel circuit in the current two rows.

[0118] The shift register included in the third scanning circuit is a third shift register, and one stage of the third shift register provides a control signal for the bias transistors T5 of the pixel circuits of the current two rows.

[0119] The shift register included in the light emission control circuit is a fourth shift register, and one stage of the fourth shift register provides a control signal for the first light emission control transistor T1 and the second light emission control transistor T6 of the pixel circuits of the current two rows.

[0120] Optionally, in another embodiment of the present invention, refer to Figure 8 , Figure 8 which is a timing diagram provided by an embodiment of the present invention.

[0121] The enable duration of the control signal provided by the first shift register is 1H.

[0122] The enable duration of the control signal provided by the second shift register is greater than or equal to 6H.

[0123] Wherein, H represents the unit clock duration.

[0124] Specifically, in the embodiment of the present invention, the enable duration of the control signal provided by the first shift register is 1H, that is, the effective duration for the data writing transistor T2 of the pixel circuit 12 of the current row and the first reset transistor T8 for the pixel circuit 12 located in the next row to be in the conducting state is 1H; the enable duration of the control signal provided by the second shift register is greater than or equal to 6H, that is, the effective duration for the threshold compensation transistor T4 to be in the conducting state is greater than or equal to 6H. While ensuring the reset of the gate of the driving transistor T3 and the writing of the data signal V data Under the condition of, to fully detect and self-compensate for the deviation of the threshold voltage of the driving transistor T3. Additionally, one stage of the second shift register can be set to correspond to two rows of pixel circuits.

[0125] Optionally, in another embodiment of the present invention, refer to Figure 9 , Figure 9 which is another timing diagram provided by an embodiment of the present invention.

[0126] The enable duration of the control signal provided by the first shift register is 1H.

[0127] The enable duration of the control signal provided by the third shift register is greater than or equal to 6H.

[0128] Wherein, H represents the unit clock duration.

[0129] Specifically, in the embodiment of the present invention, the enabling duration of the control signal provided by the first shift register is 1H, that is, the effective duration for the data writing transistor T2 of the pixel circuit 12 in the current row and the first reset transistor T8 for the pixel circuit 12 in the next row to be in the conducting state is 1H; the enabling duration of the control signal provided by the third shift register is greater than or equal to 6H, that is, the effective duration for the bias transistor T5 to be in the conducting state is greater than or equal to 6H, so as to sufficiently bias the second end of the driving transistor T5, improve the biasing effect on the driving transistor T5, solve the threshold drift problem of the driving transistor T5 to the greatest extent, improve the stability of the driving current generated by the driving transistor T5, and further improve the display effect of the display panel.

[0130] Optionally, in another embodiment of the present invention, referring to Figure 10 , Figure 10 is a schematic structural diagram of another pixel provided by the embodiment of the present invention.

[0131] The pixel 11 in the display panel includes a pixel circuit 12 and a light-emitting element Q.

[0132] The pixel circuit 12 includes a driving transistor T3, a data writing transistor T2, a threshold compensation transistor T4, a first reset transistor T8, a bias transistor T5, and a light-emitting control module 13.

[0133] The data writing transistor T2 is electrically connected to the first end of the driving transistor T3.

[0134] The threshold compensation transistor T4 is connected in series between the gate of the driving transistor T3 and the second end of the driving transistor T3, and is used to detect and self-compensate the deviation of the threshold voltage of the driving transistor T3.

[0135] The first reset transistor T8 is electrically connected to the gate of the driving transistor T3.

[0136] The bias transistor T5 is electrically connected to the second end of the driving transistor T3.

[0137] The light-emitting control module 13 is connected in series with the driving transistor T3 and the light-emitting element Q respectively, and is used to control whether the driving current flows through the light-emitting element Q.

[0138] The transistor type of the first reset transistor T8 is the same as that of the bias transistor T5.

[0139] Specifically, in the embodiment of the present invention, the first reset transistor T8 is electrically connected to the gate of the driving transistor T3. Since the transistor type of the first reset transistor T8 is the same as that of the bias transistor T5, the first reset transistor T8 and the bias transistor T5 can be controlled simultaneously by the same control signal, that is, the control signal of the first reset transistor T8 is the same as the control signal of the bias transistor T5. Then, while resetting the gate of the driving transistor T3, the second end of the driving transistor T3 is also biased.

[0140] That is to say, in the embodiment of the present invention, the bias transistor T5 and the first reset transistor T8 are controlled to be in the on state or the off state through the same signal line, which can further reduce the number of signal lines in the display panel.

[0141] Such as Figure 10 shown, the control signal of the second reset transistor T7 can be the same as the control signals of the bias transistor T5 and the first reset transistor T8.

[0142] Optionally, based on the above embodiments of the present invention, in another embodiment of the present invention, a driving method for a display panel is further provided, which is applicable to the display panel provided in any of the above embodiments of the present invention. Refer to Figure 11 , Figure 11 which is a schematic flowchart of a driving method for a display panel provided in an embodiment of the present invention.

[0143] S101: The working process of the pixel circuit 12 includes a first biasing stage, a reset stage, a data writing stage, and a light emitting stage; in the first biasing stage, the bias transistor T5 is turned on to provide a bias voltage to the second end of the driving transistor T3.

[0144] S102: In the reset stage, the first reset transistor T8 and the threshold compensation transistor T4 are turned on to provide a first reference voltage to the gate of the driving transistor T3.

[0145] S103: In the data writing stage, the data writing transistor T2 and the threshold compensation transistor T4 are turned on to provide a data signal to the gate of the driving transistor T3.

[0146] S104: In the light emitting stage, the light emitting control module 13 is turned on to control a driving current to flow through the light emitting element Q.

[0147] Specifically, in the embodiment of the present invention, in the first biasing stage, the bias transistor is turned on to provide a bias voltage to the second end of the driving transistor T3 to solve the threshold drift problem of the driving transistor T3 and improve the data signal V in the subsequent data writing stage. dataThe stability of the signal written to the gate of driving transistor T3 is based on a stable data signal V data Together with the driving transistor T3 after bias processing, the required driving current can be obtained, that is, the accuracy of the driving current generated by the driving transistor T3 is improved.

[0148] During the data writing stage, the data signal V is written through the data writing transistor T2 data to the gate of the driving transistor T3. The driving transistor T3 generates a corresponding driving current based on the data signal V data Meanwhile, the threshold compensation transistor T4 is also turned on to detect and self-compensate for the deviation of the threshold voltage of the driving transistor T3. This is also to improve the performance of the driving transistor T3, ultimately improving the accuracy of the driving current generated by the driving transistor T3 to improve the display effect of the display panel.

[0149] During the light emitting stage, the light emitting control module 13 is turned on, and the driving current generated by the driving transistor T3 flows through the light emitting element Q. The light emitting element Q emits light in response to the driving current. Then, based on the relatively accurate driving current, the target required brightness can be achieved, thereby improving the display effect of the display panel.

[0150] Optionally, in another embodiment of the present invention, refer to Figure 12 , Figure 12 which is a schematic flowchart of another driving method for a display panel provided by an embodiment of the present invention.

[0151] The driving method further includes:

[0152] S105: The working process of the pixel circuit 12 further includes a second bias stage after the data writing stage and before the light emitting stage; during the second bias stage, the bias transistor T5 is turned on to provide a bias voltage to the second end of the driving transistor T3.

[0153] Specifically, in the embodiment of the present invention, after the data signal V data is written, and before the light emitting stage, the second end of the driving transistor T3 is biased again to improve the performance of the pixel circuit, so that the light emitting element Q can reach the target required brightness during the light emitting stage, thereby improving the display effect of the display panel in all aspects.

[0154] Optionally, in another embodiment of the present invention, as Figure 8 shown, the enable duration of the threshold compensation transistor T4 receiving the control signal is greater than or equal to 6H.

[0155] Wherein, H represents the unit clock duration.

[0156] Specifically, in the embodiment of the present invention, the enabling duration for the threshold compensation transistor T4 to receive the control signal is greater than or equal to 6H, that is, the effective duration for the threshold compensation transistor T4 to be in the conducting state is greater than or equal to 6H. While ensuring the reset of the gate of the driving transistor T3 and the writing of the data signal V data to fully detect and self-compensate for the deviation of the threshold voltage of the driving transistor.

[0157] Optionally, in another embodiment of the present invention, as Figure 9 shown, the enabling duration for the bias transistor T5 to receive the control signal is greater than or equal to 6H.

[0158] Wherein, H represents the unit clock duration.

[0159] Specifically, in the embodiment of the present invention, the enabling duration for the bias transistor T5 to receive the control signal is greater than or equal to 6H, that is, the effective duration for the bias transistor T5 to be in the conducting state is greater than or equal to 6H, so as to fully bias the second end of the driving transistor T3 in both the first bias stage and the second bias stage, improve the biasing effect on the driving transistor T3, solve the threshold drift problem of the driving transistor T3 to the greatest extent, improve the stability of the driving current generated by the driving transistor T3, and further improve the display effect of the display panel.

[0160] Optionally, based on all the above embodiments of the present invention, in another embodiment of the present invention, a display device is further provided. Refer to Figure 13 , Figure 13 which is a schematic structural diagram of a display device provided by an embodiment of the present invention.

[0161] The display device 100 includes any one of the display panels provided by the above embodiments.

[0162] Since the display device 100 provided by the embodiment of the present invention includes any one of the display panels provided by the above embodiments, the display device 100 has the same or corresponding technical effects as the display panel provided by the above embodiments.

[0163] The display device 100 may specifically be a mobile phone, a computer, and other electronic devices, etc.

[0164] The above has introduced in detail a display panel and its driving method provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

[0165] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the parts that are the same or similar among the embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0166] It should also be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements also includes the elements inherent in these processes, methods, articles or devices, or further includes the elements inherent in these processes, methods, articles or devices. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device that includes the said element.

[0167] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, it includes: a pixel circuit and a light-emitting element; the pixel circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor, a first reset transistor, a bias setting transistor, and a light-emitting control module; the data writing transistor is electrically connected to a first end of the driving transistor; the threshold compensation transistor is connected in series between the gate of the driving transistor and a second end of the driving transistor; the first reset transistor is electrically connected to the second end of the driving transistor; the bias setting transistor is electrically connected to the second end of the driving transistor; the light-emitting control module is respectively connected in series with the driving transistor and the light-emitting element.

2. The display panel according to claim 1, characterized in that, the transistor type of the data writing transistor is the same as that of the first reset transistor; the gate of the data writing transistor is electrically connected to a first scan signal terminal; the gate of the first reset transistor is electrically connected to a second scan signal terminal; for pixel circuits located in adjacent rows, the signal of the second scan signal terminal electrically connected to the gate of the first reset transistor of the pixel circuit in the current row is the same as the signal of the first scan signal terminal electrically connected to the gate of the data writing transistor of the pixel circuit in the previous row.

3. The display panel according to claim 1, characterized in that, the gate of the bias setting transistor is electrically connected to a third scan signal terminal; the pixel circuit further includes a second reset transistor, a first end of the second reset transistor is electrically connected to a second reference voltage terminal, a second end of the second reset transistor is electrically connected to the light-emitting element, and the gate of the second reset transistor is electrically connected to a fourth scan signal terminal; the signal provided by the third scan signal terminal connected to the same pixel circuit is the same as the signal provided by the fourth scan signal terminal.

4. The display panel according to claim 1, characterized in that, the gate of the bias setting transistor is electrically connected to a third scan signal terminal; the pixel circuit further includes a second reset transistor, a first end of the second reset transistor is electrically connected to a second reference voltage terminal, a second end of the second reset transistor is electrically connected to the light-emitting element, and the gate of the second reset transistor is electrically connected to a fourth scan signal terminal; for pixel circuits located in adjacent two groups, the signal of the third scan signal terminal electrically connected to the gate of the bias setting transistor of the pixel circuit in the current group is the same as the signal of the fourth scan signal terminal electrically connected to the gate of the second reset transistor of the pixel circuit in the previous group; wherein, one group includes adjacent two rows of pixel circuits.

5. The display panel according to claim 1, characterized in that, the pixel circuit further includes a second reset transistor; the gate of the driving transistor is electrically connected to a first node, a first end of the driving transistor is electrically connected to a second node, and a second end of the driving transistor is electrically connected to a third node; The gate of the data writing transistor is electrically connected to the first scan signal terminal, the first end of the data writing transistor is electrically connected to the data signal terminal, and the second end of the data writing transistor is electrically connected to the second node; The gate of the first reset transistor is electrically connected to the second scan signal terminal, the first end of the first reset transistor is electrically connected to the first reference voltage terminal, and the second end of the first reset transistor is electrically connected to the third node; The gate of the bias transistor is electrically connected to the third scan signal terminal, the first end of the bias transistor is electrically connected to the bias voltage terminal, and the second end of the bias transistor is electrically connected to the third node; The gate of the threshold compensation transistor is electrically connected to the fifth scan signal terminal, the first end of the threshold compensation transistor is electrically connected to the third node, and the second end of the threshold compensation transistor is electrically connected to the first node; The gate of the second reset transistor is electrically connected to the fourth scan signal terminal, the first end of the second reset transistor is electrically connected to the second reference voltage terminal, and the second end of the second reset transistor is electrically connected to the fourth node; The light emission control module includes a first light emission control transistor and a second light emission control transistor. The first light emission control transistor is electrically connected to the second node. The first end of the second light emission control transistor is electrically connected to the third node. The second end of the second light emission control transistor is electrically connected to the fourth node. The gates of the first light emission control transistor and the second light emission control transistor are both electrically connected to the light emission control signal terminal; The light emitting element is electrically connected to the fourth node.

6. The display panel according to claim 1, wherein, it further includes a first scan circuit, a second scan circuit, a third scan circuit and a light emission control circuit. The first scan circuit, the second scan circuit, the third scan circuit and the light emission control circuit all include cascaded shift registers; The control signals of the data writing transistor and the first reset transistor are provided by the first scan circuit; The control signal of the threshold compensation transistor is provided by the second scan circuit; The control signal of the bias transistor is provided by the third scan circuit; The light emission control module includes a first light emission control transistor and a second light emission control transistor. The control signals of the first light emission control transistor and the second light emission control transistor are provided by the light emission control circuit.

7. The display panel according to claim 6, wherein, The shift register included in the first scan circuit is a first shift register. One stage of the first shift register provides a control signal for the data writing transistor of the pixel circuit in the current row and provides a control signal for the first reset transistor of the pixel circuit in the next row; The shift register included in the second scan circuit is a second shift register. One stage of the second shift register provides a control signal for the threshold compensation transistors of the pixel circuits in the current two rows; The shift register included in the third scanning circuit is a third shift register, and one stage of the third shift register provides a control signal for the bias transistors of the pixel circuits of the current two rows. The shift register included in the light emission control circuit is a fourth shift register, and one stage of the fourth shift register provides a control signal for the first light emission control transistor and the second light emission control transistor of the pixel circuits of the current two rows.

8. The display panel according to claim 7, wherein, the enable duration of the control signal provided by the first shift register is 1H; the enable duration of the control signal provided by the second shift register is greater than or equal to 6H; wherein, H represents the unit clock duration.

9. The display panel according to claim 7, wherein, the enable duration of the control signal provided by the first shift register is 1H; the enable duration of the control signal provided by the third shift register is greater than or equal to 6H; wherein, H represents the unit clock duration.

10. A display panel, wherein, comprising: a pixel circuit and a light emitting element; the pixel circuit includes a driving transistor, a data writing transistor, a threshold compensation transistor, a first reset transistor, a bias transistor, and a light emission control module; the data writing transistor is electrically connected to the first end of the driving transistor; the threshold compensation transistor is connected in series between the gate of the driving transistor and the second end of the driving transistor; the first reset transistor is electrically connected to the second end of the driving transistor; the bias transistor is electrically connected to the driving transistor; the light emission control module is connected in series with the driving transistor and the light emitting element respectively; the transistor type of the data writing transistor is the same as that of the first reset transistor.

11. The display panel according to claim 10, wherein, the gate of the data writing transistor is electrically connected to the first scanning signal terminal; the gate of the first reset transistor is electrically connected to the second scanning signal terminal; for the pixel circuits located in adjacent rows, the signal of the second scanning signal terminal to which the gate of the first reset transistor of the pixel circuit in the current row is electrically connected is the same as the signal of the first scanning signal terminal to which the gate of the data writing transistor of the pixel circuit in the previous row is electrically connected.

12. The display panel according to claim 10, wherein, the gate of the bias transistor is electrically connected to the third scanning signal terminal; the pixel circuit further includes a second reset transistor, the first end of the second reset transistor is electrically connected to the second reference voltage terminal, the second end of the second reset transistor is electrically connected to the light emitting element, and the gate of the second reset transistor is electrically connected to the fourth scanning signal terminal; the signal provided by the third scanning signal terminal connected to the same pixel circuit is the same as the signal provided by the fourth scanning signal terminal.

13. The display panel according to claim 10, wherein, the gate of the bias transistor is electrically connected to the third scanning signal terminal; The pixel circuit further includes a second reset transistor. A first end of the second reset transistor is electrically connected to a second reference voltage terminal. A second end of the second reset transistor is electrically connected to the light-emitting element. A gate of the second reset transistor is electrically connected to a fourth scan signal terminal; For pixel circuits in two adjacent groups, a signal of the third scan signal terminal electrically connected to the gate of the bias transistor of the pixel circuit in the current group is the same as a signal of the fourth scan signal terminal electrically connected to the gate of the second reset transistor of the pixel circuit in the previous group; Wherein, one group includes two adjacent rows of pixel circuits.

14. The display panel according to claim 10, wherein, the pixel circuit further includes a second reset transistor; A gate of the driving transistor is electrically connected to a first node. A first end of the driving transistor is electrically connected to a second node. A second end of the driving transistor is electrically connected to a third node; A gate of the data writing transistor is electrically connected to a first scan signal terminal. A first end of the data writing transistor is electrically connected to a data signal terminal. A second end of the data writing transistor is electrically connected to the second node; A gate of the first reset transistor is electrically connected to a second scan signal terminal. A first end of the first reset transistor is electrically connected to a first reference voltage terminal. A second end of the first reset transistor is electrically connected to the third node; A gate of the bias transistor is electrically connected to a third scan signal terminal. A first end of the bias transistor is electrically connected to a bias voltage terminal. A second end of the bias transistor is electrically connected to the third node; A gate of the threshold compensation transistor is electrically connected to a fifth scan signal terminal. A first end of the threshold compensation transistor is electrically connected to the third node. A second end of the threshold compensation transistor is electrically connected to the first node; A gate of the second reset transistor is electrically connected to a fourth scan signal terminal. A first end of the second reset transistor is electrically connected to a second reference voltage terminal. A second end of the second reset transistor is electrically connected to a fourth node; The light-emitting control module includes a first light-emitting control transistor and a second light-emitting control transistor. The first light-emitting control transistor is electrically connected to the second node. A first end of the second light-emitting control transistor is electrically connected to the third node. A second end of the second light-emitting control transistor is electrically connected to the fourth node. Gates of the first light-emitting control transistor and the second light-emitting control transistor are both electrically connected to a light-emitting control signal terminal; The light-emitting element is electrically connected to the fourth node.

15. A driving method for a display panel, wherein, it is applicable to the display panel according to any one of claims 1-14; The working process of the pixel circuit includes a first bias stage, a reset stage, a data writing stage, and a light-emitting stage; In the first bias stage, the bias transistor is turned on to provide a bias voltage to the second end of the driving transistor; In the reset stage, the first reset transistor and the threshold compensation transistor are turned on to provide a first reference voltage to the gate of the driving transistor; In the data writing stage, the data writing transistor and the threshold compensation transistor are turned on to provide a data signal to the gate of the driving transistor; In the light emitting stage, the light emitting control module is turned on to control a driving current to flow through the light emitting element.

16. The driving method according to claim 15, wherein, the operation process of the pixel circuit further includes a second biasing stage after the data writing stage and before the light emitting stage; in the second biasing stage, the biasing transistor is turned on to provide a biasing voltage to the second terminal of the driving transistor.

17. The driving method according to claim 15, wherein, the enabling duration of the control signal received by the biasing transistor is greater than or equal to 6H; wherein, H represents a unit clock duration.

18. The driving method according to claim 15, wherein, the enabling duration of the control signal received by the threshold compensation transistor is greater than or equal to 6H; wherein, H represents a unit clock duration.

19. A display device, wherein, it includes any one of the display panels described in claims 1-14.

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