Pixel circuit, driving method thereof and display panel

Abstract

The embodiment of the invention provides a pixel circuit, a driving method thereof and a display panel. In the pixel circuit, a first electrode of a driving transistor is electrically connected with a first node, a grid electrode is electrically connected with a second node, and a second electrode is electrically connected with a third node. The power voltage write-in module is electrically connected with a power signal line and a first node, the threshold compensation module is electrically connected with the first node and a second node, the data write-in module is electrically connected with a data signal line and a third node, and the auxiliary threshold compensation module is coupled with the first signal line and the third node. The working process of the pixel circuit comprises a threshold compensation stage and a subsequent data writing stage, the threshold compensation module is started in the threshold compensation stage and the data writing stage, and the data writing module is started in the data writing stage. The auxiliary threshold compensation module transmits a first voltage on the first signal line to the third node during or before a threshold compensation phase. The compensation effect of the threshold voltage of the driving transistor can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display panel. Background Art

[0002] In the field of display technologies, a pixel circuit is usually provided in a display panel to drive a light-emitting device to emit light. Among them, the threshold voltage of the driving transistor in the pixel circuit has an important impact on the light-emitting effect of the light-emitting device.

[0003] In order to eliminate the influence of the threshold voltage of the driving transistor on the display effect, usually during the operation of the pixel circuit, the threshold voltage of the driving transistor is compensated to the gate of the driving transistor. However, in the prior art, the compensation time for the threshold voltage of the driving transistor is short, which easily leads to incomplete compensation of the threshold voltage of the driving transistor, and the improvement effect on the influence of the threshold voltage of the driving transistor on the display quality is limited. Therefore, a solution is urgently needed. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a pixel circuit, a driving method thereof, and a display panel to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a pixel circuit applied to a display panel. The pixel circuit includes: A driving transistor for generating a light-emitting driving current. The first pole of the driving transistor is electrically connected to a first node, the gate is electrically connected to a second node, and the second pole is electrically connected to a third node. The driving transistor is an N-type transistor; A power supply voltage writing module, the input end of which is electrically connected to a power supply signal line and the output end is electrically connected to the first node; A threshold compensation module, the input end of which is electrically connected to the first node and the output end is electrically connected to the second node; A data writing module, the input end of which is electrically connected to a data signal line and the output end is electrically connected to the third node; An auxiliary threshold compensation module, the input end of which is electrically connected to a first signal line and the output end is coupled to the third node. The auxiliary threshold compensation module is used to transmit a first voltage on the first signal line to the third node; The operation process of the pixel circuit includes a threshold compensation stage and a data writing stage after the threshold compensation stage; Among them, the threshold compensation module is turned on during the threshold compensation stage and the data writing stage, the data writing module is turned on during the data writing stage, and the auxiliary threshold compensation module transmits the first voltage to the third node during the threshold compensation stage or before the threshold compensation stage.

[0006] Second aspect, based on the same inventive concept, an embodiment of the present application provides another pixel circuit, which is applied to a display panel. The pixel circuit includes: A driving transistor for generating a light-emitting driving current. A first pole of the driving transistor is electrically connected to a first node, a gate is electrically connected to a second node, and a second pole is electrically connected to a third node. The driving transistor is an N-type transistor; A first transistor, a first pole of the first transistor is electrically connected to a power supply signal line, and a second pole is electrically connected to the first node; A second transistor, a first pole of the second transistor is electrically connected to the first node, and a second pole is electrically connected to the second node; A third transistor, a first pole of the third transistor is electrically connected to a data signal line, and a second pole is electrically connected to the third node; A fourth transistor, a first pole of the fourth transistor is electrically connected to a first signal line, and a second pole is coupled to the third node. The fourth transistor is configured to transmit a first voltage on the first signal line to the third node; The working process of the pixel circuit includes a threshold compensation stage and a data writing stage performed after the threshold compensation stage; Wherein, the second transistor is turned on in the threshold compensation stage and the data writing stage, the third transistor is turned on in the data writing stage, and the fourth transistor transmits the first voltage to the third node in the threshold compensation stage or before the threshold compensation stage.

[0007] Third aspect, based on the same inventive concept, an embodiment of the present application provides a driving method for a pixel circuit. The pixel circuit includes: A driving transistor for generating a light-emitting driving current. A first pole of the driving transistor is electrically connected to a first node, a gate is electrically connected to a second node, and a second pole is electrically connected to a third node. The driving transistor is an N-type transistor; A power supply voltage writing module, an input end of the power supply voltage writing module is electrically connected to a power supply signal line, and an output end is electrically connected to the first node; A threshold compensation module, an input end of the threshold compensation module is electrically connected to the first node, and an output end is electrically connected to the second node; A data writing module, an input end of the data writing module is electrically connected to a data signal line, and an output end is electrically connected to the third node; An auxiliary threshold compensation module, an input end of the auxiliary threshold compensation module is electrically connected to a first signal line, and an output end is coupled to the third node. The auxiliary threshold compensation module is configured to transmit a first voltage on the first signal line to the third node; The working process of the pixel circuit includes a threshold compensation stage and a data writing stage performed after the threshold compensation stage; The method includes: In the threshold compensation stage, the threshold compensation module is turned on; During the data writing stage, the threshold compensation module and the data writing module are turned on; During the threshold compensation stage, and / or before the threshold compensation stage, the auxiliary threshold compensation module is turned on.

[0008] In a fourth aspect, based on the same inventive concept, an embodiment of the present application provides a display panel, including the pixel circuit provided in the first aspect or the second aspect.

[0009] In the embodiment of the present application, the threshold compensation stage and the data writing stage can be carried out separately. Making the auxiliary threshold compensation module transmit the first voltage to the third node during the threshold compensation stage or before the threshold compensation stage is beneficial to making the first voltage transmit to the gate of the driving transistor through the driving transistor and the turned-on threshold compensation module during the threshold compensation stage, so as to compensate the threshold voltage of the driving transistor to the gate of the driving transistor.

[0010] In this way, the threshold voltage compensation duration of the driving transistor is no longer limited by the duration of writing the data voltage Vdata, which is beneficial to making the threshold voltage of the driving transistor be completely compensated during the operation of the pixel circuit, thereby being beneficial to largely eliminating the influence of the threshold voltage of the driving transistor on the light-emitting driving current, and further being beneficial to improving the brightness uniformity of different light-emitting devices. Description of the Drawings

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0012] Figure 1 It is a schematic diagram of a pixel circuit in the related art; Figure 2 It is Figure 1 A timing diagram of the pixel circuit shown; Figure 3 It is a schematic diagram of a display panel provided by an embodiment of the present application; Figure 4 It is a schematic diagram of a pixel circuit provided by an embodiment of the present application; Figure 5 It is Figure 4 A schematic diagram of the pixel circuit shown; Figure 6 It is Figure 5 A timing diagram of the pixel circuit shown; Figure 7 It is Figure 5 Another timing diagram of the pixel circuit shown; Figure 8 Schematic diagram of another pixel circuit provided by an embodiment of the present application; Figure 9 For Figure 8 Schematic diagram of a pixel circuit shown; Figure 10 For Figure 9 Timing diagram of a pixel circuit shown; Figure 11 For Figure 9 Another timing diagram of a pixel circuit shown; Figure 12 Schematic diagram of another pixel circuit provided by an embodiment of the present application; Figure 13 For Figure 12 Schematic diagram of a pixel circuit shown; Figure 14 For Figure 13 Timing diagram of a pixel circuit shown; Figure 15 Schematic diagram of another pixel circuit provided by an embodiment of the present application; Figure 16 For Figure 15 Schematic diagram of a pixel circuit shown; Figure 17 For Figure 16 Timing diagram of a pixel circuit shown; Figure 18 For Figure 5 Another timing diagram of a pixel circuit shown; Figure 19 Schematic diagram of another pixel circuit provided by an embodiment of the present application; Figure 20 Flowchart of a driving method for a pixel circuit provided by an embodiment of the present application; Figure 21 Flowchart of another driving method for a pixel circuit provided by an embodiment of the present application. Detailed implementation

[0013] To better understand the technical solution of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0014] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0015] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0016] It should be understood that the term "and / or" used herein is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally indicates that the associated objects before and after are in an "or" relationship.

[0017] Without departing from the spirit or scope of the present application, various modifications and changes can be made in the present application, which are obvious to those skilled in the art. Therefore, the present application is intended to cover the modifications and changes of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0018] Figure 1 It is a schematic diagram of a pixel circuit in the related art. Figure 2 is Figure 1 a timing diagram of the pixel circuit shown.

[0019] In the related art, as Figure 1 shown, the pixel circuit 01' includes a driving transistor Td', a data writing transistor T1', a first reset transistor T2', a power supply voltage writing transistor T3', a light emission control transistor T4', a second reset transistor T5' and a storage capacitor C1'. The first pole of the driving transistor Td' is electrically connected to the first node N1', the gate is electrically connected to the second node N2', and the second pole is electrically connected to the third node N3'.

[0020] The driving transistor Td', the data writing transistor T1', the first reset transistor T2', the power supply voltage writing transistor T3', the light emission control transistor T4' and the second reset transistor T5' are all N-type transistors (turned on by high level and turned off by low level).

[0021] Among them, the first pole of the data writing transistor T1' receives the data voltage Vdata, the second pole is electrically connected to the third node N3, and the gate is electrically connected to the first scan line G1'. The first pole of the first reset transistor T2' is electrically connected to the first node N1', the second pole is electrically connected to the second node N2', and the gate is electrically connected to the second scan line G2'.

[0022] The first pole of the power supply voltage writing transistor T3' receives the first power supply voltage PVDD, the second pole is electrically connected to the first node N1', and the gate is electrically connected to the first light emission control signal line EM1'. The first pole of the light emission control transistor T4' is electrically connected to the third node N3', the second pole is electrically connected to the fourth node N4', and the gate is electrically connected to the second light emission control signal line EM2'. The fourth node N4' is electrically connected to the anode of the light emitting device 02', and the cathode of the light emitting device 02' receives the second power supply voltage PVEE.

[0023] The first pole of the second reset transistor T5' receives the anode reset voltage VREF, the second pole is electrically connected to the fourth node N4', and the gate is electrically connected to the third scan line G3'. One plate of the storage capacitor C1' is electrically connected to the second node N2', and the other plate is electrically connected to the fourth node N4'.

[0024] Combined Figure 2 As shown, the working process of the pixel circuit 01' includes a reset stage Z1', a data writing stage Z2' and a light emission stage Z3' that are carried out in sequence.

[0025] In the reset stage Z1', the first light emission control signal line EM1' and the second scan line G2' transmit high-level signals, the power supply voltage writing transistor T3' and the first reset transistor T2' are turned on, and the first power supply voltage PVDD is transmitted to the second node N2' through the power supply voltage writing transistor T3' and the first reset transistor T2' to complete the reset of the gate of the driving transistor Td'. At the same time, the third scan line G3' transmits a high-level signal, the second reset transistor T5' is turned on, and the anode reset voltage VREF is transmitted to the fourth node N4' through the second reset transistor T5' to reset the anode of the light emitting device 02'.

[0026] In the data writing stage Z2', the first scan line G1' and the second scan line G2' transmit high-level signals, the data writing transistor T1' and the first reset transistor T2' are turned on, and the data voltage Vdata can be transmitted to the second node N2' through the data writing transistor T1', the driving transistor Td' and the first reset transistor T2'. At the same time, the threshold voltage Vth of the driving transistor Td' is compensated to the second node N2'. That is, the data voltage Vdata and the threshold voltage Vth of the driving transistor Td' can be transmitted to the gate of the driving transistor Td'.

[0027] At the same time, the third scan line G3' transmits a high-level signal, the second reset transistor T5' remains turned on, and the anode reset voltage VREF is transmitted to the fourth node N4' through the second reset transistor T5' to continuously reset the anode of the light emitting device 02'.

[0028] In the light-emitting stage Z3', both the first light-emitting control signal line EM1' and the second light-emitting control signal line EM2' transmit high-level signals, turning on the power supply voltage writing transistor T3' and the light-emitting control transistor T4'. The driving transistor Td' generates a light-emitting current and transmits it to the light-emitting device 02', driving the light-emitting device 02' to emit light.

[0029] The inventors of the present application have found through research that in the related art, from the working process of the pixel circuit 01', when compensating the threshold voltage Vth of the driving transistor Td' to its gate, the compensation duration is limited by the duration of writing the data voltage Vdata. This results in a short compensation duration for the threshold voltage Vth of the driving transistor Td', which is less than the scanning duration of one row of pixels. As a result, the threshold voltage Vth of the driving transistor Td' is not fully compensated, and the threshold voltage Vth of the driving transistor Td' affects the magnitude of the light-emitting driving current. Since the threshold voltages of different driving transistors Td' are often different, the luminance uniformity of the light-emitting devices 02' driven by different pixel circuits 01' is poor.

[0030] Especially when the mobility of the driving transistor Td' is low, the compensation effect of the threshold voltage Vth of the driving transistor Td' is very poor, and the impact on the luminance uniformity of the light-emitting device is particularly serious.

[0031] In view of this, the inventors of the present application have conducted in-depth research and provided a solution to solve the problems existing in the related art.

[0032] Figure 3 It is a schematic diagram of a display panel provided by an embodiment of the present application. Figure 4 It is a schematic diagram of a pixel circuit provided by an embodiment of the present application.

[0033] An embodiment of the present application provides a pixel circuit 01, which is applied to a display panel 10. As Figure 3 shown, the display panel 10 further includes a light-emitting device 02. The pixel circuit 01 is electrically connected to the light-emitting device 02 to drive the light-emitting device 02 to emit light.

[0034] As Figure 4 shown, the pixel circuit 01 includes a driving transistor Td, a power supply voltage writing module 11, a threshold compensation module 12, a data writing module 13, and an auxiliary threshold compensation module 14. The driving transistor Td is used to generate a light-emitting driving current. The first pole of the driving transistor Td is electrically connected to the first node N1, the gate is electrically connected to the second node N2, and the second pole is electrically connected to the third node N3. The driving transistor Td can be an N-type transistor. Exemplarily, the driving transistor Td includes an oxide.

[0035] The input terminal of the power supply voltage writing module 11 is electrically connected to the power supply signal line DL1, and the output terminal is electrically connected to the first node N1. The power supply signal line DL1 is used to transmit the power supply voltage PVDD to the power supply voltage writing module 11.

[0036] The input terminal of the threshold compensation module 12 is electrically connected to the first node N1, and the output terminal is electrically connected to the second node N2. The input terminal of the data writing module 13 is electrically connected to the data signal line DL2, and the output terminal is electrically connected to the third node N3. The data signal line DL2 is used to transmit the data voltage Vdata to the data writing module 13.

[0037] The input terminal of the auxiliary threshold compensation module 14 is electrically connected to the first signal line XL1, and the output terminal is coupled to the third node N3. The auxiliary threshold compensation module 14 is used to transmit the first voltage V1 on the first signal line XL1 to the third node N3.

[0038] Combined Figure 5 and Figure 6 as shown, Figure 5 is Figure 4 a schematic diagram of a pixel circuit as shown, Figure 6 is Figure 5 a timing diagram of a pixel circuit as shown. The working process of the pixel circuit 01 includes a threshold compensation stage Z1 and a data writing stage Z2 after the threshold compensation stage Z1.

[0039] Among them, the threshold compensation module 12 is turned on in the threshold compensation stage Z1 and the data writing stage Z2. The data writing module 13 is turned on in the data writing stage Z2. The auxiliary threshold compensation module 13 transmits the first voltage V1 to the third node N3 in the threshold compensation stage Z1 or before the threshold compensation stage Z1.

[0040] In the embodiment of the present application, the threshold compensation stage Z1 and the data writing stage Z2 can be carried out separately. Let the auxiliary threshold compensation module 14 transmit the first voltage V1 to the third node N3 in the threshold compensation stage Z1 or before the threshold compensation stage Z1, which is beneficial to making the first voltage V1 transmit to the gate of the driving transistor Td through the driving transistor Td and the turned-on threshold compensation module 12 in the threshold compensation stage Z1, so as to compensate the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

[0041] In this way, the threshold voltage compensation duration of the driving transistor Td is no longer limited by the writing duration of the data voltage Vdata, which is beneficial to making the threshold voltage of the driving transistor Td fully compensated during the working process of the pixel circuit 01, thereby being beneficial to greatly eliminating the influence of the threshold voltage of the driving transistor Td on the light-emitting driving current, and further being beneficial to improving the brightness uniformity of different light-emitting devices.

[0042] Optionally, continue to refer to Figure 4 and Figure 5 , the pixel circuit 01 further includes a first capacitor C1 and a second capacitor C2. One plate of the first capacitor C1 is electrically connected to the second node N2, and the other plate is electrically connected to the third node N3. One plate of the second capacitor C2 is electrically connected to the power supply signal line DL1, and the other plate is electrically connected to the first node N1.

[0043] Based on this setting method, combined with Figure 6 shown, in the data writing stage Z2, the data writing module 13 and the threshold compensation module 12 are turned on. The first capacitor C1 and the second capacitor C2 are electrically connected through the threshold compensation module 12. The data voltage Vdata is transmitted to the third node N3 through the turned-on data writing module 13, and is transmitted to the second node N2 through the coupling action of the first capacitor C1 and the second capacitor C2, so as to realize writing the data voltage Vdata to the gate of the driving transistor Td.

[0044] Exemplarily, as Figure 5 shown, the power supply voltage writing module 11 includes a power supply voltage writing transistor T1. The first pole of the power supply voltage writing transistor T1 is electrically connected to the power supply signal line DL1, the second pole is electrically connected to the first node N1, and the gate is electrically connected to the first light emission control signal line EM1. The data writing module 13 includes a data writing transistor T2. The first pole of the data writing transistor T2 is electrically connected to the data signal line DL2, the second pole is electrically connected to the third node N3, and the gate is electrically connected to the first scan line G1.

[0045] The threshold compensation module 12 includes a threshold compensation transistor T3. The first pole of the threshold compensation transistor T3 is electrically connected to the first node N1, the second pole is electrically connected to the second node N2, and the gate is electrically connected to the second scan line G2. The auxiliary threshold compensation module 14 includes an auxiliary transistor T4. The first pole of the auxiliary transistor T4 is electrically connected to the first signal line XL1, the second pole is coupled to the third node N3, and the gate is electrically connected to the third scan line G3.

[0046] Exemplarily, as Figure 5 shown, the power supply voltage writing transistor T1, the data writing transistor T2, the threshold compensation transistor T3, and the auxiliary transistor T4 are all N-type transistors (turned on by high level and turned off by low level).

[0047] Combined with Figure 5 and Figure 6 shown, the working process of the pixel circuit 01 further includes a reset stage Z0, and the reset stage Z0 is carried out before the threshold compensation stage Z1.

[0048] Among them, the power supply voltage writing module 11 and the threshold compensation module 12 are turned on in the reset stage Z0.

[0049] Specifically, in combination with Figure 5 and Figure 6 As shown, in the reset stage Z0, the first light-emitting control signal line EM1 and the second scan line G2 transmit high-level signals, the power supply voltage writing transistor T1 and the threshold compensation transistor T3 are turned on, and the power supply voltage PVDD on the power supply voltage signal line DL1 can be transmitted to the first node N1 through the turned-on power supply voltage writing transistor T1 and transmitted to the second node N2 through the turned-on threshold compensation transistor T3, thereby completing the reset of the gate of the driving transistor Td.

[0050] Optionally, in the reset stage Z0, the period when the power supply voltage writing module 11 is turned on overlaps at least partially with the period when the threshold compensation module 12 is turned on. That is, the period when the first light-emitting control signal line EM1 transmits a high level overlaps at least partially with the period when the second scan line G2 transmits a high level.

[0051] Based on this setting method, it is beneficial to increase the accuracy of transmitting the power supply voltage PVDD to the second node N2, thereby being beneficial to improving the reliability of resetting the gate of the driving transistor Td.

[0052] In an embodiment of the present application, as Figure 4 shown, the pixel circuit 01 further includes a light-emitting control module 15. The input end of the light-emitting control module 15 is electrically connected to the third node N3, the output end is electrically connected to the fourth node N4, the fourth node N4 is electrically connected to the first pole of the light-emitting device 02, the light-emitting device 02 can be an organic light-emitting diode, and the first pole of the light-emitting device 02 can be its anode.

[0053] Exemplarily, as Figure 5 shown, the light-emitting control module 15 includes a light-emitting control transistor T5. The first pole of the light-emitting control transistor T5 is electrically connected to the third node N3, the second pole is electrically connected to the fourth node N4, and the gate is electrically connected to the second light-emitting control signal line EM2. The light-emitting control transistor T5 can be an N-type transistor (turned on by a high level and turned off by a low level).

[0054] The output end of the auxiliary threshold compensation module 14 is electrically connected to the fourth node N4. The auxiliary threshold compensation module 14 is turned on in the reset stage Z0 and / or the threshold compensation stage Z1. The first voltage V1 is also used to reset the first pole of the light-emitting device 02. That is, the first voltage V1 can also be used as the reset voltage for resetting the first pole of the light-emitting device 02. In at least one of the reset stage Z0 and the threshold compensation stage Z1, the first voltage V1 can be transmitted to the fourth node N4 through the turned-on auxiliary threshold compensation module 14 to complete the reset of the first pole of the light-emitting device 02.

[0055] Exemplarily, in combination with Figure 5 and Figure 6As shown, in the reset stage Z0 and the threshold compensation stage Z1, the third scan line G3 transmits a high-level signal, and the auxiliary transistor T4 is turned on in both the reset stage Z0 and the threshold compensation stage Z1. The first voltage V1 is transmitted to the fourth node N4 through the turned-on auxiliary transistor T4 to reset the first pole of the light-emitting device 02.

[0056] Among them, in the reset stage Z0 and the threshold compensation stage Z1, the on-time of the light-emitting control module 15 overlaps at least partially with the on-time of the auxiliary threshold compensation module 14.

[0057] In the embodiments of the present application, in the reset stage Z0 and the threshold compensation stage Z1, if the on-time of the light-emitting control module 15 is set to overlap at least partially with the on-time of the auxiliary threshold compensation module 14, then before and / or during the threshold compensation stage Z1, the first voltage V1 can be transmitted to the third node N3 through the turned-on auxiliary threshold compensation module 14 and the light-emitting control module 15, which is beneficial to transmit it to the second node N2 through the driving transistor Td and the threshold compensation module 12 during the threshold compensation stage Z1, and compensate the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

[0058] It should be noted that when the on-time of the light-emitting control module 15 overlaps with the on-time of the auxiliary threshold compensation module 14 in the reset stage Z0, in the reset stage Z0, the on-time of the light-emitting control module 15 and the on-time of the power supply voltage writing module 11 need to have no overlap to avoid abnormal light emission of the light-emitting device 02.

[0059] Exemplarily, in combination with Figure 5 and Figure 6 As shown, the on-time of the light-emitting control module 15 overlaps with the on-time of the auxiliary threshold compensation module 14 in the threshold compensation stage Z1 and does not overlap in the reset stage Z0. In this way, the first voltage V1 can be transmitted to the third node N3 through the auxiliary threshold compensation module 14 and the light-emitting control module 15 in the threshold compensation stage Z1, and then transmitted to the second node N2 through the driving transistor Td and the threshold compensation module 12 to compensate the threshold voltage of the driving transistor Td to the gate of the driving transistor Td. At the same time, in the reset stage Z0, the light-emitting control module 15 can remain in the off state, which is beneficial to reducing the driving complexity of the pixel circuit 01.

[0060] In an implementation manner of the embodiments of the present application, in combination with Figure 5 and Figure 7 As shown, Figure 7 is Figure 5 Another timing diagram of the pixel circuit shown. The auxiliary threshold compensation module 14 is turned on in the reset stage Z0, the threshold compensation stage Z1, and the data writing stage Z2, and the light-emitting control module 15 is turned off in the data writing stage Z2.

[0061] Thus, the first voltage V1 can be transmitted to the fourth node N4 during the reset phase Z0, the threshold compensation phase Z1, and the data writing phase Z2, which is beneficial to increasing the reset duration of the first voltage V1 on the first pole of the light-emitting device 02, and thus beneficial to improving the reset effect of the first voltage V1 on the first pole of the light-emitting device 02.

[0062] Meanwhile, by making the light-emitting control module 15 turn off during the data writing phase Z2, it is possible to avoid the data voltage Vdata being written into the fourth node N4, resulting in abnormal light emission of the light-emitting device 02.

[0063] For the convenience of understanding the technical solution of the present application, the working process of the pixel circuit 01 will be described below in conjunction with Figure 5 and Figure 7 . The working process of the pixel circuit 01 includes a reset phase Z0, a threshold compensation phase Z1, a data writing phase Z2, and a light-emitting phase Z3 that are sequentially performed.

[0064] During the reset phase Z0, the third scan line G3 transmits a high-level signal, the auxiliary transistor T4 is turned on, the first voltage V1 is transmitted to the fourth node N4 to reset the first pole of the light-emitting device 02, and the potential of the fourth node N4 is V1. The first light-emitting control signal line EM1 and the second scan line G2 transmit high-level signals, the power supply voltage writing transistor T1 and the threshold compensation transistor T3 are turned on, the power supply voltage PVDD is transmitted to the first node N1 and the second node N2 to reset the gate of the driving transistor Td, and the potentials of the first node N1 and the second node N2 are both PVDD.

[0065] During the threshold compensation phase Z1, the first light-emitting control signal line EM1 transmits a low-level signal, the power supply voltage writing transistor T1 is turned off, the third scan line G3, the second light-emitting control signal line EM2, and the second scan line G2 transmit high-level signals, the auxiliary transistor T4, the light-emitting control transistor T5, and the threshold compensation transistor T3 are turned on, and the potentials of the fourth node N4 and the third node N3 are V1. Since the first voltage V1 is usually much smaller than the power supply voltage PVDD, at this time, the driving transistor Td is turned on, and the first voltage V1 is written into the first node N1 and the second node N2 until the potentials of the first node N1 and the second node N2 are both V1 + Vth, and the driving transistor Td is turned off. Here, Vth is the threshold voltage of the driving transistor Td.

[0066] In the data writing stage Z2, both the first light emission control signal line EM1 and the second light emission control signal line EM2 transmit low-level signals, and the power supply voltage writing transistor T1 and the light emission control transistor T5 are turned off. The first scan line G1 and the second scan line G2 transmit high-level signals, the data writing transistor T2 and the threshold compensation transistor T3 are turned on, and the data voltage Vdata is transmitted to the third node N3 through the turned-on data writing transistor T2. The potential of the third node N3 changes from V1 to Vdata. Due to the coupling effect of the first capacitor C1 and the second capacitor C2, the potentials of the first node N1 and the second node N2 become V1 + Vth + (Vdata - V1) C2 / (C1 + C2). Here, C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2. At this time, the gate-source voltage difference Vgs of the driving transistor Td = the potential of the second node N2 - the potential of the third node N3 = (V1 - Vdata) C1 / (C1 + C2) + Vth.

[0067] Meanwhile, the third scan line G3 transmits a high-level signal, the auxiliary transistor T4 is turned on, and the potential of the fourth node N4 is V1, continuously resetting the first pole of the light emitting device 02.

[0068] In the light emission stage Z3, the first scan line G1, the second scan line G2, and the third scan line G3 all transmit low-level signals, the data writing transistor T2, the threshold compensation transistor T3, and the auxiliary transistor T4 are all turned off. The first light emission control signal line EM1 and the second light emission control signal line EM2 both transmit high-level signals, the power supply voltage writing transistor T1 and the light emission control transistor T5 are turned on, and the light emission driving current generated by the driving transistor Td is transmitted to the light emitting device 02 to drive the light emitting device 02 to emit light. At this time, the light emission driving current IO = K (Vgs - Vth)^2 = K ((V1 - Vdata) C1 / (C1 + C2))^2. Where K is a structural parameter, and Vgs is the gate-source voltage difference of the driving transistor Td.

[0069] From the working process of the pixel circuit 01, it can be seen that the threshold voltage Vth of the driving transistor Td no longer affects the magnitude of the light emission driving current generated by the driving transistor Td, which is beneficial to improving the brightness uniformity of different light emitting devices 02.

[0070] Figure 8 This is a schematic diagram of another pixel circuit provided by the embodiment of the present application, Figure 9 is Figure 8 a schematic diagram of the principle of the pixel circuit shown, Figure 10 is Figure 9 a timing diagram of the pixel circuit shown.

[0071] In one embodiment of the present application, as Figure 8 and Figure 9 shown, the pixel circuit 01 further includes a light emission control module 15. The input end of the light emission control module 15 is electrically connected to the third node N3, and the output end is electrically connected to the fourth node N4. The fourth node N4 is electrically connected to the first pole of the light emitting device 02. The light emitting device 02 can be an organic light emitting diode, and the first pole of the light emitting device 02 can be its anode.

[0072] Exemplarily, as Figure 9 shown, the light emission control module 15 includes a light emission control transistor T5. The first pole of the light emission control transistor T5 is electrically connected to the third node N3, the second pole is electrically connected to the fourth node N4, and the gate is electrically connected to the second light emission control signal line EM2. The light emission control transistor T5 can be an N-type transistor (turned on by high level and turned off by low level).

[0073] The output end of the auxiliary threshold compensation module 14 is electrically connected to the third node N3. The auxiliary threshold compensation module 14 is turned on in the reset stage Z0 and / or the threshold compensation stage Z1. The first voltage V1 is also used to reset the first pole of the light emitting device 02. That is, the first voltage V1 can also be used as the reset voltage for resetting the first pole of the light emitting device 02.

[0074] Combined with Figure 9 and Figure 10 shown, in the reset stage Z0 and the threshold compensation stage Z1, the on period of the light emission control module 15 overlaps at least partially with the on period of the auxiliary threshold compensation module 14, and the on period of the light emission control module 15 has no overlap with the on period of the power supply voltage writing module 11.

[0075] In the embodiments of the present application, in the reset stage Z0 and the threshold compensation stage Z1, if the on period of the light emission control module 15 is set to overlap at least partially with the on period of the auxiliary threshold compensation module 14, then in the threshold compensation stage Z1 and / or the reset stage Z0, the first voltage V1 can be transmitted to the fourth node N4 through the turned-on auxiliary threshold compensation module 14 and light emission control module 15 to reset the first pole of the light emitting device 02.

[0076] At the same time, the first voltage V1 can also be transmitted to the third node N3 through the auxiliary threshold compensation module 14 in the threshold compensation stage Z1 and / or the reset stage Z0, which is beneficial to transmitting to the second node N2 through the driving transistor Td and the threshold compensation module 12 in the threshold compensation stage Z1, and compensating the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

[0077] In addition, in the reset stage Z0 and the threshold compensation stage Z1, the period when the light emission control module 15 is turned on does not overlap with the period when the power supply voltage writing module 11 is turned on, which can prevent the light emission control module 15 and the power supply voltage writing module 11 from forming a path and causing abnormal light emission of the light emitting device 02.

[0078] Combined with Figure 9 and Figure 10 As shown, in an implementation manner of the embodiment of the present application, the reset stage Z0 includes a first sub-reset stage Z01 and a second sub-reset stage Z02, and the second sub-reset stage Z02 is performed after the first sub-reset stage Z01.

[0079] Among them, the light emission control module 15 is turned on in the first sub-reset stage Z01 and turned off in the second sub-reset stage Z02. The power supply voltage writing module 11 is turned off in the first sub-reset stage Z01 and turned on in the second sub-reset stage Z02. The threshold compensation module 13 is turned on in the second sub-reset stage Z02. The threshold compensation module 13 may be turned on or off in the first sub-reset stage Z01.

[0080] Exemplarily, combined with Figure 9 and Figure 10 As shown, in the first sub-reset stage Z01, the first light emission control signal line EM1 and the second scan line G2 transmit low-level signals, and the power supply voltage writing transistor T1 and the threshold compensation transistor T3 are turned off. The second light emission control signal line EM2 and the third scan line G3 transmit high-level signals, the light emission control transistor T5 and the auxiliary transistor T4 are turned on, and the first voltage V1 can be transmitted to the third node N3 through the turned-on auxiliary transistor T4 and transmitted to the fourth node N4 through the turned-on light emission control transistor T5, completing the reset of the first pole of the light emitting device 02.

[0081] In the second sub-reset stage Z02, the second light emission control signal line EM2 transmits a low-level signal, and the light emission control transistor T5 is turned off. The third scan line G3 transmits a high-level signal, the auxiliary transistor T4 is turned on, and the first voltage V1 is transmitted to the third node N3 through the auxiliary transistor T4. The first light emission control signal line EM1 and the second scan line G2 both transmit high-level signals, the power supply voltage writing transistor T1 and the threshold compensation transistor T3 are turned on, and the power supply voltage PVDD is transmitted to the first node N1 through the turned-on power supply voltage writing transistor T1 and transmitted to the second node N2 through the turned-on threshold compensation transistor T3 to reset the gate of the driving transistor Td.

[0082] Optionally, combined with Figure 9 and Figure 10 As shown, the auxiliary threshold compensation module 14 is turned on in both the reset stage Z0 and the threshold compensation stage Z1, and the light emission control module 15 is turned off in both the threshold compensation stage Z1 and the data writing stage Z2.

[0083] Based on this setting method, after the second light emission control signal line EM2 electrically connected to the light emission control module 15 transmits a high level during the first sub-reset stage Z01, it can transmit a low level during the second sub-reset stage Z02, the threshold compensation stage Z1, and the data writing stage Z2, which is beneficial to reducing power consumption.

[0084] At the same time, enabling the auxiliary threshold compensation module 14 to be turned on during the reset stage Z0 and the threshold compensation stage Z1 is beneficial to improving the accuracy of the transmission of the first voltage V1 to the third node N3, and further beneficial to improving the reliability of writing the first voltage V1 to the second node N2 during the threshold compensation stage Z1.

[0085] Of course, during the data writing stage Z2, the auxiliary threshold compensation module 14 is turned off to avoid affecting the writing of the data voltage Vdata to the third node N3.

[0086] Figure 11 For Figure 9 yet another timing diagram of the pixel circuit shown.

[0087] In yet another implementation manner of the embodiment of the present application, as shown in combination with Figure 9 and Figure 11 the reset stage Z0 includes a first sub-reset stage Z01 and a second sub-reset stage Z02, and the second sub-reset stage Z02 is carried out after the first sub-reset stage Z01.

[0088] Among them, the light emission control module 15 is turned off during the first sub-reset stage Z01 and turned on during the second sub-reset stage Z02. The power supply voltage writing module 11 is turned on during the first sub-reset stage Z01 and turned off during the second sub-reset stage Z02. The threshold compensation module 13 is turned on during the first sub-reset stage Z01. The threshold compensation module 13 can be turned on or off during the first sub-reset stage Z01 and the second sub-reset stage Z02.

[0089] Exemplarily, as shown in combination with Figure 9 and Figure 11 during the first sub-reset stage Z01, the second light emission control signal line EM2 transmits a low-level signal, and the light emission control transistor T5 is turned off. The third scan line G3 transmits a high-level signal, the auxiliary transistor T4 is turned on, and the first voltage V1 is transmitted to the third node N3 through the auxiliary transistor T4. The first light emission control signal line EM1 and the second scan line G2 both transmit high-level signals, the power supply voltage writing transistor T1 and the threshold compensation transistor T3 are turned on, and the power supply voltage PVDD is transmitted to the first node N1 through the turned-on power supply voltage writing transistor T1 and transmitted to the second node N2 through the turned-on threshold compensation transistor T3 to reset the gate of the driving transistor Td.

[0090] In the second sub-reset stage Z02, the first light-emitting control signal line EM1 transmits a low-level signal, and the power supply voltage writing transistor T1 is turned off. The second light-emitting control signal line EM2 and the third scanning line G3 transmit high-level signals, the light-emitting control transistor T5 and the auxiliary transistor T4 are turned on, and the first voltage V1 can be transmitted to the third node N3 through the turned-on auxiliary transistor T4 and then transmitted to the fourth node N4 through the turned-on light-emitting control transistor T5, completing the reset of the first pole of the light-emitting device 02.

[0091] Meanwhile, the second scanning line G2 transmits a high-level signal, the threshold compensation transistor T3 is turned on, the first voltage V1 is transmitted to the second node N2 through the turned-on driving transistor Td and the threshold compensation transistor T3, and the threshold voltage Vth of the driving transistor Td is compensated to the gate of the driving transistor Td, which is beneficial to further increasing the compensation duration of the threshold voltage of the driving transistor Td.

[0092] Optionally, as shown in Figure 9 and Figure 11 , the auxiliary threshold compensation module 14 is turned on in the reset stage Z0 and the threshold compensation stage Z1, the light-emitting control module 15 is turned on in the threshold compensation stage Z1, and is turned off in the data writing stage Z2.

[0093] Based on this setting method, in the threshold compensation stage Z1, the first voltage V1 can also be transmitted to the fourth node N4 through the turned-on auxiliary threshold compensation module 14 and the light-emitting control module 15, which is beneficial to increasing the reset duration of the first voltage V1 on the first pole of the light-emitting device 02, and thus beneficial to improving the reset effect of the first voltage V1 on the first pole of the light-emitting device 02.

[0094] Figure 12 It is a schematic diagram of another pixel circuit provided by an embodiment of the present application. Figure 13 It is Figure 12 a schematic diagram of the pixel circuit shown. Figure 14 It is Figure 13 a timing diagram of the pixel circuit shown.

[0095] In an embodiment of the present application, as shown in Figure 12 , the pixel circuit 01 further includes a light-emitting control module 15. The input end of the light-emitting control module 15 is electrically connected to the third node N3, the output end is electrically connected to the fourth node N4, the fourth node N4 is electrically connected to the first pole of the light-emitting device 02, the light-emitting device 02 can be an organic light-emitting diode, and the first pole of the light-emitting device 02 can be its anode.

[0096] Exemplarily, as shown in Figure 13As shown, the light-emitting control module 15 includes a light-emitting control transistor T5. The first pole of the light-emitting control transistor T5 is electrically connected to the third node N3, the second pole is electrically connected to the fourth node N4, and the gate is electrically connected to the second light-emitting control signal line EM2. The light-emitting control transistor T5 can be an N-type transistor (turned on by high level and turned off by low level).

[0097] The output terminal of the auxiliary threshold compensation module 14 is electrically connected to the third node N3. Combining Figure 14 As shown, the operation process of the pixel circuit 01 further includes an adjustment stage Z4, and the adjustment stage Z4 is carried out between the reset stage Z0 and the threshold compensation stage Z1.

[0098] Among them, the auxiliary threshold compensation module 14 is turned on in the adjustment stage Z4 and the threshold compensation stage Z1. The first voltage V1 can also be used to adjust the bias state of the driving transistor Td. That is, in the adjustment stage Z4, the first voltage V1 can also be used as an adjustment voltage for adjusting the bias state of the driving transistor Td.

[0099] Specifically, combining Figure 13 and Figure 14 As shown, in the adjustment stage Z4, the third scan line G3 transmits a high-level signal, the first scan line G1, the second scan line G2, the first light-emitting control signal line EM1, and the second light-emitting control signal line EM2 transmit low-level signals, the auxiliary transistor T4 is turned on, the power supply voltage write transistor T1, the data write transistor T2, the threshold compensation transistor T3, and the light-emitting control transistor T5 are turned off, and the first voltage V1 is transmitted to the third node N3 through the turned-on auxiliary transistor T4 to adjust the bias state of the driving transistor Td.

[0100] In the threshold compensation stage Z1, the third scan line G3 and the second scan line G2 transmit high-level signals, the auxiliary transistor T4 and the threshold compensation transistor T3 are turned on, the first voltage V1 is transmitted to the first node N1 through the driving transistor Td and transmitted to the second node N2 through the threshold compensation transistor T3 until the potential of the second node N2 is V1 + Vth, where Vth is the threshold voltage of the driving transistor Td, so as to compensate the threshold voltage Vth of the driving transistor Td to the gate of the driving transistor Td.

[0101] In the embodiment of the present application, the first voltage V1 can not only be used to adjust the bias state of the driving transistor Td, but also capture the threshold voltage of the driving transistor Td during the process of writing to the second node N2, which is beneficial to reducing the structural complexity of the pixel circuit 01.

[0102] Please continue to refer to Figure 12, in an embodiment of the present application, the pixel circuit 01 further includes a reset module 16. The input end of the reset module 16 is electrically connected to the reset signal line SL1, and the output end is electrically connected to the fourth node N4. The reset module 16 is configured to transmit the reset voltage VREF on the reset signal line SL1 to the fourth node N4 to reset the first pole of the light-emitting device 02.

[0103] Exemplarily, as Figure 13 shown, the reset module 16 includes a reset transistor T6. The first pole of the reset transistor T6 is electrically connected to the reset signal line SL1, the second pole is electrically connected to the fourth node N4, and the gate is electrically connected to the fourth scan line G4. The reset transistor T6 can be an N-type transistor (turned on by high level and turned off by low level).

[0104] Wherein, as combined with Figure 14 shown, the reset module 16 is turned on in the reset stage Z0, the adjustment stage Z4, the threshold compensation stage Z1, and the data writing stage Z2.

[0105] In this way, the reset voltage VREF can be transmitted to the fourth node N4 in the reset stage Z0, the adjustment stage Z4, the threshold compensation stage Z1, and the data writing stage Z2, which is beneficial to improving the reset effect of the reset voltage VREF on the first pole of the light-emitting device 02.

[0106] Optionally, as combined with Figure 13 and Figure 14 shown, the light emission control module 15 is turned off in the reset stage Z0, the adjustment stage Z4, the threshold compensation stage Z1, and the data writing stage Z2. In this way, it is beneficial to avoid abnormal light emission of the light-emitting device 02 in the non-light-emitting stage.

[0107] Optionally, as combined with Figure 13 and Figure 14 shown, the auxiliary threshold compensation module 14 is turned on in the reset stage Z0. That is to say, in addition to being turned on in the adjustment stage Z4 and the threshold compensation stage Z1, the auxiliary threshold compensation module 14 can also be turned on in the reset stage Z0. In this way, the first voltage V1 can be transmitted to the third node N3 in the reset stage Z0, which is beneficial to increasing the duration of the first voltage V1 for adjusting the bias state of the driving transistor Td, and thus beneficial to improving the effect of adjusting the bias of the driving transistor Td.

[0108] Figure 15 It is a schematic diagram of another pixel circuit provided by an embodiment of the present application. Figure 16 For Figure 15 a schematic diagram of the pixel circuit shown. Figure 17 For Figure 16 a timing diagram of the pixel circuit shown.

[0109] In an embodiment of the present application, asFigure 15 As shown, the pixel circuit 01 further includes a reset module 16. The input end of the reset module 16 is electrically connected to the reset signal line SL1, and the output end is electrically connected to the third node N3. The reset module 16 is used to transmit the reset voltage VREF on the reset signal line SL1 to the third node N4, and the reset voltage VREF is used to reset the first pole of the light-emitting device 02.

[0110] Exemplarily, as Figure 16 shown, the reset module 16 includes a reset transistor T6. The first pole of the reset transistor T6 is electrically connected to the reset signal line SL1, the second pole is electrically connected to the third node N3, and the gate is electrically connected to the fourth scan line G4. The reset transistor T6 can be an N-type transistor (turned on by high level and turned off by low level).

[0111] Among them, combined with Figure 17 shown, the reset module 16 is turned on in the reset stage Z0, and in the reset stage Z0, the period when the light-emitting control module 15 is turned on overlaps at least partially with the period when the reset module 16 is turned on, and the period when the light-emitting control module 15 is turned on does not overlap with the period when the power supply voltage writing module 11 is turned on.

[0112] Exemplarily, combined with Figure 16 and Figure 17 shown, the reset stage Z0 includes a first sub-reset stage Z01 and a second sub-reset stage Z02, and the second sub-reset stage Z02 is carried out after the first sub-reset stage Z01.

[0113] In the first sub-reset stage Z01, the second light-emitting control signal line EM2, the first scan line G1, and the third scan line G3 transmit low-level signals, and the data writing transistor T2, the auxiliary transistor T4, and the light-emitting control transistor T5 are turned off. The first light-emitting control signal line EM1 and the second scan signal line G2 transmit high-level signals, the power supply voltage writing transistor T1 and the threshold compensation transistor T3 are turned on, and the power supply voltage PVDD is transmitted to the second node N2 through the turned-on power supply voltage writing transistor T1 and threshold compensation transistor T3 to complete the reset of the gate of the driving transistor Td.

[0114] In the second sub-reset stage Z02, the first light-emitting control signal line EM1, the second scan signal line G2, the first scan line G1, and the third scan line G3 transmit low-level signals, and the power supply voltage writing transistor T1, the threshold compensation transistor T3, the data writing transistor T2, and the auxiliary transistor T4 are all turned off. The second light-emitting control signal line EM2 and the fourth scan line G4 transmit high-level signals, the light-emitting control transistor T5 and the reset transistor T6 are turned on, and the reset voltage VREF is transmitted to the fourth node N4 through the turned-on reset transistor T6 and light-emitting control transistor T5 to reset the first pole of the light-emitting device 02.

[0115] In addition, during the first sub-reset stage Z01, the fourth scan line G4 can also transmit a high-level signal to control the reset transistor T6 to turn on, and the reset voltage VREF can be transmitted to the third node N3 during the first sub-reset stage Z01. In this way, it is beneficial to pre-write the reset voltage VREF to the third node N3, improving the effect of resetting the first pole of the light-emitting device 02.

[0116] Optionally, as shown in Figure 16 and Figure 17 , the light-emitting control module 15 is turned off during the adjustment stage Z4, the threshold compensation stage Z1, and the data writing stage Z2. In this way, it is beneficial to avoid abnormal light emission of the light-emitting device 02 during the non-light-emitting stage.

[0117] Figure 18 For Figure 5 yet another timing diagram of the pixel circuit shown.

[0118] In an embodiment of the present application, as shown in Figure 4 , the pixel circuit 01 further includes a light-emitting control module 15. The input end of the light-emitting control module 15 is electrically connected to the third node N3, the output end is electrically connected to the fourth node N4, the fourth node N4 is electrically connected to the first pole of the light-emitting device 02, the light-emitting device 02 can be an organic light-emitting diode, and the first pole of the light-emitting device 02 can be its anode.

[0119] Exemplarily, as shown in Figure 5 , the light-emitting control module 15 includes a light-emitting control transistor T5. The first pole of the light-emitting control transistor T5 is electrically connected to the third node N3, the second pole is electrically connected to the fourth node N4, and the gate is electrically connected to the second light-emitting control signal line EM2. The light-emitting control transistor T5 can be an N-type transistor (turned on by high level and turned off by low level).

[0120] As shown in Figure 7 and Figure 18 , the working process of the pixel circuit 01 further includes a light-emitting stage Z3 after the data writing stage Z2. During the light-emitting stage Z3, the power supply voltage writing module 11 and the light-emitting control module 15 are turned on, and the time when the light-emitting control module 15 is turned on is not later than the time when the power supply voltage writing module 11 is turned on.

[0121] Exemplarily, as shown in Figure 7 , during the light-emitting stage Z3, the time when the light-emitting control module 15 is turned on is the same as the time when the power supply voltage writing module is turned on. That is, during the light-emitting stage Z3, the time when the first light-emitting control signal line EM1 starts to transmit a high level can be the same as the time when the second light-emitting control signal line EM2 starts to transmit a high level.

[0122] Exemplarily, as shown in Figure 18As shown, in the light-emitting stage Z3, the light control module 15 is turned on earlier than the power supply voltage writing module. That is, in the light-emitting stage Z3, the time when the second light control signal line EM2 starts to transmit a high level is earlier than the time when the first light control signal line EM1 starts to transmit a high level.

[0123] From the working process of the foregoing pixel circuit 01, it can be seen that in the light-emitting stage Z3, the light-emitting driving current generated by the driving transistor Td can be transmitted to the light-emitting device 02 through the light control module 15 to drive the light-emitting device 02 to emit light.

[0124] In the embodiment of the present application, setting the turn-on time of the light control module 15 not to be later than the turn-on time of the power supply voltage writing module 11, that is, the turn-on time of the power supply voltage writing module 11 is not earlier than the turn-on time of the light control module 15, is beneficial to avoiding the situation that after the power supply voltage writing module 11 is turned on first, the potential accumulated at the third node N3 is relatively high, and after the light control module 15 is turned on later, the high potential of the third node N3 impacts the first pole of the light-emitting device 02, thereby being beneficial to improving the service life of the light-emitting device 02.

[0125] Figure 19 It is a schematic diagram of another pixel circuit provided by the embodiment of the present application.

[0126] The embodiment of the present application further provides a pixel circuit 01, which can be applied to a display panel. As Figure 19 shown, the pixel circuit 01 includes a driving transistor Td, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The driving transistor Td is used to transmit a light-emitting driving current. The first pole of the driving transistor Td is electrically connected to the first node N1, the gate is electrically connected to the second node N2, and the second pole is electrically connected to the third node N3. The driving transistor Td is an N-type transistor.

[0127] The first pole of the first transistor M1 is electrically connected to the power supply signal line DL1, the second pole is electrically connected to the first node N1, and the gate is electrically connected to the first light control signal line EM1. The power supply signal line DL1 can be used to transmit the power supply voltage PVDD to the first transistor M1. The first pole of the third transistor M3 is electrically connected to the data signal line DL2, the second pole is electrically connected to the third node N3, and the gate is electrically connected to the first scan line G1. The data signal line DL2 can be used to transmit the data voltage Vdata to the third transistor M3.

[0128] The first pole of the second transistor M2 is electrically connected to the first node N1, the second pole is electrically connected to the second node N2, and the gate is electrically connected to the second scan line G2. The first pole of the fourth transistor M4 is electrically connected to the first signal line XL1, the second pole is coupled to the third node N3, and the gate is electrically connected to the third scan line G3. The fourth transistor M4 is configured to transfer the first voltage V1 on the first signal line XL1 to the third node N3.

[0129] Figure 19 The timing diagram of the pixel circuit shown can be as Figure 7 shown. The operation process of the pixel circuit 01 includes a threshold compensation stage Z1 and a data writing stage Z2 that occurs after the threshold compensation stage Z1.

[0130] Among them, the second transistor M2 is turned on during the threshold compensation stage Z1 and the data writing stage Z2, the third transistor M3 is turned on during the data writing stage Z2, and the fourth transistor M4 transfers the first voltage V1 to the third node N3 during the threshold compensation stage Z1 or before the threshold compensation stage Z1.

[0131] In the embodiment of the present application, the threshold compensation stage Z1 and the data writing stage Z2 can be carried out separately. If the fourth transistor M4 transfers the first voltage V1 to the third node N3 during the threshold compensation stage Z1 or before the threshold compensation stage Z1, then during the threshold compensation stage Z1, the first voltage V1 can be transferred to the gate of the driving transistor Td through the driving transistor Td and the turned-on second transistor M2, thereby compensating the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

[0132] In this way, the threshold voltage compensation duration of the driving transistor Td is no longer limited by the duration of writing the data voltage Vdata, which is beneficial to completely compensating the threshold voltage of the driving transistor Td during the operation process of the pixel circuit 01, thereby being beneficial to largely eliminating the influence of the threshold voltage of the driving transistor Td on the light-emitting driving current, and further being beneficial to improving the brightness uniformity of different light-emitting devices 02.

[0133] In addition, as Figure 19 shown, the pixel circuit 01 further includes a fifth transistor M5, a first capacitor C1, and a second capacitor C2. The first pole of the fifth transistor M5 is electrically connected to the third node N3, the second pole is electrically connected to the fourth node N4, and the gate is electrically connected to the second light-emitting control signal line EM2. The fourth node N4 is electrically connected to the first pole of the light-emitting device 02, and the light-emitting device 02 can be an organic light-emitting diode, and the first pole of the light-emitting device 02 can be its anode.

[0134] One plate of the first capacitor C1 is electrically connected to the second node N2, and the other plate is electrically connected to the third node N3. One plate of the second capacitor C2 is electrically connected to the power supply signal line DL1, and the other plate is electrically connected to the first node N1.

[0135] Exemplarily, as Figure 19 shown, the second pole of the fourth transistor M4 is electrically connected to the fourth node N4, and the first voltage V1 can also be used to reset the first pole of the light-emitting device 02. The driving transistor Td, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 can all be N-type transistors.

[0136] Figure 19 The working process of the pixel circuit shown can be substantially the same as that of the Figure 5 pixel circuit shown, and will not be elaborated here.

[0137] The embodiment of the present application also provides a driving method for the pixel circuit 01, which is used to drive the pixel circuit 01 provided in the above embodiment. As Figure 4 , Figure 5 , Figure 8 , Figure 9 , Figure 12 , Figure 13 , Figure 15 and Figure 16 shown, the pixel circuit 01 includes a driving transistor Td, a power supply voltage writing module 11, a threshold compensation module 12, a data writing module 13, and an auxiliary threshold compensation module 14. The driving transistor Td is used to generate a light-emitting driving current. The first pole of the driving transistor Td is electrically connected to the first node N1, the gate is electrically connected to the second node N2, and the second pole is electrically connected to the third node N3. The driving transistor Td can be an N-type transistor. Exemplarily, the driving transistor Td includes an oxide.

[0138] The input end of the power supply voltage writing module 11 is electrically connected to the power supply signal line DL1, and the output end is electrically connected to the first node N1. The power supply signal line DL1 is used to transmit the power supply voltage PVDD to the power supply voltage writing module 11.

[0139] The input end of the threshold compensation module 12 is electrically connected to the first node N1, and the output end is electrically connected to the second node N2. The input end of the data writing module 13 is electrically connected to the data signal line DL2, and the output end is electrically connected to the third node N3. The data signal line DL2 is used to transmit the data voltage Vdata to the data writing module 13.

[0140] The input end of the auxiliary threshold compensation module 14 is electrically connected to the first signal line XL1, and the output end is coupled to the third node N3. The auxiliary threshold compensation module 14 is used to transmit the first voltage V1 on the first signal line XL1 to the third node N3.

[0141] As Figure 6 , Figure 7 , Figure 10 , Figure 11 , Figure 14 , Figure 17 and Figure 18 shown, the operation process of the pixel circuit 01 includes a threshold compensation stage Z1 and a data writing stage Z2 performed after the threshold compensation stage Z1.

[0142] As Figure 20 shown, Figure 20 is a flowchart of a driving method for a pixel circuit provided by an embodiment of the present application. The driving method includes: Step S1: In the threshold compensation stage Z1, the threshold compensation module 12 is turned on.

[0143] Step S2: In the data writing stage Z2, the threshold compensation module 12 and the data writing module 13 are turned on.

[0144] Step S3: In the threshold compensation stage Z1, and / or before the threshold compensation stage Z1, the auxiliary threshold compensation module 14 is turned on.

[0145] In the driving method provided by the embodiment of the present application, the threshold compensation stage Z1 and the data writing stage Z2 can be performed separately. The auxiliary threshold compensation module 14 is turned on in the threshold compensation stage Z1, and / or before the threshold compensation stage Z1, and the first voltage V1 is transmitted to the third node N3. Then, in the threshold compensation stage Z1, it is beneficial to enable the first voltage V1 to be transmitted to the gate of the driving transistor Td through the driving transistor Td and the turned-on threshold compensation module 12, thereby compensating the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

[0146] In this way, the threshold voltage compensation duration of the driving transistor Td is no longer limited by the duration of the data voltage Vdata writing. It is beneficial to completely compensate the threshold voltage of the driving transistor Td during the operation process of the pixel circuit 01, thereby facilitating the elimination of the influence of the threshold voltage of the driving transistor Td on the light-emitting driving current to a large extent, and further facilitating the improvement of the brightness uniformity of different light-emitting devices.

[0147] In an embodiment of the present application, as shown in combination with Figure 5 and Figure 7 , the operation process of the pixel circuit 01 further includes a reset stage Z0, and the reset stage Z0 is performed before the threshold compensation stage Z1. As Figure 21 shown, Figure 21 is a flowchart of another driving method for a pixel circuit provided by an embodiment of the present application. The driving method further includes: Step S0: In the reset stage Z0, the power supply voltage writing module 11 and the threshold compensation module 12 are turned on.

[0148] Step S0 can be performed before step S1.

[0149] In the embodiment of the present application, in the reset stage Z0, when the power supply voltage writing module 11 and the threshold compensation module 12 are turned on, the power supply voltage PVDD can be transmitted to the second node N2 through the turned-on power supply voltage writing module 11 and threshold compensation module 12, so as to reset the gate of the driving transistor Td.

[0150] In an embodiment of the present application, in combination with Figure 5 and Figure 7 as shown, the pixel circuit 01 further includes a light emission control module 15. The input end of the light emission control module 15 is electrically connected to the third node N3, the output end is electrically connected to the fourth node N4, the fourth node N4 is electrically connected to the first pole of the light emitting device 02, and the output end of the auxiliary threshold compensation module 14 is electrically connected to the fourth node N4. The light emitting device 02 can be an organic light emitting diode, and the first pole of the light emitting device 02 can be its anode. The driving method further includes: In the reset stage Z0, the threshold compensation stage Z1, and the data writing stage Z2, the auxiliary threshold compensation module 14 is turned on.

[0151] In the threshold compensation stage Z1, the light emission control module 15 is turned on.

[0152] Based on this setting method, the first voltage V1 can also be used to reset the first pole of the light emitting device 02. The first voltage V1 can be transmitted to the fourth node N4 in the reset stage Z0, the threshold compensation stage Z1, and the data writing stage Z2, which is beneficial to increasing the reset duration of the first voltage V1 on the first pole of the light emitting device 02, and thus beneficial to improving the reset effect of the first voltage V1 on the first pole of the light emitting device 02.

[0153] Moreover, in the threshold compensation stage Z1, the first voltage V1 can be transmitted to the third node N3 through the turned-on auxiliary threshold compensation module 14 and light emission control module 15, and transmitted to the second node N2 through the driving transistor Td and the threshold compensation module 12, so as to compensate the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

[0154] In another embodiment of the present application, in combination with Figure 9 and Figure 10As shown, the pixel circuit 01 further includes a light emission control module 15. The input end of the light emission control module 15 is electrically connected to the third node N3, and the output end is electrically connected to the fourth node N4. The fourth node N4 is electrically connected to the first pole of the light emitting device 02, and the output end of the auxiliary threshold compensation module 14 is electrically connected to the third node N3. The light emitting device 02 may be an organic light emitting diode, and the first pole of the light emitting device 02 may be its anode. The driving method further includes: In the reset stage Z0 and the threshold compensation stage Z1, the auxiliary threshold compensation module 14 is turned on.

[0155] In the reset stage Z0, the light emission control module 15 is turned on, and the period during which the light emission control module 15 is turned on does not overlap with the period during which the power supply voltage writing module 11 is turned on.

[0156] Based on this setting method, the first voltage V1 can also be used to reset the first pole of the light emitting device 02. In the reset stage Z0, the first voltage V1 can be transmitted to the fourth node N4 through the turned-on auxiliary threshold compensation module 14 and the light emission control module 15, so as to realize the reset of the first pole of the light emitting device 02.

[0157] Moreover, in the threshold compensation stage Z1, the first voltage V1 can be transmitted to the third node N3 through the turned-on auxiliary threshold compensation module 14, and then transmitted to the second node N2 through the driving transistor Td and the threshold compensation module 12, so as to realize compensating the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

[0158] In an embodiment of the present application, in combination with Figure 13 and Figure 14 As shown, the pixel circuit 01 further includes a light emission control module 15. The input end of the light emission control module 15 is electrically connected to the third node N3, and the output end is electrically connected to the fourth node N4. The fourth node N4 is electrically connected to the first pole of the light emitting device 02, and the output end of the auxiliary threshold compensation module 14 is electrically connected to the third node N3. The light emitting device 02 may be an organic light emitting diode, and the first pole of the light emitting device 02 may be its anode.

[0159] The working process of the pixel circuit 01 further includes an adjustment stage Z4, and the adjustment stage Z4 is carried out between the reset stage Z0 and the threshold compensation stage Z1. The driving method further includes: In the adjustment stage Z4 and the threshold compensation stage Z1, the auxiliary threshold compensation module 14 is turned on.

[0160] In an embodiment of the present application, the first voltage V1 can also be used to adjust the bias state of the driving transistor Td. In the adjustment stage Z4, the first voltage V1 can be transmitted to the third node N3 through the turned-on auxiliary threshold compensation module to adjust the bias state of the driving transistor Td.

[0161] Moreover, in the threshold compensation stage Z1, the first voltage V1 can be transmitted to the third node N3 through the turned-on auxiliary threshold compensation module 14, and transmitted to the second node N2 through the driving transistor Td and the threshold compensation module 12, so as to compensate the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

[0162] In an implementation manner of the embodiment of the present application, in combination with Figure 13 and Figure 14 as shown, the pixel circuit 01 further includes a reset module 16. The input end of the reset module 16 is electrically connected to the reset signal line SL1, and the output end is electrically connected to the fourth node N4. The reset module 16 is configured to transmit the reset voltage VREF on the reset signal line SL1 to the fourth node N4 to reset the first pole of the light-emitting device 02. The driving method further includes: In the reset stage Z0, the adjustment stage Z4, the threshold compensation stage Z1, and the data writing stage Z2, the reset module 16 is turned on.

[0163] Based on this setting method, the reset voltage VREF can be transmitted to the fourth node N4 in the reset stage Z0, the adjustment stage Z4, the threshold compensation stage Z1, and the data writing stage Z2, which is beneficial to improving the reset effect of the reset voltage VREF on the first pole of the light-emitting device 02.

[0164] In another implementation manner of the embodiment of the present application, in combination with Figure 16 and Figure 17 as shown, the pixel circuit 01 further includes a reset module 16. The input end of the reset module 16 is electrically connected to the reset signal line SL1, and the output end is electrically connected to the third node N3. The reset module 16 is configured to transmit the reset voltage VREF on the reset signal line SL1 to the third node N3, and the reset voltage VREF is used to reset the first pole of the light-emitting device 02. The driving method further includes: In the reset stage Z0, the reset module 16 is turned on, and the period when the light-emitting control module 15 is turned on overlaps at least partially with the period when the reset module 16 is turned on, and the period when the light-emitting control module 15 is turned on does not overlap with the period when the power supply voltage writing module 11 is turned on.

[0165] Based on this setting method, in the reset stage Z0, the reset voltage VREF can be transmitted to the fourth node N4 through the turned-on reset module 16 and the light-emitting control module 15 to complete the reset of the first pole of the light-emitting device 02.

[0166] At the same time, in the reset stage Z0, the period when the light-emitting control module 15 is turned on does not overlap with the period when the power supply voltage writing module 11 is turned on. Then, it is possible to avoid the power supply voltage writing module 11 and the light-emitting control module 15 forming a path, resulting in abnormal light emission of the light-emitting device 02.

[0167] The embodiment of the present application further provides a display panel 10, as Figure 3 shown. The display panel 10 includes a pixel circuit 01 provided as in the above embodiment. Exemplarily, the display panel 10 can be applied to electronic devices such as mobile phones, computers, tablets, in-vehicle displays, etc., and the present application does not make specific limitations.

[0168] In the display panel 10, setting the threshold compensation stage Z1 and the data writing stage Z2 can be performed separately. Let the auxiliary threshold compensation module 14 transmit the first voltage V1 to the third node N3 during the threshold compensation stage Z1 or before the threshold compensation stage Z1. Then, during the threshold compensation stage Z1, it is beneficial for the first voltage V1 to be transmitted to the gate of the driving transistor Td through the driving transistor Td and the turned-on threshold compensation module 12, thereby compensating the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

[0169] In this way, the threshold voltage compensation duration of the driving transistor Td is no longer limited by the duration of the data voltage Vdata writing. It is beneficial to completely compensate the threshold voltage of the driving transistor Td during the operation of the pixel circuit 01, thereby facilitating the elimination of the influence of the threshold voltage of the driving transistor Td on the light-emitting driving current to a large extent, and further facilitating the improvement of the brightness uniformity of different light-emitting devices and the brightness uniformity of the display panel 10.

[0170] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of protection of the present application.

Claims

1. A pixel circuit, characterized in that: Applied to a display panel, the pixel circuit comprises: A driving transistor, used to generate a light-emitting driving current, wherein a first electrode of the driving transistor is electrically connected to the first node, a gate is electrically connected to the second node, and a second electrode is electrically connected to the third node, and the driving transistor is an N-type transistor; a power supply voltage writing module, wherein an input end of the power supply voltage writing module is electrically connected to the power supply signal line, and an output end of the power supply voltage writing module is electrically connected to the first node; a threshold compensation module, wherein an input terminal of the threshold compensation module is electrically connected to the first node, and an output terminal of the threshold compensation module is electrically connected to the second node; a data writing module, wherein an input end of the data writing module is electrically connected to the data signal line, and an output end of the data writing module is electrically connected to the third node; an auxiliary threshold compensation module, wherein an input end of the auxiliary threshold compensation module is electrically connected to the first signal line, an output end of the auxiliary threshold compensation module is coupled to the third node, and the auxiliary threshold compensation module is used to transmit the first voltage on the first signal line to the third node; The working process of the pixel circuit includes a threshold compensation stage and a data writing stage performed after the threshold compensation stage; Among them, the threshold compensation module is turned on in the threshold compensation stage and the data writing stage, the data writing module is turned on in the data writing stage, and the auxiliary threshold compensation module transmits the first voltage to the third node in the threshold compensation stage or before the threshold compensation stage.

2. The pixel circuit according to claim 1, characterized in that: The pixel circuit also includes a first capacitor and a second capacitor, one plate of the first capacitor is electrically connected to the second node, and the other plate is electrically connected to the third node, one plate of the second capacitor is electrically connected to the power signal line, and the other plate is electrically connected to the first node.

3. The pixel circuit according to claim 1, characterized in that: The power supply voltage writing module comprises a power supply voltage writing transistor, wherein a first electrode of the power supply voltage writing transistor is electrically connected to the power supply signal line, a second electrode is electrically connected to the first node, and a gate is electrically connected to a first light-emitting control signal line; the data writing module comprises a data writing transistor, wherein a first electrode of the data writing transistor is electrically connected to the data signal line, a second electrode is electrically connected to the third node, and a gate is electrically connected to a first scanning line; The threshold compensation module includes a threshold compensation transistor, a first electrode of the threshold compensation transistor is electrically connected to the first node, a second electrode is electrically connected to the second node, and a gate is electrically connected to the second scan line; the auxiliary threshold compensation module includes an auxiliary transistor, a first electrode of the auxiliary transistor is electrically connected to the first signal line, a second electrode is coupled to the third node, and a gate is electrically connected to the third scan line.

4. The pixel circuit according to claim 3, characterized in that: The power supply voltage writing transistor, the data writing transistor, the threshold compensation transistor, and the auxiliary transistor are all N-type transistors.

5. The pixel circuit according to claim 1, characterized in that: The working process of the pixel circuit further includes a reset phase, which is performed before the threshold compensation phase; The power supply voltage writing module and the threshold compensation module are turned on in the reset phase.

6. The pixel circuit according to claim 5, characterized in that: In the reset phase, a time period during which the power supply voltage writing module is turned on at least partially overlaps with a time period during which the threshold compensation module is turned on.

7. The pixel circuit according to claim 5, characterized in that: The pixel circuit further comprises a light emitting control module, wherein an input terminal of the light emitting control module is electrically connected to the third node, an output terminal of the light emitting control module is electrically connected to a fourth node, and the fourth node is electrically connected to a first electrode of the light emitting device; The output end of the auxiliary threshold compensation module is electrically connected to the fourth node, the auxiliary threshold compensation module is turned on in the reset stage and / or the threshold compensation stage, and the first voltage is used to reset the first pole of the light-emitting device; In the reset phase and the threshold compensation phase, a start period of the light emission control module and a start period of the auxiliary threshold compensation module at least partially overlap.

8. The pixel circuit according to claim 7, characterized in that: The light emitting control module includes a light emitting control transistor, a first electrode of the light emitting control transistor is electrically connected to the third node, a second electrode is electrically connected to the fourth node, and a gate is electrically connected to a second light emitting control signal line. The light emitting control transistor is an N-type transistor.

9. The pixel circuit according to claim 7, characterized in that: The auxiliary threshold compensation module is turned on in the reset phase, the threshold compensation phase and the data writing phase, and the light control module is turned off in the data writing phase.

10. The pixel circuit according to claim 5, characterized in that: The pixel circuit further comprises a light emitting control module, wherein an input terminal of the light emitting control module is electrically connected to the third node, an output terminal of the light emitting control module is electrically connected to a fourth node, and the fourth node is electrically connected to a first electrode of the light emitting device; The output end of the auxiliary threshold compensation module is electrically connected to the third node, the auxiliary threshold compensation module is turned on in the reset stage and / or the threshold compensation stage, and the first voltage is used to reset the first electrode of the light-emitting device; In the reset phase and the threshold compensation phase, the on-time period of the light emitting control module overlaps at least partially with the on-time period of the auxiliary threshold compensation module, and the on-time period of the light emitting control module overlaps with the on-time period of the power supply voltage writing module.

11. The pixel circuit according to claim 10, characterized in that: The reset phase includes a first sub-reset phase and a second sub-reset phase, wherein the second sub-reset phase is performed after the first sub-reset phase; The light emitting control module is turned on in the first sub-reset phase and turned off in the second sub-reset phase; The power supply voltage writing module is turned off in the first sub-reset phase and turned on in the second sub-reset phase; The threshold compensation module is turned on in the second sub-reset phase.

12. The pixel circuit according to claim 11, characterized in that: The auxiliary threshold compensation module is turned on in the reset phase and the threshold compensation phase, and the light control module is turned off in the threshold compensation phase and the data writing phase.

13. The pixel circuit according to claim 10, characterized in that: The reset phase includes a first sub-reset phase and a second sub-reset phase, wherein the second sub-reset phase is performed after the first sub-reset phase; The light emitting control module is turned off in the first sub-reset phase and turned on in the second sub-reset phase; The power supply voltage writing module is turned on in the first sub-reset phase and turned off in the second sub-reset phase; The threshold compensation module is turned on in the first sub-reset phase.

14. The pixel circuit according to claim 13, characterized in that: The auxiliary threshold compensation module is turned on in the reset phase and the threshold compensation phase; The light emitting control module is turned on during the threshold compensation phase and is turned off during the data writing phase.

15. The pixel circuit according to claim 5, characterized in that: The pixel circuit further comprises a light emitting control module, wherein an input terminal of the light emitting control module is electrically connected to the third node, an output terminal of the light emitting control module is electrically connected to a fourth node, and the fourth node is electrically connected to a first electrode of the light emitting device; The output end of the auxiliary threshold compensation module is electrically connected to the third node, and the operation process of the pixel circuit further includes an adjustment phase, which is performed between the reset phase and the threshold compensation phase; The auxiliary threshold compensation module is turned on during the adjustment phase and the threshold compensation phase.

16. The pixel circuit according to claim 15, characterized in that: The pixel circuit further comprises a reset module, wherein an input terminal of the reset module is electrically connected to the reset signal line, and an output terminal of the reset module is electrically connected to the fourth node; The reset module is turned on in the reset phase, the adjustment phase, the threshold compensation phase and the data writing phase.

17. The pixel circuit according to claim 16, characterized in that: The reset module comprises a reset transistor, a first electrode of the reset transistor is electrically connected to the reset signal line, a second electrode of the reset transistor is electrically connected to the fourth node, and a gate of the reset transistor is electrically connected to the fourth scan line. The reset transistor is an N-type transistor.

18. The pixel circuit according to claim 16, characterized in that: The light emitting control module is turned off in the resetting stage, the adjusting stage, the threshold compensation stage and the data writing stage.

19. The pixel circuit according to claim 15, characterized in that: The auxiliary threshold compensation module is turned on during the reset phase.

20. The pixel circuit according to claim 15, characterized in that: The pixel circuit further comprises a reset module, wherein an input terminal of the reset module is electrically connected to the reset signal line, and an output terminal of the reset module is electrically connected to the third node; The reset module is turned on in the reset phase, and in the reset phase, the time period when the light control module is turned on at least partially overlaps with the time period when the reset module is turned on, and the time period when the light control module is turned on does not overlap with the time period when the power supply voltage writing module is turned on.

21. The pixel circuit according to claim 20, characterized in that: The light emitting control module is turned off in the adjustment phase, the threshold compensation phase and the data writing phase.

22. The pixel circuit according to claim 1, characterized in that: The pixel circuit further comprises a light emitting control module, wherein an input terminal of the light emitting control module is electrically connected to the third node, an output terminal of the light emitting control module is electrically connected to a fourth node, and the fourth node is electrically connected to a first electrode of the light emitting device; The working process of the pixel circuit also includes a light-emitting stage performed after the data writing stage. In the light-emitting stage, the power supply voltage writing module and the light-emitting control module are turned on, and the light-emitting control module is turned on no later than the power supply voltage writing module.

23. A pixel circuit, characterized in that: Applied to a display panel, the pixel circuit comprises: A driving transistor, used to generate a light-emitting driving current, wherein a first electrode of the driving transistor is electrically connected to the first node, a gate is electrically connected to the second node, and a second electrode is electrically connected to the third node, and the driving transistor is an N-type transistor; a first transistor, wherein a first electrode of the first transistor is electrically connected to the power signal line, and a second electrode of the first transistor is electrically connected to the first node; a second transistor, wherein a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second node; a third transistor, wherein a first electrode of the third transistor is electrically connected to the data signal line, and a second electrode of the third transistor is electrically connected to the third node; a fourth transistor, wherein a first electrode of the fourth transistor is electrically connected to the first signal line, a second electrode of the fourth transistor is coupled to the third node, and the fourth transistor is used to transmit the first voltage on the first signal line to the third node; The working process of the pixel circuit includes a threshold compensation stage and a data writing stage performed after the threshold compensation stage; The second transistor is turned on during the threshold compensation stage and the data writing stage, the third transistor is turned on during the data writing stage, and the fourth transistor transmits the first voltage to the third node during the threshold compensation stage or before the threshold compensation stage.

24. A method for driving a pixel circuit, characterized in that: The pixel circuit comprises: A driving transistor, used to generate a light-emitting driving current, wherein a first electrode of the driving transistor is electrically connected to the first node, a gate is electrically connected to the second node, and a second electrode is electrically connected to the third node, and the driving transistor is an N-type transistor; a power supply voltage writing module, wherein an input end of the power supply voltage writing module is electrically connected to the power supply signal line, and an output end of the power supply voltage writing module is electrically connected to the first node; a threshold compensation module, wherein an input terminal of the threshold compensation module is electrically connected to the first node, and an output terminal of the threshold compensation module is electrically connected to the second node; a data writing module, wherein an input end of the data writing module is electrically connected to the data signal line, and an output end of the data writing module is electrically connected to the third node; an auxiliary threshold compensation module, wherein an input end of the auxiliary threshold compensation module is electrically connected to the first signal line, an output end of the auxiliary threshold compensation module is coupled to the third node, and the auxiliary threshold compensation module is used to transmit the first voltage on the first signal line to the third node; The working process of the pixel circuit includes a threshold compensation stage and a data writing stage performed after the threshold compensation stage; the method includes: In the threshold compensation stage, the threshold compensation module is turned on; In the data writing phase, the threshold compensation module and the data writing module are turned on; During the threshold compensation phase, and / or before the threshold compensation phase, the auxiliary threshold compensation module is turned on.

25. The method according to claim 24, characterized in that The working process of the pixel circuit further includes a reset phase, which is performed before the threshold compensation phase; the method further includes: In the reset phase, the power supply voltage writing module and the threshold compensation module are turned on.

26. The method according to claim 25, characterized in that The pixel circuit further includes a light emitting control module, wherein an input terminal of the light emitting control module is electrically connected to the third node, an output terminal of the light emitting control module is electrically connected to a fourth node, the fourth node is electrically connected to a first electrode of the light emitting device, and an output terminal of the auxiliary threshold compensation module is electrically connected to the fourth node; the method further includes: In the reset phase, the threshold compensation phase and the data writing phase, the auxiliary threshold compensation module is turned on; In the threshold compensation stage, the light emitting control module is turned on.

27. The method according to claim 25, characterized in that The pixel circuit further includes a light emitting control module, wherein an input terminal of the light emitting control module is electrically connected to the third node, an output terminal of the light emitting control module is electrically connected to a fourth node, the fourth node is electrically connected to a first electrode of the light emitting device, and an output terminal of the auxiliary threshold compensation module is electrically connected to the third node; The method further comprises: In the reset phase and the threshold compensation phase, the auxiliary threshold compensation module is turned on; In the reset phase, the light emitting control module is turned on, and the time period when the light emitting control module is turned on does not overlap with the time period when the power supply voltage writing module is turned on.

28. The method according to claim 25, characterized in that The pixel circuit further comprises a light emitting control module, wherein an input terminal of the light emitting control module is electrically connected to the third node, an output terminal of the light emitting control module is electrically connected to a fourth node, and the fourth node is electrically connected to a first electrode of the light emitting device; The output end of the auxiliary threshold compensation module is electrically connected to the third node, the operation process of the pixel circuit further includes an adjustment phase, and the adjustment phase is performed between the reset phase and the threshold compensation phase; the method further includes: In the adjustment phase and the threshold compensation phase, the auxiliary threshold compensation module is turned on.

29. The method according to claim 28, characterized in that The pixel circuit further includes a reset module, wherein an input terminal of the reset module is electrically connected to a reset signal line, and an output terminal of the reset module is electrically connected to the fourth node; the method further includes: During the reset phase, the adjustment phase, the threshold compensation phase and the data writing phase, the reset module is turned on.

30. The method according to claim 28, characterized in that The pixel circuit further includes a reset module, wherein an input terminal of the reset module is electrically connected to a reset signal line, and an output terminal of the reset module is electrically connected to the third node; the method further includes: In the reset stage, the reset module is turned on, the time period when the light control module is turned on at least partially overlaps with the time period when the reset module is turned on, and the time period when the light control module is turned on does not overlap with the time period when the power supply voltage writing module is turned on.

31. A display panel, characterized in that: Comprising a pixel circuit as described in any one of claims 1-23.

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