Scanning circuit

Abstract

The invention relates to a scanning circuit. The shifting register outputs high-level pulses one by one according to the transmission step length of one horizontal time period, wherein the lengths of the high-level pulses are larger than or equal to those of the two horizontal time periods. The shift register is controlled by a first clock signal and a second clock signal in m phases of clock signals. The shift register comprises a high-level output thin film transistor, a low-level output thin film transistor and a buffer thin film transistor. The buffer thin film transistor receives a control signal having the same pulse width and period as the first clock signal during a period in which an output terminal outputs a low level potential. The high duty ratio of the first clock signal and the second clock signal is represented as PW / mH, PW represents the pulse width of the first clock signal and the second clock signal, and H represents a horizontal time period. And the conduction duty ratio of all the thin film transistors is not greater than PW / mH.

Description

Technical Field

[0001] The present invention relates to a scanning circuit. Background Art

[0002] Current-driven light-emitting elements such as organic light-emitting diode (OLED) elements have advantages such as not requiring a backlight, achieving low power consumption, wide viewing angles, and high contrast; and are expected to contribute to the development of flat panel display devices.

[0003] An active matrix (AM) OLED display device includes a plurality of switching transistors for selecting pixels and writing data signals into storage capacitors, and driving transistors for supplying current to the pixels. The transistors in the OLED display device are thin film transistors (TFTs); they can be low temperature polycrystalline silicon (LTPS) TFTs, oxide semiconductor TFTs, and / or amorphous silicon TFTs.

[0004] In order to write a more appropriate data signal into a pixel, it is important to compensate for the differences and offsets in the threshold voltages of the TFTs. Providing a longer control period (also referred to as a threshold compensation period) for each pixel circuit to calibrate the threshold voltage enables a more appropriate data signal to be written into the storage capacitor. Summary of the Invention

[0005] In order to provide a threshold compensation period longer than the data writing period for writing a data signal into a storage capacitor for each pixel circuit, a scanning circuit is required that outputs a control signal having a pulse width longer than one horizontal period (1H period). The scanning circuit transfers a pulse having a width that is an integer multiple of the 1H period to the next stage after the 1H period. This means that multiple consecutive output lines are simultaneously in an active state during the same period. The active output signal keeps the target TFT to be controlled in the pixel circuit turned on.

[0006] The light emission duty ratio is usually very high, up to 99% or higher; therefore, each output line is almost always in an inactive state. Therefore, each output circuit in the scanning circuit includes a TFT that is almost always turned on. When the TFT remains turned on for a long time, its characteristics may deteriorate. Especially in the case of oxide TFTs or amorphous silicon TFTs, the degree of deterioration is significant. Although the above description is provided by way of example for an n-type TFT circuit, the conduction type is not limited to n-type.

[0007] One aspect of the present invention is a scanning circuit configured to output a gate signal to a pixel circuit of a display panel. The scanning circuit includes: a plurality of shift registers connected in series. Among them, the scanning circuit is configured to be controlled by an m-phase clock signal, where m is an integer greater than 1. Among them, the plurality of shift registers are configured to output high-level pulses each with a length greater than or equal to two horizontal periods one by one with a transfer step of one horizontal period. Among them, each of the plurality of shift registers is configured to be controlled by a two-phase clock signal, and the two-phase clock signal is composed of a first clock signal and a second clock signal among the m-phase clock signals. Among them, all thin-film transistors in each of the plurality of shift registers have the same conductivity type; among them, each of the plurality of shift registers includes: a high-level output thin-film transistor, the high-level output thin-film transistor includes a source connected to the output terminal of the shift register and a drain connected to a high-power line; a low-level output thin-film transistor, the low-level output thin-film transistor includes a drain connected to the output terminal of the shift register and a source connected to a low-power line; and a buffer thin-film transistor, the buffer thin-film transistor includes one of the source / drain terminals for receiving the first clock signal and the other of the source / drain terminals connected to the gate of the low-level output thin-film transistor. Among them, the buffer thin-film transistor is configured to receive a control signal having the same pulse width and period as the first clock signal at the gate of the buffer thin-film transistor during the period when the output terminal outputs a low-level potential. Among them, the high duty cycle of the first clock signal and the second clock signal is expressed as PW / mH, where PW represents the pulse width of the first clock signal and the second clock signal, H represents one horizontal period, and the conduction duty cycle of all thin-film transistors is not greater than PW / mH.

[0008] One aspect of the present invention is a scanning circuit configured to output a gate signal to a pixel circuit of a display panel. The scanning circuit includes: a plurality of shift registers connected in series. Among them, the scanning circuit is configured to be controlled by an m-phase clock signal, where m is an integer greater than 1. Among them, the plurality of shift capacitors are configured to output low-level pulses each having a length greater than or equal to two horizontal periods one by one with a transfer step of one horizontal period. Among them, each of the plurality of shift registers is configured to be controlled by a two-phase clock signal, and the two-phase clock signal is composed of a first clock signal and a second clock signal among the m-phase clock signals. Among them, all thin film transistors in each of the plurality of shift registers have the same conductivity type; among them, each of the plurality of shift registers includes: a high-level output thin film transistor, the high-level output thin film transistor includes a drain connected to the output terminal of the shift register and a source connected to a high-power line; a low-level output thin film transistor, the low-level output thin film transistor includes a source connected to the output terminal of the shift register and a drain connected to a low-power line; and a buffer thin film transistor, the buffer thin film transistor includes one of the source / drain terminals for receiving the first clock signal and the other of the source / drain terminals connected to the gate of the low-level output thin film transistor. Among them, the buffer thin film transistor is configured to receive a control signal having the same pulse width and period as the first clock signal at the gate of the buffer thin film transistor during a period when the output terminal outputs a low-level potential. Among them, the low duty cycle of the first clock signal and the second clock signal is expressed as PW / mH, where PW represents the pulse width of the first clock signal and the second clock signal, H represents one horizontal period, and the conduction duty cycle of all thin film transistors is not greater than PW / mH.

[0009] One aspect of the present invention suppresses the deterioration of TFTs in the scanning circuit.

[0010] It should be understood that the above general description and the following detailed description are both exemplary and explanatory and do not limit the present invention. Description of the Drawings

[0011] Figure 1 Schematically shows a configuration example of an OLED display device as a display device.

[0012] Figure 2 Shows a configuration example of a pixel circuit and its control signals related to an embodiment of this specification.

[0013] Figure 3 is used to control during one frame period Figure 2Timing diagram of signals of the pixel circuit in

[0014] Figure 4 Shows the time variation of the selection signals for the (k - 1)-th row, k-th row, and (k + 1)-th row.

[0015] Figure 5 Shows a configuration example of a shift register included as part of a scan circuit in the scan circuit.

[0016] Figure 6 Shows another configuration example of the shift register.

[0017] Figure 7 Shows yet another configuration example of the shift register.

[0018] Figure 8 Shows the time variation of the signals input to the shift register, the potentials at some nodes in its circuit, and its output signals.

[0019] Figure 9A Shows a state of the shift register.

[0020] Figure 9B Shows another state of the shift register.

[0021] Figure 9C Shows yet another state of the shift register.

[0022] Figure 9D Shows yet another state of the shift register.

[0023] Figure 9E Shows yet another state of the shift register.

[0024] Figure 9F Shows yet another state of the shift register.

[0025] Figure 9G Shows yet another state of the shift register.

[0026] Figure 9H Shows yet another state of the shift register.

[0027] Figure 9I Shows yet another state of the shift register.

[0028] Figure 9J Shows yet another state of the shift register.

[0029] Figure 10A Shows the potential variations at the gate, source, and drain of a transistor in the shift register.

[0030] Figure 10BShows the potential changes at the gate, source, and drain of another transistor in the shift register.

[0031] Figure 10C Shows the potential changes at the gate, source, and drain of yet another transistor in the shift register.

[0032] Figure 10D Shows the potential changes at the gate, source, and drain of yet another transistor in the shift register.

[0033] Figure 10E Shows the potential changes at the gate, source, and drain of yet another transistor in the shift register.

[0034] Figure 10F Shows the potential changes at the gate, source, and drain of yet another transistor in the shift register.

[0035] Figure 10G Shows the potential changes at the gate, source, and drain of yet another transistor in the shift register.

[0036] Figure 10H Shows the potential changes at the gate, source, and drain of yet another transistor in the shift register.

[0037] Figure 10I Shows the potential changes at the gate, source, and drain of yet another transistor in the shift register.

[0038] Figure 10J Shows the potential changes at the gate, source, and drain of yet another transistor in the shift register.

[0039] Figure 11 Shows the (k - 1)th, kth, and (k + 1)th shift registers and the input and output signals of each shift register.

[0040] Figure 12 Shows Figure 11 the time variations of some signals in the shift register.

[0041] Figure 13 Shows the partial configuration of the scan circuit to be controlled by a three - phase clock.

[0042] Figure 14 Shows Figure 13 the time variations of the clock signal and some signals of the shift register.

[0043] Figure 15A Provides the simulation results of the output waveform of the shift register when the clock signal has a pulse width of 3.00 μm.

[0044] Figure 15B The simulation results of the output waveform of the shift register are provided when the clock signal has a pulse width of 1.62 μm.

[0045] Figure 15C The simulation results of the output waveform of the shift register are provided when the clock signal has a pulse width of 0.36 μm.

[0046] Figure 16 Another configuration example of the shift register is shown.

[0047] Figure 17 Shows Figure 16 the time variation of some signals of the shift register in

[0048] Figure 18 Another configuration example of the shift register is shown.

[0049] Figure 19 Shows Figure 18 the time variation of some signals of the shift register in Detailed implementation mode

[0050] Hereinafter, the implementation mode will be specifically described with reference to the drawings. Common elements in the drawings are denoted by the same reference numerals, and some elements in the drawings are exaggerated in size or shape for a clear understanding of the description.

[0051] The following discloses a technology for improving a scanning circuit in an electroluminescent display device. An electroluminescent display device is a display device using a light-emitting element that emits light in response to a driving current, such as an organic light-emitting diode (OLED) display device or an inorganic LED display device. The type of display device to which the technology of the present invention is applicable is not limited, and the technology is also applicable to devices other than display devices.

[0052] The display device related to the implementation mode of this specification has a long pixel circuit control period (also called a threshold compensation period) for calibrating the threshold voltage of a thin film transistor (TFT) in order to write a more appropriate data signal into a storage capacitor. The display device includes a plurality of scanning circuits that output different control signals.

[0053] At least one scanning circuit outputs a control signal having a pulse width longer than one horizontal period (1H period) in order to provide a threshold compensation period longer than the data writing period for writing a data signal into a storage capacitor to the pixel circuit. The pulse width of this control signal is the period during which the signal level keeps the controlled TFT turned on (ON). In the case where the controlled object is an n-type TFT, the signal is at a high (H) level during this period. The signal that turns on the controlled TFT is also called an effective signal.

[0054] A horizontal period is calculated based on the frame rate and the number of rows of the pixel circuit. Specifically, a horizontal period = 1 / frame rate / number of rows. For example, when the frame rate is 120 Hz and the number of rows is 2952, the 1H period is 2.82 μs.

[0055] The scan circuit transmits a pulse having a width that is an integer multiple of the 1H period to the next stage after the 1H period. That is, each output line of the scan circuit starts to output a pulse 1H period after the output line of the previous stage outputs a pulse. As noted from this description, the transmission step of the pulse is the 1H period, and multiple consecutive output lines are valid together within the same period. This scanning method can be referred to as overlapping scanning.

[0056] The light emission duty ratio of the display device is usually very high, up to 99% or higher; therefore, each output line is almost always in an inactive state. In other words, in order to maintain the same signal level for a long time, each output circuit in the scan circuit may include a TFT that is almost always turned on. When the TFT remains turned on for a long time, its characteristics may deteriorate. Especially in the case of an oxide TFT or an amorphous silicon TFT, the degree of deterioration is large. Although the above description is provided by way of example for an n-type TFT circuit, the conduction type is not limited to n-type.

[0057] One embodiment of the present specification proposes a circuit configuration of a scan circuit that suppresses TFT deterioration. Figure 1 A configuration example of the OLED display device 10 in the display device is schematically shown. Figure 1 The horizontal direction in is the X-axis direction, and the vertical direction is the Y-axis direction perpendicular to the X-axis direction. The features of the present invention are applicable to display devices including other types of light-emitting elements (such as inorganic LEDs). The OLED display device 10 includes a TFT substrate 100 on which OLED elements (light-emitting elements) are manufactured and a packaging substrate 150 for packaging the OLED elements.

[0058] The space between the TFT substrate 100 and the packaging substrate 150 is filled with an inert gas such as dry nitrogen and sealed. Instead of the packaging substrate 150, a structure packaging unit having a different structure can be employed, such as a structure packaging unit using thin film packaging.

[0059] Around the cathode electrode region 114 outside the display region 125 of the TFT substrate 100, a scan circuit (also referred to as a gate driver circuit) 131, 132, and 133, a driver IC 134, and a demultiplexer 136 are provided. The driver IC 134 is connected to an external device through a flexible printed circuit (FPC) 135. The scan circuits 131, 132, and 133 drive the scan lines on the TFT substrate 100.

[0060] The driver IC 134 is mounted with an anisotropic conductive film (ACF), for example. The driver IC 134 supplies power and timing signals (control signals) to the scan circuits 131, 132, and 133, and also supplies data signals to the demultiplexer 136.

[0061] The demultiplexer 136 outputs the output of one pin of the driver IC 134 one by one to d data lines (d is an integer greater than 1). The demultiplexer 136 changes the data line to which the data signal of the driver IC 134 is output d times during each scan period to drive d times as many data lines as the output pins of the driver IC 134.

[0062] The display area 125 includes a plurality of OLED elements (pixels) and a plurality of pixel circuits for controlling the light emission of the plurality of pixels. In an example of a full-color OLED display device, each OLED element emits light of one color among red, blue, and green. The plurality of pixel circuits constitute a pixel circuit array.

[0063] As will be described later, each pixel circuit includes a driving TFT (driving transistor) and a storage capacitor for storing a signal voltage that determines the driving current of the driving TFT. The data signal transmitted by the data line is adjusted using the threshold voltage Vth of the driving TFT and stored in the storage capacitor. The voltage of the storage capacitor determines the gate voltage (Vgs) of the driving TFT. The adjusted control voltage of the storage capacitor changes the conductance of the driving TFT in an analog manner to supply a forward bias current corresponding to the light emission level to the OLED element.

[0064] Configuration of Pixel Circuit

[0065] Figure 2 FIG. shows a configuration example of a pixel circuit 200 and its control signals related to an embodiment of this specification. Figure 2 The pixel circuit in is merely an example; the configuration of the pixel circuit controlled by the scan circuit of the present invention is not limited thereto. The pixel circuit 200 is included in the k-th pixel circuit row (k is an integer). The pixel circuit 200 includes four transistors (TFTs) P1 to P4, each transistor having a gate, a source, and a drain. All the transistors P1 to P4 in this example have n-type conductivity, and they may be oxide semiconductor transistors.

[0066] The transistor P1 is a driving transistor for controlling the amount of current flowing through the OLED element E1. The drain of the driving transistor P1 is connected to the power supply line 241 for transmitting the positive power supply potential VDD. The driving transistor P1 controls the amount of current supplied from the power supply line 241 to the OLED element E1 according to the voltage stored in the series-connected storage capacitor elements CS1 and CS2. The storage capacitor elements CS1 and CS2 hold the write voltage during the entire period of one frame. The cathode of the OLED element E1 is connected to the power supply line 204 for transmitting the negative power supply potential VEE from the cathode power supply.

[0067] The capacitor elements CS1 and CS2 are connected in series between the power supply line 204 for transmitting the negative power supply potential VEE and the gate of the driving transistor P1. One end of the capacitor element CS1 is connected to the power supply line 204, and the other end of the capacitor element CS1 is connected to one end of the capacitor element CS2. The other end of the capacitor element CS2 is connected to the gate of the driving transistor P1. The source of the transistor P1 and the anode of the OLED element E1 are connected to the intermediate node between the capacitor elements CS1 and CS2.

[0068] The combined capacitor of the series-connected storage capacitor elements CS1 and CS2 stores the voltage between the gate of the driving transistor P1 and the power supply line 204. The source of the driving transistor P1 is connected to the OLED element E1. The storage capacitor elements CS1 and CS2 store the gate-source voltage of the driving transistor P1.

[0069] The transistor P4 is used to supply the reset potential Vrst to the anode of the OLED element E1 and the intermediate node between the capacitor elements CS1 and CS2. One end (source or drain) of the source / drain of the transistor P4 is connected to the power supply line 242 for transmitting the reset potential Vrst, and the other end is connected to the anode of the OLED element E1 and the intermediate node between the capacitor elements CS1 and CS2. The reset potential Vrst can be equal to the negative power supply potential VEE.

[0070] The gate of the transistor P4 is connected to the control signal line 231 for transmitting the selection signal S1, and the transistor P4 is controlled by the selection signal S1. When the transistor P4 is turned on by the selection signal S1 from the scanning circuit 131, the transistor P4 supplies the reset potential Vrst transmitted by the power supply line 242 to the anode of the OLED element E1 and the intermediate node between the capacitor elements CS1 and CS2.

[0071] The transistor P3 controls whether to supply the reference potential Vref to the gate of the transistor P1. The reference potential Vref may be a constant negative potential similar to but higher than the reset potential Vrst. One end of the source / drain of the transistor P3 is connected to the power supply line 202 for transmitting the reference potential Vref, and the other end is connected to the gate of the transistor P1. The gate of the transistor P3 is connected to the control signal line 233 for transmitting the selection signal S3, and the transistor P3 is controlled by the selection signal S3 input to its gate from the scanning circuit 133.

[0072] The transistor P2 is a switching transistor for selecting the pixel circuit to which the data signal is to be supplied and writing the data signal (data signal voltage) Vdata into the storage capacitor elements CS1 and CS2. One end of the source / drain of the transistor P2 is connected to the storage capacitor element CS2 and the gate of the transistor P1, and the other end is connected to the data line 237 for transmitting the data signal Vdata.

[0073] The gate of the transistor P2 is connected to the control signal line 232 for transmitting the selection signal S2 from the scanning circuit 132. The transistor P2 is controlled by the selection signal S2. In the pixel circuit 200, the selection signal S2 is a selection signal for controlling whether to supply the data signal Vdata to the storage capacitor elements CS1 and CS2. When the transistor P2 is turned on, the transistor P2 supplies the data signal Vdata supplied from the driver IC 134 through the data line 237 to the storage capacitor elements CS1 and CS2.

[0074] Operation of the pixel circuit

[0075] Figure 3 is a timing diagram of the signals for controlling the pixel circuit 200 in one frame period. Figure 2 in Figure 3 is a timing diagram of the pixel circuit 200 for selecting the k-th row and writing the data signal therein. Specifically, Figure 3 is a timing diagram of the selection signals S1, S2, and S3 and the data signal Vdata.

[0076] The period before the time T1 is the light-emitting period. The selection signals S1, S2, and S3 are at a low level. During this period, the transistors P2 to P4 are turned off. Due to the voltage stored in the combined capacitor of the series-connected storage capacitor elements CS1 and CS2, the drive current is supplied from the power supply line 241 through the drive transistor P1 to the OLED element E1, causing the OLED element E1 to emit light.

[0077] The period from time T1 to time T2 is the initialization period. At time T1, selection signals S1 and S3 change from low level to high level. Selection signal S2 remains at low level. At time T1, transistors P3 and P4 are turned on, and transistor P2 remains off. This state is maintained from time T1 until time T2. This period is the initialization period and has a length of one horizontal period (1H). The reference potential Vref and the reset potential Vrst are supplied to the pixel circuit.

[0078] At time T2, selection signal S1 changes from high level to low level. Selection signal S2 remains at low level, and selection signal S3 remains at high level. In response to the change in selection signal S1, transistor P4 turns off. This state is maintained from time T2 until time T3. The period from time T2 to time T3 is a period for calibrating the threshold voltage Vth of driving transistor P1. In Figure 3 the example, the length of the compensation period is 5H.

[0079] At time T3, selection signal S1 remains at low level; selection signal S2 changes from low level to high level; selection signal S3 changes from high level to low level. Since selection signal S1 remains at low level, transistor P4 remains off. In response to the change in selection signal S2, transistor P2 turns on. In response to the change in selection signal S3, transistor P3 turns off. The period from time T3 to time T4 is a data writing period for writing the data signal into storage elements CS1 and CS2. The length of this period is 1H. The period after time T4 is the light emission period. Driving transistor P1 supplies a driving current to OLED element E1 according to the voltage stored in the storage capacitor. This state continues until time T1 of the next frame.

[0080] In Figure 3 the example, the length of the initialization period is 1H, and the length of the Vth compensation period is an integer multiple of 1H, specifically five times 1H. For example, the length of the initialization period can be determined to be from 1H to 3H, and the length of the Vth compensation period can be determined to be from 3H to 40H, where 1H can be approximately 3 μs.

[0081] Figure 4 shows the time variation of selection signal S3 for some consecutive pixel rows. Selection signal S3 is output one by one from the scanning circuit 133 to each pixel row. Figure 4 shows the time variation of selection signal S3_k-1 for the (k - 1)th row, selection signal S3_k for the kth row, and selection signal S3_k+1 for the (k + 1)th row. The selection signals S3 for two consecutive rows are offset by a 1H period. The pulse width of each selection signal S3 is the same as that in the example in Figure 3 .

[0082] The scan circuit 133 continuously outputs a selection signal S3 having a pulse width greater than one horizontal period. The scan circuit 133 transfers a pulse having an integer multiple length of the 1H period (6H period in this example) to the next stage after the 1H period. That is, each output line of the scan circuit 133 starts to output a pulse 1H period after the output line of its previous stage starts to output a pulse. The transfer step of the pulse is the 1H period, and a plurality of consecutive output lines are made effective within the same period. As can be understood from this description, the scan circuit 133 performs overlapping scanning.

[0083] Figure 5 A configuration example of a shift register 300 that is part of the scan circuit 133 is shown. The shift register 300 generates a signal to be output from one output terminal of the scan circuit and outputs the signal. The scan circuit includes a plurality of shift registers 300 connected in series. Figure 5 Shown is the k-th shift register.

[0084] In Figure 5 In the configuration example, the shift register 300 receives the output OUT_k-1 from the previous shift register, the first clock signal CK1, the second clock signal CK2, the high power supply potential VGH, and the low power supply potential VGL. The shift register 300 includes nine transistors and two capacitor elements. The transistors are thin film transistors and they have n-type conductivity. The transistors can be oxide semiconductor TFTs. The conductivity type can be p-type. The shift register 300 can be fabricated on the insulating substrate of the TFT substrate 100 like the pixel circuit 200.

[0085] The shift register 300 includes transistors M1, M3 to M9, and M11 and capacitor elements C1 and C3. The capacitor elements are optional. The gate of the transistor M1 (first thin film transistor) is connected to the transmission line of the clock signal CK2 and receives the clock signal CK2. One of the source / drain is connected to the output line of the previous shift register and receives the output signal OUT_k-1 from the previous shift register. The other of the source / drain is connected to the gates of the transistor M3 (third thin film transistor) and the transistor M4 (fourth thin film transistor), and is also connected to the gate of the transistor M8 (high level output thin film transistor) through the node Q.

[0086] The gate of the transistor M11 is connected to the transmission line of the clock signal CK1, the drain is connected to the power supply line of the high power supply potential VGH, and the source is connected to the node N1. The source of the transistor M3 is connected to the power supply line of the low power supply potential VGL, and the drain is connected to the node N1.

[0087] The drain of transistor M4 is connected to the power supply line of high power supply potential VGH, and the source is connected to node N2. The source of transistor M5 (the fifth thin film transistor) is connected to the power supply line of low power supply potential VGL, and the drain is connected to node N2.

[0088] The gate of transistor M6 (the first buffer thin film transistor) is connected to node N1, the drain is connected to the transmission line of clock signal CK1, and the source is connected to node QB. The source of transistor M7 (the second buffer thin film transistor) is connected to the power supply line of low power supply potential VGL, and the drain is connected to node QB.

[0089] The gate of transistor M8 is connected to one end of the source / drain of transistor M1 through node Q. The drain is connected to the power supply line for high power supply potential VGH, and the source is connected to the output terminal (output line) of the output signal OUT_k of shift register 300. The gate of transistor M9 (low level output thin film transistor) is connected to the source of transistor M6 and the drain of transistor M7 through node QB. The source is connected to the power supply line of low power supply potential VGL, and the drain is connected to the output terminal (output line) of the output signal OUT_k of shift register 300.

[0090] Capacitor element C1 is connected to the output terminal (output line) of the output signal OUT_k of shift register 300 and node Q. In other words, capacitor element C1 is connected to the source and gate of transistor M8. Capacitor element C3 is connected to node QB and node N1. In other words, capacitor element C3 is connected to the source and gate of transistor M6.

[0091] Transistors M8 and M9 are output transistors for outputting high level signals and low level signals respectively. Transistors M6 and M7 are buffer transistors of transistor M9. One end (source or drain) of the source / drain of the buffer transistor is connected to the gate of the output transistor. The gate of the buffer transistor receives the signal generated by shift register 300 according to the signal received from the outside. The gates of transistors M6 and M7 receive an aperiodic signal within one frame period, and this aperiodic signal is different from periodic signals such as clock signals.

[0092] Output transistors M8 and M9 have a larger gate width (size) than buffer transistors M6 and M7. Buffer transistors M6 and M7 have a larger gate width than transistors M3 to M5 and M11.

[0093] Figure 6 Another configuration example 310 of the shift register is shown. Compared with Figure 5 the configuration of the shown shift register 300, shift register 310 does not include transistor M11, but includes another capacitor element C2. Capacitor element C2 is connected to the transmission line of clock signal CK1 and node N1, and helps to reduce the current flowing throughFigure 5 The direct currents of transistors M11 and M3 in

[0094] Figure 7 Another configuration example 320 of the shift register is shown. Compared with Figure 6 the shift register 310 shown, the shift register 320 includes an additional transistor M2 (second thin film transistor) and another additional transistor M10 (tenth thin film transistor). Either transistor M2 or M10 can be omitted. The gate of transistor M2 is connected to the transmission line of the reset signal RST and receives the reset signal RST. The source of transistor M2 is connected to the power supply line of the low power supply potential VGL. The drain of transistor M2 is connected to the gates of transistors M3 and M4. Transistor M2 conducts for a predetermined period in each frame period to reset the potential at node Q.

[0095] The gate of transistor M10 is connected to the transmission line of the reset signal RST and receives the reset signal RST. The source of transistor M10 is connected to the power supply line of the low power supply potential VGL. The drain of transistor M10 is connected to the output terminal of the output signal OUT_k. Transistor M10 conducts for a predetermined period within each frame period to reset the potential of the output terminal.

[0096] Figure 8 The time variations of the signals input to the shift register 300, 310 or 320, the potentials at some nodes in its circuit, and its output signal are shown. Specifically, the time variations of the clock signals CK1 and CK2, the output signal OUT_k-1 from the previous stage, the potentials at nodes N1 and N2, the output signal OUT_k, the potentials at nodes Q and QB, and the reset signal are shown. Each interval between the vertically extending dashed lines corresponds to a 1H period (transfer step).

[0097] Hereinafter, the operation of the shift register will be described using the shift register 320 as an example. As described above, Figure 8 the time variations of the signals in

[0098] Apply to the other shift registers 300 and 310. The high-level potential and the low-level potential of the clock signals CK1 and CK2 are respectively substantially equal to the power supply potentials VGH and VGL. Therefore, the power supply potentials VGH and VGL are used in the following description. Although the potentials of the nodes in the shift register 320 can take values slightly different from VGH or VGL, for simplicity of explanation, it is assumed that their potentials are VGL or VGH. Figure 8 and Figure 9A Describe the operation of the shift register 320 in the period from time T11 to time T12. The period from time T11 to time T12 is the reset period of node Q and output OUT_k. Figure 9AShows the ON / OFF state of the transistors in the shift register 320 at time T11. In the following description, the pulse of each signal represents the length of the period during which the signal is at a high level (VGH) to turn on the target transistor.

[0099] Referring to Figure 8 , the clock signal CK1 changes from VGL to VGH at time T11. The pulse width (the length of the high-level period) of the clock signal CK1 is shorter than the 1H period, and the clock signal CK1 changes from VGH to VGL before time T12. The clock signal CK2 remains at VGL from time T11 to time T12. The clock signal CK2 changes from VGL to VGH at time T12.

[0100] The clock signals CK1 and CK2 have the same pulse width and the same period. The pulse widths of the clock signals CK1 and CK2 are shorter than the 1H period; for example, they are 1H / 2 periods. The periods of the clock signals CK1 and CK2 are 2H.

[0101] The input OUT_k-1 from the previous shift register to this shift register remains at VGL from time T11 to time T12. The reset signal RST changes from VGL to VGH at time T11, remains at VGH from time T11 to time T12, and changes from VGH to VGL at time T12.

[0102] Referring to Figure 9A , since the clock signal CK2 is at VGL, the transistor M1 is turned off. Since the reset signal RST is at VGH, the transistors M2 and M10 are turned on. Since VGL is applied to the gates of the transistors M3, M4, and M8 through the transistor M2, the transistors M3, M4, and M8 are turned off. Similarly, as Figure 8 shown, the potential at the node Q is VGL.

[0103] As Figure 8 shown, since the clock signal CK1 changes from VGL to VGH, the potential at the node N1 changes from VGL to VGH due to the capacitive coupling of the capacitive element C2. Therefore, the transistor M5 is turned on. Since the transistor M5 is turned on, the potential at the node N2 is VGL. Therefore, the transistor M7 is turned off. In response to the change in the potential at the node N1, the transistor M6 is turned on, and due to the capacitive element C3, the potential at the node QB becomes VGH. Since the potential at the node QB is VGH, the transistor M9 is turned on.

[0104] As described above, the transistors M2 and M10 are turned on due to the reset signal, so that the potentials at the node Q and the output OUT_k are reset to VGL.

[0105] As Figure 8As shown, the clock signal CK1 changes from VGH to VGL before time T12. Accordingly, the potential at node N1 becomes VGL. Transistors M5 and M6 are turned off. In addition, the potential at node QB becomes VGL, and transistor M9 is turned off. Since the reset signal RST maintains VGH, transistors M2 and M10 remain turned on.

[0106] Next, the operation during the period from time T12 to time T13 is described. The states of the transistors and the changes in the signals during the period from time T14 to time T15 are the same as those during this period, except that the reset signal RST maintains VGL. During this period, node Q is refreshed to VGL. Figure 9B The on / off states of the transistors in the shift register 320 at time T12 are shown.

[0107] Refer to Figure 8 , the reset signal RST changes from VGH to VGL at time T12. Accordingly, transistors M2 and M10 are turned off. The clock signal CK2 changes from VGL to VGH. The clock signal CK1 maintains VGL. The input OUT_k-1 from the previous shift register also maintains VGL.

[0108] In response to the clock signal CK2 becoming VGH, transistor M1 is turned on. Since the input OUT_k-1 from the previous shift register is at VGL, node Q is supplied with VGL (refreshed), and transistor M8 is turned off. Transistors M3 and M4 are also turned off. The potential at node N2 remains at VGL, and transistor M7 is turned off.

[0109] Since the clock signal CK1 is at VGL, the potential at node N1 remains at VGL, and transistors M5 and M6 are turned off. The potential at node QB is VGL, and transistor M9 is turned off. The output OUT_k maintains VGL.

[0110] The clock signal CK2 changes from VGH to VGL before time T13, turning off transistor M1. However, the potentials at nodes N1, N2, Q, and QB in the shift register 320 remain unchanged. The states of the transistors other than transistor M1 also remain unchanged.

[0111] Next, the operation during the period from time T15 to time T16 is described. During this period, the output OUT_k is refreshed to VGL. Figure 9C The on / off states of the transistors in the shift register 320 at time T15 are shown.

[0112] Refer to Figure 8, the clock signal CK1 and the input OUT_k-1 from the previous shift register change from VGL to VGH at time T15. Since the clock signal CK2 remains at VGL regardless of the input OUT_k-1 changing to VGH from the previous shift register, the potential at node Q remains at VGL.

[0113] In response to the clock signal CK1 changing to VGH, the potential at node N1 becomes VGH. Accordingly, transistor M5 turns on. In response to the change at node N1, transistor M6 turns on. Additionally, due to the capacitive element C3, the potential at node QB becomes VGH. Accordingly, transistor M9 turns on, and VGL (refreshed) is supplied to the output OUT_k from the power supply line.

[0114] The clock signal CK1 changes to VGL before time T16. The input OUT_k-1 from the previous shift register remains at VGH. In response to the change in the clock signal CK1, the potential at node N1 becomes VGL. Transistors M5 and M6 turn off. In response to the change in the potential at node N1, the potential at node QB becomes VGL, and transistor M9 turns off. The output line of the output OUT_k is in a floating state, and the output OUT_k remains at VGL.

[0115] Next, the operation in the period from time T16 to time T17 is described. The output OUT_k is inverted from VGL to VGH. Figure 9D The on / off states of the transistors in the shift register 320 at time T16 are shown.

[0116] Refer to Figure 8 , the clock signal CK2 changes from VGL to VGH at time T16. As Figure 9D shown, transistor M1 turns on. Since the input OUT_k-1 from the previous shift register is at VGH, transistor M3 turns on. Since the potential at node N1 remains at VGL, transistor M6 remains off.

[0117] Since the input OUT_k-1 from the previous shift register is at VGH, transistor M4 turns on. Accordingly, the potential at node N2 changes from VGL to VGH. In response to the change in the potential at node N2, transistor M7 turns on. Since the potential at node QB remains at VGL, transistor M9 remains off.

[0118] Since transistor M1 turns on and the input OUT_k-1 from the previous shift register is at VGH, the potential at node Q changes from VGL to VGH. Transistor M8 turns on due to the bootstrap effect of the capacitive element C1, and the output OUT_k changes from VGL to VGH.

[0119] The clock signal CK2 changes from VGH to VGL before time T17. In response, the transistor M1 is turned off. However, the potential at the node Q remains at VGH. In the shift register 320, the node N1 is kept at VGL through the transistor M3, the node N2 is kept at VGH through the transistor M4, and the node QB is kept at VGL through the transistor M7. The states of the transistors other than the transistor M1 remain unchanged. The output OUT_k is kept at VGH through the transistor M8.

[0120] Next, the operation during the period from time T17 to time T18 is described. During this period, the output OUT_k remains at VGH. Figure 9E The on / off states of the transistors in the shift register 320 at time T17 are shown.

[0121] Refer to Figure 8 , the clock signal CK1 changes from VGL to VGH at time T17. The potential at the node Q is VGH (actually, slightly higher than VGH), and the transistors M3 and M4 are turned on as Figure 9E shown. Since the transistor M3 is turned on, the potential at the node N1 remains at VGL. The potential at the node QB also remains at VGL, and the transistor M9 is turned off. The clock signal CK1 changes to VGL before time T18. However, Figure 8 the node potentials in the circuit in

[0122] Next, the operation during the period from time T18 to time T19 is described. During this period, the output OUT_k remains at VGH. The potential at the node Q is refreshed to VGH. Figure 9F The on / off states of the transistors in the shift register 320 at time T18 are shown.

[0123] Refer to Figure 8 , the clock signal CK2 changes from VGL to VGH at time T18, turning on the transistor M1. Since the input OUT_k - 1 from the previous shift register is at VGH, the potential at the node Q is refreshed to VGH. Figure 8 The node potentials in the circuit of

[0124] The clock signal CK2 changes from VGH to VGL before time T19, turning off the transistor M1. Figure 8 The node potentials in the circuit of

[0125] Next, the operations in the period from time T19 to time T20 are described. The clock signal CK1 changes from VGL to VGH at time T19 and also changes from VGH to VGL before time T20. Regardless of the change in the clock signal CK1, Figure 8 the potential of the nodes in the circuit of

[0126] remains unchanged, and the states of the transistors also remain unchanged. Figure 9G The on / off states of the transistors in the shift register 320 at time T20 are shown.

[0127] At time T20, the input OUT_k-1 from the previous shift register changes from VGH to VGL. In response to the clock signal CK2 changing from VGL to VGH, the transistor M1 turns on. Since the input OUT_k-1 from the previous shift register is at VGL, the potential at node Q changes from VGH to VGL. As a result, the transistors M3, M4, and M8 turn off. However, due to the capacitance of the output line, the output OUT_k remains at VGH. The potential at node N1 remains at VGL, and the potential at node N2 remains at VGH.

[0128] The clock signal CK2 changes from VGH to VGL before time T21, causing the transistor M1 to turn off. Figure 8 The potential of the nodes in the circuit of

[0129] remains unchanged, and the states of the other transistors also remain unchanged. The output OUT_k remains at VGH. Figure 9H The on / off states of the transistors in the shift register 320 at time T21 are shown.

[0130] Referring to Figure 8 , the clock signal CK1 changes from VGL to VGH at time T21. As a result, the potential at node N1 changes from VGL to VGH. In response to the change in the potential at node N1, the transistor M5 turns on. The transistor M6 also turns on in response to the change in the potential at node N1.

[0131] When the transistor M5 turns on, node N2 is supplied with VGL from the low-power line, and the potential there changes from VGH to VGL. When the transistor M6 turns on, node QB is supplied with VGH of the clock signal CK1, and the potential there changes from VGL to VGH. In response to the potential at node QB changing from VGL to VGH, the transistor M9 turns on. As a result, the output OUT_k changes from VGH to VGL.

[0132] The clock signal CK1 changes from VGH to VGL before time T22. Accordingly, the potentials at nodes N1 and QB change from VGH to VGL. In response to the potential change at node N1, transistors M5 and M6 are turned off. In response to the potential change at node QB, transistor M9 is turned off. Although the output OUT_k is in a floating state, it remains at VGL due to the capacitance of the output line.

[0133] Next, the operation during the period from time T22 to time T23 is described. During this period, the potential at node Q is refreshed to VGL. The output OUT_k remains at VGL. Figure 9I The on / off states of the transistors in the shift register 320 at time T22 are shown.

[0134] Refer to Figure 8 , the clock signal CK2 changes from VGL to VGH at time T22. As Figure 9I shown, transistor M1 is turned on. Since the input OUT_k-1 from the previous shift register is at VGL, the potential VGL at node Q is refreshed to VGL. Figure 8 The node potentials in the circuit of remain unchanged, and the states of the other transistors also remain unchanged.

[0135] The clock signal CK2 changes from VGH to VGL before time T23. In response to the change in the clock signal CK2, transistor M1 is turned off. Figure 8 The node potentials in the circuit of remain unchanged, and the states of the other transistors also remain unchanged. The output OUT_k remains at VGL.

[0136] Next, the operation during the period from time T23 to time T24 is described. During this period, the output OUT_k at VGL is refreshed to VGL. Figure 9J The on / off states of the transistors in the shift register 320 at time T23 are shown.

[0137] The clock signal CK1 changes from VGL to VGH at time T23. In response to the change in the clock signal CK1, the potential at node N1 changes from VGL to VGH. Transistor M6 is turned on, and the potential at node QB changes from VGL to VGH. In response to the potential change at node QB, transistor M9 is turned on. Transistor M9 supplies VGL from the low-power line to the output line and refreshes the output OUT_k (at VGL) to VGL.

[0138] The clock signal CK1 changes from VGH to VGL before time T24. Accordingly, the potentials at nodes N1 and QB change from VGH to VGL. In response to the potential change at node N1, transistors M5 and M6 are turned off. In response to the potential change at node QB, transistor M9 is turned off. Due to the capacitance of the output line, the output OUT_k is in a floating state and holds VGL. Subsequently, the operations in the period from time T22 to time T24 are repeated until time T11 of the next frame.

[0139] Describe the conduction duty ratio of the transistors in the shift register 320. The conduction duty ratio is the ratio of the period during which a transistor is turned on in the operation of one frame period of the shift register. As described above, transistor M1 is controlled by the clock signal CK2. Transistors M2 and M10 are controlled by the reset signal RST. Transistors M3, M4, and M8 are controlled by the potential at node Q. Transistors M5 and M6 are controlled by the potential at node N1. Transistor M7 is controlled by the potential at node N2. Transistor M9 is controlled by the potential at node QB.

[0140] Since all the transistors in the shift register 320 are n-type transistors, the high duty ratio (H duty ratio) or the ratio of the period during which the gate signal (control signal) is high (at VGH) corresponds to the conduction duty ratio of the transistor.

[0141] Refer to Figure 8 , among the reset signal RST, the clock signals CK1 and CK2, and the potentials at nodes N1, N2, Q, and QB, the clock signals CK1 and CK2 have the longest total VGH period. Although the H duty ratios of the clock signals CK1 and CK2 depend on the length of their clock pulses per 1H period, they are not greater than 50%.

[0142] Next, describe the relationship between the shift registers 300, 310, and 320. Except for the reset signal, Figure 8 the timing diagrams of the signals

[0143] also apply to the shift registers 300 and 310. Figure 6 First, compare the shift register 310 in Figure 7 with the shift register 320 in

[0144] However, the reset signal RST is not input to the shift register 310. That is, the shift register 310 does not require a reset signal. Therefore, the shift register 310 can have a simpler circuit configuration.

[0145] Next, the shift register 300 in Figure 5 is compared with the shift register 320 in Figure 7 . Similar to the shift register 310 in Figure 6 , the shift register 300 does not include the transistors M2 and M10 in the shift register 320. In addition, the shift register 300 includes a transistor M11 in place of the capacitor element C2 in the shift register 320. The transistor M11 is controlled by the clock signal CK1, and one of the source / drain is connected to the high power line and the other is connected to the node N1.

[0146] Describe the operation of the transistor M11. The transistor M11 is turned on / off by the clock signal CK1. Referring to Figure 8 , when the clock signal CK1 changes from VGL to VGH at time T17, the transistor M11 is turned on. However, the node N1 remains at VGL because the transistor M3 remains turned on at the same time. Preferably, the transistor M3 has a low resistance. Specifically, compared with the transistor M11, the transistor M3 can have a low resistance by having a sufficiently wide channel width. However, in this case, a direct current flows from the high power line to the low power line through the transistors M11 and M3.

[0147] On the other hand, Figure 6 the shift register 310 in Figure 7 and the shift register 320 in

[0148] include a capacitor element C2 in place of the transistor M11. This configuration enables the potential at the node N1 to change according to the clock signal CK1 without reducing the impedance, and thus suppresses the direct current.

[0149] The state at time T17 continues until the clock signal CK1 becomes VGL before time T18. The same state also occurs during the period from time T19 to before the clock signal CK1 becomes VGL at time T20. Figures 9H to 9J After time T21, the input OUT_k-1 from the previous shift register is at VGL, and the transistor M3 is turned off (see Figures 9H to 9J)。The potential level at node N1 changes in the same manner as the potential level of clock signal CK1 after time T21. When the clock signal CK1 is at VGH, transistor M11 is turned on, and node N1 is supplied with VGH from the high-power line. When the clock signal CK1 then changes to VGL, the potential at node N1 becomes VGL through the gate capacitances of transistors M11 and M6. This repetitive change in the potential level between VGH and VGL at node N1 reduces the on-duty ratio of transistor M6.

[0150] Figures 10A to 10J shows the time variations of the potentials at the gates, sources, and drains of transistors M1 to M10 operating according to Figure 8 the timing diagram. As Figures 10A to 10J shown, the H duty ratio of the transistors in the shift register is not greater than 27%. The specific description is as follows.

[0151] In Figure 10A , curves 401G, 401S, and 401D represent the time variations of the potentials at the gate, source, and drain of transistor M1. The H duty ratio of transistor M1 is 26.67%. In Figure 10B , curves 402G, 402S, and 402D represent the time variations of the potentials at the gate, source, and drain of transistor M2. The H duty ratio of transistor M2 is 0.04%.

[0152] In Figure 10C , curves 403G, 403S, and 403D represent the time variations of the potentials at the gate, source, and drain of transistor M3. The H duty ratio of transistor M3 is 0.19%. In Figure 10D , curves 404G, 404S, and 404D represent the time variations of the potentials at the gate, source, and drain of transistor M4. The H duty ratio of transistor M4 is 0.19%.

[0153] In Figure 10E , curves 405G, 405S, and 405D represent the time variations of the potentials at the gate, source, and drain of transistor M5. The H duty ratio of transistor M5 is 26.67%. In Figure 10F , curves 406G, 406S, and 406D represent the time variations of the potentials at the gate, source, and drain of transistor M6. The H duty ratio of transistor M6 is 0%.

[0154] In Figure 10G , curves 407G, 407S, and 407D represent the time variations of the potentials at the gate, source, and drain of transistor M7. The H duty ratio of transistor M7 is 0.19%. In Figure 10HAmong them, curves 408G, 408S, and 408D represent the time variations of the potentials at the gate, source, and drain of transistor M8. The H duty cycle of transistor M8 is 0.19%.

[0155] In Figure 10I Among them, curves 409G, 409S, and 409D represent the time variations of the potentials at the gate, source, and drain of transistor M9. The H duty cycle of transistor M9 is 26.67%. In Figure 10J Among them, curves 410G, 410S, and 410D represent the time variations of the potentials at the gate, source, and drain of transistor M10. The H duty cycle of transistor M10 is 0.04%.

[0156] Hereinafter, the relationship between the number of phases of the clock for controlling the scan circuit and the H duty cycle of the signals (including input signals and internally generated signals) of the shift register is described. Figure 11 A partial configuration of a scan circuit (scan circuit 133) controlled by a two-phase clock is shown. Specifically, Figure 11 The (k - 1)-th, k-th, and (k + 1)-th shift registers 350 and the input and output signals of each shift register 350 are shown. Figure 11 The (k - 1)-th shift register with the reference numeral 350 is provided by way of example. The shift register 350 may have Figures 5 to 7 the circuit configuration shown in any of the figures.

[0157] Each shift register 350 includes a first clock terminal CK, a second clock terminal XCK, an input terminal IN, and an output terminal SR. The first clock terminal CK and the second clock terminal XCK receive the first clock signal CK1 or the second clock signal CK2. The input terminal IN receives the output signal from the previous shift register 350. The input terminal IN of the first shift register 350 receives the start signal. The output terminal SR outputs the output signal OUT.

[0158] Figure 12 Shows Figure 11 the time variations of some signals of the shift register in Figure 8 specifically, the time variations of the clock signals CK1 and CK2, the output signal OUT, and the potentials at nodes N1 and QB. Each interval between the dashed lines corresponds to 1H period. The clock signals CK1 and CK2 have a pulse width PW. The time variation of each signal (potential) is the same as the

[0159] Figure 13 A partial configuration of another scan circuit to be controlled by a three-phase clock is shown. Specifically, Figure 13shows the (k-1)th, kth, and (k+1)th shift registers (350_k-1, 350_k, and 350_k+1) and the input and output signals of each shift register. The terminal configuration of each shift register is the same as that of the shift register 350 in Figure 11 Each shift register may have a circuit configuration shown in any of the diagrams in Figures 5 to 7 .

[0160] Each shift register is controlled by a three-phase clock. The first clock terminals CK of three consecutive shift registers receive different clock signals, and their second clock terminals XCK receive different clock signals.

[0161] In the example of Figure 13 , the first clock terminal CK of the (k-1)th shift register 350_k-1 receives the first clock signal CK1, and its second clock terminal XCK receives the second clock signal CK2. The first clock terminal CK of the kth shift register 350_k receives the second clock signal CK2, and its second clock terminal XCK receives the third clock signal CK3. The first clock terminal CK of the (k+1)th shift register 350_k+1 receives the third clock signal CK3, and its second clock terminal XCK receives the first clock signal CK1.

[0162] The input terminal IN of each shift register receives the output signal from the previous shift register. The input terminal IN of the first shift register receives the start signal. The output terminal SR outputs the output signal OUT.

[0163] Figure 14 shows the time variations of the clock signals CK1, CK2, and CK3 and some signals (including node potentials) of the shift register 350_k-1. Specifically, Figure 14 shows the time variations of the clock signals CK1, CK2, and CK3, the output signal OUT_k-1, and the potentials at nodes N1 and QB. The time variation of the potential at node N1 is the same as the time variation of the potential at node QB. Each interval between the dashed lines corresponds to a 1H period. The clock signals CK1, CK2, and CK3 have the same pulse width (the length of one high-level period) PW and the same period.

[0164] The timing diagram showing the time variations of the clock signals CK1, CK2, and CK3 and the signals (including node potentials) of the shift register 350_k is obtained by rewriting CK1, CK2, and CK3 in the timing diagram of Figure 14 as CK2, CK3, and CK1, respectively. The timing diagram showing the time variations of the clock signals CK1, CK2, and CK3 and the signals (including node potentials) of the shift register 350_k+1 is obtained byFigure 14 obtained by rewriting CK1, CK2, and CK3 in the timing diagram of

[0165] That is to say, Figure 14 the uppermost clock signal in

[0166] Figure 13 is the clock signal input to the clock terminal CK, the next clock signal below it is the clock signal output to the clock terminal XCK, and the lowermost clock signal is the clock signal not input to the shift register. Figure 12 The period of each clock signal of the two-phase clock shown is 2H. The clock pulse width PW does not depend on the number of phases of the control clock, but has a finite length not exceeding 1H. During the period when the output OUT is at VGL, the pulse periods at nodes N1 and QB are the same as the period of the clock signal input to the shift register 350.

[0167] As described above, the number of phases of the clock for controlling the shift register in the scan circuit 133 to perform overlapping scanning is two. However, the number of phases of the clock for controlling the scan circuit including multiple shift registers can be any integer m greater than 1. As can be understood from the description provided with reference to Figures 11 to 13 the clock period increases as the number of phases m of the control clock of the scan circuit increases.

[0168] More specifically, the clock period CKP = m × H, where H represents the length of one horizontal period. The pulse width PW of each clock signal is not greater than 1H. Different clock signals have the same pulse width PW and the same clock period CKP, but their phases are different. The phase difference between the two clock signals with the closest phases is 1H.

[0169] The duty ratio H or the ratio of the period when the clock signal is at a high level depends on the pulse width of the clock signal, the number of phases m of the clock of the scan circuit, and one horizontal period H. Specifically, the following formula is established:

[0170] Duty ratio H = PW / mH.

[0171] An increase in the number of phases m of the control clock of the scan circuit extends the clock period CKP = m × H. As with reference to Figure 12 and Figure 13As described above, during the period when the output OUT of the shift register is at the high level (H-level), the potentials at nodes N1 and QB are at the low level (L-level). During the period when the output OUT of the shift register is at the low level, these potentials change in the same manner as the clock signal CK1. That is, the potentials at these nodes have the same pulse width, the same period, and the same phase. In other words, the H duty ratio of nodes N1 and QB is the same as the H duty ratio of the clock signal CK1 during this period. In one frame period, the H duty ratio of nodes N1 and QB is not greater than the H duty ratio of the clock signal CK1.

[0172] Among the signals (potentials) supplied to the gates of the transistors in the shift register, the potentials at nodes N1 and QB have the highest H duty ratio within one frame period. The potential at node N1 is supplied to the gates of transistors M5 and M6, and the potential at node QB is supplied to the gate of transistor M9. Therefore, the conduction duty ratio of transistors M5, M6, and M9 is not greater than PW / mH.

[0173] In one embodiment of the present invention, transistors M5, M6, and M9 in a scan circuit controlled by a clock having two or more phases are configured to have a conduction duty ratio not greater than 1 / 2 (50%). As can be understood from the above description, other transistors have a lower conduction duty ratio than these transistors. In other words, each transistor in the shift register has a conduction duty ratio not greater than PW / mH. This configuration effectively suppresses the deterioration of the characteristics of each transistor and the deterioration of the characteristics of the shift register including these transistors.

[0174] By reducing the H duty ratio of nodes N1 and QB, the conduction duty ratio of transistors M5, M6, and M9 can be reduced. The H duty ratio of nodes N1 and QB can be reduced by shortening the pulse width of the clock signal CK1 or increasing the number of phases of the clock.

[0175] The inventors evaluated the effect of controlling the pulse width of the clock signal on the output of the scan circuit including Figures 5 to 7 the shift register shown. The control clock of the scan circuit is a two-phase clock. As a result, the inventors found that when the pulse width of the clock signal CK1 is too narrow, the shift register cannot generate an appropriate output waveform.

[0176] Figures 15A to 15C Simulation results of the output waveforms of the shift register when the clock signal CK1 has different pulse widths are provided. One horizontal (1H) period is 3 μs. The evaluation by the inventors shows that, as Figures 15A to 15C shown, when the H duty ratio of the clock signal CK1 is 1.3% or higher (the same applies to the clock signal CK2), an appropriate output waveform can be obtained.

[0177] Figure 16 shows another configuration example 330 of the shift register. Compared with the configuration of the shift register 310 shown in Figure 6 , the shift register 330 does not include transistors M4 and M5, and the gate of transistor M7 receives the second clock signal CK2. Other components are the same as those in the shift register 310. Controlling the on / off of transistor M7 with the second clock signal CK2 allows the removal of transistors M4 and M5. Therefore, the circuit size can be reduced with a smaller number of transistors while achieving a low on-duty cycle of the transistors.

[0178] Figure 17 shows Figure 16 the time variations of some signals of the shift register in Figure 8 , specifically, the clock signals CK1 and CK2, the output signal OUT_k-1 of the previous stage, the output signal OUT_k of the current stage, and the time variations of the potentials at nodes N1, Q, and QB. Each interval between the dashed lines corresponds to a 1H period. The clock signals CK1 and CK2 have a pulse width PW. The time variation of each signal (potential) is the same as the corresponding variation in

[0179] Figure 18 shows another configuration example 370 of the shift register. Compared with the configuration of the shift register 310 shown in Figure 6 , Figure 6 in the shift register 310, the n-type thin-film transistors M1 to M9 are replaced by p-type thin-film transistors M21 to M29. In addition, the inputs of the power supply potentials VGL and VGH are replaced with each other. Specifically, the power supply potential VGL is input to the drain of transistor M28, and the power supply potential VGH is input to the sources of transistors M23, M25, M27, and M29. Similarly, Figure 5 , Figure 7 and Figure 16 the transistors in the shift register shown in

[0180] Figure 19 shows Figure 18 the time variations of some signals of the shift register in Figure 8 , specifically, the clock signals CK1 and CK2, the output signal OUT_k-1 of the previous stage, the output signal OUT_k of the current stage, and the time variations of the potentials at nodes N1, N2, Q, and QB. Regarding the high and low levels, the time variation of each signal (potential) is opposite to the corresponding variation in

[0181] For example, the low duty cycles of the clock signals CK1 and CK2 are expressed as PW / mH, where PW represents the pulse widths of the clock signals CK2 and CK1, and H represents a horizontal period. The conduction duty cycle of the thin film transistor is not greater than PW / mH. The low duty cycle may not be less than 1.3%.

[0182] As described above, embodiments of the present invention have been described; however, the present invention is not limited to the above embodiments. Those skilled in the art can easily modify, add, or replace each element of the above-described embodiments within the scope of the present invention. A part of the configuration of one embodiment can be replaced with the configuration of another embodiment, or the configuration of one embodiment can be incorporated into the configuration of another embodiment.

Claims

1. A scanning circuit, the scanning circuit being configured to output a gate signal to a pixel circuit of a display panel, the scanning circuit comprising: Multiple shift registers connected in series, The scanning circuit is configured to be controlled by an m-phase clock signal, wherein m is an integer greater than 1. The plurality of shift registers are configured to output high-level pulses having a length greater than or equal to two horizontal periods one after another with a transfer step length of one horizontal period, Each of the plurality of shift registers is configured to be controlled by a two-phase clock signal, wherein the two-phase clock signal is composed of a first clock signal and a second clock signal in the m-phase clock signal. Wherein, all thin film transistors in each of the plurality of shift registers have the same conductivity type, Wherein, each of the plurality of shift registers comprises: a high-level output thin film transistor, the high-level output thin film transistor comprising a source connected to the output terminal of the shift register and a drain connected to a high-power line; a low-level output thin film transistor including a drain connected to an output terminal of the shift register and a source connected to a low-power line; and a buffer thin film transistor including one of source / drain terminals for receiving the first clock signal and the other of the source / drain terminals connected to a gate of the low-level output thin film transistor, The buffer thin film transistor is configured to receive a control signal having the same pulse width and period as the first clock signal at the gate of the buffer thin film transistor during a period when the output terminal outputs a low level potential, wherein the high duty cycle of the first clock signal and the second clock signal is expressed as PW / mH, wherein PW represents the pulse width of the first clock signal and the second clock signal, H represents a horizontal period, and The on-duty ratio of all thin film transistors is no greater than PW / mH.

2. The scanning circuit according to claim 1, in, The buffer thin film transistor is a first buffer thin film transistor, and Wherein, the scanning circuit further includes: a second buffer thin film transistor, the second buffer thin film transistor comprising a source connected to the low power line and a drain connected to the gate of the low level output thin film transistor; a first thin film transistor, the first thin film transistor including one of a source / drain for receiving a signal from a previous shift register and the other of the source / drain connected to a gate of the high-level output thin film transistor, the first thin film transistor being configured to be controlled by the second clock signal; a third thin film transistor, the third thin film transistor comprising a gate connected to the gate of the high-level output thin film transistor and a source connected to the low-power line; a fourth thin film transistor including a gate connected to the gate of the high-level output thin film transistor, a drain connected to the high-power line, and a source connected to the gate of the second buffer thin film transistor; and a fifth thin film transistor including a gate connected to the gate of the first buffer thin film transistor, a source connected to the low-power line, and a drain connected to the gate of the second buffer thin film transistor.

3. The scanning circuit according to claim 1, in, The buffer thin film transistor is a first buffer thin film transistor, and Wherein, the scanning circuit further includes: a second buffer thin film transistor, the second buffer thin film transistor comprising a source connected to the low power line, a drain connected to the gate of the low level output thin film transistor, and a gate for receiving the second clock signal; a first thin film transistor including one of a source / drain for receiving a signal from a previous shift register and the other of the source / drain connected to a gate of the high-level output thin film transistor, the first thin film transistor being configured to be controlled by the second clock signal; and a third thin film transistor including a gate connected to the gate of the high-level output thin film transistor and a source connected to the low-power line.

4. The scanning circuit according to claim 2 or 3, wherein: The gate of the first buffer thin film transistor is also connected to the transmission line of the first clock signal through a capacitor element.

5. The scanning circuit according to claim 2 or 3, further comprising: a second thin film transistor including a source connected to the low power line and a drain connected to the gate of the high level output thin film transistor, The second thin film transistor is configured to be turned on for a predetermined period in each frame period.

6. The scanning circuit according to claim 2 or 3, further comprising: a sixth thin film transistor including a source connected to the low-power line and a drain connected to the output terminal, The sixth thin film transistor is configured to be turned on for a predetermined period in each frame period.

7. The scanning circuit according to claim 5, further comprising: a sixth thin film transistor including a source connected to the low-power line and a drain connected to the output terminal, The sixth thin film transistor is configured to be turned on for a predetermined period in each frame period.

8. The scanning circuit according to claim 7, wherein: The gate of the first buffer thin film transistor is also connected to the transmission line of the first clock signal through a capacitor element.

9. The scanning circuit according to claim 1, wherein: m is not less than 3.

10. The scanning circuit according to claim 1, wherein: The high duty cycle is not less than 1.3%.

11. A scanning circuit, the scanning circuit being configured to output a gate signal to a pixel circuit of a display panel, the scanning circuit comprising: Multiple shift registers connected in series, The scanning circuit is configured to be controlled by an m-phase clock signal, wherein m is an integer greater than 1. wherein the plurality of shift capacitors are configured to output low-level pulses each having a length greater than or equal to two horizontal periods one after another with a transfer step length of one horizontal period, Each of the plurality of shift registers is configured to be controlled by a two-phase clock signal, wherein the two-phase clock signal is composed of a first clock signal and a second clock signal in the m-phase clock signal. Wherein, all thin film transistors in each of the plurality of shift registers have the same conductivity type, Wherein, each of the plurality of shift registers comprises: a high-level output thin film transistor, the high-level output thin film transistor comprising a drain connected to the output terminal of the shift register and a source connected to a high-power line; a low-level output thin film transistor including a source connected to an output terminal of the shift register and a drain connected to a low-power line; and a buffer thin film transistor including one of source / drain terminals for receiving the first clock signal and the other of the source / drain terminals connected to a gate of the low-level output thin film transistor, The buffer thin film transistor is configured to receive a control signal having the same pulse width and period as the first clock signal at the gate of the buffer thin film transistor during a period when the output terminal outputs a low level potential, The low duty cycle of the first clock signal and the second clock signal is expressed as PW / mH, wherein PW represents the pulse width of the first clock signal and the second clock signal, H represents a horizontal period, and The on-duty ratio of all thin film transistors is no greater than PW / mH.

12. The scanning circuit according to claim 11, in, The buffer thin film transistor is a first buffer thin film transistor, and Wherein, the scanning circuit further includes: a second buffer thin film transistor, the second buffer thin film transistor comprising a drain connected to the low power line and a source connected to the gate of the low level output thin film transistor; a first thin film transistor, the first thin film transistor including one of a source / drain for receiving a signal from a previous shift register and the other of the source / drain connected to a gate of the high-level output thin film transistor, the first thin film transistor being configured to be controlled by the second clock signal; a third thin film transistor, the third thin film transistor comprising a gate connected to the gate of the high-level output thin film transistor and a drain connected to the low-power line; a fourth thin film transistor including a gate connected to the gate of the high-level output thin film transistor, a source connected to the high-power line, and a drain connected to the gate of the second buffer thin film transistor; and a fifth thin film transistor including a gate connected to the gate of the first buffer thin film transistor, a drain connected to the low-power line, and a source connected to the gate of the second buffer thin film transistor.

13. The scanning circuit according to claim 11, in, The buffer thin film transistor is a first buffer thin film transistor, and Wherein, the scanning circuit further includes: a second buffer thin film transistor, the second buffer thin film transistor comprising a drain connected to the low power line, a source connected to the gate of the low level output thin film transistor, and a gate for receiving the second clock signal; a first thin film transistor including one of a source / drain for receiving a signal from a previous shift register and the other of the source / drain connected to a gate of the high-level output thin film transistor, the first thin film transistor being configured to be controlled by the second clock signal; and a third thin film transistor including a gate connected to the gate of the high-level output thin film transistor and a drain connected to the low-power line.

14. The scanning circuit according to claim 11, wherein: m is not less than 3.

15. The scanning circuit according to claim 11, wherein: The low duty cycle is not less than 1.3%.

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