Semiconductor module and inkjet recording element substrate

Abstract

The invention provides a semiconductor module and an ink jet recording element substrate. The semiconductor module includes: a semiconductor substrate; a transistor disposed on the semiconductor substrate and connected to a first terminal having a first potential; an anti-fuse element connected between a second terminal having a second potential different from the first potential and the transistor; and a noise detection circuit electrically connected to the second terminal and configured to detect noise and output a detection signal. The transistor can be turned off based on the detection signal output from the noise detection circuit.

Description

Technical Field

[0001] The present invention relates to a semiconductor component and an inkjet recording element substrate. Background Art

[0002] A liquid discharge device for discharging liquid and performing recording on a recording medium such as paper generally has a liquid discharge head including a substrate. On such a substrate of the liquid discharge head, a semiconductor component including an anti-fuse element can be mounted. The semiconductor component is used to record product-specific information such as a chip identifier (ID) or set parameters after the product is completed. The anti-fuse element is also referred to as an OTP (one-time programmable) memory because of its characteristic of being able to perform recording only once. For example, Japanese Patent Application Laid-Open No. 2022-138607 shows a configuration using an anti-fuse element.

[0003] Japanese Patent Application Laid-Open No. 2022-138607 discloses a semiconductor component including a voltage application circuit that supplies a voltage for performing writing on the anti-fuse element. By adopting the voltage application circuit, it is possible to switch whether to apply the power supply voltage applied to the electrode pad to the anti-fuse element through a switching circuit. However, a high-frequency voltage that enters the surge electrode due to a so-called noise such as electrostatic discharge or lightning surge outside the semiconductor component is transmitted through the voltage application circuit, which may cause incorrect writing to the anti-fuse element. Summary of the Invention

[0004] The present invention has been completed in view of the above problems. An object of the present invention is to prevent incorrect writing to the anti-fuse element due to noise intrusion in a semiconductor component having an anti-fuse element.

[0005] The present invention provides a semiconductor component, which includes:

[0006] a semiconductor substrate;

[0007] a transistor disposed on the semiconductor substrate and connected to a first terminal having a first potential;

[0008] an anti-fuse element connected between a second terminal having a second potential different from the first potential and the transistor; and

[0009] a noise detection circuit electrically connected to the second terminal and configured to detect noise and output a detection signal,

[0010] wherein the transistor is configured to be cut off based on the detection signal output from the noise detection circuit.

[0011] The present invention also provides an inkjet recording element substrate, which includes:

[0012] A semiconductor substrate;

[0013] A semiconductor component disposed on the semiconductor substrate, having a transistor, an anti-fuse element, and a noise detection circuit, wherein the transistor is disposed on the semiconductor substrate and connected to a first terminal having a first potential, the anti-fuse element is connected between a second terminal having a second potential different from the first potential and the transistor, the noise detection circuit is electrically connected to the second terminal and configured to detect noise and output a detection signal, and the transistor is configured to be turned off based on the detection signal output from the noise detection circuit; and

[0014] A recording element disposed on the semiconductor substrate for giving energy to a liquid and discharging the liquid,

[0015] wherein product information of the inkjet recording element substrate is recorded on the anti-fuse element.

[0016] According to the present invention, it is possible to prevent miswriting of the anti-fuse element due to noise intrusion in a semiconductor component having an anti-fuse element.

[0017] Other features of the present invention will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A An example of a circuit structure for protecting a memory from external noise of a semiconductor substrate is shown.

[0019] Figure 1B An example of a structure of a voltage application circuit is shown.

[0020] Figure 1C An example of a structure in which a voltage application circuit performs reading and writing is shown.

[0021] Figure 1D An example of a circuit structure for protecting a memory from external noise of a semiconductor substrate is shown.

[0022] Figure 1E An example of a circuit structure for protecting a memory from external noise of a semiconductor substrate is shown.

[0023] Figure 2A A graph showing an example of an operating waveform of a noise protection circuit is shown.

[0024] Figure 2B A graph showing an example of an operating waveform of a noise protection circuit is shown.

[0025] Figure 3It is a schematic diagram of a device cross-sectional structure for implementing the capacitor and driving element of the present invention.

[0026] Figure 4A An example of the arrangement of inkjet recording elements of an exemplary memory protection circuit is shown.

[0027] Figure 4B An example of the arrangement of a substrate of inkjet recording elements of an exemplary memory protection circuit is shown.

[0028] Figure 5 An example of the structure of a memory write circuit of a comparative example is shown. Detailed Description of Specific Embodiments

[0029] Hereinafter, preferred embodiments of the present invention will be described in detail exemplarily with reference to the accompanying drawings. However, unless otherwise specified, the scope of the present invention is not limited to the dimensions, materials, shapes, relative arrangements, etc. of the constituent components described in the embodiments. In addition, unless otherwise specified, regarding the materials, shapes, etc. of the components described in the following description, they are the same as those in the initial description. In particular, well-known techniques or known techniques in the technical field can be applied to structures or steps that are not shown or described. In addition, repeated descriptions may be omitted.

[0030] Example 1

[0031] (Circuit Structure)

[0032] Figure 1A An example of the circuit structure of a semiconductor component is shown, and the state before writing information into the antifuse element Ca is shown.

[0033] The semiconductor component of this embodiment has a storage unit 10, and the storage unit 10 has a transistor MP1, a transistor MN1, a transistor MND1, and an antifuse element Ca. The antifuse element Ca is an element that has a first resistance value before writing information and a second resistance value smaller than the first resistance value after writing information. That is, the write operation of information changes the resistance value of the antifuse element Ca. A larger first resistance value is more preferable. Ideally, the first resistance value can be infinite. In addition, it is more preferable that the difference between the first resistance value and the second resistance value is large.

[0034] The antifuse element Ca functions as a capacitive element before information writing and as a resistive element after information writing. Figure 1A The state before writing information into the antifuse element Ca is shown. For this purpose, the antifuse element Ca is represented by the circuit symbol of a capacitive element. This structure enables the antifuse element Ca to hold the written information based on the change in the resistance value.

[0035] In Figure 1AAmong them, transistor MP1 is a P-type transistor, and transistor MN1 is an N-type transistor. In addition, the output signal from a noise detection signal input circuit NAND1 (described later) is input to the gates of transistors MP1 and MN1 respectively.

[0036] In addition, a power supply voltage VDD (for example, 3.3V) is supplied to the source and back gate of transistor MP1. The drain of transistor MP1 is connected to the drain of transistor MN1 and the gate of transistor MND1. The source and back gate of transistor MN1 are grounded to GND. Transistors MP1 and MN1 form a logic circuit ( Figure 1A the inverter in).

[0037] Transistor MND1 is an N-type high breakdown voltage transistor and controls the voltage applied to the antifuse element Ca. Transistor MND1 can be formed of, for example, an N-type metal oxide semiconductor (NMOS) transistor. Here, a high breakdown voltage transistor is a transistor having a higher breakdown voltage than the transistors (such as transistor MP1 or MN1) used in the logic circuit. The high breakdown voltage transistor is preferably formed so that it will not be damaged even when a large voltage (for example, 32V) that cannot be withstood by the transistors of a general logic circuit such as a control unit is applied. In addition, by setting transistors MP1 and MN1 forming the logic circuit as transistors having a lower breakdown voltage than transistor MND1, the logic circuit can operate at high speed.

[0038] The antifuse element Ca is connected to wire B via transistor MND1. For example, an antifuse element having a MOS (metal oxide semiconductor) structure can be used as the antifuse element Ca. The antifuse element Ca is connected to wire A.

[0039] Both wire A and wire B are connection parts for electrically connecting the storage unit 10 to an external circuit, and are terminals for applying a voltage to the antifuse element Ca or measuring the voltage of the antifuse element Ca. For example, the potential of wire A can be set to a high voltage (for example, 32V) when writing information. The drain of transistor MND1 is connected to one terminal of the antifuse element Ca, and the source of transistor MND1 is grounded to GND. The other terminal of the antifuse element Ca is connected to wire A. Wire B (the first terminal) is set at, for example, a ground potential (the first potential).

[0040] The voltage application circuit 11 is a circuit for switching whether to supply the high voltage (the second potential) to be applied to the VH terminal to wire A based on the control signal Sig2. The VH terminal is an external connection terminal of, for example, 32V and corresponds to the second terminal. The voltage application circuit 11 can be configured to include, for example, a P-type high breakdown voltage MOS transistor MPD1 as shown in Figure 1B in.

[0041] The transistor MPD1 can be configured to perform a switching operation based on a control signal Sig4 (as control signal Sig2) to be output from a separately provided write / read control circuit 15, as Figure 1C shown. The write / read control circuit 15 may include a boosting circuit for boosting the logic power supply voltage VDD to the voltage of the control signal Sig4. In addition, when the high voltage to be applied to the VH terminal is higher than the writing voltage of the antifuse element Ca, the voltage application circuit 11 may be configured to include a bucking circuit for reducing the high voltage (e.g., 32V) applied to the VH terminal to the writing voltage (e.g., 24V).

[0042] When reading whether the antifuse element Ca is in a written state, it can be determined by detecting the voltage of the VID terminal electrically connected to the wire C from the outside of the semiconductor component, as Figure 1B shown. Alternatively, as shown in the same drawing, the written state can be detected by the reading circuit 16. When the reading circuit 16 is mounted on the same semiconductor component, the following configuration is preferable: the high breakdown voltage transistor MND3 is connected between the reading circuit 16 and the wire C so that the reading circuit 16 and the wire C can be electrically separated from each other at times other than the reading time.

[0043] As Figure 1C shown, the control signal Sig5 can be output from the write / read control circuit 15 synchronously with the control signal Sig4 for the voltage application circuit 11 as the control signal Sig3 for the transistor MND3. Incidentally, when the high breakdown voltage MOS transistors MPD1 and MND3 are turned on simultaneously, the voltages output from the voltage application circuit 11 and the reading circuit 16 may interfere with each other, resulting in a failure. In addition, when the reading circuit 16 is configured to include a low breakdown voltage transistor used in a logic circuit, the high voltage applied from the VH terminal is applied to the low breakdown voltage transistor, which may damage the reading circuit 16. For this reason, it is necessary to control the write / read control circuit 15 to prevent the high breakdown voltage MOS transistors MPD1 and MND3 from being turned on simultaneously.

[0044] Next, with reference to Figure 1B , the operation for writing information into the antifuse element Ca will be described. When writing information into the antifuse element Ca, the transistor MPD1 of the voltage application circuit 11 is turned on. Accordingly, the high voltage (e.g., 32V) applied to the VH terminal is applied to the wire C connected to the antifuse element Ca. At this step, it is necessary to turn off the transistor MND3 so that the reading circuit 16 and the wire C are in an electrically separated state (high impedance).

[0045] Then, the control signal Sig1 corresponding to the antifuse element Ca to be written is set to a high level (e.g., 3.3 V) to turn on the transistor MND1. Here, the control signal Sig1 and the detection signal Vgn1 output from the noise detection circuit 12 described later are input to the noise detection signal input circuit NAND1. In addition, during normal times other than the time when noise is detected, the detection signal Vgn1 output from the noise detection circuit 12 is at a high level. Therefore, the wire E at the output terminal of the noise detection signal input circuit NAND1 becomes low level (e.g., ground potential), and a high-level signal is output from the node Vga, turning on the transistor MND1. As a result, the high voltage applied to the wire C is applied to the gate insulating film of the antifuse element Ca. As a result, the gate insulating film of the antifuse element Ca suffers dielectric breakdown, causing the resistance value of the antifuse element Ca to decrease significantly. Therefore, before writing, the antifuse element Ca is a capacitive element. In contrast, after writing, the antifuse element Ca becomes a resistive element.

[0046] Next, with reference to Figure 1B , the information reading operation when the reading circuit 16 and the antifuse element Ca are mounted on the same semiconductor component will be described. Before performing information reading, it is necessary to turn off the transistor MPD1 so that the VH terminal is electrically separated (high impedance) from the wire C connected to the antifuse element Ca. In addition, the transistor MND3 is turned on so that the reading circuit 16 and the wire C are electrically connected to each other.

[0047] In this state, the control signal Sig1 corresponding to the antifuse element Ca to be used for information reading is set to a high-level signal, turning on the transistor MND1. As a result, a reading current Iread is supplied from the reading circuit 16 to the antifuse element Ca. Here, the reading voltage Vread of Iread×Ra is input to the voltage comparator provided in the reading circuit 16 via the wire C, where Ra represents the resistance of the antifuse element Ca. The reading voltage Vread is compared with the comparison reference voltage Vref. When the reading voltage Vread is larger, a high-level signal is output to the output terminal OUT. When Vread is smaller, a low-level signal is output.

[0048] The antifuse element Ca generally includes an insulating film. For this reason, in the unwritten state, the resistance value is large. When writing is performed, the insulating film is damaged, resulting in a conductive state. Therefore, the resistance value decreases. In the case of the exemplary reading circuit, a high-level signal is output in the unwritten state, and a low-level signal is output in the written state. However, an inverter can be added to the output stage of the voltage comparator in the reading circuit 16 to achieve reverse logic. Incidentally, the reading circuit 16 can be constructed by a method different from the method of detecting the resistance value by a current source mentioned in this example.

[0049] On the other hand, during the product manufacturing process or in the usage environment, due to electrostatic discharge (ESD), lightning surges in the AC 100V power supply entering the building, etc., extremely large surge voltages may enter the semiconductor component from the VH terminal. In particular, consider the following situation: during information reading, although Figure 1B the transistor MPD1 shown in is in the cut-off state, when a surge voltage is applied to the VH terminal, the surge voltage will enter the wire C via the parasitic capacitance Cp formed on the semiconductor substrate.

[0050] In this step, the transistor MND3 is in the conducting state. For this reason, a high-voltage surge voltage may be applied to the reading circuit 16, resulting in damage. In addition, in this step, the transistor MND1 is conducting, that is, the lower electrode of the anti-fuse element Ca is grounded to GND. For this reason, even if a relatively small surge voltage equivalent to the breakdown voltage of the insulating film of the anti-fuse element Ca (about 10V) is applied to the upper electrode of the anti-fuse element Ca, writing will be performed. As a result, the anti-fuse element Ca that should not be written may be written, and thus the information recorded in the semiconductor component may be changed. In addition, during the electrical measurement in the factory inspection step of the product, for example, during the integrity confirmation of the anti-fuse element Ca or the operation confirmation of the reading circuit, the same problem may occur.

[0051] (Conventional structure)

[0052] Figure 5 A specific circuit diagram with a conventional structure is shown. The voltage application circuit 211 generally includes a transistor. Figure 5 An example in which the voltage application circuit 211 includes a MOS transistor is specifically shown. By turning off the MOS transistor MP202 at other times than the writing time, the anti-fuse element Ca is electrically separated from the power supply pad VH. For this reason, operations different from writing, such as reading determination by a separately provided reading circuit 212, can be performed.

[0053] Here, in an environment where the power supply / ground voltage is stable, the MOS transistor MP202 can normally maintain the cut-off state. However, when a high-frequency voltage or surge voltage due to electrostatic discharge, lightning surge, etc. received from outside the semiconductor component enters the power supply pad VH, the surge voltage may be transmitted through the MOS transistor MP202 due to the parasitic capacitance Cp201 formed in the MOS transistor MP202, etc. In particular, if a surge voltage enters the wire Z during the reading operation, it may cause damage to the reading circuit 212 or incorrect writing to the anti-fuse element Ca.

[0054] (Effect of the structure of the example of the present invention)

[0055] In this case, in the present invention, as Figure 1A shown in, a noise detection circuit 12 is connected near the VH terminal where the noise voltage enters. The noise detection circuit 12 is configured to output a detection signal Vgn1 to turn off the transistor MND1 when noise is detected. In the semiconductor substrate, the noise detection circuit 12 is arranged at least at a position closer to the VH terminal as an external connection terminal than the positions where the voltage application circuit 11 and the antifuse element Ca are arranged.

[0056] In this example, the detection signal Vgn1 and the control signal Sig1 are input to the noise detection signal input circuit NAND1. The noise detection circuit 12 outputs a detection signal Vgn1 at a high level during normal times, and outputs a detection signal Vgn1 at a low level when noise is detected. As a result, during normal times, the inverted data of the control signal Sig1 is input to the memory module (storage unit 10), and thus the transistor MND1 is controlled according to the control signal Sig1.

[0057] On the other hand, when the noise voltage that has entered from the VH terminal is detected, the noise detection circuit 12 outputs a detection signal Vgn1 at a low level. Inputting the signal at a low level to one terminal of the noise detection signal input circuit NAND1 causes a signal at a high level to be output from the noise detection signal input circuit NAND1 to the wire E regardless of the voltage of the control signal Sig1. Therefore, a signal at a high level is input to the storage unit 10, so that the transistor MND1 is normally in an off state.

[0058] Therefore, when a signal at a high level is input to the control signal Sig1 to turn on the transistor MND1 during a read operation of the antifuse element Ca, a factory inspection step, etc., if noise or a surge voltage enters, the transistor MND1 is also turned off. That is, the lower electrode of the antifuse element Ca is in a high impedance state. For this reason, no high voltage is applied across the antifuse element Ca. Therefore, writing operations at times when writing operations to the antifuse element Ca are not desired are suppressed. Therefore, changes in the information recorded in the semiconductor component at unexpected times can be suppressed. Incidentally, here, the noise detection signal input circuit NAND1 is used as a combinational circuit. However, the present invention is not limited to this, and any combinational circuit can be used as long as it can achieve the same function.

[0059] Referring to Figure 1B the circuit diagram of Figure 2ADescribe a more detailed voltage waveform. The noise voltage applied to the VH terminal is represented by the VH waveform, and the voltage across the anti-fuse element Ca is represented by the Vca waveform. A voltage serving as a write voltage is supplied to the VH terminal. In a steady state, a high voltage (e.g., 32V) is applied to the VH terminal. However, when reading information, the transistor MPD1 of the voltage application circuit 11 is in an off state. For this reason, the voltage value of the wire C becomes 0V, or a value equal to the read voltage value of the anti-fuse element Ca.

[0060] Here, it is assumed that a noise voltage of several tens of megahertz with a peak value of 60V is applied to the VH terminal. In this case, the high-frequency component is transmitted to the wire C via the parasitic capacitance Cp. Here, when no countermeasure against noise is taken specifically (in the case of the related art), the voltage across the anti-fuse element Ca may reach a voltage of 15V, as indicated by the dotted line in the Vca waveform. When the breakdown voltage of the insulating film of the anti-fuse element Ca is assumed to be, for example, 10V (represented by the broken line for the Vca waveform), writing to the anti-fuse element Ca is performed.

[0061] On the other hand, when a countermeasure against noise as in this example is taken, the high-frequency component of the noise voltage is transmitted through the noise detection capacitor Cn1 (capacitive element) in the noise detection circuit 14 (corresponding to Figure 1A the noise detection circuit 12 in Figure 2A such that the voltage increases as the noise detection signal Vgn2 increases as shown in the Vgn2 waveform in Figure 2A During the period (the operation time of the inverter INV2) when the noise detection signal Vgn2 exceeds the threshold voltage Vth (represented by the broken line for the Vgn2 waveform) at which the inverter INV2 in the noise detection circuit 14 operates, the inverter INV2 outputs a signal at a low level and supplies it to one end of the noise detection signal input circuit NAND1. As a result, the transistor MND1 is turned off, and the potential difference across the anti-fuse element Ca is suppressed. For this reason, as shown by the solid line in the Vca waveform in Figure 2A the increase in the voltage across the anti-fuse element Ca is suppressed. As a result, the voltage across the anti-fuse element Ca can be kept lower than the breakdown voltage of the insulating film of the anti-fuse element Ca (e.g., 10V). Therefore, it is possible to prevent incorrect writing to the anti-fuse element Ca due to the noise voltage entering from the VH terminal.

[0062] Incidentally, the noise detection circuit 14 is provided with a pull-down resistor Rn1 (first resistive element) in order to prevent the inverter INV2 from operating in a state where no noise enters (i.e., a steady state where the voltage is stable). In addition, preferably, a protection diode that is usually used as a protection element is connected between the VH terminal and the ground GND in order to prevent the element from being broken down due to the noise voltage.

[0063] Incidentally, as inFigure 1C As shown, it is more preferably structured as follows: A resistor Rp (third resistor element) is connected in parallel with the antifuse element Ca to prevent information from being erroneously written to the antifuse element Ca. Specifically, it is possible to prevent the following situation: When a write voltage (e.g., 32 V) is applied to the wire D, although the memory driving transistor MND1 is in the non-conducting state, a high voltage is also applied across the antifuse element Ca, resulting in a write state.

[0064] (Cross-sectional structure)

[0065] Figure 3 Shows including Figure 1C A specific example of the cross-sectional structure of the semiconductor substrate 110 including the antifuse element Ca, the resistor element Rp, and the transistor MND1 shown in

[0066] In the semiconductor substrate 110, a P-well region 101 and N-well regions 102a, 102b, and 102c are formed on the P-type silicon substrate 100. The P-well region 101 can be formed by the same steps as those for forming the P-well of the NMOS transistor constituting the logic circuit. In addition, the N-well regions 102a, 102b, and 102c can be formed by the same steps as those for forming the N-well of the PMOS transistor constituting the logic circuit.

[0067] Incidentally, the impurity concentration of the N-well region with respect to the P-type silicon substrate 100 is set such that each breakdown voltage between the N-well regions 102a, 102b, and 102c and the P-type silicon substrate 100 is higher than the high voltage VID. In addition, the impurity concentration of each of the P-well region 101 and the N-well regions 102a, 102b, and 102c is set such that each breakdown voltage between the P-well region 101 and the N-well regions 102a and 102b is higher than the high voltage VID.

[0068] In the P-well region 101 and the N-well regions 102a, 102b, and 102c, a field oxide film 103, high-concentration N-type diffusion regions 106a to 106e, and a high-concentration P-type diffusion region 107 are formed. The field oxide film 103 can be formed by, for example, the local oxidation of silicon (LOCOS, Local Oxidation of Silicon) method.

[0069] The structure of the transistor MND1, which is a high breakdown voltage NMOS transistor, will be described below. The gate electrode 105a is disposed across the gate insulating film 104 on the adjacent P-well region 101 and N-well region 102a. The region where the P-well region 101 overlaps with the gate electrode 105a becomes the channel formation region.

[0070] The high concentration N-type diffusion region 106a is the source of the transistor MND1, and the high concentration P-type diffusion region 107 is the back gate electrode. The N-well region 102a has a portion extending below the gate electrode 105a as an electric field relaxation region of the drain. The high concentration N-type diffusion region 106b formed in the N-well region 102a becomes the drain electrode of the transistor MND1.

[0071] In addition, the transistor MND1 has a structure in which the drain side of the gate electrode 105a extends on the field oxide film 103 formed in the N-well region 102a, that is, a so-called LOCOS offset structure. Therefore, even if the transistor MND1 is in an off state, that is, a state in which the voltage of the gate electrode is the ground potential and the voltage of the drain electrode has increased to the high voltage VID, a high gate-drain breakdown voltage can be ensured.

[0072] The structure of the anti-fuse element Ca will be described below. The anti-fuse element Ca has an upper electrode, a lower electrode, and an insulating layer between the upper electrode and the lower electrode. For example, the electrode 105b disposed on the N-well region 102b via the gate insulating film 104 is used as the upper electrode of the anti-fuse element Ca. In addition, in the N-well region 102b, a portion that is connected to the high-concentration N-type diffusion region 106c and overlaps with the upper electrode in a plan view of the surface of the semiconductor substrate 110 on which an element such as the transistor MND1 is to be disposed is used as a lower electrode. Incidentally, the plan view of the surface of the element such as the transistor MND1, the anti-fuse element Ca, and the resistance element Rp to be disposed is, for example, a plan view of the surface of the channel formation region of the transistor MND1.

[0073] In the accompanying drawings, the high concentration N-type diffusion region 106c is formed only in the region of the N-well region 102b that does not overlap with the upper electrode in a plan view. However, the arrangement of the high concentration N-type diffusion region 106c is not limited thereto. For example, the high concentration N-type diffusion region 106c may be formed in a portion of the portion overlapping with the upper electrode, or in the entire region of the overlapping portion. When the high concentration N-type diffusion region 106c is also formed in the region overlapping with the upper electrode in a plan view, the overlapping portion of the high concentration N-type diffusion region 106c also serves as the lower electrode of the anti-fuse element Ca.

[0074] In addition, in the drawings, the lower electrode of the anti-fuse element Ca is connected to the drain of the transistor MND1. However, the upper electrode may be connected to the drain of the transistor MND1, and the lower electrode may be connected to the high voltage terminal ( Figure 1A The wires shown in A) are connected.

[0075] The gate insulating film 104 can be formed through the formation steps of the gate insulating films of the transistors MP1 and MN1 that constitute the logic circuit. For example, an oxide film can be used as the material for the gate insulating film 104. In addition, the electrodes 105a and 105b can be formed as, for example, polysilicon layers. The polysilicon layer, the high-concentration N-type diffusion regions 106a to 106c, and the high-concentration P-type diffusion region 107 can be formed through the same steps as the formation steps of each element of the transistors MP1 and MN1 that constitute the low breakdown voltage logic circuit.

[0076] Therefore, the antifuse element Ca is a capacitive element having a MOS structure, and the transistor that controls the writing to the antifuse element Ca is a MOS transistor. Thus, the antifuse element Ca and the transistor can be formed through the same steps. For this purpose, the semiconductor component can be formed at low cost with a small number of steps.

[0077] An insulating film having a plurality of contact portions 108 is provided on the high-concentration P-type diffusion region 107, the high-concentration N-type diffusion regions 106a to 106e, and the field oxide film 103. On this insulating film, conductive layers 109a to 109g are provided. The conductive layers 109a to 109g can be formed of a metal such as aluminum, for example. Incidentally, there are no restrictions on the manufacturing process, material, and structure of the conductive layers 109a to 109g and each electrode and wire as long as they can be electrically connected.

[0078] In the drawings, as an example, a capacitive element including a lower electrode and an upper electrode formed of an N-well region and polysilicon, respectively, is shown as the antifuse element Ca. However, the antifuse element Ca is not limited to this structure and can be, for example, a capacitive element using a PMOS transistor. As long as one of the lower electrode and the upper electrode of the antifuse element Ca is used as one terminal and the other is used as the other terminal.

[0079] The resistance element Rp has an N-well region 102c as a semiconductor region in the semiconductor substrate 110 and is connected to the conductive layers 109e and 109f via the high-concentration N-type diffusion regions 106d and 106e, respectively. However, the resistance element Rp is not limited to the structure of this common diffusion resistor. For example, a resistance element of a conductive layer or a resistance element of polysilicon can be used as the resistance element Rp.

[0080] The insulating film is an insulating layer formed on the semiconductor substrate 110 so as to cover the transistor MND1, the resistance element Rp, etc., and is formed of, for example, silicon oxide. In addition, the insulating layer is not limited to this and can be formed of silicon nitride or silicon carbide and can be a laminated or mixed layer thereof.

[0081] The conductive layer 109a is connected to the source and back gate of the transistor MND1 via the contact portion 108, and is supplied with a ground potential. The conductive layer 109c is connected to the drain electrode of the transistor MND1 and the lower electrode of the anti-fuse element Ca via the contact portion 108. The conductive layer 109d is connected to the upper electrode of the anti-fuse element Ca via the contact portion 108, and is connected to the wire A shown in the part not shown Figure 1A at the time of writing, a high voltage (for example, 32V) is applied to the conductive layer 109d via the wire A. The conductive layer 109e is connected to the conductive layer 109c (not shown), and the conductive layer 109f is connected to the conductive layer 109d (not shown).

[0082] Example 2

[0083] Subsequently, Example 2 will be described. The structures identical to those in Example 1 are denoted by the same numerals and symbols, and the description thereof is simplified. The noise detection circuit of this example can drive the noise detection signal input circuit more stably, thereby effectively suppressing the increase in the voltage across the anti-fuse element Ca.

[0084] In Figure 1C the noise detection circuit 17 shown in (corresponding to the noise detection circuit 12 in Figure 1A ), the signal from the noise detection capacitor Cn2 is input to the transistor MN2. The voltage signal Vgn4 obtained by dividing the logic power supply voltage VDD by the pull-up resistor Rn3 (fourth resistance element) and the transistor MN2 (third transistor) is output as the voltage signal Vgn5 after passing through the buffer circuit BUF1. In this example, the noise detection signal input circuit NAND1 is configured to be driven according to the output voltage signal Vgn5.

[0085] A detailed voltage waveform will be described with reference to Figure 2B The noise voltage applied to the VH terminal is represented by the VH waveform. A voltage serving as a write voltage is supplied to the VH terminal. In the steady state, a high voltage (for example, 32V) is applied to the VH terminal. However, at the time of information reading, the transistor MPD1 of the voltage application circuit 11 is in the cut-off state. For this reason, the voltage value of the wire D is 0V, or a value equal to the read voltage value of the anti-fuse element Ca.

[0086] Here, it is assumed that a noise voltage of several tens of megahertz with a peak value of 60V is applied to the VH terminal. In this case, the high-frequency component is transmitted to the wire D via the parasitic capacitance Cp. Here, when no countermeasure against noise is taken in particular (in the case of the related art), the voltage across the anti-fuse element Ca may reach 15V as shown by the dotted line in the Vca waveform. When the breakdown voltage of the insulating film of the anti-fuse element Ca is assumed to be, for example, 10V (represented by the broken line for the Vca waveform), writing to the anti-fuse element Ca is performed.

[0087] On the other hand, in the case of taking countermeasures against noise as in this example, the high-frequency component of the noise voltage is transmitted through the noise detection capacitor Cn2 in the noise detection circuit 17, and its voltage increases as the waveform of the noise detection signal Vgn3 in Figure 2B . Here, during the period (MN2 conduction time) when the noise detection signal Vgn3 exceeds the threshold voltage Vth of the transistor MN2, the transistor MN2 conducts.

[0088] When the transistor MN2 conducts, the voltage signal Vgn4 at the input terminal of the buffer circuit BUF1 becomes 0V, that is, the voltage signal Vgn5 at the input terminal of the noise detection signal input circuit NAND1 becomes 0V. For this reason, the output of the noise detection signal input circuit NAND1 becomes high level, and the transistor MND1 is cut off, thereby suppressing the increase in the voltage across the anti-fuse element Ca. Thereafter, the noise voltage immediately drops. For this reason, the noise detection signal Vgn3 also drops. Subsequently, the transistor MN2 is cut off. However, the input voltage signal Vgn4 of the buffer circuit BUF1 requires a time proportional to the time constant τ = Rn3 × Cinv to transition from the 0V state to the VDD voltage. The time constant τ is determined by the pull-up resistor Rn3 and the capacitance Cinv (not shown) applied to the gate of the buffer circuit BUF1. The voltage signal Vgn4 needs to exceed the threshold voltage (about 1 / 2 of the VDD voltage) to achieve the logic inversion of the buffer circuit BUF1. For this reason, during the period when the voltage signal Vgn4 does not exceed this value, the signal at the low level continues to be input to the noise detection signal input circuit NAND1. For this reason, the transistor MND1 remains cut off, so that the increase in the voltage across the anti-fuse element Ca can be continuously suppressed.

[0089] As an example, when it is assumed that the pull-up resistor Rn3 = 100 kΩ and the additional capacitance Cinv = 1 pF, the time constant τ = 1 μsec is obtained. Therefore, the time until the buffer circuit BUF1 is inverted is about 0.7 μsec. During this period, the signal at the low level may continue to be input to the noise detection signal input circuit NAND1. During this period, for the voltage Vca across the anti-fuse element Ca, the voltage increase can be suppressed, as shown by the solid line. For this reason, the voltage can be kept lower than the breakdown voltage of the insulating film of the anti-fuse element Ca (for example, 10V). Therefore, it is possible to prevent the miswriting of the anti-fuse element Ca caused by the noise voltage entering from the VH terminal.

[0090] In addition, during the period until the noise detection circuit 17 detects noise and supplies a signal at the low level to the noise detection signal input circuit NAND1 and the transistor MND1 is cut off, the noise voltage may be transmitted through the voltage application circuit 11 to reach the wire D. For this reason, the following configuration is preferred: asFigure 1C As shown, a noise delay resistor Rd (second resistor element) is inserted into the output terminal of the voltage application circuit 11 to delay the noise reaching the wire D, as Figure 2B shown by the Vca waveform in; and the transistor MND1 is turned off before the voltage increase of the Vca waveform becomes high. The noise delay resistor Rd may have an effect including reducing the voltage or applying a write current limit when writing to the antifuse element Ca. For this reason, it is preferable to set the noise delay resistor Rd to about several tens of ohms to make these effects small. The noise delay resistor Rd has a relatively small resistance value and can thus be formed of a polysilicon layer or high-concentration N-type diffusion.

[0091] Figure 4A Shows a connection diagram of the recording element Rh, the antifuse element Ca, and the selection circuit 86 when the circuit of this embodiment is mounted on an inkjet recording element substrate. An operation is performed such that the recording element Rh or the antifuse element Ca is exclusively selected according to the logic state of the function selection signal 88 which is an output signal from the selection circuit 86. For a specific bit selection, the selection is performed according to the bit selection signal 87 which is an output signal from the selection circuit 86. In order to transmit the bit selection signal 87, a common signal line is used at the recording element Rh and the antifuse element Ca.

[0092] The output terminal of the noise detection circuit 12 is connected to one terminal of the noise detection signal input circuit NAND1 of the circuit 85 formed by the storage unit 20 (storage module) and the input NAND1 circuit, and the voltage application circuit 11 is provided between the storage unit 20 and the VH terminal.

[0093] Figure 4B Shows an example in which the circuit of this embodiment is arranged on the recording element substrate 81 of an inkjet system. The recording element substrate 81 has an ink supply port 82, an external connection terminal 83b, and a recording element 84, where the ink supply port 82 is for supplying a liquid such as ink. The recording element substrate 81 can preferably be used for an inkjet system recording device (liquid ejection device). By using such a recording element substrate 81, the antifuse element can be used as an OTP memory for recording product information (such as a chip ID or setting parameters) after the product is completed. The recording element 84 has a functional component such as a heating element or a piezoelectric element, and imparts energy to a liquid such as ink to eject it, thereby performing recording.

[0094] In the recording element substrate 81, the storage unit 20 and the noise detection signal input circuit NAND1 are arranged parallel to the arrangement direction of the recording elements 84. The noise detection circuit 12 and the voltage application circuit 11 are arranged in the region between the array group of the external connection terminals 83b and the array group of the recording elements 84. Figure 4A and Figure 4BThe aspects shown above can provide the above effects. However, the arrangement on the substrate is not limited to this.

[0095] The noise detection circuit 12 is preferably arranged near the VH terminal which is an external connection terminal, so that the noise voltage can be detected with good responsiveness and high sensitivity, and more preferably arranged adjacent to the VH terminal. In addition, the selection circuit 86 is arranged in the area between the array group of the external connection terminals 83b and the array group of the recording elements 84. With the above arrangement according to the same drawing, the symmetry of the outer shape of the inkjet recording element substrate can be maintained as much as possible, and the area for wire connection in the substrate can be set smaller.

[0096] Example 3

[0097] This example shows an example in which a plurality of voltage application circuits shown in this embodiment are arranged. Structures identical to those of each example are denoted by the same numbers and symbols, and the description thereof is simplified.

[0098] Figure 1D is a circuit diagram of a semiconductor component according to this example. The semiconductor component has a plurality of storage parts 20, and each storage part 20 includes a capacitive element as an antifuse element Ca, a parallel resistor Rp, and a transistor MND1. The wire E and the wire F are electrically separated from each other. Each wire has its own connection switches MND31 and MND32 between its respective voltage application circuits 110 and 111 and its respective noise detection signal input circuit NAND1 and the reading circuit 160.

[0099] The noise detection circuit 17 can output a noise detection signal Vgn5 at a low level and input it to each noise detection signal input circuit NAND1 respectively. As a result, each noise detection signal input circuit NAND1 outputs a signal at a high level regardless of the voltages of the control signals Sig10 and Sig20. Therefore, a signal at a high level is input to the storage part 20, so that the transistor MND1 is normally in an off state.

[0100] In this embodiment, two voltage application circuits are provided. For this reason, writing to the antifuse element Ca can be performed stably, and thus the writing time can be shortened. Incidentally, in this embodiment, for the sake of description, an example of a semiconductor component having two voltage application circuits is shown. However, if a shorter writing time for the antifuse element Ca is desired within a single time, a large number of voltage application circuits can be included. Similarly, if a shorter reading time for the antifuse element Ca is desired within a single time, a plurality of reading circuits can be included. The configuration of this example can prevent erroneous writing to the antifuse element Ca due to the noise voltage from the VH terminal.

[0101] Example 4

[0102] Subsequently, Example 4 will be described. Structures identical to those of each example are denoted by the same numbers and symbols, and the description thereof is simplified.

[0103] In this example, as Figure 1E shown, on one terminal side of the antifuse element Ca, a high breakdown voltage transistor MND4 controlled only by the control signal Sig1 and a high breakdown voltage transistor MND5 controlled only by the detection signal Vgn1 are connected in series. The transistor MND4 corresponds to the second transistor, and the transistor MND5 corresponds to the first transistor. The transistors MND4 and MND5 are respectively connected to transistors MP2 / MN2 and MP3 / MN3 both having a lower breakdown voltage, thereby forming an inverter of the logic circuit. It is configured such that the control signal Sig1 is input to the gates of the transistors MP2 and MN2 respectively, and the detection signal Vgn1 is input to the gates of the transistors MP3 and MN3 respectively.

[0104] During normal times, the detection signal Vgn1 with a low level output (high level in Example 1) causes the transistor MND5 to conduct. On the other hand, when noise is detected, the detection signal Vgn1 with a high level output (low level in Example 1) causes the transistor MND5 to turn off. In addition, the transistor MND4 turns on / off in response to the control signal Sig1. That is, during normal times, reading or writing to the antifuse element Ca is performed in response to the control signal Sig1. When noise is detected, the transistor MND5 turns off. For this reason, regardless of the value of the control signal Sig1, reading and writing to the antifuse element Ca are not performed.

[0105] Modified Example

[0106] Furthermore, in the aspect of arranging a plurality of antifuse elements Ca as Figure 1C and Figure 1D shown, the ground GND lines connected to the source sides of the corresponding memory driving transistors MND1 can be bundled into one bundle. Then, the bundled lines can be commonly connected to the drain side of one high breakdown voltage transistor MND controlled only by the noise detection signal Vgn1. In the aspect of using the NAND circuits shown in Examples 1 to 3, it is necessary to set a NAND circuit for each antifuse element Ca. In contrast, in this aspect, one high breakdown voltage transistor MND can control reading and writing to all the antifuse elements Ca.

[0107] In Examples 1 to 3 described so far, it is assumed that the noise voltage enters from the VH terminal, and the noise detection circuit 12 is provided to be connected near the VH terminal. However, the present invention is not limited thereto, and a logic power supply terminal or an external connection terminal dedicated to noise detection may be provided. Alternatively, the number of the noise detection terminals and the noise detection circuits is not limited to one, but may be plural.

[0108] As described so far, according to each example of the present invention, the noise detection circuit is arranged near the external connection terminal that is the noise entry end, and the noise detection circuit detects the noise. As a result, by outputting a control signal to turn off the antifuse drive transistor, erroneous writing can be prevented. Therefore, it is possible to suppress erroneous writing caused by external noise or the like that enters via the antifuse writing circuit.

[0109] Although the present invention has been described with reference to the exemplary embodiments, it should be understood that the present invention is not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation so as to include all such modifications as well as equivalent structures and functions.

Claims

1. A semiconductor component, comprising: Semiconductor substrates; A transistor, arranged on the semiconductor substrate and connected to a first terminal having a first potential; an anti-fuse element connected between a second terminal having a second potential different from the first potential and the transistor; as well as a noise detection circuit, electrically connected to the second terminal and configured to detect noise and output a detection signal, The transistor is configured to be turned off based on the detection signal output from the noise detection circuit.

2. The semiconductor component according to claim 1, further comprising: A combination circuit is configured to receive the detection signal output from the noise detection circuit and a control signal for the anti-fuse element, and output a control signal for the transistor to turn off the transistor when the noise detection circuit detects noise.

3. The semiconductor component according to claim 2, wherein: The combinational circuit turns off the transistor when the detection signal output from the noise detection circuit exceeds a threshold voltage.

4. The semiconductor component according to claim 1, wherein The transistor includes a first transistor and a second transistor connected in series, The first transistor is a transistor that is turned off when the noise detection circuit detects noise, and The second transistor is a transistor controlled by a control signal for the anti-fuse element.

5. The semiconductor component according to claim 1, wherein The noise detection circuit includes a capacitance element and a first resistance element connected in series between the second terminal and the first terminal, and outputs a voltage between the capacitance element and the first resistance element as the detection signal.

6. The semiconductor component according to any one of claims 1 to 5, further comprising: A voltage applying circuit is configured to supply a voltage from the second terminal to the anti-fuse element.

7. The semiconductor component according to claim 6, wherein: The voltage application circuit is configured to supply a write voltage to the anti-fuse element.

8. The semiconductor component according to claim 6, wherein: A second resistance element for delaying noise is connected in series to the output terminal of the voltage applying circuit.

9. The semiconductor component according to claim 6, wherein: The voltage applying circuit includes a P-type high breakdown voltage MOS transistor.

10. The semiconductor component according to claim 6, wherein On the semiconductor substrate, the noise detection circuit is arranged at a position closer to the second terminal than positions where the voltage applying circuit and the anti-fuse element are arranged.

11. The semiconductor device according to claim 6, comprising a plurality of said voltage applying circuits.

12. The semiconductor component according to claim 1, further comprising: A third resistance element is connected in parallel with the anti-fuse element between the second terminal and the transistor.

13. The semiconductor component according to claim 12, wherein: The third resistance element is a common diffusion resistor.

14. The semiconductor component according to claim 5, wherein The noise detection circuit further includes a fourth resistance element and a third transistor connected to the first terminal, and The third transistor is configured to be turned on based on the voltage between the capacitance element and the first resistance element.

15. The semiconductor component according to claim 1, further comprising: A read circuit is configured to read a written state of the anti-fuse element.

16. An inkjet recording element substrate, comprising: Semiconductor substrates; a semiconductor component arranged on the semiconductor substrate, having a transistor, an anti-fuse element, and a noise detection circuit, wherein the transistor is arranged on the semiconductor substrate and connected to a first terminal having a first potential; the anti-fuse element is connected between a second terminal having a second potential different from the first potential and the transistor; the noise detection circuit is electrically connected to the second terminal and is configured to detect noise and output a detection signal; the transistor is configured to be turned off based on the detection signal output from the noise detection circuit; and a recording element, arranged on the semiconductor substrate, for imparting energy to the liquid and discharging the liquid, Here, product information of the inkjet recording element substrate is recorded on the anti-fuse element.

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