Flash memory error correction method based on adaptive learning and readable storage medium

Abstract

The application discloses a flash memory error correction method based on adaptive learning and a readable storage medium. The method determines offset steps under different bias types according to historical error correction data, then performs data reading according to a reference voltage and the offset steps to obtain soft data, and finally optimizes the offset steps in real time according to deviation data generated by error correction of the reference data and the soft data, so as to realize dynamic adjustment of the offset steps and voltage offset. Compared with a preset fixed step in a traditional error correction method, the offset steps of the application can be set according to actual conditions of data, so that the error correction process can flexibly adjust bias conditions according to actual states of different flash memory units, effectively adapt to different application scenarios, and effectively reduce the probability of flash memory data reading errors.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a flash memory error correction method based on adaptive learning and a readable storage medium. Background Art

[0002] NAND flash memory (a non-volatile storage technology) stores data by injecting electrons into a floating gate. Due to quantum effects, flash memory cannot precisely control the number of electrons injected into the floating gate, resulting in a normally distributed threshold voltage. Ideally, the voltage distributions of two adjacent memory cells do not overlap, allowing the threshold voltage to determine the data in the memory cell. However, during use, as data is stored for a longer period of time or due to environmental noise, the number of electrons in the memory cell changes, leading to bit flips and random errors, resulting in voltage shift and spread. When the voltage distribution of some memory cells exceeds the threshold voltage range, misjudgment and read errors can occur. When the voltage distributions of adjacent memory cells overlap, simply adjusting the threshold voltage offset cannot correct the actual voltage distribution at the overlapping area. Therefore, flash memory typically uses methods such as rereading to ensure data integrity.

[0003] During the error correction process, flash memory first performs a Read Retry error correction method. This method attempts to correct read errors caused by cell voltage offsets by changing the threshold voltage used in read operations. If the Read Retry error correction method fails, the Soft Retry error correction method is executed. This method uses additional data and an algorithm to perform error correction. The traditional Soft Retry error correction method only adjusts the bias voltage on one side of the reference voltage during the correction process, with a fixed bias step size. This method works well in normal scenarios, but in extreme environments such as high and low temperatures, the flash memory's reference voltage may deviate unpredictably to the left or right, resulting in poor error correction capabilities and adaptability, which can lead to user data errors. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a flash memory error correction method and terminal based on adaptive learning, which can adaptively adjust the bias voltage and step size to reduce the probability of data reading errors.

[0005] In order to solve the above technical problems, a technical solution adopted by the present invention is:

[0006] A flash memory error correction method based on adaptive learning, comprising:

[0007] Acquiring a reference voltage, and reading data according to the reference voltage to obtain reference data;

[0008] Acquiring historical error correction data corresponding to the reference data, and determining offset step sizes of different bias types according to the historical error correction data;

[0009] Reading data based on the offset step size and the reference voltage in a current reading mode to obtain soft data of the different bias types, wherein the number of soft data read in each reading mode is different;

[0010] determining whether error correction is successful in a current reading mode according to the soft data and the reference data;

[0011] If the error correction fails, the current reading mode is switched to the reading mode of the next priority, the offset step is updated according to the deviation data between the reference data and the soft data, and the step of reading data based on the current reading mode according to the offset step and the reference voltage to obtain the soft data of the different bias types is returned to execution until the error correction is successful.

[0012] In order to solve the above technical problems, another technical solution adopted by the present invention is:

[0013] A computer-readable storage medium stores a computer program, which is executed to implement the various steps of the above-mentioned flash memory error correction method based on adaptive learning.

[0014] The present invention has the beneficial effects of obtaining reference data by reading data based on a reference voltage, determining the offset step size under different bias types based on historical error correction data corresponding to the reference data, and thereby obtaining soft data by reading data based on the reference voltage and offset step size. Furthermore, the offset step size can be optimized in real time based on the reference data and the deviation data generated by soft data error correction, achieving dynamic adjustment of the offset step size and voltage offset. Compared to the fixed step size preset in traditional error correction methods, the offset step size of the present invention can be set based on the actual data conditions, allowing the error correction process to flexibly adjust the bias conditions according to the actual state of different flash memory cells, effectively adapting to different application scenarios. Furthermore, since the soft data reflects the data state under different bias types, it can provide more detailed information about the voltage distribution of the memory cells, helping the error correction algorithm to more accurately determine the error location and type. The number of soft data reads represents the error correction capability of the current read mode. Therefore, if the current soft data error correction fails, a read mode with stronger error correction capability can be selected to improve the error correction success rate, thereby effectively reducing the probability of flash memory data read errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Fig. 1 A flowchart of a flash memory error correction method based on adaptive learning provided by an embodiment of the present invention;

[0016] Fig. 2 A threshold voltage distribution diagram of an existing soft retry error correction method;

[0017] Fig. 3 A threshold voltage distribution diagram of a flash memory error correction method based on adaptive learning provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] To illustrate the technical content, achieved objectives and effects of the present invention in detail, the following description is given in conjunction with the embodiments and accompanying drawings.

[0019] An embodiment of the present invention provides a flash memory error correction method based on adaptive learning, comprising:

[0020] Acquiring a reference voltage, and reading data according to the reference voltage to obtain reference data;

[0021] Acquiring historical error correction data corresponding to the reference data, and determining offset step sizes of different bias types according to the historical error correction data;

[0022] Reading data based on the offset step size and the reference voltage in a current reading mode to obtain soft data of the different bias types, wherein the number of soft data read in each reading mode is different;

[0023] determining whether error correction is successful in a current reading mode according to the soft data and the reference data;

[0024] If the error correction fails, the current reading mode is switched to the reading mode of the next priority, the offset step is updated according to the deviation data between the reference data and the soft data, and the step of reading data based on the current reading mode according to the offset step and the reference voltage to obtain the soft data of the different bias types is returned to execution until the error correction is successful.

[0025] As can be seen from the above description, the beneficial effects of the present invention are: data is read based on a reference voltage to obtain reference data, and then the offset step size under different bias types is determined based on the historical error correction data corresponding to the reference data. Thus, data is read based on the reference voltage and offset step size to obtain soft data. Furthermore, the offset step size can be optimized in real time based on the reference data and the deviation data generated by soft data error correction, achieving dynamic adjustment of the offset step size and voltage offset. Compared to the fixed step size preset in traditional error correction methods, the offset step size of the present invention can be set according to the actual data situation, allowing the error correction process to flexibly adjust the bias conditions according to the actual state of different flash memory cells, effectively adapting to different application scenarios. Furthermore, the soft data reflects the data state under different bias types, and therefore can provide more detailed information about the voltage distribution of the memory cells, helping the error correction algorithm to more accurately determine the error location and type. The number of soft data reads represents the error correction capability of the current read mode. Therefore, if the current soft data error correction fails, a read mode with stronger error correction capability can be selected to improve the error correction success rate, thereby effectively reducing the probability of flash memory data read errors.

[0026] Further, according to the offset step size and the reference voltage, performing data reading based on the current reading mode to obtain the soft data of the different bias types includes:

[0027] determining offset voltages of the reference voltage under the different bias types according to the offset step size and the current reading mode;

[0028] Data is read respectively according to the offset voltages of the different bias types to obtain soft data of the different bias types.

[0029] As can be seen from the above description, the offset voltage is dynamically determined in combination with the offset step size and the read mode to ensure that a corresponding amount of soft data can be obtained according to different offset voltages in different read modes, thereby refining the voltage distribution data of the storage cell, providing a more accurate basis for voltage adjustment, further optimizing the error correction process, and improving the success rate and efficiency of error correction.

[0030] Further, determining the offset voltages of the reference voltage under the different bias types according to the offset step size and the current reading quantity includes:

[0031] determining the number of soft data to be read according to the current reading mode;

[0032] A plurality of offset voltages of the reference voltage under the different bias types are determined according to the offset step, and the number of the plurality of offset voltages is the read number.

[0033] As can be seen from the above description, by flexibly adjusting multiple offset voltages according to the number of soft data reads and the offset step size, the voltage adjustment space can be explored more carefully to find a more optimal read threshold combination, thereby improving the overall performance of the system.

[0034] Further, determining a plurality of offset voltages of the reference voltage under the different bias types according to the offset step size includes:

[0035] Under each bias type, the reading number is used as the number of offsets, the reference voltage is cumulatively offset according to the offset step corresponding to the bias type, and the reference voltage after each cumulative offset is marked as an offset voltage.

[0036] As can be seen from the above description, the offset voltage under each bias type is adjusted based on the offset step size corresponding to the bias type, rather than relying on the same step size for all bias types. Adjusting the offsets differently for different bias types allows the system to respond to changes in the memory cell state in real time, ensuring that the optimal read threshold can be found under different conditions. Furthermore, by accumulating offsets, the system can gradually explore the optimal read threshold, rather than simply selecting a fixed offset voltage value. This gradual adjustment method can more accurately locate the bias voltage that best suits the current memory cell state, thereby improving the accuracy and success rate of error correction.

[0037] Furthermore, the reading mode includes a first mode, a second mode and a third mode;

[0038] The priority of the first mode is higher than that of the second mode, and the priority of the second mode is higher than that of the third mode;

[0039] The read quantities of soft data in the first mode, the second mode and the third mode under each voltage offset type are respectively a first value, a second value and a third value, the first value is smaller than the second value, and the second value is smaller than the third value.

[0040] As can be seen from the above description, while reading more soft data improves error correction capabilities, it also requires more reading time. Therefore, dynamically switching between multiple reading modes based on error correction needs can optimize error correction efficiency while ensuring error correction success rates. Low-priority mode is suitable for simple error scenarios, while high-priority mode is used for complex error scenarios. This allows the system to operate efficiently in different situations, balancing performance and resource consumption.

[0041] Furthermore, after the error correction is successful, the following steps are also included:

[0042] The characteristic information of the reference data, the updated offset step length, and the offset voltage determined by the reference voltage based on the updated offset step length are stored in a history database as a set of historical error correction data.

[0043] From the above description, it can be seen that storing successful error correction data as historical experience makes it easier to quickly call relevant data for error correction when similar data errors occur in the flash memory in the future, reducing the time for repeated calculations and attempts, further improving the error correction efficiency, and at the same time providing a richer reference basis for subsequent adaptive adjustments, thereby enhancing the intelligence of the system.

[0044] Further, determining whether error correction is successful in the current reading mode according to the soft data and the reference data includes:

[0045] Performing comprehensive decoding verification on the reference data and all soft data read in the current reading mode;

[0046] If the decoding is successful, the error correction is successful in the current reading mode;

[0047] If decoding fails, error correction fails in the current reading mode.

[0048] As can be seen from the above description, soft data, the data read after adjusting the reference voltage, is different from the baseline data at the reference voltage. Soft data can reflect the state changes of the storage cell under different voltage conditions. Therefore, more soft data means that the algorithm has more reference points to determine the correctness of the data, thereby improving the success rate of error correction.

[0049] Furthermore, obtaining the reference voltage includes:

[0050] Obtaining a preset error correction reference voltage table and reading an effective error correction voltage table of successful errors corrected during retry error correction;

[0051] Determining a storage unit location for performing data error correction;

[0052] Obtaining the effective voltage corresponding to the storage unit position from the error correction effective voltage table;

[0053] If the effective voltage is obtained, determining the effective voltage as a reference voltage;

[0054] If the valid voltage is not obtained, a reference voltage corresponding to the storage unit position is obtained from the error correction reference voltage table.

[0055] From the above description, it can be seen that combining the error correction effective voltage table and the error correction reference voltage table to obtain the reference voltage fully utilizes the historical error correction successful experience and the original factory reference data, can quickly determine the appropriate reference voltage in different situations, improve the accuracy and efficiency of error correction, and enhance the stability and reliability of the system.

[0056] Further, updating the offset step size according to the deviation data between the reference data and the soft data includes:

[0057] The offset step sizes under the different bias types are updated respectively by an adaptive gradient descent method to minimize the deviation data between the reference data and the soft data.

[0058] As can be seen from the above description, the use of adaptive gradient descent method to dynamically adjust the offset step size can optimize the bias adjustment strategy in real time according to the error correction gap between the current benchmark data and soft data, quickly adapt to changes in the storage unit state and the influence of environmental factors, further improve the accuracy and adaptability of error correction, reduce the data read error rate, and enhance the overall performance of the system.

[0059] Furthermore, before obtaining the reference voltage, the method further includes:

[0060] If a read request is received, data is read according to the read request to obtain initial data;

[0061] Decoding and verifying the initial data; if the decoding of the initial data fails, performing error correction processing on the initial data by retrying reading to obtain initial error-corrected data;

[0062] Decoding and verifying the initial error correction data;

[0063] If the initial error correction data is decoded successfully, the initial error correction data is returned;

[0064] If the initial error correction data decoding fails, the step of obtaining the reference voltage is performed.

[0065] As can be seen from the above description, a read retry is performed first when a data read error occurs. Since read retry can quickly reduce the bit error rate without increasing complex calculations, if data error correction can be completed through read retry, there is no need to enter the more complex data error correction stage, which effectively saves computing resources.

[0066] Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. The computer program is executed to implement the various steps in the above-mentioned flash memory error correction method based on adaptive learning.

[0067] From the above description, it can be seen that the beneficial effects of the present invention are: determining the offset step size under different bias types based on historical error correction data, then reading data based on the reference voltage and offset step size to obtain soft data, and finally optimizing the offset step size in real time based on the deviation data generated by the reference data and soft data error correction, thereby realizing dynamic adjustment of the offset step size and voltage offset. Compared with the fixed step size preset in the traditional error correction method, the offset step size of the present invention can be set according to the actual situation of the data, so that the error correction process can flexibly adjust the bias situation according to the actual state of different flash memory units, effectively adapt to different application scenarios, and effectively reduce the probability of flash memory data reading errors.

[0068] The above-mentioned flash memory error correction method and readable storage medium based on adaptive learning of the present invention are applicable to related storage media in some extreme environments, such as high or low temperatures. When the flash memory threshold voltage shifts, the method can adaptively adjust the bias voltage and step size to perform data error correction, thereby reducing the probability of data read errors. The following is an explanation of the specific implementation method:

[0069] Please refer to Figs. 1 to 3 , embodiment 1 of the present invention is:

[0070] like Fig. 1 As shown, a flash memory error correction method based on adaptive learning includes:

[0071] S1. Obtain a reference voltage, and read data according to the reference voltage to obtain reference data.

[0072] Specifically, obtaining the reference voltage in step S1 includes:

[0073] S11, obtaining a preset error correction reference voltage table and reading an error correction effective voltage table of successful error correction in retry error correction;

[0074] S12. Determine the location of the storage unit for data error correction.

[0075] S13. Obtaining a valid voltage corresponding to the storage unit position from the error correction valid voltage table.

[0076] S14: If the effective voltage is obtained, determine the effective voltage as a reference voltage.

[0077] S15. If the valid voltage is not obtained, obtain a reference voltage corresponding to the storage unit position from the error correction reference voltage table.

[0078] The error correction effective voltage table is a dynamic reread table maintained by the flash memory during use. During the read retry phase, all read voltages that successfully correct errors are recorded in this table. In the present invention, when a read failure occurs at different locations within the same plane of the flash memory and the read retry error correction fails, the read voltage from the error correction effective voltage table is preferentially used as the reference voltage for subsequent bias operations.

[0079] The error correction reference voltage table is an original reference table developed by the flash memory manufacturer through testing in a large number of application scenarios. However, it is unknown what specific scenarios each set of voltage values ​​in the original reference table is applicable to. Therefore, it takes multiple attempts to find the voltage value that is suitable for different application scenarios.

[0080] Specifically, before step S1, the method further includes:

[0081] S101: If a read request is received, data is read according to the read request to obtain initial data.

[0082] S102 , decoding and verifying the initial data. If the decoding of the initial data fails, performing error correction processing on the initial data by retrying reading to obtain initial error-corrected data.

[0083] S103: Decode and verify the initial error correction data.

[0084] S104: If the initial error correction data is decoded successfully, return the initial error correction data.

[0085] S105: If the initial error correction data decoding fails, executing the step of obtaining the reference voltage.

[0086] S2. Acquire historical error correction data corresponding to the reference data, and determine offset step sizes of different bias types according to the historical error correction data.

[0087] In some embodiments, the historical error correction data includes characteristic information of historical reference data and a historical offset step that can correctly read the data, wherein the characteristic information includes data characteristics of the reference data, error correction position, storage unit status, etc. Obtaining the historical error correction data corresponding to the reference data specifically involves searching for historical reference data with the same or similar characteristic information, and obtaining the historical offset step corresponding to the historical reference data. The upper offset voltage is obtained by adding the historical offset step to the reference voltage, and the lower offset voltage is obtained by subtracting the historical offset step from the reference voltage. In this way, the bias voltage is adjusted based on the data of the historical offset step, effectively addressing voltage offset problems caused by environmental changes or aging of storage units, improving the pertinence and effectiveness of error correction, and further improving the adaptability and reliability of the system.

[0088] S3. Read data based on the offset step size and the reference voltage in a current reading mode to obtain soft data of different bias types, wherein the amount of soft data read in each reading mode is different.

[0089] Specifically, the read mode includes a first mode, a second mode, and a third mode. The first mode has a higher priority than the second mode, and the second mode has a higher priority than the third mode. The number of soft data read in the first mode, the second mode, and the third mode under each bias type is a first value, a second value, and a third value, respectively, wherein the first value is smaller than the second value, and the second value is smaller than the third value.

[0090] In some embodiments, the first mode is MODE N4, the second mode is MODE N6, and the third mode is MODE N8. In MODE N4, one soft data needs to be read under each bias type, two soft data need to be read under each bias type in MODE N6, and three soft data need to be read under each bias type in MODE N8. Therefore, the corresponding first value, second value, and third value are 1, 2, and 3, respectively.

[0091] It should be noted that when the reference voltage is first obtained for soft retry error correction, the reading mode defaults to the first mode with the highest priority. After the error correction in the first mode fails, it switches to the second mode for error correction; after the error correction in the second mode fails, it switches to the third mode for error correction; if the error correction in the third mode also fails, a prompt message is returned to inform that the current data cannot be read correctly.

[0092] Specifically, step S3 includes:

[0093] S31 , determining offset voltages of the reference voltage under the different bias types according to the offset step size and the current reading mode.

[0094] Specifically, step S31 includes:

[0095] S311 : Determine the read quantity of the soft data according to the current read mode.

[0096] S312 , determining a plurality of offset voltages of the reference voltage under the different bias types according to the offset step, where the number of the plurality of offset voltages is the read number.

[0097] Specifically, step S312 includes: under each bias type, taking the number of reads as the number of offsets, accumulatively offsetting the reference voltage according to the offset step corresponding to the bias type, and marking the reference voltage after each accumulated offset as an offset voltage.

[0098] Taking the first mode, MODE N4, as an example, in MODE N4, the reference voltage needs to be shifted upward once according to the upward shift step size to obtain an upward offset voltage, and the reference voltage needs to be shifted downward once according to the downward shift step size to obtain a downward offset voltage. Taking the second mode, MODE N6, as an example, in MODE N6, the reference voltage needs to be shifted upward twice according to the upward shift step size to obtain two upward offset voltages, and the reference voltage needs to be shifted downward twice according to the downward shift step size to obtain two downward offset voltages. Specifically, the upward shift step size is i (V), the downward shift step size is j (V), i>j>0, and the reference voltage is M (V). In MODE N4, the upward offset voltage is M+i, and the downward offset voltage is Mj. In MODE N6, the upward offset voltages are M+i and M+2i, respectively, and the downward offset voltages are Mj and M-2j, respectively.

[0099] S32 , reading data according to the offset voltages of the different bias types to obtain soft data of the different bias types.

[0100] Taking the first mode MODE N4 as an example, in MODE N4, the upper offset voltage is M+i and the lower offset voltage is Mj. At this time, in MODE N4, data is read based on the upper offset voltage M+i to obtain one soft data set, and data is read based on the lower offset voltage Mj to obtain one soft data set, for a total of two soft data sets. Taking the second mode MODE N6 as an example, in MODE N6, the upper offset voltage is M+i and the lower offset voltage is Mj. At this time, in MODE N6, data is read based on the upper offset voltage M+i to obtain one soft data set, data is read based on the upper offset voltage M+2i to obtain one soft data set, data is read based on the lower offset voltage Mj to obtain one soft data set, and data is read based on the lower offset voltage M-2j to obtain one soft data set, for a total of four soft data sets.

[0101] S4. Determine whether error correction is successful in the current reading mode according to the soft data and the reference data.

[0102] Specifically, step S4 includes:

[0103] S41 , performing comprehensive decoding verification on the reference data and all soft data read in the current reading mode.

[0104] In some embodiments, the reference data and the soft data read in the current reading mode are respectively combined by an XOR calculation or an XOR calculation to form a comprehensive data, and the comprehensive data is decoded and verified.

[0105] S42: If the decoding is successful, the error correction is successful in the current reading mode.

[0106] S43. If the decoding fails, the error correction fails in the current reading mode.

[0107] S5. If the error correction fails, after switching the current read mode to a read mode of the next priority, updating the offset step size according to the deviation data between the reference data and the soft data, and returning to the step of reading data based on the current read mode according to the offset step size and the reference voltage to obtain the soft data of the different bias types until the error correction is successful.

[0108] Specifically, in step S5, updating the offset step size according to the deviation data between the reference data and the soft data includes: updating the offset step sizes under the different bias types respectively by an adaptive gradient descent method to minimize the deviation data between the reference data and the soft data.

[0109] In some embodiments, after error correction fails, the error correction algorithm may determine the difference between the current offset voltage and the ideal offset voltage based on previously corrected historical data and the deviation between the current baseline data and the soft data, thereby updating the offset step size. Specifically, if the soft data read at the current offset voltage still contains a significant number of errors, the error correction algorithm may adjust the offset step size based on the error type and severity of the soft data. For example, the error correction algorithm may determine, by analyzing the error type and severity of the soft data, that some data cannot be correctly read due to an excessively low upper offset voltage. Therefore, the algorithm may appropriately increase the upward offset step size, thereby increasing the upper offset voltage.

[0110] In some embodiments, the offset step size for each bias type is updated based on the reference data corresponding to the deviation data of the soft data read under each bias type. In this way, the soft data of each bias type is comprehensively considered to adjust the offset step size combination. That is, when the data error conditions of the upward-shifted soft data and the downward-shifted soft data are different, it may be necessary to adjust the upper offset voltage and the lower offset voltage simultaneously to balance the accuracy of data reading. For example, if the soft data errors read under the current upper offset voltage are mainly concentrated in certain specific bits, while the soft data errors read under the lower offset voltage are mainly concentrated in other bits, the error correction algorithm will appropriately increase the upper offset voltage and appropriately reduce the lower offset voltage to achieve better error correction effect for the overall data.

[0111] After the error correction is successful, the method further includes:

[0112] S6. Store the characteristic information of the reference data, the updated offset step length, and the offset voltage determined by the reference voltage based on the updated offset step length as a set of historical error correction data in a history database.

[0113] In some embodiments, if soft data read at a certain set of offset voltages is successfully decoded, it indicates successful data error correction, and the upper and lower offset voltages associated with the successful correction are recorded. For example, in MODE N4, if soft data read at upper offset voltage M+i and lower offset voltage Mj are successfully corrected, upper offset voltage M+i and lower offset voltage Mj are recorded. Upper offset voltage M+i and lower offset voltage Mj are associated with current data characteristics, memory cell status, and other related information to form historical error correction data. This allows these offset voltages to be quickly referenced for future reference when encountering the same or similar situations.

[0114] Based on the existing soft retry error correction method (using a fixed offset step size for soft retry), the VT diagram of the flash memory reading error occurs in normal temperature and high temperature (85°C) writing and low temperature (-25°C) reading scenarios, as shown in the following figure: Fig. 2 Based on the flash memory error correction method of the present invention, the VT diagram of the flash memory reading error occurs in the normal temperature and high temperature (85℃) writing and low temperature (-25℃) reading scenarios, as shown in FIG. Fig. 3 As shown. The horizontal axis in the VT graph represents different voltages, the vertical axis in the VT graph represents the number of cells (basic storage units) under the corresponding voltage, the blue curve in the VT graph represents the voltage and number of cells read at a certain storage location at normal temperature, and the yellow curve in the VT graph represents the voltage and number of cells read at the same storage location when writing at high temperature and reading at low temperature. Fig. 2 and Fig. 3 It can be seen that when reading the same position using the existing soft retry error correction method, the result is UNC (uncorrectable error), and the two curves do not overlap, that is, the error correction capability at extreme temperature is quite different from that at normal temperature; while when reading the same position using the error correction method of the present invention, no UNC (uncorrectable error) occurs, and the two curves have a high degree of overlap, that is, the error correction capability at extreme temperature is similar to that at normal temperature.

[0115] The second embodiment of the present invention is:

[0116] A computer-readable storage medium stores a computer program, wherein the computer program is executed to implement the various steps of the flash memory error correction method based on adaptive learning as described in the first embodiment.

[0117] In summary, the present invention provides a flash memory error correction method and readable storage medium based on adaptive learning. The offset step size is optimized in real time based on the deviation data generated by the baseline data and soft data error correction, achieving dynamic adjustment of the offset step size and voltage offset. Compared with the fixed step size preset in traditional error correction methods, the offset step size of the present invention can be set according to the actual data situation, so that the error correction process can flexibly adjust the bias voltage according to the actual state of different flash memory cells, effectively adapting to different application scenarios. In addition, this method can finely adjust the voltage through the offset step size, thereby finding the optimal read voltage threshold, reducing the data error rate, and improving data reliability. At the same time, the offset step size can be adjusted separately for the upper and lower offset voltages to adapt to data error conditions under different bias voltages, more effectively correcting data errors. In addition, by switching the read mode to read different amounts of soft data, a read mode with stronger error correction capability is selected to improve the error correction success rate, thereby effectively reducing the probability of flash memory data read errors.

[0118] In the above embodiments provided in the present application, it should be understood that the disclosed methods, devices, computer-readable storage media, and electronic devices can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple components or modules can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or components or modules, which can be electrical, mechanical or other forms.

[0119] The components described as separate parts may or may not be physically separate, and the components shown as components may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of these components may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, the functional modules in various embodiments of the present invention may be integrated into a single processing module, or each component may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0121] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0122] It should be noted that for the aforementioned method embodiments, for ease of description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present invention is not limited by the order of the actions described, because according to the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0123] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0124] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's description and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A flash memory error correction method based on adaptive learning, characterized in that: include: Acquiring a reference voltage, and reading data according to the reference voltage to obtain reference data; Acquiring historical error correction data corresponding to the reference data, and determining offset step sizes of different bias types according to the historical error correction data; Reading data based on the offset step size and the reference voltage in a current reading mode to obtain soft data of the different bias types, wherein the number of soft data read in each reading mode is different; determining whether error correction is successful in a current reading mode according to the soft data and the reference data; If the error correction fails, after switching the current reading mode to a reading mode of the next priority, updating the offset step size according to the deviation data between the reference data and the soft data, and returning to the step of reading data based on the current reading mode according to the offset step size and the reference voltage to obtain the soft data of the different bias types until the error correction succeeds; Reading data based on the current read mode according to the offset step size and the reference voltage to obtain soft data of different bias types includes: determining offset voltages of the reference voltage under the different bias types according to the offset step size and the current reading mode; Data is read respectively according to the offset voltages of the different bias types to obtain soft data of the different bias types.

2. The method according to claim 1, characterized in that Determining the offset voltages of the reference voltage under the different bias types according to the offset step size and the current reading quantity includes: determining the number of soft data to be read according to the current reading mode; A plurality of offset voltages of the reference voltage under the different bias types are determined according to the offset step, and the number of the plurality of offset voltages is the read number.

3. The method according to claim 2, characterized in that Determining a plurality of offset voltages of the reference voltage under the different bias types according to the offset step size includes: Under each bias type, the reading number is used as the number of offsets, the reference voltage is cumulatively offset according to the offset step corresponding to the bias type, and the reference voltage after each cumulative offset is marked as an offset voltage.

4. The method according to claim 1, wherein The reading mode includes a first mode, a second mode and a third mode; The priority of the first mode is higher than that of the second mode, and the priority of the second mode is higher than that of the third mode; The read quantities of soft data in the first mode, the second mode and the third mode under each bias type are respectively a first value, a second value and a third value, the first value is smaller than the second value, and the second value is smaller than the third value.

5. The method according to claim 1, wherein After successful error correction, it also includes: The characteristic information of the reference data, the updated offset step length, and the offset voltage determined by the reference voltage based on the updated offset step length are stored in a history database as a set of historical error correction data.

6. The method according to claim 5, characterized in that Determining whether error correction is successful in the current reading mode according to the soft data and the reference data includes: Performing comprehensive decoding verification on the reference data and all soft data read in the current reading mode; If the decoding is successful, the error correction is successful in the current reading mode; If decoding fails, error correction fails in the current reading mode.

7. The method according to claim 1, characterized in that Obtaining the reference voltage includes: Obtaining a preset error correction reference voltage table and reading an effective error correction voltage table of successful errors corrected during retry error correction; Determining a storage unit location for performing data error correction; Obtaining the effective voltage corresponding to the storage unit position from the error correction effective voltage table; If the effective voltage is obtained, determining the effective voltage as a reference voltage; If the valid voltage is not obtained, a reference voltage corresponding to the storage unit position is obtained from the error correction reference voltage table.

8. The method according to claim 1, characterized in that Updating the offset step size according to the deviation data between the reference data and the soft data includes: The offset step sizes under the different bias types are updated respectively by an adaptive gradient descent method to minimize the deviation data between the reference data and the soft data.

9. The method according to claim 1, characterized in that Before obtaining the reference voltage, it also includes: If a read request is received, data is read according to the read request to obtain initial data; Decoding and verifying the initial data; if the decoding of the initial data fails, performing error correction processing on the initial data by retrying reading to obtain initial error-corrected data; Decoding and verifying the initial error correction data; If the initial error correction data is decoded successfully, the initial error correction data is returned; If the initial error correction data decoding fails, the step of obtaining the reference voltage is performed.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is executed to implement the various steps in the flash memory error correction method based on adaptive learning as described in any one of claims 1 to 9.

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