High-reliability high-rail space stepping motor control scheme

Abstract

The invention relates to a high-reliability high-orbit space stepping motor control method, which belongs to the field of satellites, and comprises the following steps: establishing a satellite platform, and controlling communication among a combination and a stepping motor; the control combination comprises an FPGA (Field Programmable Gate Array), a FLASH memory and a motor driving module; the satellite platform sends a stepping motor control instruction to the control combination, and the FPGA outputs a PWM pulse control signal and a direction control signal to the motor driving module based on the stepping motor control instruction. The motor driving module uses software current subdivision control to calculate a step angle corresponding to each signal in the PWM pulse control signals according to a set micro step number to generate a corresponding subdivision pulse control signal, and drives the stepping motor to move based on the subdivision pulse control signal and the direction control signal; the FPGA returns the telemetering parameters and the working state of the stepping motor and outputs the telemetering parameters and the working state to the satellite platform; the satellite platform judges whether online reconstruction is carried out or not based on the returned telemetry parameters and the working state of the stepping motor; timed refreshing is carried out in the power-on and operation process. And a reliable method is provided for high-orbit space stepping motor control.

Description

Technical Field

[0001] The present invention belongs to the technical field of satellite technology, and particularly relates to a high-reliability high-orbit space stepping motor control method. Background Art

[0002] With the diversity of the development of on-orbit payloads in space, the stepping motor has become a commonly used control method for on-orbit payload actuators at present. For example, solar wings, hatch doors, hinge mechanisms, servo nozzles, etc. are all controlled by stepping motors. The stepping motor adopts a pulse control method, and its slow, precise and stable control characteristics are the preferred control scheme for current space payload actuators.

[0003] Space actuators are usually key mechanisms, so it is necessary to ensure the precision and reliability of stepping motor control. Traditional stepping motor control methods generally use a single-chip microcomputer or DSP (Digital Signal Processing) as the main control chip. At present, DSP can only be used for low-orbit products. There is no DSP chip at home and abroad that can meet the requirements of on-orbit experience and high-orbit space radiation environment, and the reliability of on-orbit operation is difficult to guarantee. At present, domestic manufacturers such as 772 and 771 have radiation-resistant single-chip microcomputer products. However, the drawback is that the single-chip microcomputer usually has an 8051 core and is an 8-bit single-chip microcomputer, which has defects such as insufficient memory capacity and low processing speed, does not meet the requirements of a large amount of data processing and fast operation, and has limited applicable scenarios.

[0004] In summary, due to the inapplicability of DSP chips to the high-orbit space radiation environment, the performance limitations of single-chip microcomputers, and the insufficient memory capacity and processing speed, the ability to handle complex tasks is limited. Therefore, there is an urgent need for a new method that is more suitable for high-reliability high-orbit space stepping motor control. Summary of the Invention

[0005] In view of the above analysis, the present invention aims to disclose a high-reliability high-orbit space stepping motor control method for reliable control of stepping motors in a high-orbit space environment.

[0006] The present invention discloses a high-reliability high-orbit space stepping motor control method, including the following steps:

[0007] Establish communication between the satellite platform, the control combination and the stepping motor;

[0008] The control combination includes an FPGA chip, a FLASH memory and a motor drive module;

[0009] The satellite platform sends a stepper motor control instruction to the control assembly. Based on the stepper motor control instruction, the FPGA chip outputs a PWM pulse control signal and a direction control signal to the motor drive module. The motor drive module uses a software current subdivision control method to calculate the corresponding subdivision pulse control signal according to the set number of microsteps for the step angle corresponding to each signal in the PWM pulse control signal, and drives the stepper motor to move based on the subdivision pulse control signal and the direction control signal. The FPGA chip transmits back the telemetry parameters and the working state of the stepper motor to the satellite platform;

[0010] The satellite platform determines whether to perform an online reconfiguration of the FPGA chip based on the transmitted back telemetry parameters and the working state of the stepper motor; when the satellite platform powers on the control assembly and during operation, the FPGA chip is refreshed at a preset period.

[0011] Further, the control assembly includes a first control board and a second control board, and the two control boards are in a dual-machine cold standby mode;

[0012] Each control board includes the FPGA chip, the FLASH memory, and the refresh chip;

[0013] The motor control module includes multiple AD chips and multiple driver chips. Each AD chip corresponds to one driver chip, and each driver chip corresponds to one stepper motor.

[0014] Further, establishing communication between the satellite platform, the control assembly, and the stepper motor includes:

[0015] The satellite platform serves as the server, and the first control board and the second control board in the control assembly serve as clients and are connected to the satellite platform through channels of 1553B bus A and 1553B bus B. The 1553B bus A and the 1553B bus B are redundant to each other;

[0016] The motor drive module in the control assembly is connected to the stepper motor through a control line.

[0017] Further, the motor drive module using the software current subdivision control method to calculate the corresponding subdivision pulse control signal according to the set number of microsteps for the step angle corresponding to each signal in the PWM pulse control signal includes:

[0018] The driver chip calculates the step angle corresponding to each PWM pulse signal based on the PWM pulse control signal;

[0019] Calculate the microstep angle based on the step angle and the preset number of microsteps;

[0020] Based on the micro step angle, each PWM pulse signal is subdivided into N micro steps as the subdivision pulse control signal.

[0021] Further, calculate the step angle as follows:

[0022] θ setp = θ full ×DutyCycle

[0023] where, θ setp is the step angle corresponding to each PWM pulse control signal, θ full is the rotation angle of the complete stepper motor, and DutyCycle is the duty cycle of the PWM pulse control signal;

[0024] Calculate the micro step angle as follows:

[0025]

[0026] where, θ microsetp is the micro step angle and N is the preset number of micro steps.

[0027] Further, when the telemetry parameter or the working state of the stepper motor exceeds its standard range, online reconfiguration of the FPGA chip will be performed;

[0028] Online reconfiguration of the FPGA chip is carried out in the following way:

[0029] The ground station creates a program to be reconfigured and uploads it to the satellite platform, and the satellite platform uploads the program to be reconfigured to the FLASH memory through the RS485 interface and the RS485 bus;

[0030] The refresh chip loads the program to be reconfigured in the FLASH memory into the FPGA chip for online reconfiguration;

[0031] After online reconfiguration of the FPGA chip, the satellite platform restarts the FPGA chip, and after the FPGA chip is powered on, it performs self-detection and then starts normal operation.

[0032] Further, the satellite platform sends a stepper motor control instruction to the control assembly through the AB dual-channel redundant 1553B bus;

[0033] The AB dual-channel redundant 1553B bus includes two channels: 1553B bus A and 1553B bus B;

[0034] The 1553B bus A channel is used as the main channel, and the 1553B bus B channel is used as the backup channel;

[0035] By default, the 1553B bus A channel is used first;

[0036] Based on the channel self-detection mechanism, the satellite platform periodically sends self-check frames to the 1553B bus A channel and the 1553B bus B channel;

[0037] When a fault occurs in the 1553B bus A channel, the satellite platform, based on the error retransmission mechanism, retransmits the self-check frame to the 1553B bus A channel again. When there is no response from the A channel again, the satellite platform switches to the 1553B bus B channel to continue communication;

[0038] When there is no response from both the 1553B bus A and B channels, the satellite platform is responsible for performing the control unit switching operation to switch the first control board and the second control board of the control combination.

[0039] Furthermore, the dual-redundancy cold standby mode of the first control board and the second control board includes:

[0040] The first control board is the main control board, and the second control board is the standby control board. By default, the first control board is enabled first;

[0041] The FPGA chip on the first control board periodically sends the telemetry parameters of the first control board to the satellite platform, including power status, temperature, current, and voltage;

[0042] The satellite platform judges the status of the first control board by monitoring the changes in the telemetry parameters. When any of the telemetry parameters changes beyond the standard range, it is judged that there is a fault in the first control board;

[0043] When the first control board detects a fault, the satellite platform is responsible for switching to the second control board, and the satellite platform sends an OC switching instruction to switch the control board;

[0044] After the first control board is repaired and normal, the satellite platform sends the OC instruction again to switch back from the second control board to the first control board.

[0045] Furthermore, outputting the working state of the stepping motor to the satellite platform includes:

[0046] The AD chip is physically connected to the current detection pin of the drive chip;

[0047] The AD chip collects the current of the stepping motor in real time through the current detection pin, and then obtains the working state of the stepping motor, and sends the working state of the stepping motor to the satellite platform through the FPGA chip.

[0048] Furthermore, when the satellite platform powers on the control combination and periodically refreshes the FPGA chip during operation according to a preset period includes:

[0049] When the satellite platform powers on the control combination for the first time, the refresh chip uses the original program pre-stored in the FLASH memory to refresh the FPGA chip;

[0050] During operation, the FPGA chip is refreshed based on the preset period. When the FPGA chip is reconfigured online, the program to be reconfigured stored in the FLASH memory serves as the new original program.

[0051] Compared with the prior art, the present invention can at least achieve one of the following beneficial effects:

[0052] 1. In the control combination of the stepping motor actuator of the present invention, a dual-machine cold backup working mode is adopted, and the machine switching is controlled by the satellite platform;

[0053] 2. An SRAM (Static Random-Access Memory)-type FPGA (Field Programmable Gate Array) chip is used as the main control chip, and a refresh chip and a FLASH memory are supported to achieve the functions of on-orbit timing refresh and reconfiguration, meeting the high-orbit space radiation environment conditions;

[0054] 3. Communicates with the satellite platform through a 1553B (an information transmission bus standard) bus, and a dual-redundancy channel can effectively ensure communication reliability; the 1553B bus communication standard has the characteristics of reliability, real-time performance, flexibility, and standardization;

[0055] 4. Conducts on-orbit timing refresh through the refresh chip and the FLASH memory, and conducts software on-orbit reconfiguration through the RS485 serial bus. RS485 has the advantages of long-distance transmission, high data transmission rate, and half-duplex communication;

[0056] 5. Controls the rotation of the stepping motor through the drive circuit, and can accurately and smoothly control the rotation angle, torque, and speed of the stepping motor.

[0057] The present invention can meet the accurate and reliable control of the rotation of the stepping motor in the high-orbit space environment, and provides a reliable method for the control of the high-orbit space stepping motor. Description of the Drawings

[0058] The drawings are only for the purpose of showing specific embodiments, and are not considered to limit the present invention.

[0059] Figure 1 It is a flowchart of a high-reliability space stepping motor control method;

[0060] Figure 2It is a block diagram of a high-reliability space stepping motor control method;

[0061] Figure 3 It is a block diagram of an on-orbit refresh and reconstruction scheme;

[0062] Figure 4 It is a block diagram of the stepping motor driving principle. Specific implementation manners

[0063] The preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings, where the accompanying drawings form a part of this application and are used together with the embodiments of the present invention to explain the principles of the present invention.

[0064] The hardware devices involved in the method of the present invention are as follows:

[0065] As Figure 2 shown, the stepping motor actuator includes a control combination and a stepping motor.

[0066] The control combination includes an FPGA chip, a FLASH memory, and a motor drive module;

[0067] The control combination includes a first control board and a second control board, and the two control boards are in a dual-machine cold standby mode;

[0068] Each control board includes the FPGA chip, the FLASH memory, a motor drive module, and a refresh chip;

[0069] The motor control module includes multiple AD chips and multiple drive chips. Each AD chip corresponds to a drive chip, and each drive chip corresponds to a stepping motor.

[0070] The first control board and the second control board of the control combination are connected to the satellite platform through a 1553B dual-channel redundant bus ( Figure 2 1553B bus A and 1553B bus B in it), and include: an FPGA chip, a FLASH memory (not shown in the figure), a refresh chip (not shown in the figure), a motor drive module, a power supply, a 1553B communication interface, a grounding stake. The FPGA chip is connected to the satellite platform through an RS485 interface and an RS485 bus;

[0071] Since the first control board and the second control board are in a dual-machine cold standby mode, the corresponding stepping motor is connected to the motor drive module on the control board during on-orbit operation. For the stepping motor, it also belongs to the main and standby modes correspondingly;

[0072] The grounding stake is used to reduce electromagnetic interference, prevent static electricity accumulation, and stabilize the operation of the equipment.

[0073] As Figure 4 shown, each stepping motor drive circuit (that is Figure 2The'motor drive module' contains multiple AD chips and multiple drive chips. The AD chips and drive chips have a one-to-one relationship, and each drive chip and the stepper motor also have a one-to-one relationship.

[0074] Each stepper motor is respectively connected to the drive chips on the motor drive modules on the first control board and the second control board through control lines.

[0075] The satellite platform is responsible for supplying power to the control combination and the stepper motor, controlling power on and off, sending stepper motor control instructions, and receiving the telemetry parameters transmitted back by the FPGA chip and the working status of the stepper motor monitored by the drive chip.

[0076] Among them, the SRAM-based FPGA chip is the main control chip of the first control board and the second control board.

[0077] Such as Figure 1 As shown, an embodiment of the present invention discloses a highly reliable space stepper motor control method, including the following steps:

[0078] Step S1, establish communication between the satellite platform, the control combination, and the stepper motor;

[0079] Step S2, the satellite platform sends a stepper motor control instruction to the control combination. The FPGA chip outputs a PWM (Pulse-width modulation) pulse control signal and a DIR (Direct, direction) direction control signal to the motor drive module based on the stepper motor control instruction. The motor drive module uses a software current subdivision control method to calculate and generate corresponding subdivision pulse control signals for the step angle corresponding to each signal in the PWM pulse control signal according to the set number of microsteps, and drives the stepper motor to move based on the subdivision pulse control signal and the direction control signal. The FPGA transmits back the telemetry parameters and the working status of the stepper motor to the satellite platform;

[0080] Step S3, the satellite platform determines whether to perform online reconfiguration of the FPGA chip based on the transmitted back telemetry parameters and the working status of the stepper motor; when the satellite platform powers on the control combination and refreshes the FPGA chip regularly according to a preset period during operation.

[0081] The control combination includes an FPGA chip, a FLASH memory, and a motor drive module.

[0082] In step S1, the establishment of communication between the satellite platform, the control combination, and the stepper motor includes:

[0083] The satellite platform serves as the server, and the first control board and the second control board in the control combination serve as clients and are connected to the satellite platform through channels of 1553B bus A and 1553B bus B. The 1553B bus A and the 1553B bus B are redundant to each other.

[0084] In the control combination, the motor drive module is connected to the stepper motor through a control line.

[0085] After the satellite platform, the control combination and the stepper motor are connected, communication self-check is performed.

[0086] Step S2 is divided into steps S21 - S23 as follows:

[0087] Step S21, the satellite platform sends a stepper motor control instruction to the control combination.

[0088] The satellite platform sends a stepper motor control instruction to the control combination through the 1553B bus with AB dual-channel redundancy;

[0089] The 1553B bus with AB dual-channel redundancy includes two channels of 1553B bus A and 1553B bus B;

[0090] The 1553B bus A channel serves as the main channel, and the 1553B bus B channel serves as the standby channel;

[0091] By default, the 1553B bus A channel is used first;

[0092] Based on the channel self-detection mechanism, the satellite platform regularly sends self-check frames to the 1553B bus A channel and the 1553B bus B channel;

[0093] When a fault occurs in the 1553B bus A channel, the satellite platform, based on the error retransmission mechanism, retransmits the self-check frame to the 1553B bus A channel again. When there is still no response from channel A, the satellite platform switches to the 1553B bus B channel to continue communication;

[0094] When there is no response from both the 1553B bus A and B channels, the satellite platform is responsible for performing the operation of switching the machine and switching the first control board and the second control board of the control combination.

[0095] The error retransmission mechanism is generally AAB or BBA. The present invention preferably uses the AAB error retransmission mechanism.

[0096] Each channel is equipped with a self-detection mechanism. By default, channel A is used in the present invention.

[0097] (1) The satellite platform regularly sends self-check frames to the 1553B bus A channel;

[0098] Exemplarily, the time interval for regular transmission is 10 milliseconds.

[0099] (2) After receiving the self-check frame, the FPGA of the control board generates a response and transmits it back to the satellite platform through Channel A of the 1553B bus;

[0100] (3) If the satellite platform does not receive the expected response within the specified time, it is determined that a fault has occurred in Channel A of the 1553B bus;

[0101] (4) Repeat the above operations 1 to 3;

[0102] Exemplarily, the specified time is 5 milliseconds.

[0103] (5) The satellite platform sends an instruction to switch to Channel B of the 1553B bus;

[0104] The satellite platform records the results of each self-check and the channel switching situation as the basis for fault diagnosis and analysis.

[0105] "AAB" or "BBA" in the error retransmission mechanism is a control strategy in redundant transmission.

[0106] AAB: It means that in redundant transmission, the main channel (Channel A of the 1553B bus) is used first. If an error occurs, communication on Channel A of the 1553B bus is attempted again. If the same error occurs, then switch to the backup channel (Channel B of the 1553B bus);

[0107] BBA: It means that in redundant transmission, the backup channel (Channel B of the 1553B bus) is used first. If an error occurs, communication on Channel B is attempted again. If the same error occurs, then switch to the main channel (Channel A of the 1553B bus).

[0108] This retransmission mechanism increases the reliability of the communication system. By adopting the error retransmission mechanism, it is possible to switch to the backup channel as soon as an error occurs to ensure the normal transmission of data. The choice between using AAB or BBA depends on the specific application scenario.

[0109] The dual redundant channels of Channel A and Channel B of the 1553B bus can effectively ensure communication reliability.

[0110] The control combination includes a first control board and a second control board, and the two control boards adopt a dual-machine cold standby mode.

[0111] The dual-machine cold standby mode of the first control board and the second control board includes:

[0112] The first control board is the main control board, and the second control board is the backup control board. By default, the first control board is enabled first;

[0113] The FPGA chip on the first control board periodically sends telemetry parameters of the first control board to the satellite platform, including power supply status, temperature, current, and voltage;

[0114] The satellite platform determines the state of the first control board by monitoring the change of the telemetry parameters, and determines that the first control board is faulty when the change of any telemetry parameter exceeds the standard range;

[0115] When the first control panel detects a fault, the satellite platform is responsible for switching to the second control panel, and the satellite platform sends an OC switch command to switch the control panel;

[0116] After the first control board is repaired and becomes normal, the satellite platform sends the OC command again to switch from the second control board back to the first control board.

[0117] Among them, for control panel repair, ground station personnel can also comprehensively determine the telemetry parameters to troubleshoot the fault.

[0118] The control combination adopts a dual-machine cold backup working mode. The control combination includes the first control board and the second control board. The power supply, 1553B communication interface, FPGA chip, and motor drive module are respectively solidified on the first control board and the second control board. The FPGA chip is the main control chip of the first control board and the second control board. The SRAM type FPGA chip supports unlimited programming.

[0119] The satellite platform determines whether the control board is faulty as follows:

[0120] (1) The FPGA chip periodically sends telemetry parameters of the first control board and the second control board to the satellite platform, wherein the telemetry parameters include power supply status, FPGA temperature, current, and voltage;

[0121] Exemplarily, the period for the FPGA chip to feedback telemetry parameters is 10 milliseconds.

[0122] (2) The satellite platform determines the status of the first control board and the second control board by monitoring the change of the telemetry parameters, and determines that a fault exists when the parameter change exceeds the rated standard range;

[0123] (3) In the present invention, the first control board is enabled by default. When the first control board detects a fault, the satellite platform is responsible for switching to the second control board. The satellite platform sends an OC (Orbital Command) instruction to switch the first control board and the second control board to ensure the continuity and reliability of the stepper motor.

[0124] (4) After the first control board is repaired and functions normally, the satellite platform sends an OC command to switch from the second control board back to the first control board.

[0125] Step S22: The FPGA chip outputs a PWM pulse control signal and a DIR direction control signal to the motor drive module based on the stepping motor control instruction. The motor drive module uses a software current subdivision control method to calculate and generate corresponding subdivision pulse control signals for the step angle corresponding to each signal in the PWM pulse control signal according to the set number of microsteps.

[0126] As Figure 4 shown, based on the stepping motor control instruction, the FPGA chip outputs a PWM pulse control signal and a DIR direction control signal to the driving chip of the stepping motor drive circuit, and the driving chip drives the stepping motor to rotate.

[0127] Among them, Figure 4 the stepping motor drive circuit in Figure 2 is the'motor drive' module in

[0128] The FPGA chip is responsible for outputting a PWM pulse control signal and a DIR direction control signal to the driving chip, thereby controlling the rotation of the stepping motor. The stepping motor driving chip usually selects the LMD18200 of Texas Instruments, USA, but it does not have an anti-radiation function. At present, the mainstream high-orbit application solutions all adopt the domestic stepping motor driving chip LLMD18200-2D produced by 771 with the same original replacement. This chip is a dual H-bridge drive, controlled by the cooperation of a PWM pulse control signal and a DIR direction control signal. It also has a current detection pin and an over-temperature detection pin, with anti-radiation ability and in-orbit experience, which can ensure the reliability of high-orbit space applications;

[0129] The pulse width and frequency of the PWM pulse control signal determine the rotation angle and speed of the stepping motor; the DIR direction control signal is used to control the forward / backward rotation direction of the stepping motor.

[0130] The motor drive module uses a software current subdivision control method to calculate and generate corresponding subdivision pulse control signals for the step angle corresponding to each signal in the PWM pulse control signal according to the set number of microsteps, including:

[0131] The driving chip calculates the step angle corresponding to each PWM pulse signal based on the PWM pulse control signal;

[0132] Calculate the microstep angle based on the step angle and the preset number of microsteps;

[0133] Based on the microstep angle, each PWM pulse signal is subdivided into N microsteps as the subdivision pulse control signal.

[0134] Calculate the step angle as follows:

[0135] θ setp = θfull ×Duty Cycle

[0136] where θ setp is the step angle corresponding to each PWM pulse control signal, θ full is the rotation angle of the complete stepper motor, and Duty Cycle is the duty cycle of the PWM pulse control signal;

[0137] Calculate the microstep angle as follows:

[0138]

[0139] where θ microsetp is the microstep angle and N is the preset number of microsteps.

[0140] The drive chip changes the duty cycle of the PWM pulse control signal to adjust the current magnitude. For the step angle corresponding to each PWM pulse signal, it is divided into N PWM pulse control signals according to the preset number of microsteps N as the microstepping pulse control signals.

[0141] The duty cycle of the PWM pulse control signal refers to the proportion of the high-level time of the pulse in one cycle, usually expressed as a percentage. For example: If the stepper motor needs to work with a larger torque, the duty cycle of the PWM pulse signal can be increased to increase the average current of the stepper motor. Conversely, if it is necessary to reduce the torque of the stepper motor, the duty cycle of the PWM pulse signal can be reduced. Therefore, the duty cycle of the PWM pulse signal is used to adjust the motion characteristics of the stepper motor in stepper motor control.

[0142] The drive chip uses the software current microstepping control method for each step angle of the stepper motor corresponding to each signal in the PWM pulse control signal. The each step angle is calculated and generated into corresponding microstepping pulse control signals according to the set number of microsteps, and these microstepping pulse control signals will control the stepper motor to move at a smaller angle.

[0143] The FPGA chip outputs the PWM pulse control signal and the DIR direction control signal to the drive chip in the motor drive module to control the rotation of the stepper motor, so as to achieve precise and smooth control of the rotation angle, torque, speed, and direction of the stepper motor.

[0144] During the movement of the stepper motor, the drive chip further divides the PWM pulse control signal into N microsteps. Exemplarily, one step of the stepper motor is divided into 4 microsteps, that is, one step angle is divided into 4 parts, and the angle of each microstep is smaller and the control is more precise;

[0145] In the control of a stepper motor, a PWM pulse control signal is used. By changing the duty cycle of the PWM pulse control signal, the magnitude of the current is adjusted. For each step angle, N PWM pulse control signals for microsteps are generated;

[0146] Microstep setting: Determine how many microsteps each step angle is divided into, which is decided according to specific requirements and the specifications of the stepper motor. A larger number of microsteps will improve the control resolution, but also increase the complexity;

[0147] Exemplarily, N is taken as 4.

[0148] Pulse number calculation: For each step angle, it is divided into the set number of microsteps, and the corresponding subdivided pulse control signals are calculated and generated. The subdivided pulse control signals will control the stepper motor to move at a smaller angle;

[0149] Current control adjustment: As the number of microsteps increases, the duty cycle of the PWM pulse control signal is adjusted to control the magnitude of the current. By finely adjusting the current, the stepper motor can move more smoothly at the microstep level;

[0150] Support of the drive chip: The stepper motor drive chip supports software current subdivision control, generating the corresponding subdivided pulse control signals and adjusting the current according to the number of microsteps.

[0151] Combining software current subdivision control and the PWM pulse control signal enables the stepper motor to move with higher precision, achieving higher precision and smoothness during the control process of the stepper motor and improving the system performance.

[0152] Outputting the working state of the stepper motor to the satellite platform includes:

[0153] The AD chip is physically connected to the current detection pin of the drive chip;

[0154] The AD chip collects the current of the stepper motor in real time through the current detection pin, thereby obtaining the working state of the stepper motor, and sending the working state of the stepper motor to the satellite platform through the FPGA chip.

[0155] By physically connecting the AD chip (an acquisition chip for converting analog signals to digital signals) to the current detection pin of the drive chip, collecting the current of the stepper motor output by the drive chip to monitor the current of the stepper motor, and obtaining information on the working state of the stepper motor by collecting the current signal generated by the stepper motor, ensuring the reliable operation of the stepper motor.

[0156] The stepper motor uses a permanent magnet stepper motor, which has good dynamic performance and large output torque, and can meet different structures and is suitable for different working conditions. The stepper motor is driven by a driver chip, and the PWM pulse control signal and direction signal output by the FPGA chip control the driver chip to drive the stepper motor to rotate.

[0157] The pulse control method of the stepper motor can accurately calculate the rotation angle, torque and speed, and combined with the software current subdivision control method, it can accurately and smoothly control the load movement; the stepper motor rotates by receiving PWM pulse control signals and direction control signals. Each signal drives the stepper motor to rotate a fixed angle, which is called the step angle. The driver chip can achieve precise angle control by accurately calculating the number of pulse signals sent to the stepper motor; the software current subdivision control method can further improve the control accuracy of the stepper motor. The software current subdivision control method divides each step into more microsteps, thereby achieving smoother rotation of the stepper motor.

[0158] The combination of PWM pulse control signal and software current subdivision control method can realize precise and stable control of stepper motor, ensuring its accuracy and reliability.

[0159] The working state of the stepper motor acquired by the AD chip includes:

[0160] The AD chip is solidified in the motor driving module and is physically connected to the current detection pin of the driving chip;

[0161] The AD chip collects the working status of the stepper motor in real time by monitoring the current of the stepper motor, and sends the working status of the stepper motor acquired by the AD chip to the satellite platform through the FPGA chip.

[0162] (1) The AD chip collects the stepper motor current signal and transmits it to the satellite platform through the FPGA and 1553B bus. The satellite platform adjusts the stepper motor PWM pulse control signal in real time and reconstructs the FPGA chip online:

[0163] (2) AD chip connected to the current detection pin of the driver chip: The AD chip is physically connected to the current detection pin of the stepper motor driver chip to collect the current signal of the stepper motor in real time;

[0164] (3) AD chip digital-to-analog conversion: The AD chip converts the collected analog current signal into a digital signal for subsequent digital signal processing;

[0165] (4) FPGA Data Processing: The digitized current signal is processed in real time by the FPGA. The FPGA can execute a series of algorithms to analyze the current situation of the stepper motor, so as to obtain information about the working state of the stepper motor, such as the current magnitude, waveform characteristics, etc.;

[0166] (5) 1553B Communication: Use the 1553B bus to transmit the current information processed by the FPGA to the satellite platform. The 1553B bus communication standard features reliability, real-time performance, flexibility, and standardization;

[0167] (6) RS485 Interface: The satellite platform is configured with an RS485 interface to receive remote sensing information and the working state information of the stepper motor from the FPGA chip. RS485 is a serial communication protocol suitable for long-distance communication and is often used to connect various subsystems in the satellite system;

[0168] (7) Satellite Platform Data Processing: After the satellite platform receives the current information from the 1553B bus, it performs further data processing. This includes parsing data packets, verifying the integrity and accuracy of the data, etc.;

[0169] (8) Adjust Parameters and Reconfigure the FPGA Chip Online: The satellite platform adjusts the PWM pulse control signal of the stepper motor according to the need through remote control instructions, and regularly refreshes the FLASH memory and reconfigures the FPGA chip online to achieve real-time adjustment.

[0170] In a high-reliability geostationary space stepper motor control system, the AD chip is used to monitor the current of the stepper motor, and mainly has the following functions:

[0171] (1) Current Monitoring: The AD chip is responsible for collecting the current signal generated by the stepper motor. By monitoring the current, the system obtains information about the working state of the stepper motor. The change in current reflects the load, operating condition, and possible fault conditions of the stepper motor;

[0172] (2) Fault Detection: By monitoring the current of the stepper motor, abnormal current waveforms or changes in current values may be detected. These changes may be caused by motor faults, abnormal loads, or other problems. Fault detection helps to take timely measures when problems occur, improving the reliability and stability of the system

[0173] (3) Closed-loop Control: By monitoring the current, closed-loop control is achieved. The control of the stepper motor is adjusted according to the actual current value, which helps to ensure that the stepper motor operates as expected. The satellite platform makes adjustments according to the need to meet the requirements;

[0174] (4) Performance optimization: By analyzing the current signal, the satellite platform can understand the working performance of the stepper motor. The control algorithm can be optimized to perform on-orbit reconfiguration of the FPGA, improving the efficiency and accuracy of the stepper motor.

[0175] The main functions of the stepper motor drive circuit include:

[0176] (1) Receiving control signals: Receiving PWM pulse control signals and direction control signals from the FPGA;

[0177] (2) The pulse width and frequency of the PWM pulse control signal determine the rotation angle and speed of the stepper motor;

[0178] (3) The drive chip generates a microstepping pulse control signal based on the PWM pulse control signal using the software current microstepping control method, determines the rotation direction of the stepper motor according to the direction control signal, and ensures that the stepper motor rotates in the expected direction.

[0179] The stepper motor drive circuit coordinates and executes the instructions of the FPGA to achieve precise control of the stepper motor.

[0180] The FPGA chip is of the SRAM type and includes a timing logic device and programmable registers;

[0181] The timing logic device generates the PWM pulse control signal and the DIR direction control signal based on the received stepper motor control instructions sent by the satellite platform;

[0182] The programming registers inside the FPGA chip store telemetry parameter data and the working status of the stepper motor collected in real time by the AD chip.

[0183] Step S23, the satellite platform determines whether to perform on-orbit reconfiguration of the FPGA chip based on the returned telemetry parameters and the working status of the stepper motor.

[0184] The FPGA chip transmits the returned telemetry parameters and the working status of the stepper motor obtained by the AD chip to the satellite platform through the 1553B bus.

[0185] Specifically, in step S3, when the telemetry parameters or the working status of the stepper motor exceed their standard ranges, on-orbit reconfiguration of the FPGA chip will be performed;

[0186] The on-orbit reconfiguration of the FPGA chip is carried out in the following way:

[0187] The ground station creates a program to be reconfigured and uploads it to the satellite platform. The satellite platform uploads the program to be reconfigured to the FLASH memory through the RS485 interface and the RS485 bus;

[0188] The refresh chip loads the program to be reconstructed in the FLASH memory into the FPGA chip for online reconstruction;

[0189] After the FPGA chip is online reconstructed, the satellite platform restarts the FPGA chip. After the FPGA chip is powered on, it performs self-detection and then starts normal operation.

[0190] As Figure 2 shown, both the first control board and the second control board use SRAM-based FPGA chips as the main control chips, and are equipped with refresh chips and FLASH memories to achieve software in-orbit timed refresh and online reconstruction, meeting the high-orbit space irradiation environment conditions and ensuring the flexibility of software in-orbit upgrade;

[0191] The refresh chip and the FLASH memory are respectively solidified on the first control board and the second control board.

[0192] In orbit, the satellite platform burns the program to be reconstructed required for timed refresh and online reconstruction into the FLASH memory through the RS485 interface of the satellite platform and the RS485 bus.

[0193] For the specific in-orbit refresh work, the refresh chip regularly refreshes the program to be reconstructed in the FLASH memory (i.e., the rbt bitstream file in Figure 3 ) into the FPGA chip to ensure that the registers and signals in the FPGA can be refreshed and corrected in time after being affected by space single particles.

[0194] As Figure 3 shown, the refresh chip for timed refresh and online reconstruction works in coordination with the FPGA chip and the FLASH memory;

[0195] The FLASH memory is used to store the program to be reconstructed (the rbt bitstream file in Figure 3 ) and the program to be reconstructed transmitted by the satellite platform through the RS485 interface;

[0196] The timed in-orbit refresh function is realized by the refresh chip to regularly load and refresh the program to be reconstructed stored in the FLASH memory into the FPGA chip.

[0197] The satellite platform and the FLASH memory perform in-orbit reconstruction of the FPGA chip through the RS485 communication interface and the RS485 bus.

[0198] The programmable registers inside the FPGA are used to store configuration information and support unlimited programming to provide high programmability and adaptability;

[0199] The timing logic device in the FPGA chip generates a PWM pulse control signal and a DIR direction control signal based on the received stepping motor control instruction sent by the satellite platform;

[0200] The FPGA chip sends the PWM pulse control signal and the DIR direction control signal to the motor control module, and the driving chip in the motor control module drives the stepping motor to move.

[0201] Radiation hardening of the FPGA chip in the high-orbit space radiation environment ensures the reliability of the system in the radiation environment

[0202] The satellite platform and the FLASH chip have RS485 interfaces, and the two communicate through the RS485 bus. RS485 is a serial communication standard, and RS485 has the advantages of long-distance transmission, high data transmission rate, and half-duplex communication.

[0203] (1) The satellite platform receives the first control board telemetry parameters periodically sent by the control board FPGA chip, including power status, temperature, current, and voltage, and judges whether the program needs to be refreshed;

[0204] (2) Create a program to be reconstructed, transfer it from the ground station to the satellite platform, and update it to the FLASH memory through the RS485 bus;

[0205] (3) Real-time online reconstruction: The refresh chip loads the program to be reconstructed in the FLASH memory into the FGPA chip;

[0206] (4) Monitoring and correction: After refreshing the FPGA chip in orbit, perform self-detection to ensure that the internal state of the FPGA chip is correct.

[0207] Communication between the ground station and the satellite platform: Establish a communication link between the ground station and the satellite platform, and transfer a new program to be reconstructed to the satellite platform through this link. This can be completed through the wireless communication device on the satellite or other devices communicating with the ground station.

[0208] When the satellite platform powers on the control combination and periodically refreshes the FPGA chip during operation, it includes:

[0209] When the satellite platform powers on the control combination for the first time, the refresh chip uses the original program pre-stored in the FLASH memory to refresh the FPGA chip;

[0210] During operation, based on the preset period, the FPGA chip is refreshed. When the FPGA chip is online reconstructed, the program to be reconstructed stored in the FLASH memory is used as the new original program.

[0211] Exemplarily, the preset period is 2 minutes.

[0212] The preset period can be set according to specific requirements.

[0213] In the high-orbit high-irradiation environment, due to the influence of single particles in the space environment, the registers and signals in the FPGA chip may be incorrect or changed. To ensure the normal operation of the system, these errors are detected and repaired regularly. Through timed on-orbit refreshing, the system can correct the changes caused by the high-irradiation environment, maintain the consistency of the internal register state of the FPGA chip, reduce the influence of single-event effects, and thus ensure the reliability and performance of the system.

[0214] 1. An SRAM-based FPGA is used as the main control chip of the stepper motor. This type of FPGA chip is made by radiation-hardening technology and is combined with a refreshing chip and a FLASH memory to achieve software on-orbit timed refreshing and reconstruction, reducing the influence of the high-orbit space irradiation environment;

[0215] 2. The FPGA chip controls the driving chip, and then controls the rotation of the stepper motor. The stepper motor control is controlled by a PWM pulse control signal and a direction control signal. Using an FPGA timing logic device, the PWM pulse control signal can be accurately generated to ensure the reliability of the stepper motor control;

[0216] 3. The FPGA chip internally contains programmable registers, supports unlimited programming, provides high programmability and adaptability, can meet different control requirements, and has high reliability.

[0217] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0218] 1. The control combination in the stepper motor actuator of the present invention adopts a dual-machine cold backup working mode, and the machine is switched by the satellite platform control;

[0219] 2. An SRAM (Static Random-Access Memory)-type FPGA (Field Programmable Gate Array) is used as the main control chip, and at the same time, a refreshing chip and a FLASH memory are used to realize the on-orbit timed refreshing and reconstruction functions, meeting the conditions of the high-orbit space irradiation environment;

[0220] 3. Communicates with the satellite platform through a 1553B (an information transmission bus standard) bus. The dual-redundant channel can effectively ensure the communication reliability; the 1553B bus communication standard has the characteristics of reliability, real-time performance, flexibility, and standardization;

[0221] 4. Perform on-orbit timing refresh through the refresh chip and FLASH memory, which has the advantages of long-distance transmission, high data transmission rate, and half-duplex communication;

[0222] 5. Control the rotation of the stepper motor through the drive circuit, and can accurately and smoothly control the rotation angle, torque, and speed of the stepper motor.

[0223] The present invention can meet the accurate and reliable control of the rotation of the stepper motor in the high-orbit space environment, and provides a reliable method for the control of the stepper motor in the high-orbit space.

[0224] Those skilled in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. Among them, the computer-readable storage medium is a magnetic disk, an optical disk, a read-only memory, or a random access memory, etc.

[0225] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A high-reliability high-orbit space stepper motor control method, characterized in that, it includes the following steps: Establish communication between the satellite platform, the control combination, and the stepper motor; The control combination includes an FPGA chip, a FLASH memory, and a motor drive module; The satellite platform sends a stepper motor control instruction to the control combination. The FPGA chip outputs a PWM pulse control signal and a direction control signal to the motor drive module based on the stepper motor control instruction. The motor drive module uses a software current subdivision control method to calculate and generate corresponding subdivision pulse control signals for the step angle corresponding to each signal in the PWM pulse control signal according to the set number of microsteps, and drives the stepper motor to move based on the subdivision pulse control signal and the direction control signal. The FPGA chip transmits telemetry parameters and the working state output of the stepper motor to the satellite platform; The satellite platform determines whether to perform online reconfiguration of the FPGA chip based on the transmitted telemetry parameters and the working state of the stepper motor; when the satellite platform powers on the control combination and during operation, the FPGA chip is periodically refreshed according to a preset period.

2. The method according to claim 1, characterized in that, the control combination includes a first control board and a second control board, and the two control boards are in a dual-machine cold standby mode; Each control board includes the FPGA chip, the FLASH memory, a motor drive module, and a refresh chip; The motor control module includes multiple AD chips and multiple drive chips. Each AD chip corresponds to one drive chip, and each drive chip corresponds to one stepper motor.

3. The method according to claim 2, characterized in that, establishing communication between the satellite platform, the control combination, and the stepper motor includes: The satellite platform is used as the server, and the first control board and the second control board in the control combination are used as clients and are connected to the satellite platform through 1553B bus A and 1553B bus B channels. The 1553B bus A and 1553B bus B are redundant to each other; The motor drive module in the control combination is connected to the stepper motor through a control line.

4. The method according to claim 1, characterized in that, the motor drive module using a software current subdivision control method to calculate and generate corresponding subdivision pulse control signals for the step angle corresponding to each signal in the PWM pulse control signal according to the set number of microsteps includes: The drive chip calculates the step angle corresponding to each PWM pulse signal based on the PWM pulse control signal; Calculate the microstep angle based on the step angle and the preset number of microsteps; Based on the microstep angle, each PWM pulse signal is subdivided into N microsteps as the subdivision pulse control signal.

5. The method according to claim 4, characterized in that, calculate the step angle as follows: θ setp = θ full × Duty Cycle where θ setp is the step angle corresponding to each PWM pulse control signal, and θ full is the rotation angle of the complete stepper motor, and DutyCycle is the duty cycle of the PWM pulse control signal; calculate the microstep angle as follows: Among them, θ microsetp is the micro-step angle, and N is the preset number of micro-steps.

6. The method according to claim 5, characterized in that, when the telemetry parameters or the working state of the stepper motor exceeds its standard range, online reconfiguration of the FPGA chip will be performed; Online reconfiguration of the FPGA chip is carried out in the following manner: The ground station creates the program to be reconfigured and uploads it to the satellite platform, and the satellite platform uploads the program to be reconfigured to the FLASH memory through the RS485 interface and the RS485 bus; The refresh chip loads the program to be reconfigured in the FLASH memory into the FPGA chip for online reconfiguration; After online reconfiguration of the FPGA chip, the satellite platform restarts the FPGA chip. After the FPGA chip is powered on, it performs self-detection and then starts normal operation.

7. According to the method described in claim 6, It is characterized in that, The satellite platform sends a stepping motor control instruction to the control assembly through the AB dual-channel redundant 1553B bus; The AB dual-channel redundant 1553B bus includes two channels: 1553B bus A and 1553B bus B; The 1553B bus A channel is used as the main channel, and the 1553B bus B channel is used as the backup channel; By default, the 1553B bus A channel is used first; Based on the channel self-detection mechanism, the satellite platform periodically sends self-check frames to the 1553B bus A channel and the 1553B bus B channel; When a fault occurs in the 1553B bus A channel, the satellite platform, based on the error retransmission mechanism, retransmits the self-check frame to the 1553B bus A channel again. When there is no response from the A channel again, the satellite platform switches to the 1553B bus B channel to continue communication; When there is no response from both the 1553B bus A and B channels, the satellite platform is responsible for performing the control board switching operation to switch the first control board and the second control board of the control assembly.

8. According to the method described in claim 7, It is characterized in that, The dual-machine cold standby mode of the first control board and the second control board includes: The first control board is the main control board, and the second control board is the standby control board. By default, the first control board is enabled first; The FPGA chip on the first control board periodically sends telemetry parameters of the first control board to the satellite platform, including power status, temperature, current, and voltage; The satellite platform judges the status of the first control board by monitoring the changes in the telemetry parameters. When any of the telemetry parameters changes beyond the standard range, it is judged that there is a fault in the first control board; When a fault is detected in the first control board, the satellite platform is responsible for switching to the second control board, and the satellite platform sends an OC control board switching instruction to switch the control board; After the first control board is repaired and normal, the satellite platform sends the OC instruction again by the Second control board switches back to the first control board.

9. According to the method described in claim 8, It is characterized in that, Outputting the working state of the stepping motor to the satellite platform includes: The AD chip is physically connected to the current detection pin of the drive chip; The AD chip collects the stepping motor current in real time through the current detection pin, thereby obtaining the working state of the stepping motor, and sends the working state of the stepping motor to the satellite platform through the FPGA chip.

10. The method according to any one of claims 1-9, characterized in that, when the satellite platform powers on the control assembly, and when timing and refreshing the FPGA chip according to a preset period during operation, it includes: when the satellite platform powers on the control assembly for the first time, the refreshing chip refreshes the FPGA chip by using the original program pre-stored in the FLASH memory; during operation, when refreshing the FPGA chip based on the preset period, when the FPGA chip is reconfigured online, the program to be reconfigured stored in the FLASH memory serves as the new original program.

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