Quantum-resistant cryptographic encryption methods, devices, quantum-resistant SIM cards, equipment and media

Abstract

This application discloses a quantum-resistant cryptographic encryption method, apparatus, quantum-resistant SIM card, device, and medium, applicable to terminals including a SIM card. The SIM card includes a central processing unit (CPU), a post-quantum cryptography hardware accelerator, input / output buffers, and a bus. The CPU includes an instruction cache unit. The method includes: the CPU receiving an encryption request sent by an upper-layer application through the instruction cache unit, and converting the encryption request into a set of instructions, including a data loading instruction and a data encryption instruction; executing the data loading instruction to transmit data to the input / output buffer via the bus; and executing the data encryption instruction through the post-quantum cryptography hardware accelerator to encrypt the data in the input / output buffer. Using this application, the communication response delay caused by the long computation time of quantum-resistant cryptography can be reduced, enabling post-quantum security encryption to be supported in the SIM card.

Description

Technical Field

[0001] This invention relates to the field of quantum-resistant cryptography, and in particular to a quantum-resistant cryptographic encryption method, apparatus, quantum-resistant SIM card, device, and medium. Background Technology

[0002] A SIM (Subscriber Identity Module) card is an IC card held by mobile users in the GSM system, also known as a subscriber identification card. Current SIM card technology is becoming increasingly mature, offering not only mobile communication functions but also numerous expanded applications, such as SIM shields and public transport cards—a technology known as the Super SIM card. With the increasing demand for daily financial transactions, people are paying more attention to the security of their SIM cards. Currently, operators like China Mobile have launched Super SIM cards with security chips incorporating Chinese cryptographic algorithms. These SIM cards use these algorithms to ensure the security of user payment transactions. However, with the development of quantum computers in recent years, existing cryptographic algorithms based on mathematical problems such as large prime number factorization and discrete elliptic curves are no longer secure. Summary of the Invention

[0003] This application provides a quantum-resistant cryptographic encryption method, apparatus, quantum-resistant SIM card, device, and medium, which can reduce the communication response delay caused by the long computation time of quantum-resistant cryptography itself, and realize post-quantum security encryption in the SIM card.

[0004] The first aspect of this application provides a quantum-resistant cryptographic encryption method applied to a terminal including a SIM card. The SIM card includes a central processing unit, a post-quantum cryptographic hardware accelerator, an input / output buffer, and a bus. The central processing unit includes an instruction cache unit. The method includes:

[0005] The central processing unit receives encryption requests sent by upper-layer applications through the instruction cache unit and converts the encryption requests into a set of instructions, including data loading instructions and data encryption instructions.

[0006] The central processing unit executes the data loading instruction to transfer data to the input / output buffer via the bus;

[0007] The central processing unit executes the data encryption instructions through the post-quantum cryptography hardware accelerator to encrypt the data in the input / output buffer.

[0008] Optionally, the SIM card further includes a dedicated static random access memory (SRAM), a general static random access memory (SRAM), and flash memory. The data includes a key stored in the general static random access memory. Before the central processing unit executes the data loading instruction to transfer the data to the input / output buffer via the bus, the method further includes:

[0009] The central processing unit periodically detects the number of times the key is used;

[0010] If the number of times the key is used exceeds a first threshold, the central processing unit moves the key to the dedicated static random access memory, which is directly connected to the input / output buffer through hardware mapping.

[0011] If the number of times the key is used is less than a second threshold, the central processing unit moves the key to the flash memory, where the second threshold is less than the first threshold.

[0012] Optionally, the SIM card further includes a direct access memory controller, the data loading instruction includes a load key instruction, and the central processing unit executes the data loading instruction to transfer data to the input / output buffer via the bus, including:

[0013] If the key is stored in the dedicated static random access memory, the central processing unit directly executes the key loading instruction to transfer the key from the dedicated static random access memory to the input / output buffer via the bus;

[0014] If the key is stored in the general static random access memory, the central processing unit executes the load key instruction through the direct access memory controller to transfer the key from the general static random access memory to the input / output buffer via the bus.

[0015] Optionally, the data further includes data to be encrypted, which is stored in the flash memory. The data loading instruction further includes a data loading instruction. The central processing unit executes the key loading instruction through the direct access memory controller to transfer the key from the general static random access memory to the input / output buffer via the bus. The method further includes:

[0016] The central processing unit executes the load data instruction through the direct access memory controller to transfer the data to be encrypted from the flash memory to the input / output buffer via the bus. The direct access memory controller includes multiple channels, and the channel used to execute the load key instruction is different from the channel used to execute the load data instruction.

[0017] Optionally, the SIM card further includes a register, and the method further includes:

[0018] The central processing unit adjusts the execution order of the group of instructions through the instruction cache unit according to at least one of the instruction read address, type, and application priority; wherein, the instruction read address is in the flash memory, the instruction read address is in the general static random access memory and the dedicated static random access memory, the instruction read address is in the register, the instruction of type read / write has a higher priority than the instruction of type calculation, and the instruction with higher application priority has a higher priority.

[0019] Optionally, the set of instructions further includes result storage instructions. After the central processing unit executes the data encryption instructions via the post-quantum cryptography hardware accelerator, the method further includes:

[0020] Upon receiving the interrupt information returned by the post-quantum cryptography hardware accelerator, the central processing unit sends a result storage instruction to the direct access memory controller. The result storage instruction carries a source address and a destination address, so that the direct access memory controller can extract the encrypted data from the input / output buffer according to the source address and transmit it to the destination address of the flash memory through the bus.

[0021] A second aspect of this application provides a quantum-resistant cryptographic encryption device applied to a terminal including a SIM card. The SIM card includes a central processing unit, a post-quantum cryptographic hardware accelerator, a static random access memory, an input / output buffer, and a bus. The central processing unit includes an instruction cache unit. The device includes:

[0022] The instruction translation unit is used to receive an encryption request sent by an upper-layer application through the instruction caching unit, and convert the encryption request into a set of instructions, the set of instructions including a data loading instruction and a data encryption instruction;

[0023] A data transmission unit is used to execute the data loading instruction to transmit data to the input / output buffer via the bus;

[0024] A data encryption unit is used to execute the data encryption instructions through the post-quantum cryptography hardware accelerator to encrypt the data in the input / output buffer.

[0025] A third aspect of this application provides a quantum-resistant SIM card, which includes a central processing unit (CPU), a post-quantum cryptography hardware accelerator, an input / output buffer, a bus, a dedicated static random access memory (SRAM), a general static random access memory (SRAM), flash memory, and a direct access memory controller. The CPU includes an instruction cache unit; wherein:

[0026] The instruction cache unit is used to receive encryption requests sent by upper-layer applications, convert the encryption requests into a set of instructions, and adjust the priority of the set of instructions;

[0027] The central processing unit is used to directly or indirectly execute the set of instructions with adjusted priority;

[0028] The input / output buffer is used to cache the data to be encrypted and the key;

[0029] The post-quantum cryptography hardware accelerator is used to encrypt the data to be encrypted according to the key;

[0030] The dedicated static random access memory is used to store the key whose usage exceeds a first threshold; the ordinary static random access memory is used to store the key whose usage is less than the first threshold but more than a second threshold; the flash memory is used to store the key whose usage is less than the second threshold and the data to be encrypted, where the second threshold is less than the first threshold.

[0031] The direct access memory controller is used to transmit at least one of the data to be encrypted, the key, and the encrypted data via a bus.

[0032] A fourth aspect of this application provides an electronic device, including: a processor and a memory;

[0033] The processor is connected to a memory, wherein the memory is used to store computer programs and the processor is used to invoke the computer programs to execute the methods as described in the first aspect of the embodiments of this application.

[0034] The fifth aspect of this application provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, perform the method as described in the first aspect of this application.

[0035] This application incorporates a post-quantum cryptography hardware accelerator and an input / output buffer within the SIM card. Data is transmitted via a bus to the input / output buffer, where the accelerator executes encryption instructions to encrypt the data. The input / output buffer eliminates the need for cumbersome internal data conversion before encryption, optimizing memory access and improving speed. Furthermore, the dedicated accelerator allows the central processing unit (CPU) to offload encryption instructions, further accelerating data encryption. Therefore, this application's embodiment reduces communication response latency caused by the long computation time of quantum cryptography by improving memory access speed and accelerating data encryption, thus enabling post-quantum security encryption within the SIM card. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This invention illustrates a schematic diagram of the structure of a quantum-resistant SIM card according to an embodiment of this application;

[0038] Figure 2 A flowchart illustrating a quantum-resistant cryptographic encryption method provided in one embodiment of this application is shown;

[0039] Figure 3 A flowchart illustrating a quantum-resistant cryptographic encryption method provided in yet another embodiment of this application is shown;

[0040] Figure 4 A flowchart illustrating a quantum-resistant cryptographic encryption method provided in yet another embodiment of this application is shown;

[0041] Figure 5 A flowchart illustrating a quantum-resistant cryptographic encryption method provided in yet another embodiment of this application is shown;

[0042] Figure 6 A flowchart illustrating a quantum-resistant cryptographic encryption method provided in yet another embodiment of this application is shown;

[0043] Figure 7 A flowchart illustrating a quantum-resistant cryptographic encryption method provided in yet another embodiment of this application is shown;

[0044] Figure 8A schematic diagram of the structure of a quantum-resistant cryptographic encryption device provided in one embodiment of this application is shown;

[0045] Figure 9 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0047] Please refer to Figure 1 This illustration shows a schematic diagram of the structure of a quantum-resistant SIM card provided in an embodiment of this application. The SIM card 100 includes a central processing unit (CPU) 110, a post-quantum cryptography (PQC) hardware accelerator 120, an input / output buffer 130, a bus 140, a dedicated static random-access memory (SRAM) 150, a general static random-access memory (SRAM) 160, flash memory 170, and a direct memory access controller (DMA) 180. The central processing unit 110 includes an instruction cache unit (I-Cache) 111; wherein:

[0048] The instruction cache unit 111 is used to receive encryption requests sent by upper-layer applications, convert the encryption requests into a set of instructions, and adjust the priority of the set of instructions;

[0049] The central processing unit 110 is used to directly or indirectly execute the set of instructions with adjusted priority;

[0050] The input / output buffer 130 is used to cache the data to be encrypted and the key;

[0051] The post-quantum cryptography hardware accelerator 120 is used to encrypt the data to be encrypted according to the key;

[0052] The dedicated static random access memory 150 is used to store the key whose usage exceeds a first threshold; the ordinary static random access memory 160 is used to store the key whose usage is less than the first threshold but more than a second threshold; the flash memory 170 is used to store the key whose usage is less than the second threshold and the data to be encrypted, where the second threshold is less than the first threshold.

[0053] The direct access memory controller 180 is used to transmit at least one of the data to be encrypted, the key, and the encrypted data via the bus 140.

[0054] Furthermore, the SIM card 100 may also include a true random number generator 190, which is used to generate true random numbers through physical processes (such as thermal noise, photon behavior), and the true random numbers are used for key generation in the PQC algorithm.

[0055] This application embodiment incorporates a post-quantum cryptography hardware accelerator and an input / output buffer within the SIM card. Data is transmitted via a bus to the input / output buffer, where the accelerator executes encryption instructions to encrypt the data. The input / output buffer eliminates the need for cumbersome internal data conversion before encryption, optimizing memory access and improving speed. Furthermore, the dedicated accelerator allows the central processing unit (CPU) to offload encryption instructions, further accelerating data encryption. Therefore, this application embodiment reduces response latency errors caused by the relatively long computation time resulting from large keys in quantum-resistant cryptography algorithms by improving memory access speed and accelerating data encryption, achieving post-quantum security level encryption protection for the SIM card.

[0056] Please refer to Figure 2 This illustrates a flowchart of a quantum-resistant cryptographic encryption method provided in one embodiment of this application. It is applicable to methods including the above-described... Figure 1 For a terminal with the SIM card shown, the method may include the following steps:

[0057] Step 21: The central processing unit receives the encryption request sent by the upper-layer application through the instruction cache unit, and converts the encryption request into a set of instructions, the set of instructions including data loading instructions and data encryption instructions.

[0058] Among them, a request is a service request made by an application to system resources (such as CPU, memory, etc.), and an encryption request is a service request to encrypt data; an instruction is a machine language command that the system resources can directly execute; a request can be converted into at least one instruction, usually a set of instructions, which may include data loading instructions, data encryption instructions, data storage instructions, etc.

[0059] For example, when an upper-layer application calls an encryption function through an interface unit, it triggers a system call to enter kernel mode. The operating system adds the encryption request to the CPU scheduling queue through an interrupt handler, and the compiler compiles the encryption request into specific encryption instructions.

[0060] Among them, such as Figure 3 As shown, after executing step 21, that is, after the central processing unit receives the encryption request sent by the upper-layer application through the instruction cache unit and converts the encryption request into a set of instructions, the method further includes:

[0061] Step 24: The central processing unit adjusts the execution order of the group of instructions through the instruction cache unit according to at least one of the instruction read address, type, and application priority; wherein, the instruction read address is in the flash memory, the instruction read address is in the general static random access memory and the dedicated static random access memory, the instruction read address is in the register, the instruction of type read / write has a higher priority than the instruction of type calculation, and the instruction with higher application priority has a higher priority.

[0062] The read address of the instruction indicates which hardware the instruction is reading data from. This hardware can be, for example, flash memory, general static random access memory (SRAM), dedicated static random access memory (DRAM), main memory, registers, etc. In this application, the data to be encrypted is usually stored in flash memory, while the key is usually stored in general static random access memory (SRAM) or dedicated static random access memory (DRAM). The size of the data to be encrypted is usually larger than the size of the key. The instruction with the read address of the flash memory has a higher priority than the instruction with the read address of the general static random access memory (SRAM) and the DRAM, which has a higher priority than the instruction with the read address of the register. This makes the data loading instruction precede the key loading instruction, thereby shortening the time spent in the loading instruction and achieving the effect of overall computational acceleration.

[0063] In encryption operations, instructions are mainly categorized into read / write instructions and computation instructions. Read / write instructions can be further subdivided into key loading instructions, data loading instructions (i.e., loading the data to be encrypted, which can be plaintext or intermediate state data), and result storage instructions. Computation instructions can be categorized according to different encryption algorithms, such as row shifting instructions, column obfuscation instructions, and round key addition instructions. In this application, read / write instructions have higher priority than computation instructions. By preloading the data required for subsequent rounds using read / write instructions, computation instructions do not require excessive waiting time, thus accelerating the overall computation.

[0064] The encryption request received by the instruction cache unit can be sent by multiple upper-layer applications. In this case, the instruction priority of the corresponding instruction for each application is determined according to the application priority of these multiple upper-layer applications.

[0065] Step 22: The central processing unit executes the data loading instruction to transfer data to the input / output buffer via the bus.

[0066] The data includes a key stored in the ordinary static random access memory, such as... Figure 4 As shown, before executing step 22, that is, before the central processing unit executes the data loading instruction to transfer data to the input / output buffer via the bus, the method further includes:

[0067] Step 25: The central processing unit periodically detects the number of times the key has been used;

[0068] Step 26: If the number of times the key is used exceeds the first threshold, the central processing unit moves the key to the dedicated static random access memory, which is directly connected to the input / output buffer through hardware mapping.

[0069] Step 27: If the number of times the key is used is less than the second threshold, the central processing unit moves the key to the flash memory, where the second threshold is less than the first threshold.

[0070] Furthermore, the number of times the key is used can be counted within a certain time interval, such as 3 months, half a year, or one year, without any limitation on the time interval. The first threshold can be, for example, 10 times, 15 times, or 20 times, and the second threshold can be 5 times, 10 times, or 15 times. The specific values ​​of the first and second thresholds are not limited here, but it should be noted that the second threshold is less than the first threshold.

[0071] In this embodiment, keys are hierarchically managed according to their access frequency. Keys with different access frequencies are stored in different memories. More frequently used keys can be accessed more quickly through their corresponding storage keys, ensuring a shorter overall response time for key loading during encryption operations, thereby improving the overall efficiency of encryption operations.

[0072] The data loading instructions include loading key instructions, such as... Figure 5 As shown, during step 22, i.e., when the central processing unit executes the data loading instruction to transfer data to the input / output buffer via the bus, the process includes:

[0073] Step 221: Determine whether the key is stored in the dedicated static random access memory or the ordinary static random access memory;

[0074] Step 222: If the key is stored in the dedicated static random access memory, the central processing unit directly executes the key loading instruction to transfer the key from the dedicated static random access memory to the input / output buffer via the bus;

[0075] Step 223: If the key is stored in the general static random access memory, the central processing unit executes the load key instruction through the direct access memory controller to transfer the key from the general static random access memory to the input / output buffer through the bus.

[0076] Furthermore, the method also includes: if the key is stored in the flash memory, the central processing unit first decrypts and loads it into the ordinary static random access memory via the bus, and then executes step 223.

[0077] In this embodiment, if the key is stored in dedicated static random access memory (SRAM), it indicates that the key is accessed frequently. The CPU directly executes the key loading instruction, directly connecting the dedicated SRAM to the input / output buffer of the PQC hardware accelerator via hardware mapping. If the key is stored in ordinary static random access memory (SRAM), it indicates that the key is accessed at a moderate frequency and can be dynamically managed by the operating system. The CPU directly accesses the memory controller to execute the key loading instruction, transferring the key from SRAM to the input / output buffer via the bus. If the key is stored in flash memory, it indicates that the key is accessed less frequently. The CPU first decrypts and loads the key into SRAM via the bus, and then performs the read operation when the key is stored in SRAM. The multi-level key storage and loading mechanism provided in this application enables faster key access, ensuring a shorter overall response time for key loading during encryption operations, thereby improving the overall efficiency of encryption operations.

[0078] The data also includes data to be encrypted, which is stored in the flash memory. The data loading instruction also includes a data loading instruction, such as... Figure 6 As shown, while performing step 222, that is, while the central processing unit executes the load key instruction through the direct access memory controller to transfer the key from the general static random access memory to the input / output buffer via the bus, the method further includes:

[0079] Step 224: The central processing unit executes the load data instruction through the direct access memory controller to transfer the data to be encrypted from the flash memory to the input / output buffer through the bus. The direct access memory controller includes multiple channels, and the channel used to execute the load key instruction is different from the channel used to execute the load data instruction.

[0080] The data to be encrypted can be plaintext or intermediate state data during the encryption process; no limitation is made here. In this embodiment, a multi-channel mechanism that directly accesses the memory controller is used to simultaneously execute data loading instructions and key loading instructions, so that the key and data are loaded into the specified area at the same time. Both are loading instructions, which reduces the overall execution time of the loading instructions.

[0081] Step 23: The central processing unit executes the data encryption instructions through the post-quantum cryptography hardware accelerator to encrypt the data in the input / output buffer.

[0082] The post-quantum cryptography hardware accelerator is equipped with dedicated circuits, such as polynomial multipliers and hash engines, which can perform efficient operations on the data in the input and output buffers. In addition to the keys (public keys or temporary keys, etc.) and the data to be encrypted (plaintext, intermediate data, etc.) mentioned above, the data in the input and output buffers can also include other data determined by the selected post-quantum cryptography algorithm, such as random numbers generated by a true random number generator.

[0083] The set of instructions also includes result storage instructions, such as... Figure 7 As shown, after executing step 23, that is, after the central processing unit executes the data encryption instructions through the post-quantum cryptography hardware accelerator, the method further includes:

[0084] Step 28: Receive the interrupt information returned by the post-quantum cryptography hardware accelerator. The central processing unit sends a result storage instruction to the direct access memory controller. The result storage instruction carries a source address and a destination address, so that the direct access memory controller can extract the encrypted data from the input / output buffer according to the source address and transmit it to the destination address of the flash memory through the bus.

[0085] For example, the interrupt information can be an interrupt signal sent by the post-quantum cryptography hardware accelerator to the central processing unit (CPU) through the interrupt controller, and the encryption status is marked in the status register. The CPU suspends its current task, jumps to the interrupt service routine, reads the status register of the post-quantum cryptography hardware accelerator, confirms the operation is successful, and clears the interrupt flag. Based on the location of the encryption result and storage requirements, the CPU constructs a storage instruction for the direct access memory controller (DRAM). This storage instruction carries the following information: source address and destination address, and may also include transfer length and transfer mode. The source address represents the starting physical address of the encrypted data in the input / output buffer of the post-quantum cryptography hardware accelerator. The destination address represents the target storage address in the flash memory. The transfer length represents the total size of the encrypted data. The transfer mode can be either burst mode or block transfer. The CPU writes the above parameters to the DRAM through the memory-mapped register or a dedicated instruction port, and the DRAM performs the transfer to achieve the storage of the encryption result.

[0086] This application embodiment incorporates a post-quantum cryptography hardware accelerator and an input / output buffer within the SIM card. Data is transmitted via a bus to the input / output buffer, where the accelerator executes encryption instructions to encrypt the data. The input / output buffer eliminates the need for cumbersome internal data conversion before encryption, optimizing memory access and improving speed. Furthermore, the dedicated accelerator allows the central processing unit (CPU) to offload encryption instructions, further accelerating data encryption. Therefore, this application embodiment reduces communication response latency caused by the long computation time of quantum cryptography by improving memory access speed and accelerating data encryption, thus enabling post-quantum security encryption within the SIM card.

[0087] Figure 8 A schematic diagram of a quantum-resistant cryptographic encryption device according to an embodiment of this application is shown. Applied to a terminal including a SIM card, the SIM card includes a central processing unit, a post-quantum cryptography hardware accelerator, a static random access memory, an input / output buffer, and a bus. The central processing unit includes an instruction cache unit. The device includes:

[0088] The instruction translation unit 801 is used to receive an encryption request sent by an upper-layer application through the instruction cache unit, and convert the encryption request into a set of instructions, the set of instructions including a data loading instruction and a data encryption instruction;

[0089] The data transmission unit 802 is used to execute the data loading instruction to transmit data to the input / output buffer via the bus;

[0090] The data encryption unit 803 is used to execute the data encryption instructions through the post-quantum cryptography hardware accelerator to encrypt the data in the input / output buffer.

[0091] Figure 9 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the functions of the computer system of the quantum-resistant cryptographic encryption method in any of the above embodiments.

[0092] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the functions of the computer system with quantum-resistant cryptographic encryption method in any of the above embodiments.

[0093] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the functions of the computer system using the quantum-resistant cryptographic encryption method described in any of the above embodiments.

[0094] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0095] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0096] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0097] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0098] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0099] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0100] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0101] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0102] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0103] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0104] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0105] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0106] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A quantum-resistant cryptographic encryption method, characterized in that, Applied to a terminal including a SIM card, the SIM card including a central processing unit, a post-quantum cryptography hardware accelerator, an input / output buffer, a bus, a dedicated static random access memory, a general static random access memory, and flash memory, the central processing unit including an instruction cache unit, the method comprising: The central processing unit receives encryption requests sent by upper-layer applications through the instruction cache unit and converts the encryption requests into a set of instructions, including data loading instructions and data encryption instructions. The central processing unit executes the data loading instruction to transfer data to the input / output buffer via the bus, the data including a key stored in the general static random access memory; The central processing unit executes the data encryption instructions through the post-quantum cryptography hardware accelerator to encrypt the data in the input / output buffer; Before the central processing unit executes the data loading instruction to transfer data to the input / output buffer via the bus, the method further includes: The central processing unit periodically detects the number of times the key is used; If the number of times the key is used exceeds a first threshold, the central processing unit moves the key to the dedicated static random access memory, which is directly connected to the input / output buffer through hardware mapping. If the number of times the key is used is less than a second threshold, the central processing unit moves the key to the flash memory, where the second threshold is less than the first threshold.

2. The method according to claim 1, characterized in that, The SIM card also includes a direct access memory controller, the data loading instruction includes a load key instruction, and the central processing unit executes the data loading instruction to transfer data to the input / output buffer via the bus, including: If the key is stored in the dedicated static random access memory, the central processing unit directly executes the key loading instruction to transfer the key from the dedicated static random access memory to the input / output buffer via the bus; If the key is stored in the general static random access memory, the central processing unit executes the load key instruction through the direct access memory controller to transfer the key from the general static random access memory to the input / output buffer via the bus.

3. The method according to claim 2, characterized in that, The data also includes data to be encrypted, which is stored in the flash memory. The data loading instruction also includes a data loading instruction. The central processing unit executes the key loading instruction through the direct access memory controller to transfer the key from the general static random access memory to the input / output buffer via the bus. The method further includes: The central processing unit executes the load data instruction through the direct access memory controller to transfer the data to be encrypted from the flash memory to the input / output buffer via the bus. The direct access memory controller includes multiple channels, and the channel used to execute the load key instruction is different from the channel used to execute the load data instruction.

4. The method according to claim 3, characterized in that, The SIM card also includes a register, and the method further includes: The central processing unit adjusts the execution order of the group of instructions through the instruction cache unit according to at least one of the instruction read address, type, and application priority; wherein, the instruction read address is in the flash memory, the instruction read address is in the general static random access memory and the dedicated static random access memory, the instruction read address is in the register, the instruction of type read / write has a higher priority than the instruction of type calculation, and the instruction with higher application priority has a higher priority.

5. The method according to any one of claims 2-4, characterized in that, The set of instructions also includes result storage instructions. After the central processing unit executes the data encryption instructions via the post-quantum cryptography hardware accelerator, the method further includes: Upon receiving the interrupt information returned by the post-quantum cryptography hardware accelerator, the central processing unit sends a result storage instruction to the direct access memory controller. The result storage instruction carries a source address and a destination address, so that the direct access memory controller can extract the encrypted data from the input / output buffer according to the source address and transmit it to the destination address of the flash memory through the bus.

6. A quantum-resistant cryptographic encryption device, characterized in that, An apparatus applicable to a terminal including a SIM card, wherein the SIM card includes a central processing unit, a post-quantum cryptography hardware accelerator, static random access memory, an input / output buffer, a bus, dedicated static random access memory, general static random access memory, and flash memory, wherein the central processing unit includes an instruction cache unit, and the apparatus includes: The instruction translation unit is used to receive an encryption request sent by an upper-layer application through the instruction caching unit, and convert the encryption request into a set of instructions, the set of instructions including a data loading instruction and a data encryption instruction; A data transmission unit is configured to execute the data loading instruction to transmit data to the input / output buffer via the bus, the data including a key stored in the general static random access memory; A data encryption unit is used to execute the data encryption instructions through the post-quantum cryptography hardware accelerator to encrypt the data in the input / output buffer; Before the central processing unit executes the data loading instruction to transfer data to the input / output buffer via the bus, the data transfer unit is further configured to: The number of times the key is used is periodically checked; If the number of times the key is used exceeds a first threshold, the key is moved to the dedicated static random access memory, which is directly connected to the input / output buffer through hardware mapping. If the number of times the key is used is less than a second threshold, the key is moved to the flash memory, where the second threshold is less than the first threshold.

7. A quantum-resistant SIM card, characterized in that, The SIM card includes a central processing unit (CPU), a post-quantum cryptography hardware accelerator, an input / output buffer, a bus, a dedicated static random access memory (SRAM), a general static random access memory (SRAM), flash memory, and a direct access memory controller. The CPU includes an instruction cache unit. The instruction cache unit is used to receive encryption requests sent by upper-layer applications, convert the encryption requests into a set of instructions, and adjust the priority of the set of instructions; The central processing unit is used to directly or indirectly execute the set of instructions with adjusted priority; The input / output buffer is used to cache the data to be encrypted and the key; The post-quantum cryptography hardware accelerator is used to encrypt the data to be encrypted according to the key; The dedicated static random access memory is used to store the key whose usage exceeds a first threshold; the ordinary static random access memory is used to store the key whose usage is less than the first threshold but more than a second threshold; the flash memory is used to store the key whose usage is less than the second threshold and the data to be encrypted, where the second threshold is less than the first threshold. The direct access memory controller is used to transmit at least one of the data to be encrypted, the key, and the encrypted data via a bus.

8. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to perform the method as described in any one of claims 1-5.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in any one of claims 1-5.

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