Signal processing techniques

Abstract

The invention discloses a signal processing technology, and particularly discloses a device, a system and a technology for guiding and transmitting wireless signals by utilizing a neural network to jointly infer signal parameters. In at least one embodiment, one or more neural networks are trained using reinforcement learning techniques to deduce hybrid beamforming parameters used by one or more devices to transmit wireless signals.

Description

[0001] Cross - Reference to Related Applications

[0002] This application also incorporates by reference in its entirety for all purposes the entire disclosure of co-pending U.S. Patent Application No. 18 / 536,048, titled "SIGNAL PROCESSING TECHNIQUES USING SIGNAL INFORMATION", filed concurrently with this application. TECHNICAL FIELD

[0003] At least one embodiment relates to processing resources for performing and facilitating wireless communication. For example, at least one embodiment relates to a processor or computing system that uses a neural network to process signals for transmission. TECHNICAL BACKGROUND

[0004] Processing signals in wireless communication consumes a large amount of memory, time, or computing resources, which can limit the effectiveness of each signal. For example, due to computational limitations, some signal processing techniques may generate suboptimal signals. Therefore, signal processing techniques in wireless communication can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A block diagram of a neural network training system using deep reinforcement learning techniques according to at least one embodiment is shown;

[0006] Figure 2 A block diagram of a system for training a neural network to infer hybrid beamforming signal parameters according to at least one embodiment is shown;

[0007] Figure 3 A block diagram of a system for training a neural network to infer hybrid beamforming signal parameters and transmit power according to at least one embodiment is shown;

[0008] Figure 4 A block diagram of a system for training a neural network using a reward according to at least one embodiment is shown;

[0009] Figure 5 A block diagram of a system for training a neural network using a reward according to at least one embodiment is shown;

[0010] Figure 6 A process of training a neural network to infer hybrid beamforming signal parameters according to at least one embodiment is shown;

[0011] Figure 7 A block diagram of a process of training a neural network to infer hybrid beamforming signal parameters according to at least one embodiment is shown;

[0012] Figure 8A A block diagram showing a driver and / or runtime including an API for inferring hybrid beamforming signal parameters according to at least one embodiment;

[0013] Figure 8B A block diagram showing a processor and modules for training a neural network to infer hybrid beamforming parameters according to at least one embodiment;

[0014] Figure 9A A block diagram showing logic according to at least one embodiment;

[0015] Figure 9B A block diagram showing logic according to at least one embodiment;

[0016] Figure 10 A block diagram showing the training and deployment of a neural network according to at least one embodiment;

[0017] Figure 11 A block diagram showing an example data center system according to at least one embodiment;

[0018] Figure 12A A block diagram showing an example of an autonomous vehicle according to at least one embodiment;

[0019] Figure 12B A block diagram showing according to at least one embodiment Figure 12A an example of the camera positions and fields of view of an autonomous vehicle;

[0020] Figure 12C is a block diagram showing an example system architecture of an autonomous vehicle according to at least one embodiment Figure 12A ;

[0021] Figure 12D is a diagram showing a system for communication between one or more cloud-based servers and Figure 12A an autonomous vehicle according to at least one embodiment;

[0022] Figure 13 is a block diagram showing a computer system according to at least one embodiment;

[0023] Figure 14 is a block diagram showing a computer system according to at least one embodiment;

[0024] Figure 15 A block diagram showing a computer system according to at least one embodiment;

[0025] Figure 16 A block diagram showing a computer system according to at least one embodiment;

[0026] Figure 17A A block diagram showing a computer system according to at least one embodiment;

[0027] Figure 17B shows a computer system in accordance with at least one embodiment;

[0028] Figure 17C shows a computer system in accordance with at least one embodiment;

[0029] Figure 17D shows a computer system in accordance with at least one embodiment;

[0030] Figure 17E and Figure 17F shows a shared programming model in accordance with at least one embodiment;

[0031] Figure 18 shows an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

[0032] Figures 19A - 19B shows an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

[0033] Figures 20A - 20B shows additional exemplary graphics processor logic in accordance with at least one embodiment;

[0034] Figure 21 shows a computer system in accordance with at least one embodiment;

[0035] Figure 22A shows a parallel processor in accordance with at least one embodiment;

[0036] Figure 22B shows a partitioning unit in accordance with at least one embodiment;

[0037] Figure 22C shows a processing cluster in accordance with at least one embodiment;

[0038] Figure 22D shows a graphics multiprocessor in accordance with at least one embodiment;

[0039] Figure 23 shows a multi-graphics processing unit (GPU) system in accordance with at least one embodiment;

[0040] Figure 24 shows a graphics processor in accordance with at least one embodiment;

[0041] Figure 25 is a block diagram showing a processor microarchitecture for a processor in accordance with at least one embodiment;

[0042] Figure 26 shows a deep learning application processor in accordance with at least one embodiment;

[0043] Figure 27 is a block diagram showing an example neuromorphic processor according to at least one embodiment;

[0044] Figure 28 shows at least a portion of a graphics processor according to one or more embodiments;

[0045] Figure 29 shows at least a portion of a graphics processor according to one or more embodiments;

[0046] Figure 30 shows at least a portion of a graphics processor according to one or more embodiments;

[0047] Figure 31 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0048] Figure 32 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0049] Figures 33A - 33B shows thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core;

[0050] Figure 34 shows a parallel processing unit ("PPU") according to at least one embodiment;

[0051] Figure 35 shows a general processing cluster ("GPC") according to at least one embodiment;

[0052] Figure 36 shows a memory partition unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0053] Figure 37 shows a streaming multiprocessor according to at least one embodiment;

[0054] Figure 38 is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0055] Figure 39 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline according to at least one embodiment;

[0056] Figure 40 includes an example illustration of an advanced computing pipeline for processing imaging data according to at least one embodiment;

[0057] Figure 41AExample data flow diagrams for virtual instruments supporting ultrasound devices according to at least one embodiment;

[0058] Figure 41B Example data flow diagrams for virtual instruments supporting CT scanners according to at least one embodiment;

[0059] Figure 42A Data flow diagrams showing a process for training a machine learning model according to at least one embodiment;

[0060] Figure 42B An example illustration of a client - server architecture for enhancing an annotation tool using a pre - trained annotation model according to at least one embodiment; and

[0061] Figure 43 Shows components of a system for accessing a large language model according to at least one embodiment. Detailed Description

[0062] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, one of ordinary skill in the art will appreciate that the concepts of the present invention may be practiced without one or more of these specific details, and that two or more aspects of any one or more of the embodiments described herein may be combined.

[0063] In at least one embodiment, a neural network infers hybrid beamforming parameters and / or transmit power that a device will use to transmit wireless signals based on signal data input into the neural network. In at least one embodiment, the neural network is trained using reinforcement learning techniques, which will be described further below. In at least one embodiment, the neural network generates hybrid beamforming parameters by jointly inferring analog beamforming parameters and digital beamforming parameters. In at least one embodiment, the neural network jointly infers hybrid beamforming parameters, which means inferring analog beamforming parameters and digital beamforming parameters that are mixed with each other during a single forward pass, where input data is processed through the neural network from the input layer to the output layer during the training of the neural network. In at least one embodiment, a single forward pass is referred to as a single inference pass or a single inference run. In at least one embodiment, the trained neural network jointly infers analog and digital signal parameters for use as part of a hybrid beamforming process. In at least one embodiment, inferring the hybrid beamforming parameters is used to optimize the signal - to - noise ratio (SNR) of the transmitted signal. In at least one embodiment, optimizing the SNR means increasing the SNR.

[0064] In at least one embodiment, the hybrid beamforming parameters include baseband weights used in digital beamforming and radio frequency (RF) weights used in analog beamforming. In at least one embodiment, the baseband weights and RF weights are values applied to a signal to modify the signal. In at least one embodiment, the baseband weights are complex values, which may be referred to as complex numbers. In at least one embodiment, the baseband weights are applied to a signal to modify the amplitude and phase of the signal. In at least one embodiment, the RF weights are applied to a signal to modify the phase of the signal. In at least one embodiment, the phase of a signal is the position of the signal at a certain point in time on the waveform period and is indicated using degrees (0 - 360) or radians (0 - 2π). In at least one embodiment, the phase of a signal is referred to as the phase angle.

[0065] In at least one embodiment, the hybrid beamforming parameters are phase values, such as phase angles and phase shifts. In at least one embodiment, the hybrid beamforming parameter is a phase shift, which is a value expressed in degrees or radians indicating how to modify the phase of a signal. In at least one embodiment, the hybrid beamforming parameters are power values, gain values, amplitude values, magnitude values, or some combination thereof. In at least one embodiment, the hybrid beamforming parameters are regarded as coefficients. In at least one embodiment, the hybrid beamforming parameters include carrier frequency information. In at least one embodiment, the hybrid beamforming parameters include an indication of a specific signal, device, cell, or some combination thereof to which the hybrid beamforming parameters are to be applied.

[0066] In at least one embodiment, the neural network identifies the beam direction and / or transmit power to be used by a device to transmit a signal based on information about another signal being transmitted or received by another device. In at least one embodiment, identifying the beam direction and / or transmit power based on information about another signal is used to optimize the signal-to-interference-and-noise ratio (SINR) of all signals being transmitted in a wireless network, which in turn increases the total data throughput of the network. In at least one embodiment, optimizing the SINR means increasing the SINR.

[0067] In at least one embodiment, the hybrid beamformer is a combination of hardware, firmware, and software that modifies a signal so that a signal can be transmitted in a specific direction using multiple antennas and constructive interference and destructive interference. In at least one embodiment, the hybrid beamformer uses a combination of analog and digital beamformer components and techniques. In at least one embodiment, a beam is a directional signal transmitted by one or more antennas.

[0068] In at least one embodiment, joint inference simulation and digital beamforming parameters refer to neural network training that includes inferring one or more analog beamforming parameters associated with one or more digital beamforming parameters, and / or vice versa.

[0069] In at least one embodiment, neural network inference will use hybrid beamforming parameters and / or transmit power used by devices in a wireless network such as a 5G network. In at least one embodiment, devices used in a wireless network include, but are not limited to, beamformers, user equipment (UE), antenna arrays, and base stations. In at least one embodiment, transmit power refers to a transmit power parameter or a power parameter. In at least one embodiment, transmit power refers to the output of a transmitter power amplifier. In at least one embodiment, increasing the transmit power of a signal can increase the amplitude of that signal.

[0070] In at least one embodiment, a wireless signal is referred to as a radio frequency (RF) signal. In at least one embodiment, a directional wireless signal is referred to as a beam. In at least one embodiment, a wireless signal is referred to as a radio signal or a wireless radio signal. In at least one embodiment, a signal is a wireless signal. In at least one embodiment, a signal is a wired signal. In at least one embodiment, a signal refers to any aspect of a communication signal, including any data carried by the signal. In at least one embodiment, various wireless communication devices convert wired signals to wireless signals and / or vice versa.

[0071] In at least one embodiment, training a neural network to perform hybrid beamforming as described herein creates a wider range of possible directions for pilot signals while meeting signal processing latency requirements. In at least one embodiment, the neural network is trained to infer hybrid beamforming parameters and / or transmit power to increase the total rate of at least a portion of a wireless network. In at least one embodiment, the total rate refers to the total data transmission rate or throughput of all signals in at least a portion or all of a wireless network. In at least one embodiment, a portion of a wireless network refers to a cell. In at least one embodiment, a cell refers to the geographical area covered by a base station. In at least one embodiment, a base station is a receiver and transmitter of wireless signals and can serve as a hub for wireless devices, a connection to a wired network, a connection to different wireless networks, or some combination thereof.

[0072] Figure 1FIG. 0 shows a neural network training system 100 according to at least one embodiment. In at least one embodiment, the neural network training system 100 trains one or more neural networks to infer parameters for performing hybrid beamforming and / or to infer transmit power that will be used by a device to transmit wireless signals as part of a communication network. In at least one embodiment, one or more aspects of one or more embodiments described herein in connection with Figure 1 one or more aspects of one or more embodiments described herein (including at least in connection with Figures 2 - 8B those embodiments described) are combined with one or more aspects of one or more embodiments described herein. In at least one embodiment, one or more processors perform one or more operations used by the neural network training system 100. In at least one embodiment, the one or more processors that perform one or more operations used by the neural network training system 100 are any one or combination of processors described herein, including in connection with Figure 8B one or more processors 822 described, in connection with Figure 19A graphics processor 1910 described, and in connection with Figure 34 parallel processing unit (“PPU”) 3400 described. In at least one embodiment, one or more processors 822 perform operations used by the deep reinforcement learning agent system 104, such as inferring signal parameters using the neural network module 114 and calculating a reward function using the reward module 122.

[0073] In at least one embodiment, the neural network training system 100 includes one or more input signals 102, a deep reinforcement learning agent module 104, an actor module 106, an environment module 108, a signal preprocessing module 112, a neural network module 114, a signal parameter module 116, a signal characteristic calculation module 118, a channel state information (CSI) module 120, and a reward module 122.

[0074] In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or is clearly contrary, terms such as “system” and “module” and nounified verbs (e.g., compiler and / or other terms) refer to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functions described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions. In at least one embodiment, hardware alone or in any combination includes hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware storing instructions executed by programmable circuitry. In at least one embodiment, modules may be embodied jointly or separately as circuitry that forms part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), etc.

[0075] In at least one embodiment, the neural network training system 100 uses one or more reinforcement learning techniques to train a neural network to generate signal parameters for hybrid beamforming. In at least one embodiment, reinforcement learning refers to a type of neural network training, neural network learning, or machine learning. In at least one embodiment, the neural network training system 100 uses one or more reinforcement learning techniques to train a neural network to modify the transmit power of one or more wireless signals. In at least one embodiment, reinforcement learning refers to one or more machine learning operations that include an autonomous agent further described herein, the autonomous agent generating modifications to data and / or functions to maximize a reward function within a given set of constraints. In at least one embodiment, maximizing the reward function is used to update the parameters (e.g., weights) of the neural network. In at least one embodiment, deep reinforcement learning is referred to as reinforcement learning. In at least one embodiment, any module or combination of modules that performs one or more operations of reinforcement learning is referred to as a reinforcement learning system.

[0076] In at least one embodiment, one or more input signals 102 include one or more signals of a wireless communication network. In at least one embodiment, one or more input signals 102 are a dataset of signal parameters for training a neural network. In at least one embodiment, the dataset of signal parameters includes data representing frequency values, phase angle values, phase shift values, gain values, transmit power values, or some combination thereof. In at least one embodiment, one or more input signals 102 are simulated signals determined by software for simulating a wireless communication system. In at least one embodiment, one or more input signals 102 are simulated signals that include a set of signal parameters, rather than actual signals transmitted by a transmitter. In at least one embodiment, one or more input signals 102 are wireless signals generated by a wireless signal generator. In at least one embodiment, one or more input signals 102 are signals of any wireless communication network operating under a current or future protocol or standard, such as fifth generation new radio (5G or 5G NR), sixth generation wireless (6G), IEEE 802, Wi-Fi 7. In at least one embodiment, a wireless signal is any signal of any wireless communication network operating under a current or future protocol or standard, such as fifth generation new radio (5G or 5G NR), sixth generation wireless (6G), IEEE 802, Wi-Fi 7. In at least one embodiment, a wireless signal is a wireless signal transmitted and / or received by a base station. In at least one embodiment, a wireless communication network refers to any combination of hardware, firmware, software, architecture, signal, method, or the like used in 5G wireless communication.

[0077] In at least one embodiment, a wireless communication network is referred to as a wireless network or a network. In at least one embodiment, one or more input signals 102 are digital signals or their representations. In at least one embodiment, one or more input signals 102 are analog signals or their representations. In at least one embodiment, data includes discrete and / or continuous numerical values. In at least one embodiment, one or more input signals 102 are data sets representing parameters of a signal, such as amplitude and phase. In at least one embodiment, data includes imaginary and / or real numbers. In at least one embodiment, data includes complex numbers, which include an imaginary part and a real part. In at least one embodiment, the rate at which data carried by any signal is transmitted or received per unit time is referred to as the data transmission rate. In at least one embodiment, the rate at which desired data is transmitted or received per unit time is referred to as the effective data rate or throughput. The rate at which all data in a part or all of a wireless network is transmitted is referred to as the total rate. In at least one embodiment, the total rate refers to the total data throughput in a part or all of a wireless network. In at least one embodiment, two or more signals among one or more input signals 102 use different bandwidths within different frequency ranges.

[0078] In at least one embodiment, the deep reinforcement learning agent module 104 uses one or more modules (e.g., the actor module 106, the signal characteristic calculation module 118, and the reward module 122) to maximize a signal characteristic given an input signal and constraints included in the environment module 108. In at least one embodiment, the deep reinforcement learning agent module 104 attempts to maximize the signal-to-noise ratio (SNR) of a modified input signal with respect to environmental conditions in the form of channel state information (CSI). In at least one embodiment, the deep reinforcement learning agent module 104 attempts to increase the signal-to-noise ratio of the modified input signal to meet or exceed a threshold or target value. In at least one embodiment, CSI refers to any property of a communication link between a transmitter and a receiver.

[0079] In at least one embodiment, the deep reinforcement learning agent module 104 performs one or more operations used in reinforcement learning. In at least one embodiment, the deep reinforcement learning module 104 includes other modules for performing operations used in reinforcement learning. In at least one embodiment, the deep reinforcement learning agent module 104 acts as an agent in a deep reinforcement learning system. In at least one embodiment, an agent is a combination of hardware, firmware, or software that attempts to maximize a reward, which will be further described herein. In at least one embodiment, the deep reinforcement learning agent module 104 performs data transmission between modules, as Figure 1As shown by the arrow in, including transmitting the data output by the signal preprocessing module 112 to the actor module 106, where the actor module 106 receives the data as input data. In at least one embodiment, the deep reinforcement learning agent module 104 performs Figure 1 data transmission between any two modules shown in. In at least one embodiment, any module of the deep reinforcement learning agent module 104 is communicatively connected to any one or more other modules of the deep reinforcement learning agent module 104. In at least one embodiment, one or more modules of the deep reinforcement learning agent module 104 are implemented on another module, and the other module includes a reward module 122 implemented on the environment module 108, as Figure 1 shown. In at least one embodiment, a module implemented on another module refers to the hardware, firmware, software, or some combination thereof of the module installed on the hardware components (such as a processor and / or memory) of another module. In at least one embodiment, the deep reinforcement learning agent module 104 performs one or more operations of other types of neural network training, such as supervised learning, semi-supervised learning, unsupervised learning, or some combination thereof.

[0080] In at least one embodiment, the deep reinforcement learning agent module 104 is referred to as an autonomous agent or an agent. In at least one embodiment, an agent is one or more modules that include algorithms and / or functions that cause data to be modified, such as modifying wireless signal parameters based on the data included and / or generated by the environment module 108. In at least one embodiment, the deep reinforcement learning agent module 104 performs the modification of the signal parameters by using the neural network included in the actor module 106.

[0081] In at least one embodiment, the actor module 106 performs data modification on signal parameters (e.g., hybrid beamforming parameters). In at least one embodiment, one or more data modifications performed by the actor module 106 are referred to as one or more actions. In at least one embodiment, an action conceptually refers to a state-changing decision made by the actor module 106. In at least one embodiment, the state includes the current value of the signal parameters to be input into the neural network. In at least one embodiment, the state includes information about the actions previously taken by the actor module 106, which will be further described herein. In at least one embodiment, the state includes the SNR of each signal being used by the UE. In at least one embodiment, the signal being used by the UE refers to the signal being received by the UE. In at least one embodiment, the signal being used by the UE refers to the signal being transmitted by the UE. In at least one embodiment, the state of the deep reinforcement learning agent system 104 includes the signal parameters output by the signal preprocessing module 112. In at least one embodiment, the state includes the channel state information provided by the environment module 108. In at least one embodiment, the state includes the signal parameters previously generated by the actor module 106. In at least one embodiment, conceptually, the actor is used for actor-critic type reinforcement learning. In at least one embodiment, conceptually, the actor decides what action to take for the current state. In at least one embodiment, conceptually, the actor associates the state with these previously executed actions by obtaining and / or otherwise receiving action-based rewards. In at least one embodiment, the reward is an integer. In at least one embodiment, the actor module 106 uses a neural network (e.g., the neural network included in the neural network module 114) to infer the action to be taken. In at least one embodiment, the action is a set of one or more new signal parameters inferred by the neural network. In at least one embodiment, at least conceptually, the new signal parameters inferred by the neural network are considered actions because they change the input signal parameters to new parameters. In at least one embodiment, the actor module 106 uses a separate neural network to update the neural network weights of the neural network module 114. In at least one embodiment, the input to the neural network of the actor module 106 is data representing the current state. In at least one embodiment, the output of the neural network of the actor module 106 is considered the modified state. In at least one embodiment, the output of the neural network of the actor module 106 is one or more indications of the actions required to modify the state.

[0082] In at least one embodiment, the actor module 106 performs operations to modify signal parameters of one or more wireless signals as part of a hybrid beamforming process and / or a transmit power modification process to maximize the SNR and / or SINR of the one or more signals. In at least one embodiment, the actor module 106 performs operations to modify signal parameters of one or more wireless signals such that the SNR and / or SINR of the one or more signals meets or exceeds a threshold. In at least one embodiment, the actor module 106 performs operations to modify signal parameters based on the expected SNR and / or SINR of a wireless signal when it is transmitted. In at least one embodiment, the expected SNR and / or SINR is generated by performing a mathematical function on the signal parameters of an analog signal. In at least one embodiment, the signal parameters are output by a signal preprocessing module 112 in the actor module 106. In at least one embodiment, the state includes the signal parameters output by the signal preprocessing module 112 and / or the signal parameters previously output by the signal preprocessing module 112.

[0083] In at least one embodiment, the environment module 108 includes parameters related to how signals are processed and / or transmitted. In at least one embodiment, the environment module 108 includes a number of modules that generate and / or otherwise output data that the actor module 106 uses to reason about actions to take to maximize signal characteristics such as SNR and / or SINR. In at least one embodiment, the environment module 108 includes a number of modules that generate and / or otherwise output data that the actor module 106 uses to update neural network weights and / or functions. In at least one embodiment, the neural network weights and / or functions are considered part of a policy updated during a reinforcement learning process. In at least one embodiment, the actor module 106 updates the policy to maximize a reward, which will be further described herein. In at least one embodiment, the environment module 108 includes parameters related to channel state information (CSI). In at least one embodiment, the environment module 108 includes parameters related to channel impulse response (CIR), channel frequency response (CFR). In at least one embodiment, the CSI includes information related to scattering, fading, power attenuation, delay, amplitude, phase, or some combination thereof of devices and / or signals in a wireless network.

[0084] In at least one embodiment, the signal preprocessing module 112 processes one or more input signals 102 to make them suitable as inputs to a neural network. In at least one embodiment, the signal preprocessing module 112 samples one or more input signals 102 to convert analog signals into digital signals. In at least one embodiment, the signal preprocessing module 112 filters one or more input signals 102 to remove unwanted aspects such as noise, interference, distortion, or some combination thereof. In at least one embodiment, the signal preprocessing module 112 modifies the data of one or more input signals 102 into tensors of a specific dimension such that the neural network can process these tensors as input data. In at least one embodiment, scalars and vectors are types of tensors.

[0085] In at least one embodiment, the neural network module 114 includes one or more neural networks. In at least one embodiment, the neural network module 114 infers signal parameters used in hybrid beamforming. In at least one embodiment, the neural network module 114 infers the transmit power for transmitted signals. In at least one embodiment, the processor sends the signal parameters inferred by the neural network module 114 to the signal parameter module 116. In at least one embodiment, the neural network includes any neural network discussed herein, including the neural network combined Figure 10 with the neural network discussed. In at least one embodiment, the neural network includes a processor, data, functions, and neural network parameters for making inferences based on input data. In at least one embodiment, the neural network parameters include neural network weights. In at least one embodiment, the neural network parameters are periodically modified based on rewards generated during the deep learning enhanced neural network training process. In at least one embodiment, the neural network parameters are parameters used by the actor module 104 to determine the performance characteristics (such as accuracy) of the neural network. In at least one embodiment, the neural network parameters include parameters indicating the learning rate of the neural network, the local iteration of the neural network, the aggregated weights of the neural network, the number of neurons in the neural network, or some combination thereof.

[0086] In at least one embodiment, the neural network is a recurrent neural network (RNN), a convolutional neural network (CNN), a generative adversarial network (GAN), a transformer, a graph neural network (GNN), or some combination thereof. In at least one embodiment, the neural network is a CNN (e.g., U-Net) with a 5-level encoder-decoder network architecture, where there are residual blocks at each level. In at least one embodiment, a residual block is a stack of neural network layers, where the output of one layer is added to another deeper layer in the residual block. In at least one embodiment, a layer is a structure or network topology that includes nodes corresponding to features extracted from a dataset. In at least one embodiment, the encoder-decoder network includes two recurrent neural networks, one for encoding the input data and another for decoding the encoded data. In at least one embodiment, the recurrent network is a neural network that uses sequential data. In at least one embodiment, the training system uses training data to train an untrained neural network using systems and methods such as those described herein to generate a trained neural network. In at least one embodiment, the untrained neural network is a neural network that has been partially trained and will be further trained. In at least one embodiment, the training data is a training dataset.

[0087] In at least one embodiment, the signal parameter module 116 includes a memory that stores parameters inferred by the neural network module 114. In at least one embodiment, the parameters include values such as amplitude, phase angle, baseband bandwidth, number of radio frequency (RF) chains, number of resource elements (REs), number of component carriers, transmit power, or some combination thereof, all of which will be described in further detail Figure 2 below. In at least one embodiment, the signal parameter module 116 stores in the memory signal parameters inferred based on at least some of the previous actions taken by the actor module 106. In at least one embodiment, the signal parameter module 116 performs operations such as F.normalize(), Argmax, Pmax F.Sigmoid(), as described in conjunction with Figure 2 and Figure 3 described further below. In at least one embodiment, the signal parameter module 116 converts the phase angle into a one-hot encoded vector. In at least one embodiment, one-hot encoding is a data format that represents an integer value as a vector, where the values of the vector are encoded in binary and indicate the integer value. In at least one embodiment, the vector used in one-hot encoding is called a one-hot vector. In at least one embodiment, one-hot encoding is used to satisfy the unit modulus constraint. In at least one embodiment, the unit modulus constraint is used for the analog components of the hybrid beamforming system to constrain the magnitude of the complex number representing the phase angle to be no greater than 1.

[0088] In at least one embodiment, the signal characteristic calculation module 118 calculates signal characteristics using the signal parameters output by the neural network module 114 and modified by the signal parameter module 116. In at least one embodiment, the signal characteristic calculation module 118 calculates signal characteristics using the signal parameters and the channel state information output by the channel state information module 120. In at least one embodiment, signal characteristics refer to any characteristic or quality of one or more signals. In at least one embodiment, signal characteristics refer to SNR, SINR, total rate, or some combination thereof. In at least one embodiment, the signal characteristic calculation module 118 calculates one or more signal characteristics of one or more input signals 102, which have been modified at least conceptually using the signal parameters inferred by the neural network and the CSI. In at least one embodiment, at least conceptually, the actor module 106 modifies the parameters of a signal (such as one or more input signals 102) to attempt to cause the signal characteristic calculation module 118 to output signal characteristics that are maximized or above a threshold, as indicated by the reward module 122. In at least one embodiment, the signal processing neural network training system 100 trains a neural network to infer signal parameters used in hybrid beamforming, which, when applied to a signal, maximize the signal-to-noise ratio of the signal. In at least one embodiment, the signal processing neural network training system 100 trains a neural network to infer signal parameters and transmit power, which, when applied to multiple signals within a portion of a wireless communication network, can maximize the total rate of that portion.

[0089] In at least one embodiment, the channel state information (CSI) module 120 stores the CSI in a memory. In at least one embodiment, the CSI module 120 includes CSI for one or various wireless network scenarios. In at least one embodiment, the CSI module 120 generates hypothesized CSI for training the neural network. In at least one embodiment, the CSI module 120 stores CSI information recorded from real-world scenarios. In at least one embodiment, the CSI module 120 stores CSI information recorded from channel state information reference signals (CSI-RS). In at least one embodiment, the CSI includes information that can be used to estimate the time difference of arrival (TDOA) and the angle of arrival (AOA). In at least one embodiment, the CSI includes channel frequency response (CFR) information, which can be used to estimate how the channel affects different components of a signal (e.g., amplitude, phase). In at least one embodiment, the CSI includes channel quality indicator (CQI) information, which can be used to indicate how well a signal is received and decoded. In at least one embodiment, the CSI information includes parameters such as a precoding type indicator (PTI), a precoding matrix indicator (PMI), a rank indicator (RI), a layer indicator (LI), or some combination thereof.

[0090] In at least one embodiment, the reward module 122 uses one or more functions to calculate a reward for the actor module 104. In at least one embodiment, the reward indicates the effectiveness of the parameters inferred by the neural network in improving signal characteristics such as signal-to-noise ratio (SNR) or signal-to-interference-plus-noise (SINR) ratio. In at least one embodiment, the reward module 122 includes one or more reward functions, such as the reward function described in the process 600 in combination with Figure 6 . In at least one embodiment, the reward function is a continuous reward function that varies with the channel state information. In at least one embodiment, the reward function is a discrete reward function that varies discontinuously with the channel state information. In at least one embodiment, the discrete reward function varies with the occurrence of an event, such as when the actor module 114 receives a reward exceeding a target value. In at least one embodiment, the reward function is a combination of a continuous reward function and a discrete reward function.

[0091] In at least one embodiment, the neural network training system 100 includes a computer-readable storage medium and / or code stored on the computer-readable storage medium in the form of a computer program, the computer program including a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions that can be used to perform the operations described herein (including the operations described in combination with Figures 1 - 8B ) are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within a transceiver of a transient signal. In at least one embodiment, the neural network training system 100 is implemented as a non-transitory computer-readable storage medium storing executable instructions that, if executed by one or more processors of a computer system, cause the computer system to perform the operations of a neural network that infers hybrid beamforming parameters and / or transmit power to be used by a device to transmit wireless signals.

[0092] Figure 2 FIG. 200 shows a system for training a neural network to infer signal parameters used in hybrid beamforming according to at least one embodiment. In at least one embodiment, one or more aspects of one or more embodiments described in combination with Figure 2 are combined with one or more aspects of one or more embodiments described herein, including at least in combination with Figure 1 and Figures 3 - 8BThe described embodiments. In at least one embodiment, one or more processors that perform one or more operations used by system 200 are any one or combination of processors described herein, including those in conjunction with Figure 8B the one or more processors 822 described in conjunction with Figure 19A the graphics processor 1910 described in conjunction with Figure 34 the parallel processing unit (“PPU”) 3400 described in conjunction with. In at least one embodiment, one or more processors 822 perform the operations of actor 210. In at least one embodiment, one or more processors 822 perform action 230 to update state 220 to be input into neural network 214. In at least one embodiment, action 230 is a set of one or more modifications to be applied to state 220. In at least one embodiment, action 230 is the output of neural network 214. In at least one embodiment, action 230 is signal parameter 219 or its representation. In at least one embodiment, updating state 220 using action 230 means replacing the signal parameter included in state 220 with signal parameter 219. In at least one embodiment, actor 210 performs one or more operations performed by Figure 1 the actor module 106 of Figure 3 such as modifying signal parameters. In at least one embodiment, actor 210 performs one or more operations performed by Figure 4 the actor 310 of Figure 5 where such operations include generating an action for modifying the transmit power of a signal. In at least one embodiment, actor 210 is Figure 4 the actor 410 of Figure 5 and / or Figure 4 the actor 510 of Figure 5 In at least one embodiment, actor 210 outputs data, such as signal parameters, to Figure 4 the environment 450 of Figure 5 and / or Figure 7 the environment 550 of. In at least one embodiment, actor 210 performs any one or more operations of process 600, such as updating analog and digital precoding vectors with operation 606. In at least one embodiment, actor 210 performs one or more operations of the reinforcement learning neural network training process as shown in Figure 7 including generating an action for updating the critic module.

[0093] In at least one embodiment, neural network 214 is the neural network included in Figure 1 the neural network module 114 of. In at least one embodiment, any neural network appearing in any figure (including Figure 2 the neural network 214 of 1 does not represent any specific type or structure of neural network, but is only for illustrative purposes. In at least one embodiment, neural network 214 includes weights W from layer 1 to layer L 1 to W L。In at least one embodiment, neural network 214 includes biases b 1 through b L 。In at least one embodiment, the nodes of the neural network are represented by lowercase sigmas within circles.

[0094] In at least one embodiment, state 220 is input into neural network 214. In at least one embodiment, state 220 represents signal parameters of a signal transmitted or received by a user equipment. In at least one embodiment, the signal parameters represented by state 220 are signal parameters included in an input dataset of the signal. In at least one embodiment, the signal parameters represented by state 220 are signal parameters that have been updated by actor 210 as a result of a training round or inference pass. In at least one embodiment, the input dataset of the signal is generated based on real-world signals. In at least one embodiment, the input dataset of the signal is generated by a simulator. In at least one embodiment, the signal parameters represented by state 220 are generated by neural network 214 during a previous training round.

[0095] In at least one embodiment, state 220 includes channel state information (CSI) or a channel matrix. In at least one embodiment, state 220 is represented by s t where t represents a particular time step. In at least one embodiment, the stage in the deep learning reinforcement neural network training process is indicated by the time step. In at least one embodiment, the time step is related to the number of times a forward pass and / or actor 210 has performed action 230 at least conceptually. In at least one embodiment, state 220 represents the SNR most recently generated by an environment module (such as environment 108 described in conjunction with Figure 1 ). In at least one embodiment, state 220 includes any environmental information, such as any information indicating the characteristics of a wireless network and its environment. In at least one embodiment, the environmental information includes information about signal quality, hardware type, software type, architecture, the number of connected devices and / or stations, or some combination thereof. In at least one embodiment, state 220 represents any information related to the signal parameters output by neural network 214 that will result in a stronger and more reliable signal than without neural network 214. In at least one embodiment, state 220 represents any information about the signal and / or wireless network related to the signal parameters output by neural network 214 that can be used to generate a signal with a signal-to-noise ratio exceeding a threshold. In at least one embodiment, state 220 represents a history of previous state information input into actor 210, including the inputs and outputs of neural network 214. In at least one embodiment, state 220 represents a history of previously calculated SNR and / or reward values. In at least one embodiment, state 220 represents a history of previously used channel state information.

[0096] In at least one embodiment, the neural network 214 uses the inference to generate signal parameters 216. In at least one embodiment, the signal parameters 216 include the real and imaginary parts of the baseband parameters to be used for the real baseband signal or the analog baseband signal, where these parameters are organized in vector form. In at least one embodiment, the baseband parameters are referred to as baseband weights. In at least one embodiment, the real part of the baseband parameter is represented as Real(W bb ), and the imaginary part of the baseband parameter is represented as Imag(W bb ). In at least one embodiment, the signal parameters 216 include phase values represented by phi, Φ. In at least one embodiment, the phase values include the values of each phase shifter in the analog part of the hybrid beamforming system and are represented as a length-N one-hot vector. In at least one embodiment, a linear output of the signal parameter representing the phase angle and / or phase shift is used instead of one-hot encoding to satisfy the unit modulus constraint. In at least one embodiment, the phase values include the phase angles corresponding to the analog phase shifters. In at least one embodiment, N RF identifies a specific RF chain. In at least one embodiment, N r identifies a specific receiving antenna among the N receiving antennas. In at least one embodiment, N c identifies a specific carrier frequency. In at least one embodiment, the number N is based on the total number of analog components in the hybrid beamforming system including RF chains and antennas.

[0097] In at least one embodiment, one or more signal parameters 216 are modified by the function F.normalize() 217 and Argmax 218. In at least one embodiment, F.normalize() 217 is a function of an application programming interface (API) library used in machine learning to normalize the values in a tensor in one or more dimensions. In at least one embodiment, normalizing the values includes scaling the values of the vector so that they fall between 0 and 1. In at least one embodiment, normalizing the values includes scaling the values of the vector so that they have a mean of 0 and a standard deviation of 1. In at least one embodiment, the signal parameters 216 are at least partially normalized by techniques or functions other than F.normalize(), which include min-max scaling and z-score normalization. In at least one embodiment, the real and imaginary parts of the baseband parameters output by the neural network 214 are normalized.

[0098] In at least one embodiment, Argmax 218 is a function of an API library used in machine learning to generate one or more indices of one or more maximum values based on a function. In at least one embodiment, Argmax 218 is performed on the phase value of the signal parameter 216. In at least one embodiment, the phase value (e.g., phase angle) of the signal parameter 216 is represented using a one-hot encoding format. In at least one embodiment, one-hot encoding represents an integer value as a binary vector, where the values of the binary vector indicate the integer value. In at least one embodiment, each phase shifter is represented as a one-hot vector expressed as b = {0, 1}^N, such that ||b||_0 = 1, where N is the number of possible discrete phase angles. In at least one embodiment, one or more functions (e.g., Argmax 218) are performed to transform the phase value of the signal parameter 216 into a corresponding phase shift. In at least one embodiment, the representation of discrete values and / or quantized values is implemented using one-hot encoding.

[0099] In at least one embodiment, after performing F.normalize() 217 and Argmax 218 on the signal parameter 216, the resulting data set is the signal parameter 219. In at least one embodiment, the signal parameter 219 includes normalized baseband parameters, which are represented as Real(W bb ) and Imag(W bb ), as Figure 2 shown. In at least one embodiment, the signal parameter 219 includes a phase shift represented by θ. In at least one embodiment, the phase shift of the signal parameter 219 is represented in one-hot encoding format. In at least one embodiment, the actor 210 outputs the signal parameter 219 to the environment 250.

[0100] In at least one embodiment, the action 230 is represented by a t , where t represents a specific time step. In at least one embodiment, the stage in the deep learning reinforcement neural network training process is indicated by the time step. In at least one embodiment, the time step is related to the number of times the forward pass and / or the actor 210 has performed the action 230 at least conceptually. In at least one embodiment, the action at time step t is Real(W bb ) and Imag(W bb) and the concatenated vector of one-hot encoded phase angles, which are the values found in the signal parameters 219. In at least one embodiment, at least conceptually, by using the neural network 214 to reason about the signal parameters that make up the concatenated vector, this concatenated vector representing the action at time step t indicates one or more actions that the actor 210 has taken. In at least one embodiment, the actions taken by the actor 210 refer at least in part to the reasoning performed by the neural network 214. In at least one embodiment, in addition to the environment 250, the actions 230 are also sent to the critic 240.

[0101] In at least one embodiment, the critic 240 is a module that includes a neural network that provides feedback on the quality of the actions 230 taken by the actor 210. In at least one embodiment, the critic 240 includes a value function. In at least one embodiment, as further described herein, the value function estimates future rewards based on the state and the corresponding actions inferred based on that state. In at least one embodiment, the value function is based on past rewards and estimates of future rewards for a given state and expected actions generated by the actor 210. In at least one embodiment, the output of the value function improves the actions generated by the actor 210 over multiple time steps. In at least one embodiment, the output of the value function is referred to as the Q-value. In at least one embodiment, the value function is used to help continuously improve the performance of the neural network during training.

[0102] In at least one embodiment, the environment 250 shares one or more aspects of the environment module 108 described in conjunction with Figure 1 and the environment 450 described in conjunction with Figure 4 In at least one embodiment, the environment 250 includes the signal characteristic calculation module 118, the channel state information module 120, and the reward module 122 described in conjunction with Figure 1 In at least one embodiment, the environment 250 includes signal parameters 419a - b, channel state information 430, a signal-to-noise ratio calculation module 440, a reward 450, and a next state 460, as described in conjunction with Figure 4 as described.

[0103] Figure 3 FIG. shows a system 300 used in a reinforcement learning neural network training system for training a neural network to identify beam directions and reason about transmit power within a wireless communication network. In at least one embodiment, one or more aspects of one or more embodiments described in conjunction with Figure 3 are combined with one or more aspects of one or more embodiments described herein, including at least in conjunction with Figures 1 - 2 and Figures 4 - 8BThe aspects described. In at least one embodiment, one or more processors for one or more operations used by execution system 300 are any one processor or combination of processors described herein, including in conjunction with Figure 8B one or more processors 822 described, in conjunction with Figure 19A graphics processor 1910 described, and in conjunction with Figure 34 parallel processing unit (“PPU”) 3400 described. In at least one embodiment, one or more processors 822 perform operations of actor 310. In at least one embodiment, one or more processors 822 perform action 330 to update state 320 to be input into neural network 314. In at least one embodiment, actor 310 performs one or more operations performed by Figure 1 actor module 106 of Figure 2 , such as modifying signal parameters. In at least one embodiment, actor 310 performs one or more operations performed by Figure 4 actor 210 of Figure 5 , where these operations include generating an action to modify the transmit power of a signal. In at least one embodiment, actor 310 is Figure 4 actor 410 of Figure 5 and / or Figure 4 actor 510 of Figure 5 . In at least one embodiment, actor 310 outputs data, such as signal parameters, to Figure 4 environment 450 of Figure 5 and / or Figure 4 environment 550 of Figure 5 . In at least one embodiment, actor 310 performs any one or more operations of process 600, such as updating analog and digital precoding vectors with operation 606. In at least one embodiment, actor 310 performs any one or more operations of reinforcement learning shown in Figure 7 , such as updating a critic module.

[0104] In at least one embodiment, neural network 314 is a neural network included in Figure 1 neural network module 114 of Figure 3 . In at least one embodiment, neural network 314 shares one or more aspects of neural network 214. In at least one embodiment, neural network 314 shown in Figure 3 does not represent any particular type or structure of neural network and is included only for illustrative purposes. In at least one embodiment, neural network 314 includes weights W 1 to W L for layers 1 to L. In at least one embodiment, neural network 3 includes biases b 1 to b L。In at least one embodiment, a node of a neural network is represented by a lowercase sigma inside a circle. In at least one embodiment, neural network 314 is being trained to identify one or more beam directions to be used by one or more first user equipment (UE) to transmit wireless signals based on information about beams used by one or more second UEs. In at least one embodiment, neural network 314 is being trained to identify beam directions based on inferred signal parameters and / or transmit power of two or more signals that result in a signal-to-interference-plus-noise ratio (SINR) and / or sum rate higher than a threshold. In at least one embodiment, the neural network identifies a beam direction to be used by a first device to transmit a signal by inferring a beam direction that optimizes an overall SINR that includes information (such as transmit power and beam direction) of another signal that is being transmitted or is to be transmitted. In at least one embodiment, after identifying a beam direction to be used by a signal, the neural network infers hybrid beamforming parameters to be used to steer the transmission of the signal in a beam in the identified direction. In at least one embodiment, a beam direction is a direction in which a signal is transmitted as described by an angular value. In at least one embodiment, the process of directing or steering a signal is referred to as beamforming. In at least one embodiment, beamforming a signal at least refers to applying signal parameters to the signal in order to direct the signal. In at least one embodiment, beamforming includes other modifications to the signal, including modifications to shape the signal. In at least one embodiment, a UE includes devices such as a laptop computer, a tablet computer, a mobile phone, a portable Internet hotspot, and an autonomous vehicle. In at least one embodiment, neural network 314 is being trained to identify beam directions of signals to be transmitted by a first UE based on information about beams transmitted by a second UE in order to reduce overall signal interference generated by multiple signals in one or more cells of a wireless network. In at least one embodiment, reducing overall signal interference increases data throughput in one or more cells of a wireless network.

[0105] In at least one embodiment, state 320 is input into neural network 314. In at least one embodiment, state 320 represents signal parameters of two or more signals transmitted or received by two or more user devices connected to a single base station. In at least one embodiment, the two or more signals transmitted or received by two or more user devices connected to a single base station partially describe a part of the wireless network. In at least one embodiment, a part of the wireless network is a cell, where each cell includes a single base station. In at least one embodiment, the signal parameters represented by state 320 are signal parameters included in the input data set of the signal. In at least one embodiment, the signal parameters represented by state 320 are signal parameters that have been updated by actor 310 as a result of a training round or an inference pass. In at least one embodiment, the input data set of the signal is generated based on calculations and / or recordings of real-world signals. In at least one embodiment, the signal parameters represented by state 220 are generated by neural network 214 in a previous training round.

[0106] In at least one embodiment, state 320 includes channel state information (CSI) or a channel matrix of two or more signals. In at least one embodiment, state 320 is represented by s t where t represents a specific time step. In at least one embodiment, state 320 represents any information indicating characteristics of the wireless network and its environment, including information about its signal quality, hardware type, software type, architecture, the number of connected devices and / or stations, or some combination thereof. In at least one embodiment, state 320 represents any information related to the output signal and transmit power parameters of neural network 314, where the signal and transmit power parameters are estimated to result in an increase in the total data throughput of a part of the wireless network, the wireless network including two or more wireless signals transmitted between a user device and a base station. In at least one embodiment, the total data throughput of a part of the wireless network is referred to as the total rate. In at least one embodiment, state 320 represents any information related to the signal and / or the wireless network related to the output signal parameters of neural network 414, where the signal parameters can be used to generate multiple signals that jointly exhibit a SINR exceeding a threshold, where such SINR can be referred to as common SINR, total SINR, or overall SINR. In at least one embodiment, the threshold is referred to as the target value. In at least one embodiment, state 420 represents a history of previous state information input into actor 310, including the input and output of neural network 314. In at least one embodiment, state 320 represents a history of previously calculated SINR and / or reward values. In at least one embodiment, state 320 represents a history of previously used channel state information.

[0107] In at least one embodiment, the neural network 314 generates signal parameters 316 by using inference. In at least one embodiment, the signal parameters 316 include the types of signal parameters described in conjunction with Figure 2 the signal parameters 216. In at least one embodiment, the signal parameters 316 include a power parameter, denoted as p. In at least one embodiment, the power parameter is referred to as the transmit power parameter or transmit power. In at least one embodiment, N u indicates a specific user or user equipment.

[0108] In at least one embodiment, one or more signal parameters 316 are modified by the functions F.normalize() 317 and Argmax 318 (which are also described as F.normalize() 217 and Argmax 218). In at least one embodiment, one or more signal parameters 316 are modified by the function Pmax F.Sigmoid() 321, which is a function of an API library used in machine learning. In at least one embodiment, Pmax represents the maximum transmit power value, and F.Sigmoid() is an activation function. In at least one embodiment, Pmax F.Sigmoid() 321 scales the output of the activation function to adjust the transmit power of two or more signals.

[0109] In at least one embodiment, after performing F.normalize() 317 and Argmax 318 on the signal parameters 316, the resulting data set is the signal parameters 319. In at least one embodiment, as Figure 3 shown, the signal parameters 319 include the normalized baseband parameters represented as Real(W bb ) and Imag(W bb ). In at least one embodiment, the signal parameters 319 include a phase shift represented by θ. In at least one embodiment, the phase shift of the signal parameters 319 is encoded using one-hot encoding. In at least one embodiment, the signal parameters include a scaled transmit power value represented by p, as Figure 3 shown. In at least one embodiment, the actor 310 outputs the signal parameters 319 to the environment 350.

[0110] In at least one embodiment, the action 330 is represented by a t , where t represents a specific time step. In at least one embodiment, the action at time step t is Real(W bb ) and Imag(W bb) A concatenated vector of one-hot encoded phase angles and transmit powers, which are values found in signal parameter 319. In at least one embodiment, at least conceptually, by using neural network 314 to infer the signal parameters that make up the concatenated vector, this concatenated vector representing the action at time step t indicates one or more actions that actor 310 has taken. In at least one embodiment, the actions taken by actor 310 at least partially refer to the inferences made by neural network 314. In at least one embodiment, in addition to environment 350, action 330 is also sent to critic 340.

[0111] In at least one embodiment, critic 340 includes a neural network that provides feedback on the quality of the actions 330 taken by actor 310. In at least one embodiment, critic 340 includes one or more aspects and performs one or more operations of critic 240, as described in conjunction with Figure 2 above. In at least one embodiment, environment 350 shares one or more aspects and performs one or more operations of environment module 108 described in conjunction with Figure 1 , environment 250 described in conjunction with Figure 2 and environment 450 described in conjunction with Figure 4 . In at least one embodiment, critic 340 is updated to minimize the gap between the values represented as Q(s t ,a t ) and , which will be further described in conjunction with Figure 7 . In at least one embodiment, actor 310 is updated to maximize Q. In at least one embodiment, critic 340 outputs Q(s t ,a t ).

[0112] Figure 4 FIG. shows system 400 used in a reinforcement learning neural network training system according to at least one embodiment, which uses environment 450 to evaluate the actions performed by actor 410. In at least one embodiment, one or more aspects of one or more embodiments described in conjunction with Figure 4 are combined with one or more aspects of one or more embodiments described herein, including at least in conjunction with Figures 1 - 3 and Figures 5 - 8B described aspects. In at least one embodiment, one or more processors that perform one or more operations used by system 400 are any one or combination of processors described herein, including one or more processors 822 described in conjunction with Figure 8B , graphics processor 1910 described in conjunction with Figure 19A and in conjunction with Figure 34The described parallel processing unit (“PPU”) 3400. In at least one embodiment, one or more processors 822 perform the operations of the actor 410. In at least one embodiment, one or more processors 822 perform the operations of the signal-to-noise ratio (SNR) calculation module 440 to output data used by the reward module 442 to generate a reward value. In at least one embodiment, the SNR calculation module 440 performs Figure 1 one or more operations of the signal characteristic calculation module 118 of Figure 2 , such as calculating the SNR. In at least one embodiment, the environment 450 performs one or more operations performed by the Figure 4 environment 250 of Figure 3 . In at least one embodiment, the Figure 7 environment 450 is the

[0113] environment 350 of Figure 1 . In at least one embodiment, the environment 450 performs one or more operations of the environment 550, including calculating the next state using the next state module 560. In at least one embodiment, the environment 450 performs any one or more operations of the process 600, such as calculating the SNR with operation 608. In at least one embodiment, the environment 450 performs Figure 2 one or more operations of the reinforcement learning neural network training process shown in Figure 3 , including generating the next state. Figure 2 In at least one embodiment, the actor 410 shares any one or more aspects and performs at least one or more operations in combination with the Figure 4 actor module 106 described in

[0114] , the actor 210 described in Figure 1 and the actor 310 described in

[0115] In at least one embodiment, the SNR calculation module 440 calculates the SNR of a signal using the signal parameters 419a, the signal parameters 419b, and the channel state information of the CSI module 430. In at least one embodiment, the SNR calculation module 440 uses the operations described in Figure 6 operation 608 to calculate the SNR.

[0116] In at least one embodiment, the SNR calculation module 440 outputs the SNR value to the reward module 442. In at least one embodiment, the reward module 442 uses the SNR as an input to one or more functions to output a value that indicates how much the action of the actor 410 improves the SNR of the signal. In at least one embodiment, the reward function outputs a positive or negative integer value, the magnitude of which corresponds to the amount of increase or decrease in the SNR of the signal. In at least one embodiment, the reward module 442 outputs the reward value to the actor 410, the target actor 480, the target critic 470, or some combination thereof.

[0117] In at least one embodiment, the next state module 460 outputs the next state represented by s t+1 where t + 1 indicates the next time step in the reinforcement learning neural network training process. In at least one embodiment, the next state represents the environment, which includes the SNR output by the SNR calculation module 440 during the next time step. In at least one embodiment, the data output by the next state module 460 becomes the current state data, such as the state 220 described in Figure 2 . In at least one embodiment, the data output by the next state module 460 includes the SNR output by the SNR calculation module 440, the channel state information of the channel state information module 430, the signal parameters 419a, the signal parameters 419b, or some combination thereof. In at least one embodiment, the data output by the next state module 460 and the reward value output by the reward module 442 are used by the actor 410 to update the parameters of the neural network, such as the neural network 214 described in Figure 2 . In at least one embodiment, the next state module outputs the data to the target critic 470.

[0118] In at least one embodiment, the target critic 470 is a neural network and uses one or more aspects of the neural network architecture used by the Figure 2 critic 240 and / or Figure 3 critic 340. In at least one embodiment, the weights of the target critic 470 are updated less frequently than the weights of critics such as the critic 240 and the critic 340. In at least one embodiment, the target critic 470 helps to mitigate the problem of overestimation of the value output by the value function and improve the training of the actor neural network (e.g.,Figure 3 During the weight adjustment of the neural network 314), the stability. In at least one embodiment, the value output by the value function is referred to as the Q-value.

[0119] In at least one embodiment, the target critic 470 uses the output of the target actor 480. In at least one embodiment, the target actor 480 is a neural network and uses one or more aspects of the neural network architecture used by an actor such as the actor 410. In at least one embodiment, the weights of the target actor 480 are updated less frequently than the weights of an actor such as the actor 410. In at least one embodiment, the target actor 480 helps to mitigate the problem of overestimation of the value output by the value function and improve the stability of the weight adjustment performed during the training of the actor neural network (such as the neural network 314) described in conjunction with Figure 3 the stability of the weight adjustment during the training of the neural network 314) described.

[0120] Figure 5 FIG. shows a system 500 used in a reinforcement learning neural network training system according to at least one embodiment, which uses an environment 550 to evaluate the actions performed by an actor 510. In at least one embodiment, one or more aspects of one or more embodiments described in conjunction with Figure 5 are combined with one or more aspects of one or more embodiments described herein, including at least in combination with Figures 1 - 4 and Figures 6 - 8B the aspects described. In at least one embodiment, one or more processors that perform one or more operations used by the system 500 are any one of the processors or combinations of processors described herein, including in combination with Figure 8B one or more processors 822 described, in combination with Figure 19A the graphics processor 1910 described, and in combination with Figure 34 the parallel processing unit (“PPU”) 3400 described. In at least one embodiment, one or more processors 822 perform the operations of the actor 410. In at least one embodiment, one or more processors 822 perform the operations of the signal-to-interference-and-noise ratio (SINR) calculation module 540 to output data used by the reward module 542 to generate a reward value. In at least one embodiment, the SINR calculation module 540 performs Figure 1 one or more operations of the signal characteristic calculation module 118, such as calculating the SINR. In at least one embodiment, the environment 550 performs one or more operations performed by the Figure 2 environment 250. In at least one embodiment, the environment 550 is Figure 3environment 350. In at least one embodiment, environment 550 performs one or more operations of environment 450, including calculating a next state using next state module 460. In at least one embodiment, environment 550 performs any one or more operations of process 600, such as calculating SNR with operation 708. In at least one embodiment, environment 550 performs Figure 7 any one or more operations of the reinforcement learning neural network training process shown, including generating a next state.

[0121] In at least one embodiment, actor 510 shares any one or more aspects and performs operations in conjunction with Figure 1 actor module 106 described, in conjunction with Figure 2 actor 210 described, and in conjunction with Figure 3 actor 310 described. In at least one embodiment, actor 510 outputs signal parameters, such as signal parameter 219 described in conjunction with Figure 2 or signal parameter 319 described in conjunction with Figure 3 to be received by environment 550 or otherwise obtained by environment 550. In at least one embodiment, actor 510 outputs signal parameters depicted as signal parameters 519a - c. In at least one embodiment, signal parameter 519a is an analog beamforming parameter, and signal parameter 519b is a digital beamforming parameter. In at least one embodiment, signal parameter 519c is a transmit power modification parameter.

[0122] In at least one embodiment, signal parameters 519a - c are input into SINR calculation module 540. In at least one embodiment, channel state information (CSI) module 530 outputs channel state information to be received as input data by SINR calculation module 540. In at least one embodiment, CSI module 530 includes any one or more aspects of CSI module 120 described in conjunction with Figure 1 or performs any one or more operations of CSI module 120.

[0123] In at least one embodiment, SINR calculation module 540 uses signal parameter 519a, signal parameter 519b, signal parameter 519c, and channel state information of CSI module 530 to calculate the SINR of a signal. In at least one embodiment, SINR calculation module 540 uses the operations described with operation 708 in conjunction with Figure 7 to calculate the SINR.

[0124] In at least one embodiment, the SINR calculation module 540 outputs the SINR value to the reward module 542. In at least one embodiment, the reward module 542 uses the SINR as an input to one or more functions to output a value that indicates how much the action of the actor 510 improves the SINR of the signal. In at least one embodiment, the reward function outputs a positive or negative integer value, the magnitude of which corresponds to the amount of increase or decrease in the SNR of the signal. In at least one embodiment, the reward module 542 outputs a reward value to the actor 510, the target actor 580, the target critic 570, or some combination thereof.

[0125] In at least one embodiment, the next state module 560 outputs the next state represented by s t+1 where t+1 represents the next time step in the reinforcement learning neural network training process. In at least one embodiment, the next state represents the environment, which includes the SINR output by the SINR calculation module 540 during the next time step. In at least one embodiment, the data output by the next state module 560 becomes the current state data, such as the state 220 described in conjunction with Figure 2 . In at least one embodiment, the data output by the next state module 560 includes the SINR output by the SINR calculation module 540, the channel state information of the channel state information module 530, the signal parameters 519a, the signal parameters 519b, the signal parameters 519c, or some combination thereof. In at least one embodiment, the data output by the next state module 560 and the reward value output by the reward module 542 are used by the actor 510 to update the parameters of the neural network, such as the neural network 214 described in conjunction with Figure 2 . In at least one embodiment, the next state module outputs data to the target critic 570.

[0126] In at least one embodiment, the target critic 570 is a neural network and uses one or more aspects of the neural network architecture used by the critic 240 described in conjunction with Figure 2 and / or the critic 340 described in conjunction with Figure 3 . In at least one embodiment, the weights of the target critic 570 are updated less frequently than the weights of critics such as the critic 240 and the critic 340. In at least one embodiment, the target critic 570 helps to mitigate the problem of overestimation of the value output by the value function and improve the stability of the weight adjustment performed during the training of the actor neural network (such as the neural network 314 described in conjunction with Figure 3 ).

[0127] In at least one embodiment, the target critic 570 uses the output of the target actor 580. In at least one embodiment, the target actor 580 is a neural network and uses one or more aspects of the neural network architecture used by an actor such as actor 510. In at least one embodiment, the weights of the target actor 580 are updated less frequently than the weights of an actor such as actor 510. In at least one embodiment, the target actor 580 helps mitigate the problem of overestimating the value of the value function output and improves the stability of the weight adjustment performed during the training of the actor neural network (such as the neural network 314 described in connection with Figure 3 ).

[0128] Figure 6 FIG. 600 shows a process 600 according to at least one embodiment, which is used by a reinforcement learning neural network training system to train a neural network to modify both the analog and digital parameters of a signal using hybrid beamforming techniques to achieve an SNR, SINR, total rate, or some combination thereof above a threshold. In at least one embodiment, one or more aspects of one or more embodiments described in connection with Figure 6 are combined with one or more aspects of one or more embodiments described herein, including at least in combination with Figures 1 - 5 and Figures 7 - 8B described aspects. In at least one embodiment, one or more processors that perform one or more operations used in process 600 are any one processor or combination of processors described herein, including one or more processors 822 described in connection with Figure 8B , a graphics processor 1910 described in connection with Figure 19A , and a parallel processing unit (“PPU”) 3400 described in connection with Figure 34 . In at least one embodiment, one or more processors 822 perform the operations of actor 410. In at least one embodiment, one or more processors 822 perform operation 608 to calculate the SNR such that the SNR calculation module 440 described in connection with Figure 4 can output the SNR that will be used by the reward module 442 also described in connection with Figure 4 . In at least one embodiment, the reward module 122 described in connection with Figure 1 performs operation 610 of process 600 to output a reward value. In at least one embodiment, the actor 210 described in connection with Figure 2 and the actor 310 described in connection with Figure 3 perform operation 606 of process 600 to update the analog and digital precoding vectors. In at least one embodiment, the environment 450 described in connection with Figure 4 and the environment 550 described in connection with Figure 5 perform operation 608 of process 600 to calculate the SNR.

[0129] In at least one embodiment, process 600 begins with obtaining a signal with operation 602. In at least one embodiment, obtaining a signal means that a processor receives one or more parameters of a wireless signal as input. In at least one embodiment, these parameters include values related to amplitude, phase angle, and frequency.

[0130] In at least one embodiment, the signal obtained with operation 602 is part of a multiple-input multiple-output (MIMO) uplink system of a 5G wireless network. In at least one embodiment, the MIMO uplink system uses a steering vector of a uniform linear array (ULA) to beamform the signal using the analog component of a hybrid beamforming system. In at least one embodiment, a uniform linear array is a set of sensors placed equidistantly along a straight line, where the sensors can be antennas. In at least one embodiment, the ULA steering vector is expressed as follows:

[0131] a(θ,N) = [1,e 2π(d / λ)sinθ ,…,e 2π(N-1)(d / λ)sinθ T

[0132] In at least one embodiment, θ represents the angle of arrival of the signal; N represents the number of elements in the ULA; d represents the distance between each element of the ULA; λ represents the wavelength of the signal; and e 2π(d / λ)sinθ represents the phase shift applied to each element of the ULA to direct the beam to direction θ. In at least one embodiment, the ULA steering vector is a complex-valued vector that describes how to weight the signals at the array elements to form a beam in a specific direction. In at least one embodiment, a complex-valued vector is a vector that includes complex values (sometimes called complex numbers). In at least one embodiment, each element of the ULA steering vector corresponds to a different array element.

[0133] In at least one embodiment, the MIMO uplink system uses a discrete ray propagation model, also known as a geometric channel model, which is a line-of-sight channel model. In at least one embodiment, the discrete ray propagation model expresses the channel matrix as:

[0134]

[0135] In at least one embodiment, is the sum over p, where p is the index of the path in the wireless channel; N p represents the number of paths; α p represents the complex gain of path p; a(θ p ,N r ) represents the steering vector at the receiving antenna of path p; θ p ​Denotes the arrival angle of path p; N r Represents the number of receiving antennas.

[0136] In at least one embodiment, the discrete ray propagation model expresses the received signal at the hybrid beamforming system as:

[0137]

[0138] In at least one embodiment, Denotes the baseband and RF precoders that modify the signal parameters. In at least one embodiment, it is applied at the transmitter And is used to maximize the signal quality at the receiver. ρ represents the transmit power of the signal. In at least one embodiment, H represents the channel matrix; s represents the transmit signal; n represents the noise at the receiver.

[0139] In at least one embodiment, a set of RF precoding matrices used in beamforming is represented as:

[0140] Where

[0141] In at least one embodiment, Denotes a matrix of size N r ×N RF Where N r Is the number of receiving antennas, and N RF Is the number of RF chains. In at least one embodiment, Denotes a set of phase angles. In at least one embodiment, the values included in the precoding matrix (RF or baseband) are the weights applied to the signal, such as phase and gain.

[0142] In at least one embodiment, a set of baseband precoding matrices is expressed as:

[0143]

[0144] In at least one embodiment, Denotes a set of complex matrices. In at least one embodiment, N u Refers to the number of data streams being transmitted, which are the signals carrying user data.

[0145] In at least one embodiment, the processor continues process 600 by inputting the obtained signal data into a neural network by performing operation 604. In at least one embodiment, the neural network is part of the actor module described herein. In at least one embodiment, the neural network is Figure 2 The neural network 214 of Figure 3The neural network 314 or some combination thereof. In at least one embodiment, the neural network obtains signal parameters, such as the values included in the Rf and baseband precoding matrices, and infers new signal parameters to improve the SNR of a signal or the total SINR of two or more signals.

[0146] In at least one embodiment, the processor continues process 600 by performing operation 606 to calculate the SNR and / or SINR based on the signal parameters output by the neural network (such as the values of the precoding matrix). In at least one embodiment, the formula for calculating the SNR is expressed as:

[0147]

[0148] In at least one embodiment, the formula for calculating the SINR is expressed as:

[0149]

[0150] In at least one embodiment, c refers to a specific cell within the wireless network. In at least one embodiment, represents the uplink channel from the u*-th user equipment (UE) in the c*-th cell of the c*-th gNB. In at least one embodiment, represents the u-th UE in the c-th cell (w / peak power p max ). In at least one embodiment, represents the hybrid beamforming defined as .

[0151] In at least one embodiment, the processor continues process 600 by performing operation 608 to output a reward value. In at least one embodiment, the reward value is received or otherwise obtained by the actor module for evaluating its actions. In at least one embodiment, the reward value quantifies how actions such as updating the values of the precoding matrix increase or decrease the signal characteristics of one or more signals, such as SNR or SINR. In at least one embodiment, the signal characteristics refer to the characteristics of a part of the wireless network regarded as a whole, such as the total SINR or total rate of that part. In at least one embodiment, the goal of the actor module is to maximize or satisfy the reward value in the case of the target SNR, which is expressed as: R u =∏ u SNR u . In at least one embodiment, the goal of the actor module is to maximize or satisfy the reward value in the case of the target SINR, which is expressed as In at least one embodiment, another reward value based on satisfying the target SINR is expressed as where w uDenotes the weight, which will be further described in this article. In at least one embodiment, the formula for maximizing the total SINR at which two or more signals are co-presented is expressed as: ∑ c,u log 2 (1 + SINR c,u ). In at least one embodiment, the goal of the actor module is to maximize or satisfy the reward value under the target total rate, which is expressed as R t = ∑ (c,u) log 2 log 2 (1 + SINR c,u ) - ∑ (c,u) p c,u .

[0152] In at least one embodiment, the reward value is designed to conceptually motivate the reinforcement learning agent to achieve the goal with the highest reward at least. In at least one embodiment, if the goal (or target throughput) of SNR >= SNR is currently achieved, the reward value is += 100. In at least one embodiment, when creating the reward value, SINR can be used instead of SNR. In at least one embodiment, if the achieved SNR increases, the reward value is += 1. In at least one embodiment, the reward value is equal to the sum of the transmit powers in dB. In at least one embodiment, depending on the quality of service (QoS) metric or the performance of the UE, a weighted sum with w u is used. In at least one embodiment, a user u with lower performance may not be able to afford high transmit power, so a higher w u can be inserted into the reward formula to more severely penalize the actions of the actor. In at least one embodiment, the neural network is trained to minimize the transmit power of the UE, so a negative penalty is applied to the reward formula proportional to the transmit power inferred by the neural network. Therefore, the agent attempts to maximize the reward by partially minimizing the transmit power.

[0153] In at least one embodiment, maximizing the total rate is expressed as maximizing the sum of log 2 (1 + SINR c,u ). In at least one embodiment, to minimize the attention to a single UE with the highest channel gain, a fairness condition is added, such that maximizing the total rate is expressed as maximizing the sum of log 2 log 2 (1 + SINR c,u ).

[0154] In at least one embodiment, the processor continues process 600 by performing operation 610 to determine whether the signal characteristics have been maximized or satisfied. In at least one embodiment, the reward value output by operation 608 is used to determine whether the signal characteristics have been maximized or satisfied. In at least one embodiment, the signal characteristics are compared with target signal characteristics set by a user or software to determine whether the characteristics have been maximized or satisfied.

[0155] In at least one embodiment, the processor continues process 600 by performing operation 614 to determine whether there are additional input signals and their signal parameters available for training the neural network described herein. In at least one embodiment, if additional signals are available as input data for training the neural network, process 600 repeats starting at operation 602. In at least one embodiment, if no additional signals are available as input data for training the neural network, process 600 ends.

[0156] Figure 7 A block diagram 700 is shown in accordance with at least one embodiment, which depicts a process flow of aspects of a reinforcement learning neural network training system for training a neural network to modify analog and digital parameters of a signal using hybrid beamforming techniques to achieve signal characteristics above a threshold. In at least one embodiment, one or more aspects of one or more embodiments described in Figure 7 are combined with one or more aspects of one or more embodiments described herein, including at least in combination with Figures 1 - 6 and Figures 8A - 8B the aspects described. In at least one embodiment, one or more processors that perform one or more operations used in block diagram 700 are any one processor or combination of processors described herein, including in combination with Figure 8B one or more processors 822 described in Figure 19A the graphics processor 1910 described in Figure 34 and the parallel processing unit (“PPU”) 3400 described in t as shown in Figure 7 In at least one embodiment, one or more processors 822 perform operations to update the actor to maximize r Figure 7 as depicted in Figure 3 or Figure 4 the operations used by the critic described in Figure 5 or the operations used by the target critic described in

[0157] In at least one embodiment, the state s as shown in block diagram 700 tis information used by a reinforcement learning neural network training agent. In at least one embodiment, the state s t includes the previous action a t-1 , and the SNR implemented for each UE respectively. In at least one embodiment, the action a t modifies the design factors under the control of the agent. In at least one embodiment, the action a t uses the concatenation of vectors W BB and W RF . In at least one embodiment, the action a t is expressed as a signal vector. In at least one embodiment, the action a t is the output of a neural network such as Figure 2 the neural network 214. In at least one embodiment, and are for a non-beam grid (GoB) system for hybrid beamforming, where in at least one embodiment, each θ is represented by a length-N one-hot encoding. In at least one embodiment, Figure 7 the environment not shown in t fragments the action a BB into W RF and W, which means the environment divides the parameters in the action into the parameters used in digital beamforming and the parameters used in analog beamforming. In at least one embodiment, the soft update of the neural network parameters is a more gradual combination of the current parameters and the previously used parameters in order to achieve greater stability of the neural network during training.

[0158] Figure 8A shows a block diagram of a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, any one processor or combination of processors executes the API 810, including Figure 8B one or more processors 822 of Figure 19A described in conjunction with Figure 34 the graphics processor 1910 described in conjunction with Figures 1 - 5 and the parallel processing unit (“PPU”) 3400 described in conjunction with Figure 1An actor module, such as actor module 106, performs an operation that trains a neural network to output hybrid beamforming signal parameters for forming and transmitting a directional beam, as further described herein. In at least one embodiment, API 810 causes a neural network trained according to one or more techniques described herein (including at least the techniques described in conjunction with Figures 1 - 7 the techniques described) to receive an input: the hybrid beamforming signal parameters of the transmitted signal, and output other hybrid beamforming signal parameters so as to transmit a directional beam having signal characteristics that meet a target value, as further described herein.

[0159] In at least one embodiment, software program 802 is a software module. In at least one embodiment, software program 802 includes one or more software modules. In at least one embodiment, one or more APIs 810 are software instruction sets that, if executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, one or more APIs 810 are distributed or otherwise provided as part of one or more libraries 806, runtimes 804, drivers 804, and / or any other grouping of software and / or executable code further described herein. In at least one embodiment, one or more APIs 810 perform one or more computational operations in response to a call by software program 802. In at least one embodiment, software program 802 is a collection of software code, commands, instructions, or other text sequences for instructing a computing device to perform one or more computational operations and / or call one or more other instruction sets (such as API 810 or API function 812) to be executed. In at least one embodiment, the functionality provided by one or more APIs 810 includes software functions 812, such as software functions that can be used to accelerate one or more portions of software program 802 using one or more parallel processing units (PPUs) (such as a graphics processing unit GPU). In at least one embodiment, the software program is a compiler.

[0160] In at least one embodiment, API 810 is a hardware interface to one or more circuits for performing one or more computational operations. In at least one embodiment, one or more of the software APIs 810 described herein are implemented as one or more circuits for performing one or more of the techniques described herein. In at least one embodiment, one or more software programs 802 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform one or more of the techniques further described herein.

[0161] In at least one embodiment, a software program 802, such as a user-implemented software program, utilizes one or more application programming interfaces (APIs) 810 to perform various computational operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computational operation performed by a parallel processing unit (PPU) (e.g., a graphics processing unit (GPU)), as further described herein. In at least one embodiment, one or more APIs 810 provide a set of callable functions 812, referred to herein as APIs, API functions, and / or functions, which perform one or more computational operations, such as computational operations related to parallel computing. For example, in one embodiment, one or more APIs 810 provide functions 812 to enable a scheduler to schedule instructions for execution by these processors based on the latency of the interconnect coupled to the processors.

[0162] In at least one embodiment, one or more software programs 802 interact with or otherwise communicate with one or more APIs 810 to perform one or more computational operations using one or more PPUs (such as GPUs). In at least one embodiment, one or more computational operations using one or more PPUs include at least one or more sets of computational operations that will be accelerated by being at least partially performed by the one or more PPUs. In at least one embodiment, one or more software programs 802 interact with one or more APIs 810 to facilitate parallel computing using a remote or local interface.

[0163] In at least one embodiment, an interface is software instructions that, when executed, provide access to one or more functions 812 provided by one or more APIs 810. In at least one embodiment, a software program 802 uses a local interface when a software developer compiles one or more software programs 802 in conjunction with one or more libraries 806 that include one or more APIs 810 or otherwise provide access to one or more APIs 810. In at least one embodiment, one or more software programs 802 are statically compiled in conjunction with a pre-compiled library 806 or uncompiled source code that includes instructions to execute one or more APIs 810. In at least one embodiment, one or more software programs 802 are dynamically compiled, and the one or more software programs utilize a linker to link to one or more pre-compiled libraries 806 that include one or more APIs 810.

[0164] In at least one embodiment, when a software developer executes a software program that utilizes or otherwise communicates with a library 806 including one or more APIs 810 over a network or other remote communication medium, the software program 802 uses a remote interface. In at least one embodiment, one or more libraries 806 including one or more APIs 810 will be executed by a remote computing service (such as a computing resource service provider). In another embodiment, one or more libraries 806 including one or more APIs 810 will be executed by any other computing host that provides the one or more APIs 810 to one or more software programs 802.

[0165] In at least one embodiment, a processor that executes or uses one or more software programs 802 invokes, uses, executes, or otherwise implements one or more APIs 810 to allocate or otherwise manage memory to be used by the software program 802. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 to allocate and otherwise manage memory to be used by one or more portions of the software program 802 to accelerate using one or more PPUs (such as a GPU or any other accelerator or processor further described herein). These software programs 802 may be executed by one or more processors at least in part based on functions 812 provided by one or more APIs 810 in one embodiment using the latency of an interconnect coupled to the one or more processors.

[0166] In at least one embodiment, API 810 is an API that facilitates parallel computing. In at least one embodiment, API 810 is any other API further described herein. In at least one embodiment, API 810 is provided by driver and / or runtime 804. In at least one embodiment, API 810 is provided by the CUDA user mode driver. In at least one embodiment, API 810 is provided by the CUDA runtime. In at least one embodiment, driver 804 is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 812 of API 810 during the loading and execution of one or more portions of software program 802. In at least one embodiment, runtime 804 is data values and software instructions that, if executed, perform or otherwise facilitate the operation of one or more functions 812 of API 810 during the execution of software program 802. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 implemented or otherwise provided by driver and / or runtime 804 to perform combined arithmetic operations during execution by one or more PPU such as GPUs.

[0167] In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by driver and / or runtime 804 to perform combined arithmetic operations on one or more PPU such as GPUs. In at least one embodiment, as described above, one or more APIs 810 provide combined arithmetic operations through driver and / or runtime 804. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by driver and / or runtime 804 to allocate or otherwise reserve one or more blocks of memory 814 of one or more PPU (e.g., GPUs). In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by driver and / or runtime 804 to allocate or otherwise reserve memory blocks. In at least one embodiment, one or more APIs 810 are used to perform combined mathematical functions as described herein.

[0168] In at least one embodiment, to improve the usability of software program 802 and / or the optimization of one or more portions of the software program 802 accelerated by one or more PPUs (such as GPUs), one or more APIs 810 provide one or more API functions 812 to execute a scheduling system used by or available to one or more of the computing devices described herein. In at least one embodiment, a processor executes one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, the processor uses an API to cause a scheduler to select a thread selection mechanism and / or otherwise perform the operations described herein. In at least one embodiment, an API calls a scheduler to cause resource allocation. In at least one embodiment, the processor uses an exemplary API to schedule one or more instructions for execution by one or more processors at least partially based on the latency of one or more interconnects coupled to one or more processors.

[0169] In at least one embodiment, memory 814 is the system memory 1904 of computing system 1900. In at least one embodiment, memory 814 stores data parameters, such as baseband and RF weights of one or more signals being transmitted. In at least one embodiment, memory 814 stores data parameters used by various modules of the reinforcement learning system, such modules as Figure 1 the actor module 106, Figure 2 the action module 230, for storing Figure 3 the signal parameters 319 of the actor module 310, Figure 4 the next state module, and Figure 5 the target critic module 570. In at least one embodiment, memory 814 stores SINR values calculated using operation 608. In at least one embodiment, as Figure 7 shown, memory 814 stores the results of attempts to minimize by updating the critic. In at least one embodiment, memory 814 stores functions, such as the reward function and value function described herein. In at least one embodiment, memory 814 stores a neural network by at least partially storing neural network parameters such as neural network weights, biases, and activation values.

[0170] Figure 8B FIG. 800 shows a block diagram according to at least one embodiment, the block diagram 800 including means for performing at least in combination with the present text Figures 1 - 7One or more processors 822 for any one or more operations of the described one or more modules. In at least one embodiment, the one or more processors 822 are used to perform the training of a neural network using reinforcement learning, as further described herein. In at least one embodiment, one or more aspects of one or more embodiments described in conjunction with Figure 8B are combined with one or more aspects of one or more embodiments described herein, including at least in combination with Figures 1 - 7 the aspects described. In at least one embodiment, the one or more processors 822 are any one processor or combination of processors described herein, including in combination with Figure 19A the graphics processor 1910 described, and in combination with Figure 34 the parallel processing unit (“PPU”) 3400 described. In at least one embodiment, the one or more processors 822 are the processors 1902 of the computing system 1900.

[0171] In at least one embodiment, one or more of the modules described herein (including at least in combination with Figures 1 - 5 the modules described) are installed on the one or more processors 822. In at least one embodiment, an exemplary module on the one or more processors 822 is the actor module 824. In at least one embodiment, the actor module 824 includes Figure 1 the actor module 106 of Figure 2 the actor 210 of Figure 3 the actor 310 of Figure 4 the 410 of Figure 5 the actor 510 of or any one or more aspects of some combination thereof. In at least one embodiment, the actor module 824 includes Figure 8A one or more APIs 810 of

[0172] for performing one or more operations related to the actor of the reinforcement learning system, such as jointly inferring signal parameters to be used in a hybrid beamforming system. Figure 1 the environment module 108 of Figure 2 the environment 250 of Figure 3 the environment 350 of Figure 4 the environment 450 of Figure 5 the environment 550 of or any one or more aspects of some combination thereof. In at least one embodiment, the environment module 826 includes Figure 8AOne or more APIs 810 for performing one or more operations related to an environment module in a reinforcement learning system, such as calculating a reward indicating the degree to which an action generated by an actor module improves the signal characteristics of the transmitted signal.

[0173] Logic

[0174] Figure 9A Illustrates logic 915 according to at least one embodiment, such as described elsewhere herein, which can be used in one or more devices to perform operations such as those discussed herein. In at least one embodiment, logic 915 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 915 is inference and / or training logic. Details regarding logic 915 are provided below in conjunction with Figure 9A and / or Figure 9B In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic for providing the functions or operations described herein, where the logic can be embodied jointly or separately as circuitry forming part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., a CPU, a GPU)).

[0175] In at least one embodiment, logic 915 can include, but is not limited to, code and / or data storage 901 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 915 can include or be coupled to code and / or data storage 901 for storing graph code or other software to control timing and / or sequencing, where weights and / or other parameter information are loaded to configure the logic, which includes integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 901 stores the weight parameters and / or input / output data of each layer of the neural network used or trained during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 901 can be included within other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory.

[0176] In at least one embodiment, any portion of the code and / or data storage 901 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 901 can be a cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 901 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, can depend on the on-chip versus off-chip available storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0177] In at least one embodiment, the logic 915 can include, but is not limited to, the code and / or data storage 905 for storing the backward and / or output weights and / or input / output data corresponding to the neurons or layers of the neural network that are trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 905 stores the weight parameters and / or input / output data of each layer of the neural network that is trained or used in combination with one or more embodiments during the backpropagation of the input / output data and / or weight parameters. In at least one embodiment, the logic 915 can include or be coupled to the code and / or data storage 905 for storing the graph code or other software to control the timing and / or sequence, where the weights and / or other parameter information are loaded to configure the logic that includes integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)).

[0178] In at least one embodiment, code (such as a graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any portion of the code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 905 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 905 is internal or external to the processor, e.g., including DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0179] In at least one embodiment, the code and / or data storage 901 and the code and / or data storage 905 may be separate storage structures. In at least one embodiment, the code and / or data storage 901 and the code and / or data storage 905 may be the same storage structure. In at least one embodiment, the code and / or data storage 901 and the code and / or data storage 905 may be partially combined and partially separated. In at least one embodiment, any portion of the code and / or data storage 901 and the code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0180] In at least one embodiment, logic 915 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910 (including integer and / or floating point units) for performing logical and / or mathematical operations at least in part based on and / or as directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in activation store 920, which are a function of input / output and / or weight parameter data stored in code and / or data store 901 and / or code and / or data store 905. In at least one embodiment, the activations stored in activation store 920 are generated according to linear algebra and / or matrix-based mathematics performed by ALU 910 in response to executing instructions or other code, where the weight values stored in code and / or data store 905 and / or code and / or data store 901 are used as operands along with other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data store 905 or code and / or data store 901 or other on-chip or off-chip storage.

[0181] In at least one embodiment, one or more ALUs 910 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 910 may be external to the processors or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, ALU 910 may be included within the execution units of a processor or otherwise included in an ALU bank accessible by the execution units of a processor, which execution units may be within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data store 901, code and / or data store 905, and activation store 920 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation store 920 may be included with other on-chip or off-chip data storage, including the L1, L2, or L3 cache of a processor or system memory. Additionally, inference and / or training code may be stored along with other code accessible by the processor or other hardware logic or circuits and may be extracted and / or processed using the fetch, decode, schedule, execute, retire, and / or other logic circuits of the processor.

[0182] In at least one embodiment, the activation store 920 can be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the activation store 920 can be wholly or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether the activation store 920 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, can depend on the on-chip versus off-chip available storage, the latency requirements for performing training and / or inference functions, the batch size of the data used in inferring and / or training a neural network, or some combination of these factors.

[0183] In at least one embodiment, Figure 9A the logic 915 shown in can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 9A the logic 915 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware (e.g., field programmable gate array (“FPGA”)).

[0184] Figure 9B Logic 915 is shown in accordance with at least one embodiment. In at least one embodiment, the logic 915 is inference and / or training logic. In at least one embodiment, the logic 915 can include, but is not limited to, hardware logic where computing resources are dedicated or otherwise exclusively used with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 9B the logic 915 shown in can be used in conjunction with an application specific integrated circuit (ASIC), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 9BThe logic 915 shown in the figure can be used in combination with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (such as a field programmable gate array (FPGA)). In at least one embodiment, the logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which can be used to store code (such as graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 9B In at least one embodiment shown in the figure, each of the code and / or data storage 901 and the code and / or data storage 905 is respectively associated with dedicated computing resources (such as computing hardware 902 and computing hardware 906). In at least one embodiment, each of the computing hardware 902 and the computing hardware 906 includes one or more ALUs that respectively perform mathematical functions (such as linear algebra functions) only on the information stored in the code and / or data storage 901 and the code and / or data storage 905, and the results are stored in the activation storage 920.

[0185] In at least one embodiment, each of the code and / or data storage 901 and 905 and the corresponding computing hardware 902 and 906 respectively corresponds to different layers of a neural network, such that the activation obtained from one storage / computation pair 901 / 902 of the code and / or data storage 901 and the computing hardware 902 is provided as the input to the next storage / computation pair 905 / 906 of the code and / or data storage 905 and the computing hardware 906, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 901 / 902 and 905 / 906 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the logic 915 after or in parallel with the storage / computation pairs 901 / 902 and 905 / 906.

[0186] Neural network training and deployment

[0187] Figure 10Illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, a training dataset 1002 is used to train an untrained neural network 1006. In at least one embodiment, the training framework 1004 is the PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008. In at least one embodiment, the weights can be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training can be performed in a supervised, partially supervised, or unsupervised manner.

[0188] In at least one embodiment, supervised learning is used to train the untrained neural network 1006, where the training dataset 1002 includes inputs paired with desired outputs for the inputs, or where the training dataset 1002 includes inputs with known outputs and the outputs of the neural network 1006 are manually graded. In at least one embodiment, the untrained neural network 1006 is trained in a supervised manner, processes inputs from the training dataset 1002, and compares the resulting outputs with a set of desired or wanted outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 1006. In at least one embodiment, the training framework 1004 adjusts the weights that control the untrained neural network 1006. In at least one embodiment, the training framework 1004 includes tools for monitoring the degree to which the untrained neural network 1006 converges to a model (such as the trained neural network 1008) suitable for generating correct answers (such as results 1014) based on input data (such as a new dataset 1012). In at least one embodiment, the training framework 1004 repeatedly trains the untrained neural network 1006 while adjusting the weights to refine the output of the untrained neural network 1006 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 reaches a desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to implement any number of machine learning operations.

[0189] In at least one embodiment, unsupervised learning is used to train an untrained neural network 1006, where the untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1002 will include input data without any associated output data or "groundtruth" data. In at least one embodiment, the untrained neural network 1006 can learn groupings within the training dataset 1002 and can determine how each input relates to the untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 1008, which can perform operations useful for reducing the dimensionality of a new dataset 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the new dataset 1012 that deviate from the normal pattern of the new dataset 1012.

[0190] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1002. In at least one embodiment, the training framework 1004 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1008 to adapt to a new dataset 1012 without forgetting the knowledge injected into the trained neural network 1008 during initial training.

[0191] In at least one embodiment, the training framework 1004 is a framework that is processed in combination with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit developed by Intel Corporation of Santa Clara, California, for example. In at least one embodiment, OpenVINO includes logic 915 or uses logic 915 to perform the operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0192] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (especially neural network applications) for various tasks and operations such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof.

[0193] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., of a person and / or an object), monocular depth estimation, inpainting, style transfer, action recognition, coloring, and / or variants thereof.

[0194] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as the Model Optimizer. In at least one embodiment, the Model Optimizer is a command-line tool that facilitates the conversion between the training and deployment of a neural network model. In at least one embodiment, the Model Optimizer optimizes a neural network model for execution on various devices and / or processing units such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the Model Optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the Model Optimizer reduces the number of layers of the model. In at least one embodiment, the Model Optimizer removes layers of the model used for training. In at least one embodiment, the Model Optimizer performs various neural network operations such as modifying the input of the model (e.g., resizing the input of the model), modifying the size of the input of the model (e.g., modifying the batch size of the model), modifying the model structure (e.g., modifying the layers of the model), normalization, standardization, quantization (e.g., converting the weights of the model from a first representation such as floating point to a second representation such as integer), and / or variants thereof.

[0195] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as the Inference Engine. In at least one embodiment, the Inference Engine is a C++ library or a library in any suitable programming language. In at least one embodiment, the Inference Engine is used to infer input data. In at least one embodiment, the Inference Engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the Inference Engine implements one or more API functions to process the intermediate representation, set the input and / or output format, and / or execute the model on one or more devices.

[0196] In at least one embodiment, OpenVINO provides various capabilities for the heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., execute a first set of layers on a first device (e.g., GPU) and a second set of layers on a second device (e.g., CPU)).

[0197] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0198] Data center

[0199] Figure 11 An example data center 1100 in which at least one embodiment can be used is shown. In at least one embodiment, data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0200] In at least one embodiment, as Figure 11As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources ("node C.R.") 1116(1)-1116(N), where "N" represents a positive integer (which may be a different integer "N" from the integers used in other figures). In at least one embodiment, the node C.R. 1116(1)-1116(N) may include, but is not limited to, any number of central processing units ("CPU") or other processors (including accelerators, field programmable gate arrays (FPGA), graphics processors, etc.), memory storage devices 1118(1)-1118(N) (such as dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VM"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R. 1116(1)-1116(N) may be servers having one or more of the above computing resources.

[0201] In at least one embodiment, the grouped computing resources 1114 may include separate groupings of node C.R. housed within one or more racks (not shown), or many racks housed within data centers (also not shown) in various geographical locations. In at least one embodiment, the separate groupings of node C.R. within the grouped computing resources 1114 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0202] In at least one embodiment, the resource coordinator 1112 may configure or otherwise control one or more of the node C.R. 1116(1)-1116(N) and / or the grouped computing resources 1114. In at least one embodiment, the resource coordinator 1112 may include a software design infrastructure ("SDI") management entity for the data center 1100. In at least one embodiment, the resource coordinator 1112 may include hardware, software, or some combination thereof.

[0203] In at least one embodiment, as Figure 11As shown, the framework layer 1120 includes a job scheduler 1122, a configuration manager 1124, a resource manager 1126, and a distributed file system 1128. In at least one embodiment, the framework layer 1120 may include a framework that supports software 1132 of the software layer 1130 and / or one or more applications 1142 of the application layer 1140. In at least one embodiment, the software 1132 or the application 1142 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1120 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark that can utilize the distributed file system 1128 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1122 may include a Spark driver for facilitating the scheduling of workloads supported by the various layers of the data center 1100. In at least one embodiment, the configuration manager 1124 may be capable of configuring different layers, such as the software layer 1130 and the framework layer 1120 including Spark and the distributed file system 1128 for supporting large-scale data processing. In at least one embodiment, the resource manager 1126 may be capable of managing clustered or grouped computing resources mapped to or allocated for supporting the distributed file system 1128 and the job scheduler 1122. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1114 at the data center infrastructure layer 1110. In at least one embodiment, the resource manager 1126 may coordinate with the resource coordinator 1112 to manage these mapped or allocated computing resources.

[0204] In at least one embodiment, the software 1132 included in the software layer 1130 may include software used by at least respective parts of the nodes C.R. 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0205] In at least one embodiment, one or more applications 1142 included in the application layer 1140 may include one or more types of applications used by at least respective portions of nodes C.R. 1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (such as PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0206] In at least one embodiment, any one of the configuration manager 1124, the resource manager 1126, and the resource coordinator 1112 may implement any number and type of self-modifying actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions may relieve the data center operator of the data center 1100 from making potentially bad configuration decisions and may avoid underutilization and / or poorly performing portions of the data center.

[0207] In at least one embodiment, the data center 1100 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture by using the software and computing resources described above with respect to the data center 1100. In at least one embodiment, by using the weight parameters calculated by one or more training techniques described herein, the resources described above with respect to the data center 1100 may be used to infer or predict information using the trained machine learning model corresponding to one or more neural networks.

[0208] In at least one embodiment, the data center may use a CPU, an application specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to perform training and / or inference using the above resources. In addition, one or more of the above software and / or hardware resources may be configured as a service for allowing a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0209] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 9A and / or Figure 9BProvide details regarding logic 915. In at least one embodiment, logic 915 may be used in data center 1100 for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0210] In at least one embodiment, at least one component shown or described is used to implement the techniques and / or functions associated with Figures 9A - 11 described. In at least one embodiment, logic 915 performs one or more aspects of scaling values according to a differential order and as further described herein (including at least in conjunction with Figures 1 - 6 ) Figure 1

[0211] Autonomous vehicle

[0212] Figure 12A FIG. shows an example of an autonomous vehicle 1200 according to at least one embodiment. In at least one embodiment, autonomous vehicle 1200 (alternatively referred to herein as "vehicle 1200") may be, but is not limited to, a passenger vehicle such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1200 may be a semi-trailer truck for hauling cargo. In at least one embodiment, vehicle 1200 may be an airplane, robotic vehicle, or other type of vehicle.

[0213] Autonomous vehicles may be described according to the levels of automation defined by the National Highway Traffic Safety Administration ("NHTSA") under the U.S. Department of Transportation and the Society of Automotive Engineers ("SAE") in "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016 - 201806 released on June 15, 2018, Standard No. J3016 - 201609 released on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, vehicle 1200 may be capable of having functionality according to one or more of levels 1 through 5 of the autonomous driving levels. For example, in at least one embodiment, vehicle 1200 may be capable of having conditional automation (level 3), highly automated (level 4), and / or fully automated (level 5), depending on the embodiment.

[0214] In at least one embodiment, vehicle 1200 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle.

[0215] In at least one embodiment, vehicle 1200 may include, but is not limited to, a propulsion system 1250, such as an internal combustion engine, a hybrid arrangement, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1250 may be connected to the driveline of vehicle 1200, which may include, but is not limited to, a transmission for enabling propulsion of vehicle 1200. In at least one embodiment, propulsion system 1250 may be controlled in response to receiving a signal from a throttle / accelerator 1252.

[0216] In at least one embodiment, when propulsion system 1250 is operating (e.g., when vehicle 1200 is in motion), a steering system 1254 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1200 (e.g., along a desired path or route). In at least one embodiment, steering system 1254 may receive a signal from a steering actuator 1256. In at least one embodiment, for fully automated (level 5) functionality, the steering wheel may be optional. In at least one embodiment, a brake sensor system 1246 may be used to operate vehicle brakes in response to receiving a signal from a brake actuator 1248 and / or a brake sensor.

[0217] In at least one embodiment, one or more controllers 1236, which may include, but is not limited to, one or more system-on-chips (“SoC”) ( Figure 12A(not shown) and / or a graphics processing unit (“GPU”), providing signals (e.g., representing commands) to one or more components and / or systems of the vehicle 1200. For example, in at least one embodiment, one or more controllers 1236 may send signals to operate vehicle brakes via a brake actuator 1248, operate a steering system 1254 via one or more steering actuators 1256, and operate a propulsion system 1250 via one or more throttles / accelerators 1252. In at least one embodiment, one or more controllers 1236 may include one or more on-vehicle (e.g., integrated) computing devices that process sensor signals and output operation commands (e.g., signals representing commands) to achieve autonomous driving and / or assist a human driver in driving the vehicle 1200. In at least one embodiment, one or more controllers 1236 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may process two or more of the above functions, and two or more controllers may process a single function and / or any combination thereof.

[0218] In at least one embodiment, one or more controllers 1236 provide signals for controlling one or more components and / or systems of the vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example but not limited to, the following sensors: one or more Global Navigation Satellite System (“GNSS”) sensors 1258 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1260, one or more ultrasonic sensors 1262, one or more LIDAR sensors 1264, one or more Inertial Measurement Unit (IMU) sensors 1266 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1296, one or more stereo cameras 1268, one or more wide-angle cameras 1270 (e.g., fish-eye cameras), one or more infrared cameras 1272, one or more surround cameras 1274 (e.g., 360-degree cameras), remote cameras ( Figure 12A (not shown), mid-range cameras ( Figure 12A(not shown), one or more speed sensors 1244 (e.g., for measuring the speed of vehicle 1200), one or more vibration sensors 1242, one or more steering sensors 1240, one or more braking sensors (e.g., as part of a braking sensor system 1246), and / or other sensor types.

[0219] In at least one embodiment, one or more controllers 1236 may receive inputs (e.g., represented by input data) from the instrument panel 1232 of vehicle 1200 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1234, a sound annunciator, a speaker, and / or via other components of vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., high-definition map ( Figure 12A (not shown), location data (e.g., the location of vehicle 1200, e.g., on a map), direction, the locations of other vehicles (e.g., occupied grids), information about objects, and the status of objects sensed by one or more controllers 1236, etc. For example, in at least one embodiment, the HMI display 1234 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic signal changes, etc.) and / or information about driving maneuvers that the vehicle has made, is making, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0220] In at least one embodiment, vehicle 1200 further includes a network interface 1224, which may communicate via one or more networks using one or more wireless antennas 1226 and / or one or more modems. For example, in at least one embodiment, the network interface 1224 may be capable of communicating via Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1226 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (“LPWAN”) (such as LoRaWAN, SigFox, etc. protocols).

[0221] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 9A and / or Figure 9BDetails regarding logic 915 are provided. In at least one embodiment, logic 915 can be used in vehicle 1200 for performing inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0222] In at least one embodiment, at least one component shown or described regarding Figure 12A is used to implement the techniques and / or functions described in connection with Figures 1 - 8B described. In at least one embodiment, one or more wireless antennas 1226 are used to transmit and / or receive one or more wireless signals using hybrid beamforming parameters and / or transmit power for neural network inference described in connection with Figure 1 and as described elsewhere herein.

[0223] Figure 12B An example of the camera positions and fields of view of autonomous vehicle 1200 according to at least one embodiment is shown. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on vehicle 1200. Figure 12A

[0224] In at least one embodiment, the camera types for the cameras can include, but are not limited to, digital cameras that can be adapted to be used with components and / or systems of vehicle 1200. In at least one embodiment, one or more cameras can operate at an automotive safety integrity level (“ASIL”) B and / or other ASIL. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or a combination thereof. In at least one embodiment, the color filter array can include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer (RGGB) sensor color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, transparent pixel cameras, such as cameras having RCCC, RCCB, and / or RBGC color filter arrays, can be used to attempt to improve photosensitivity.

[0225] ​In at least one embodiment, one or more cameras can be used to perform Advanced Driver Assistance System (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-functional monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and smart headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can record and provide image data (e.g., video) simultaneously.

[0226] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D”) printed) assembly, to remove stray light and reflected light from within the vehicle 1200 (e.g., reflected light from the dashboard reflected in the windshield mirror), which may interfere with the camera's image data capture ability. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed customized such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side cameras, one or more cameras can also be integrated within the four pillars at each corner of the cabin.

[0227] In at least one embodiment, a camera having a field of view of portions of the environment in front of the vehicle 1200 (e.g., a forward camera) can be used for surround view to help identify the forward path and obstacles, and to assist in providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path with the help of one or more controllers 1236 and / or a control SoC. In at least one embodiment, the forward camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (such as traffic sign recognition).

[0228] In at least one embodiment, a variety of cameras can be used in a forward configuration, including for example a monocular camera platform including a CMOS (“Complementary Metal Oxide Semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1270 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 12BOnly one wide - angle camera 1270 is shown, but in other embodiments, any number (including zero) of wide - angle cameras may be present on the vehicle 1200. In at least one embodiment, any number of long - range cameras 1298 (e.g., tele - vision stereo camera pairs) can be used for depth - based object detection, especially for objects for which a neural network has not been trained. In at least one embodiment, one or more long - range cameras 1298 can also be used for object detection and classification and basic object tracking.

[0229] In at least one embodiment, any number of stereo cameras 1268 can also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1268 can include an integrated control unit that includes a scalable processing unit that can provide programmable logic (“FPGA”) and a multi - core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit can be used to generate a 3D map of the environment of the vehicle 1200, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1268 can include, but are not limited to, compact stereo vision sensors, which can include, but are not limited to, two camera lenses (one on the left and one on the right) and an image - processing chip, which can measure the distance from the vehicle 1200 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1268 can be used in addition to or in place of those described herein.

[0230] In at least one embodiment, a camera with a field of view that includes portions of the environment on the sides of the vehicle 1200 (e.g., a side - view camera) can be used for surround - view, which provides information for creating and updating an occupancy grid, as well as generating side - impact collision warnings. For example, in at least one embodiment, surround cameras 1274 (e.g., four surround cameras as Figure 12B shown) can be positioned on the vehicle 1200. In at least one embodiment, one or more surround cameras 1274 can include, but are not limited to, any number and combination of wide - angle cameras, one or more fisheye cameras, one or more 360 - degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be located at the front, rear, and sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 can use three surround cameras 1274 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward camera) as the fourth surround - view camera.

[0231] In at least one embodiment, a camera (e.g., a rear-view camera) having a view of portions of the environment behind vehicle 1200 can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward cameras (e.g., long-range camera 1298 and / or one or more mid-range cameras 1276, one or more stereo cameras 1268, one or more infrared cameras 1272, etc.), as described herein.

[0232] In at least one embodiment, at least one component shown or described with respect to Figures 12A - 12B is used to implement the techniques and / or functions associated with Figures 1 - 8B described. In at least one embodiment, one or more wireless antennas 1226 are used to transmit and / or receive signals using hybrid beamforming parameters and / or transmit power for neural network inference described with respect to Figure 1 and as described elsewhere herein.

[0233] Figure 12C is a block diagram showing an example system architecture of an autonomous vehicle 1200 according to at least one embodiment of Figure 12A . In at least one embodiment, each of the components, features, and systems of vehicle 1200 in Figure 12C is shown as being connected via bus 1202. In at least one embodiment, bus 1202 can include, but is not limited to, a CAN data interface (alternatively referred to herein as the "CAN bus"). In at least one embodiment, CAN can be a network within vehicle 1200 for assisting in controlling various features and functions of vehicle 1200, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1202 can be configured to have dozens or even hundreds of nodes, each having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1202 can be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle state indicators. In at least one embodiment, bus 1202 can be an ASIL B-compliant CAN bus.

[0234] In at least one embodiment, in addition to or instead of CAN, FlexRay and / or Ethernet protocols may also be used. In at least one embodiment, there may be any number of buses forming bus 1202, which may include but are not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, the first bus may be used for collision avoidance functions, and the second bus may be used for actuation control. In at least one embodiment, each bus in bus 1202 may communicate with any component of vehicle 1200, and two or more buses in bus 1202 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chips (“SoC”) 1204 (e.g., SoC 1204(A) and SoC 1204(B)), each of one or more controllers 1236, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of vehicle 1200) and may be connected to a common bus, such as a CAN bus.

[0235] In at least one embodiment, vehicle 1200 may include one or more controllers 1236, such as those described herein with respect to Figure 12A In at least one embodiment, controller 1236 may be used for a variety of functions. In at least one embodiment, controller 1236 may be coupled to any one of various other components and systems of vehicle 1200 and may be used to control vehicle 1200, the artificial intelligence of vehicle 1200, the infotainment of vehicle 1200, and / or other functions.

[0236] In at least one embodiment, vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of the SoCs 1204 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1206, a graphics processing unit (“one or more GPUs”) 1208, one or more processors 1210, one or more caches 1212, one or more accelerators 1214, one or more data stores 1216, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1204 may be used to control vehicle 1200 in a variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 1204 may be combined with a high-definition (“HD”) map 1222 in a system (e.g., the system of vehicle 1200), and the HD map 1222 may obtain map refreshes and / or updates from one or more servers ( Figure 12C not shown in the figure) via network interface 1224.

[0237] In at least one embodiment, one or more CPUs 1206 may include a CPU cluster or CPU complex (alternatively referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1206 may include multiple cores and / or secondary (“L2”) caches. For example, in at least one embodiment, one or more CPUs 1206 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, one or more CPUs 1206 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2-megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, which allows any combination of the clusters of one or more CPUs 1206 to be active at any given time.

[0238] In at least one embodiment, one or more CPUs 1206 may implement power management functions, which may include, but are not limited to, one or more of the following features: automatically clock-gating individual hardware blocks when idle to save dynamic power; clock-gating each core clock when the core is not actively executing instructions due to execution of wait-for-interrupt ("WFI") / wait-for-event ("WFE") instructions; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, one or more CPUs 1206 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power states to enter for cores, clusters, and CCPLEX. In at least one embodiment, the processing cores may support a simplified power state entry sequence in software, where the work is offloaded to the microcode.

[0239] In at least one embodiment, one or more GPUs 1208 may include an integrated GPU (alternatively referred to herein as "iGPU"). In at least one embodiment, one or more GPUs 1208 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1208 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1208 may include one or more streaming microprocessors, where each streaming microprocessor may include a level-1 ("L1") cache (e.g., an L1 cache having a storage capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having a storage capacity of 512 KB). In at least one embodiment, one or more GPUs 1208 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1208 may use one or more compute application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1208 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0240] In at least one embodiment, one or more GPUs 1208 may be power optimized to achieve optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1208 may be fabricated on fin field-effect transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. By way of example and not limitation, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or an orderer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, the streaming microprocessor may include separate parallel integer and floating-point data paths for efficient execution of workloads employing a mix of computational and addressing operations. In at least one embodiment, the streaming microprocessor may include separate thread scheduling capabilities for finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0241] In at least one embodiment, one or more GPUs 1208 may include high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem, which in some examples provides a peak memory bandwidth of approximately 900 GB / second. In at least one embodiment, synchronous graphics random access memory (“SGRAM”), such as fifth generation graphics double data rate type synchronous random access memory (“GDDR5”), may be used in addition to or in place of HBM memory.

[0242] In at least one embodiment, one or more GPUs 1208 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 1208 to directly access the page tables of one or more CPUs 1206. In at least one embodiment, when the memory management unit ("MMU") of a GPU in one or more GPUs 1208 experiences a miss, an address translation request may be sent to one or more CPUs 1206. In response, in at least one embodiment, two CPUs in one or more CPUs 1206 may look up the virtual-physical mapping of the address in their page tables and send the translation back to one or more GPUs 1208. In at least one embodiment, unified memory technology may allow a single unified virtual address space for the memory of both one or more CPUs 1206 and one or more GPUs 1208, thus simplifying the programming of one or more GPUs 1208 and porting applications to one or more GPUs 1208.

[0243] In at least one embodiment, one or more GPUs 1208 may include any number of access counters, which may track the access frequency of one or more GPUs 1208 to the memory of other processors. In at least one embodiment, one or more access counters may help ensure that memory pages are moved to the physical memory of the processor that most frequently accesses the pages, thus improving the efficiency of sharing the memory range among processors.

[0244] In at least one embodiment, one or more SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, one or more caches 1212 may include a level three ("L3") cache that can be used by both one or more CPUs 1206 and one or more GPUs 1208 (e.g., connected to one or more CPUs 1206 and one or more GPUs 1208). In at least one embodiment, one or more caches 1212 may include a write-back cache that can track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, depending on the embodiment, the L3 cache may include 4MB of memory or more.

[0245] In at least one embodiment, one or more SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1204 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memories. In at least one embodiment, a large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1208 and offload some tasks of one or more GPUs 1208 (e.g., to free up more cycles of one or more GPUs 1208 to perform other tasks). In at least one embodiment, one or more accelerators 1214 may be used for target workloads that are stable enough to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based or region convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0246] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for a particular set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU and generally far exceed the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including supporting, for example, INT8, INT16, and FP16 data types for single-instance convolution functions for features and weights and post-processor functions. In at least one embodiment, one or more DLAs may execute a neural network, especially a CNN, quickly and efficiently on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and identification and detection using data from a microphone; a CNN for face recognition and vehicle owner identification using data from a camera sensor; and / or a CNN for security- and / or safety-related events.

[0247] In at least one embodiment, one or more DLAs may perform any function of one or more GPUs 1208, and by using an inference accelerator, for example, a designer may target one or more DLAs or one or more GPUs 1208 for any function. For example, in at least one embodiment, a designer may concentrate the processing and floating-point operations of a CNN on one or more DLAs and leave other functions to one or more GPUs 1208 and / or one or more accelerators 1214.

[0248] In at least one embodiment, one or more accelerators 1214 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1238, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0249] In at least one embodiment, the RISC cores may interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, depending on the embodiment, the RISC cores may use any one of a variety of protocols. In at least one embodiment, the RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices may be used to implement the RISC cores. For example, in at least one embodiment, the RISC cores may include an instruction cache and / or tightly coupled RAM.

[0250] In at least one embodiment, the DMA may enable the components of the PVA to access system memory independently of one or more CPUs 1206. In at least one embodiment, the DMA may support any number of features for optimizing the delivery to the PVA, including but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more dimensions of addressing, which may include but are not limited to block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0251] In at least one embodiment, a vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines) and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a single instruction multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may improve throughput and speed.

[0252] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a general computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on one image, or even different algorithms on a sequence of images or parts of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code (“ECC”) memory for enhancing overall system security.

[0253] In at least one embodiment, one or more accelerators 1214 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the one or more accelerators 1214. In at least one embodiment, the on-chip memory may include at least 4MB SRAM, which includes, for example but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0254] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and the DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communication for continuous data transfer. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0255] In at least one embodiment, one or more SoCs 1204 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of an object (e.g., within a world model) to generate a real-time visualization simulation for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0256] In at least one embodiment, one or more accelerators 1214 can have a wide range of uses for autonomous driving. In at least one embodiment, PVA can be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA at low power and low latency match well with algorithm domains that require predictable processing. In other words, PVA excels in semi-dense or dense general computations, even on small data sets that may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1200, PVA can be designed to run classical computer vision algorithms as they can be efficient in object detection and integer math operations.

[0257] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, algorithms based on semi-global matching can be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for level 3 - 5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on inputs from two monocular cameras.

[0258] In at least one embodiment, PVA can be used to perform dense optical flow. For example, in at least one embodiment, PVA can process raw RADAR data (e.g., using 4D fast Fourier transform) to provide processed RADAR data. In at least one embodiment, for example, PVA is used for time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0259] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example but not limited to, a neural network, the output of which is a measure of the confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measure enables the system to make further decisions, namely, which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence, and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, false positive detections will cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered as triggers for AEB. In at least one embodiment, the DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network can take at least some subset of parameters as its input, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), and the outputs of one or more IMU sensors 1266 related to the vehicle 1200 direction, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1264 or one or more RADAR sensors 1260).

[0260] In at least one embodiment, one or more SoCs 1204 can include one or more data stores 1216 (e.g., memories). In at least one embodiment, one or more data stores 1216 can be on-chip memories of one or more SoCs 1204, which can store neural networks to be executed on one or more GPUs 1208 and / or DLAs. In at least one embodiment, one or more data stores 1216 can have a large enough capacity to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, one or more data stores 1216 can include one or more L2 or L3 caches.

[0261] In at least one embodiment, one or more SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). In at least one embodiment, one or more processors 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions as well as associated secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1204 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low power state transitions, manage one or more SoC 1204 thermal and temperature sensors, and / or manage one or more SoC 1204 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1204 may use the ring oscillator to detect the temperature of one or more CPUs 1206, one or more GPUs 1208, and / or one or more accelerators 1214. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1204 in a lower power state and / or place the vehicle 1200 in a driver's safe parking mode (e.g., cause the vehicle 1200 to safely park).

[0262] In at least one embodiment, one or more processors 1210 may further include a set of embedded processors that may be used as an audio processing engine, and the audio processing engine may be an audio subsystem that provides full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0263] In at least one embodiment, one or more processors 1210 may further include an always-on processor engine that may provide the necessary hardware features to support low power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0264] In at least one embodiment, one or more processors 1210 may further include a security cluster engine, which includes but is not limited to a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In a security mode, in at least one embodiment, two or more cores may operate in a lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1210 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1210 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0265] In at least one embodiment, one or more processors 1210 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required for a video playback application to produce a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1270, one or more surround cameras 1274, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 1204, which is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform but is not limited to lip reading to activate cellular services and make phone calls, indicate emails, change the destination of the vehicle, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are otherwise disabled.

[0266] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the case of motion occurring in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of the information provided by adjacent frames. In at least one embodiment, in the case where an image or a portion of the image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from a previous image to reduce the noise in the current image.

[0267] In at least one embodiment, the video image synthesizer may also be configured to perform stereoscopic correction on the input stereoscopic shot frames. In at least one embodiment, when the operating system desktop is in use, the video image synthesizer may also be used for user interface synthesis and does not require one or more GPUs 1208 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1208 are powered on and active for 3D rendering, the video image synthesizer may be used to offload one or more GPUs 1208 to improve performance and responsiveness.

[0268] In at least one embodiment, one or more of the SoCs 1204 may further include a Mobile Industry Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block for receiving video and inputs from cameras, which can be used for camera and related pixel input functions. In at least one embodiment, one or more of the SoCs 1204 may further include an input / output controller, which can be software-controlled and can be used to receive I / O signals not committed to a specific role.

[0269] In at least one embodiment, one or more of the SoCs 1204 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoder / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1204 can be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., one or more LIDAR sensors 1264, one or more RADAR sensors 1260, etc., which can be connected via Ethernet channels), data from the bus 1202 (e.g., the speed of the vehicle 1200, the steering wheel position, etc.), data from one or more GNSS sensors 1258 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more of the SoCs 1204 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and can be used to free one or more CPUs 1206 from routine data management tasks.

[0270] In at least one embodiment, one or more SoCs 1204 can be an end-to-end platform with a flexible architecture that spans automation levels 3 - 5, thus providing an integrated functional safety architecture for a platform that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a flexible, reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1204 can be faster, more reliable, and even more energy - efficient and space - efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1214, when combined with one or more CPUs 1206, one or more GPUs 1208, and one or more data stores 1216, can provide a fast, efficient platform for level 3 - 5 autonomous vehicles.

[0271] In at least one embodiment, computer vision algorithms can be executed on the CPU, which can be configured using a high - level programming language (such as C) to execute various processing algorithms on various visual data. However, in at least one embodiment, the CPU generally cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in in - vehicle ADAS applications and actual level 3 - 5 autonomous vehicles.

[0272] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined together to achieve level 3 - 5 autonomous driving functions. For example, in at least one embodiment, the CNN executed on the DLA or discrete GPU (e.g., one or more GPUs 1220) can include text and word recognition, thus allowing traffic signs to be read and understood, including signs that the neural network has not been specifically trained for. In at least one embodiment, the DLA can also include a neural network that can recognize, interpret, and provide semantic understanding of the signs, and pass this semantic understanding to a path - planning module running on the CPU complex.

[0273] In at least one embodiment, for level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign that states "Caution: flashing lights indicate icy conditions", along with the electric lights, can be interpreted independently or jointly by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executed on the CPU complex) that when flashing lights are detected, there is an icy condition. In at least one embodiment, the flashing lights can be recognized by operating a third deployed neural network on multiple frames, and the vehicle's path planning software can be notified of the presence (or absence) of the flashing lights. In at least one embodiment, all three neural networks can run simultaneously, e.g., within the DLA and / or on one or more GPUs 1208.

[0274] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from a camera sensor to recognize the presence of an authorized driver and / or the owner of the vehicle 1200. In at least one embodiment, a normally open sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in a security mode, it can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1204 provide protection against theft and / or carjacking.

[0275] In at least one embodiment, a CNN for emergency vehicle detection and recognition can use data from a microphone 1296 to detect and recognize an emergency vehicle siren. In at least one embodiment, one or more SoCs 1204 use a CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, a CNN running on the DLA is trained to recognize the relative approach speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to recognize emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1258. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to recognize only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1262 to execute an emergency vehicle safety routine, slow down the vehicle, drive the vehicle to the side of the road, park, and / or idle the vehicle until the emergency vehicle passes.

[0276] In at least one embodiment, vehicle 1200 may include one or more CPUs 1218 (e.g., one or more discrete CPUs or one or more dCPUs), which may be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, one or more CPUs 1218 may include, for example, X86 processors. One or more CPUs 1218 may be used to perform any of a variety of functions, such as arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 1204, and / or monitoring the status and health of one or more controllers 1236 and / or the on-chip infotainment system (“infotainment SoC”) 1230. In at least one embodiment, SoC 1204 includes one or more interconnects, and the interconnects may include Peripheral Component Interconnect Express (PCIe).

[0277] In at least one embodiment, vehicle 1200 may include one or more GPUs 1220 (e.g., one or more discrete GPUs or one or more dGPUs), which may be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, one or more GPUs 1220 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks at least in part based on inputs from sensors of vehicle 1200 (e.g., sensor data).

[0278] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include, but is not limited to, one or more wireless antennas 1226 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1224 may be used to implement a wireless connection to an Internet cloud service (e.g., with a server and / or other network devices), to other vehicles, and / or to a computing device (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1200 and another vehicle and / or an indirect link may be established (e.g., via a network and the Internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles in the vicinity of vehicle 1200 (e.g., vehicles in front of, to the side of, and / or behind vehicle 1200). In at least one embodiment, the foregoing function may be part of the cooperative adaptive cruise control function of vehicle 1200.

[0279] In at least one embodiment, network interface 1224 may include a SoC that provides modulation and demodulation functions and enables one or more controllers 1236 to communicate over a wireless network. In at least one embodiment, network interface 1224 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functions may be provided by a separate chip. In at least one embodiment, the network interface may include wireless capabilities for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0280] In at least one embodiment, vehicle 1200 may further include one or more data stores 1228, which may include but are not limited to off-chip (e.g., one or more off-chip SoCs 1204) storage. In at least one embodiment, one or more data stores 1228 may include but are not limited to one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices that can store at least one bit of data.

[0281] In at least one embodiment, vehicle 1200 may further include one or more GNSS sensors 1258 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including, for example but not limited to, GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0282] In at least one embodiment, vehicle 1200 may further include one or more RADAR sensors 1260. In at least one embodiment, one or more RADAR sensors 1260 may be used by vehicle 1200 for remote vehicle detection, even in dark and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1260 may use the CAN bus and / or bus 1202 (e.g., for transmitting data generated by one or more RADAR sensors 1260) to control and access object tracking data and, in some examples, may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example but not limited to, one or more RADAR sensors 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1260 are pulsed Doppler RADAR sensors.

[0283] In at least one embodiment, one or more RADAR sensors 1260 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 m (meters)). In at least one embodiment, one or more RADAR sensors 1260 may assist in differentiating between static and moving objects and may be used by ADAS system 1238 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1260 included in the long-range RADAR system may include but are not limited to a monostatic multimodal RADAR having multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, with six antennas, the central four antennas may create a focused beam pattern designed to record the surrounding environment of vehicle 1200 at a relatively high speed with minimal traffic interference from adjacent lanes. In at least one embodiment, the other two antennas may widen the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1200.

[0284] In at least one embodiment, by way of example, a mid-range RADAR system can include a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system can include, but is not limited to, any number of RADAR sensors 1260 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two beams that continuously monitor the rear direction of the vehicle and the blind spots in the vicinity. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1238 for blind spot detection and / or lane change assistance.

[0285] In at least one embodiment, the vehicle 1200 can further include one or more ultrasonic sensors 1262. In at least one embodiment, one or more ultrasonic sensors 1262 that can be positioned at the front, rear, and / or side positions of the vehicle 1200 can be used for parking assistance and / or creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1262 can be used, and different ultrasonic sensors 1262 can be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1262 can operate at a functional safety level of ASIL B.

[0286] In at least one embodiment, the vehicle 1200 can include one or more LIDAR sensors 1264. In at least one embodiment, one or more LIDAR sensors 1264 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LIDAR sensors 1264 can operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1200 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1264 that can use an Ethernet channel (e.g., to provide data to a gigabit Ethernet switch).

[0287] In at least one embodiment, one or more LIDAR sensors 1264 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1264 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm - 3 cm, and support an Ethernet connection of 100 Mbps. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1264 may include small devices that can be embedded in the front, rear, sides, and / or corner positions of the vehicle 1200. In at least one embodiment, one or more LIDAR sensors 1264, in such an embodiment, may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and have a range of 200 m. In at least one embodiment, the one or more forward-mounted LIDAR sensors 1264 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0288] In at least one embodiment, LIDAR technologies (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 m around the vehicle 1200. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1200 to the object. In at least one embodiment, flash LIDAR may allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, with one deployed on each side of the vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera that has no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device may use a Class I (eye-safe) laser pulse of 5 nanoseconds per frame and may capture the reflected laser as a 3D range point cloud and co-registered intensity data.

[0289] In at least one embodiment, vehicle 1200 may further include one or more IMU sensors 1266. In at least one embodiment, one or more IMU sensors 1266 may be located at the center of the rear axle of vehicle 1200. In at least one embodiment, one or more IMU sensors 1266 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1266 may include but are not limited to accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1266 may include but are not limited to accelerometers, gyroscopes, and magnetometers.

[0290] In at least one embodiment, one or more IMU sensors 1266 may be implemented as a miniature high-performance GPS-aided inertial navigation system (“GPS / INS”) that combines microelectromechanical system (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm, for providing estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1266 may enable vehicle 1200 to estimate its heading by directly observing and correlating the speed changes from GPS to one or more IMU sensors 1266, without input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1266 and one or more GNSS sensors 1258 may be combined in a single integrated unit.

[0291] In at least one embodiment, vehicle 1200 may include one or more microphones 1296 placed inside and / or around vehicle 1200. In at least one embodiment, one or more microphones 1296 may be used for emergency vehicle detection and identification.

[0292] In at least one embodiment, vehicle 1200 may further include any number of camera types, including one or more stereo cameras 1268, one or more wide-angle cameras 1270, one or more infrared cameras 1272, one or more surround cameras 1274, one or more long-range cameras 1298, one or more mid-range cameras 1276, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of vehicle 1200. In at least one embodiment, the type of camera used depends on vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around vehicle 1200. In at least one embodiment, the number of cameras deployed may vary according to the embodiment. For example, in at least one embodiment, vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera is described in more detail previously herein with reference to Figure 12A and Figure 12B More detailed descriptions of each camera are provided.

[0293] In at least one embodiment, vehicle 1200 may further include one or more vibration sensors 1242. In at least one embodiment, one or more vibration sensors 1242 may measure the vibration of components of vehicle 1200 (e.g., the axle). For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1242 are used, the difference between the vibrations may be used to determine the friction or slip of the road surface (e.g., when there is a vibration difference between a powered drive axle and a free-rotating axle).

[0294] In at least one embodiment, vehicle 1200 may include an ADAS system 1238. In at least one embodiment, the ADAS system 1238 may include, in some examples but not limited to, a SoC. In at least one embodiment, the ADAS system 1238 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions.

[0295] In at least one embodiment, the ACC system may use one or more RADAR sensors 1260, one or more LIDAR sensors 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of vehicle 1200 and automatically adjusts the speed of vehicle 1200 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and, when needed, advises vehicle 1200 to change lanes. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0296] In at least one embodiment, the CACC system uses information from other vehicles, which may be received indirectly from other vehicles via the network interface 1224 and / or one or more wireless antennas 1226 via a wireless link or through a network connection (e.g., via the Internet). In at least one embodiment, a direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while an indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Generally, V2V communication provides information about the vehicle immediately ahead (e.g., a vehicle immediately in front of and in the same lane as vehicle 1200), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of an I2V and a V2V information source. In at least one embodiment, given information about the vehicles in front of a given vehicle 1200, the CACC system may be more reliable and has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0297] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward camera and / or one or more RADAR sensors 1260, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings, such as in the form of a sound, visual warning, vibration, and / or a rapid braking pulse.

[0298] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can use one or more forward cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes in an attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision imminent braking.

[0299] In at least one embodiment, when vehicle 1200 crosses a lane marking, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibration, to alert the driver. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system can use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1200 starts to leave its lane, the LKA system provides steering input or braking to correct vehicle 1200.

[0300] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of a vehicle. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0301] In at least one embodiment, when the vehicle 1200 detects an object outside the rear camera range while reversing, the RCTW system can provide visual, audible, and / or tactile notifications. In at least one embodiment, the RCTW system includes an AEB system for ensuring that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0302] In at least one embodiment, conventional ADAS systems may be prone to producing false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems will warn the driver and allow the driver to decide whether a safety situation truly exists and take action accordingly. In at least one embodiment, in the case of conflicting results, the vehicle 1200 itself decides whether to follow the result of the primary computer or the secondary computer (e.g., the first controller or the second controller in the controller 1236). For example, in at least one embodiment, the ADAS system 1238 can be a backup and / or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run various software redundantly on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1238 can be provided to the supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU decides how to reconcile the conflict to ensure safe operation.

[0303] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU, which indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the instructions of the primary computer, regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, in the case where the confidence score does not meet the threshold and the primary computer and the secondary computer indicate different results (e.g., conflict), the supervisory MCU can arbitrate between the computers to determine an appropriate result.

[0304] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides an error alert based at least in part on outputs from the host computer and outputs from the auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU can learn when the output of the auxiliary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU can learn when the FCW system is identifying metal objects that are not actually dangerous, such as drain grates or manhole covers that would trigger an alert. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when there is a bicyclist or pedestrian present and lane departure is actually the safest course of action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can be included as and / or be a component of one or more SoCs 1204.

[0305] In at least one embodiment, the ADAS system 1238 can include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer can use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU can improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementation and intentional non-identity make the overall system more fault-tolerant, especially for faults caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the host computer and the not-identical software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can have greater confidence that the overall result is correct, and the vulnerability in the software or hardware on the host computer will not result in a major error.

[0306] In at least one embodiment, the output of the ADAS system 1238 can be fed into the perception block of the host computer and / or the dynamic driving task block of the host computer. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward collision warning due to an object directly ahead, the perception block can use that information when identifying the object. In at least one embodiment, as described herein, the auxiliary computer can have its own neural network that is trained to reduce the risk of false alarms.

[0307] In at least one embodiment, vehicle 1200 may further include an infotainment SoC 1230 (e.g., in-vehicle infotainment (IVI)). Although shown and described as an SoC, in at least one embodiment, infotainment system SoC 1230 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, infotainment SoC 1230 may include, but is not limited to, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total covered distance, brake fuel level, oil level, door open / closed, air filter information, etc.) to vehicle 1200. For example, infotainment SoC 1230 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, in-vehicle computer, in-vehicle entertainment system, WiFi, steering wheel audio control, hands-free voice control, head-up display (“HUD”), HMI display 1234, telematics device, control panel (e.g., for controlling various components, features, and / or systems and / or interacting therewith), and / or other components. In at least one embodiment, infotainment SoC 1230 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of vehicle 1200, such as information from ADAS system 1238, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0308] In at least one embodiment, infotainment SoC 1230 may include any number and type of GPU functionality. In at least one embodiment, infotainment SoC 1230 may communicate with other devices, systems, and / or components of vehicle 1200 via bus 1202. In at least one embodiment, infotainment SoC 1230 may be coupled to a supervisory MCU such that the GPU of the infotainment system may perform some autonomous driving functions in the event of a failure of one or more main controllers 1236 (e.g., the main computer and / or standby computer of vehicle 1200). In at least one embodiment, infotainment SoC 1230 may place vehicle 1200 into a driver-to-safe parking mode as described herein.

[0309] In at least one embodiment, vehicle 1200 may further include a dashboard 1232 (e.g., a digital dashboard, an electronic dashboard, a digital instrument panel, etc.). In at least one embodiment, the dashboard 1232 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, the dashboard 1232 may include, but is not limited to, a set of gauges in any number and combination, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine fault lights, airbag (e.g., auxiliary restraint system) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1230 and the dashboard 1232. In at least one embodiment, the dashboard 1232 may be included as part of the infotainment SoC 1230, and vice versa.

[0310] In at least one embodiment, at least one component shown or described with respect to Figure 12C is used to implement the techniques and / or functions associated with Figures 1 - 8B described. In at least one embodiment, data from one or more data stores 1216 is transmitted using hybrid beamforming parameters and / or transmit power of neural network inference described with respect to Figure 1 and as described elsewhere herein via one or more wireless antennas 1226.

[0311] Figure 12D is according to at least one embodiment between one or more cloud-based servers and [[ID1200. In at least one embodiment, the system may include, but is not limited to, one or more servers 1278, one or more networks 1290, and any number and type of vehicles, including vehicle 1200. In at least one embodiment, one or more servers 1278 may include, but are not limited to, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(D) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected with a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1288 and / or PCIe connection 1286 developed by NVIDIA. In at least one embodiment, the GPUs 1284 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1284 and PCIe switches 1282 are connected via PCIe interconnects. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1278 may include, but is not limited to, any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination. For example, in at least one embodiment, one or more servers 1278 may each include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0312] In at least one embodiment, one or more servers 1278 may receive image data representing an image from a vehicle via one or more networks 1290 that shows an unexpected or changed road condition, such as a recently started road project. In at least one embodiment, one or more servers 1278 may send updated neural networks 1292 and / or map information 1294 to the vehicle via one or more networks 1290, including, but not limited to, information about traffic and road conditions. In at least one embodiment, updates to the map information 1294 may include, but are not limited to, updates to the HD map 1222, such as information about construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1292 and / or map information 1294 may have been generated by new training and / or experience represented in data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1278 and / or other servers).

[0313] In at least one embodiment, one or more servers 1278 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by a vehicle and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., in the case where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., in the case where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., sent to the vehicle via one or more networks 1290, and / or the machine learning model may be used by one or more servers 1278 to remotely monitor the vehicle).

[0314] In at least one embodiment, one or more servers 1278 may receive data from a vehicle and apply the data to a latest real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1278 may include a deep learning supercomputer powered by one or more GPUs 1284 and / or a dedicated AI computer, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1278 may include a deep learning infrastructure of a data center powered by a CPU.

[0315] In at least one embodiment, the deep learning infrastructure of one or more servers 1278 may be capable of performing fast, real-time inference and may use that ability to evaluate and verify the health of processors, software, and / or associated hardware in vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1200, such as an image sequence and / or objects located in the image sequence by vehicle 1200 (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify the objects and compare them with the objects identified by vehicle 1200, and if the results do not match and the deep learning infrastructure determines that the AI in vehicle 1200 is malfunctioning, one or more servers 1278 may send a signal to vehicle 1200 that instructs the fail-safe computer of vehicle 1200 to take control, notify the passengers, and complete a safe parking operation.

[0316] In at least one embodiment, one or more servers 1278 may include one or more GPUs 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 device). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time response. In at least one embodiment, in cases where performance is less critical, for example, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 915 are used to execute one or more embodiments. This document combines ​ and / or ​ to provide details about the hardware structure 915.

[0317] Computer system

[0318] ​ is a block diagram showing an exemplary computer system according to at least one embodiment. The exemplary computer system can be a system with interconnected devices and components, a system-on-chip (SOC), or some combination thereof formed with a processor that may include execution units for executing instructions. In at least one embodiment, according to the present disclosure, such as in the embodiments described herein, the computer system 1300 may include, but is not limited to, components such as a processor 1302 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, the computer system 1300 may include a processor, such as those available from Intel Corporation of Santa Clara, California, processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessors, although other systems (including PCs, engineering workstations, set-top boxes, etc. with other microprocessors) can also be used. In at least one embodiment, the computer system 1300 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0319] Embodiments can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, an embedded application can include a microcontroller, a digital signal processor (“DSP”), a system-on-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0320] In at least one embodiment, computer system 1300 can include, but is not limited to, a processor 1302, which can include, but is not limited to, one or more execution units 1308 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1300 is a single-processor desktop or server system, but in another embodiment, computer system 1300 can be a multi-processor system. In at least one embodiment, processor 1302 can include, but is not limited to, for example, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing an instruction set combination, or any other processor device such as a digital signal processor. In at least one embodiment, processor 1302 can be coupled to a processor bus 1310, which can transfer data signals between processor 1302 and other components in computer system 1300.

[0321] In at least one embodiment, processor 1302 can include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 1304. In at least one embodiment, processor 1302 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory can reside outside of processor 1302. Depending on the particular implementation and requirements, other embodiments can also include a combination of internal and external caches. In at least one embodiment, register file 1306 can store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0322] In at least one embodiment, execution unit 1308, which includes, but is not limited to, logic for performing integer and floating point operations, is also located in processor 1302. In at least one embodiment, processor 1302 may also include a microcode (“ucode”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1308 may include logic for processing a packed instruction set 1309. In at least one embodiment, by including the packed instruction set 1309 in the instruction set of a general-purpose processor and the associated circuitry to execute instructions, operations used by many multimedia applications can be performed using packed data in processor 1302. In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, which can eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0323] In at least one embodiment, execution unit 1308 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1300 may include, but is not limited to, memory 1320. In at least one embodiment, memory 1320 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1320 may store one or more instructions 1319 and / or data 1321 represented by data signals that can be executed by processor 1302.

[0324] In at least one embodiment, the system logic chip may be coupled to a processor bus 1310 and a memory 1320. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1316, and the processor 1302 may communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 may provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 may direct data signals among the processor 1302, the memory 1320, and other components in the computer system 1300, and may bridge data signals among the processor bus 1310, the memory 1320, and the system I / O interface 1322. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1316 may be coupled to the memory 1320 via the high-bandwidth memory path 1318, and the graphics / video card 1312 may be coupled to the MCH 1316 via an Accelerated Graphics Port (“AGP”) interconnect 1314.

[0325] In at least one embodiment, the computer system 1300 may use the system I / O interface 1322 as a proprietary hub interface bus to couple the MCH 1316 to an I / O controller hub (“ICH”) 1330. In at least one embodiment, the ICH 1330 may provide direct connections to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1320, the chipset, and the processor 1302. Examples may include, but are not limited to, an audio controller 1329, a firmware hub (“Flash BIOS”) 1328, a wireless transceiver 1326, a data storage 1324, a legacy I / O controller 1323 that includes a user input and keyboard interface 1325, a serial expansion port 1327 (such as a Universal Serial Bus (“USB”) port), and a network controller 1334. In at least one embodiment, the data storage 1324 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash device, or other mass storage devices.

[0326] In at least one embodiment, ​ a system including interconnected hardware devices or “chips” is shown, while in other embodiments, ​ an exemplary SoC may be shown. In at least one embodiment, ​The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1300 are interconnected using Compute Express Link (CXL) interconnects.

[0327] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding ​ and / or ​ Logic 915 are provided. In at least one embodiment, Logic 915 can be used in computer system 1300 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0328] In at least one embodiment, at least one component shown or described with respect to ​ is used to implement the techniques and / or functions described in connection with ​ In at least one embodiment, processor 1302 performs one or more operations related to a neural network for inferring hybrid beamforming parameters and / or transmit power for use by a device to transmit wireless signals described in connection with ​ and as described elsewhere herein.

[0329] ​ is a block diagram illustrating an electronic device 1400 for utilizing processor 1410 according to at least one embodiment. In at least one embodiment, electronic device 1400 can be, for example but not limited to, a laptop computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0330] In at least one embodiment, electronic device 1400 can include, but is not limited to, processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1410 is coupled using a bus or interface such as an I 2 C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advanced Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, ​ illustrates a system that includes interconnected hardware devices or “chips,” while in other embodiments, ​An exemplary SoC can be shown. In at least one embodiment, ​ the devices shown in can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, ​ one or more components of are interconnected using Compute Express Link (CXL) interconnects.

[0331] In at least one embodiment, ​ it can include a display 1424, a touch screen 1425, a touchpad 1430, a near field communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, an Embedded Controller (“EC”) 1435, a Trusted Platform Module (“TPM”) 1438, a BIOS / Firmware / Flash (“BIOS, FW Flash”) 1422, a DSP 1460, a drive 1420 (such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”)), a Wireless Local Area Network unit (“WLAN”) 1450, a Bluetooth unit 1452, a Wireless Wide Area Network unit (“WWAN”) 1456, a Global Positioning System (GPS) unit 1455, a camera (“USB 3.0 camera”) 1454 (such as a USB 3.0 camera) and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented to, for example, the LPDDR3 standard. These components can each be implemented in any suitable manner.

[0332] In at least one embodiment, other components can be communicatively coupled to the processor 1410 through the components described herein. In at least one embodiment, an accelerometer 1441, an Ambient Light Sensor (“ALS”) 1442, a compass 1443, and a gyroscope 1444 can be communicatively coupled to the sensor hub 1440. In at least one embodiment, a thermal sensor 1439, a fan 1437, a keyboard 1436, and a touchpad 1430 can be communicatively coupled to the EC 1435. In at least one embodiment, a speaker 1463, headphones 1464, and a microphone (“mic”) 1465 can be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 1462, which in turn can be communicatively coupled to the DSP 1460. In at least one embodiment, the audio unit 1462 can include, for example but not limited to, an audio encoder / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a Subscriber Identity Module (“SIM”) 1457 can be communicatively coupled to the WWAN unit 1456. In at least one embodiment, components (such as the WLAN unit 1450, the Bluetooth unit 1452, and the WWAN unit 1456) can be implemented in a next-generation form factor (“NGFF”).

[0333] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with ​ and / or ​ Details regarding Logic 915 are provided. In at least one embodiment, Logic 915 may be used in an electronic device 1400 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0334] In at least one embodiment, at least one component shown or described with respect to ​ is used to implement the techniques and / or functions described in connection with ​ In at least one embodiment, a processor 1415 performs one or more operations related to a neural network that is used to infer hybrid beamforming parameters and / or transmit power for use by a device to transmit wireless signals described in connection with ​ and as described elsewhere herein.

[0335] ​ FIG. 1500 shows a computer system 1500 in accordance with at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement the various processes and methods described throughout this disclosure.

[0336] In at least one embodiment, the computer system 1500 includes, but is not limited to, at least one central processing unit (“CPU”) 1502 that is connected to a communication bus 1510 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1500 includes, but is not limited to, a main memory 1504 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in the main memory 1504 that may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1522 provides an interface to other computing devices and networks for receiving data from other systems and transmitting data to other systems using the computer system 1500.

[0337] In at least one embodiment, computer system 1500 includes, but is not limited to, input device 1508, parallel processing system 1512, and display device 1506 in at least one embodiment, which may be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”) display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device 1508 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each module described herein may be located on a single semiconductor platform to form a processing system.

[0338] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding ​ and / or ​ Logic 915 are provided. In at least one embodiment, Logic 915 may be used in computer system 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0339] In at least one embodiment, at least one component shown or described with respect to ​ is used to implement the techniques and / or functions described in connection with ​ In at least one embodiment, computer system 1500 performs one or more operations related to a neural network for inferring hybrid beamforming parameters and / or transmit power for use by a device to transmit wireless signals described in connection with ​ and as described elsewhere herein.

[0340] ​ FIG. shows computer system 1600 according to at least one embodiment. In at least one embodiment, computer system 1600 includes, but is not limited to, computer 1610 and USB drive 1620. In at least one embodiment, computer 1610 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, computer 1610 includes, but is not limited to, servers, cloud instances, laptop computers, and desktop computers.

[0341] In at least one embodiment, the USB drive 1620 includes, but is not limited to, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, the processing unit 1630 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1630 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1630 includes an application specific integrated circuit (“ASIC”) that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1630 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1630 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0342] In at least one embodiment, the USB interface 1640 can be any type of USB connector or USB socket. For example, in at least one embodiment, the USB interface 1640 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, the USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1650 can include any number and type of logic that enables the processing unit 1630 to interface with a device (such as computer 1610) via the USB connector 1640.

[0343] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding ​ and / or ​ Logic 915 are provided herein. In at least one embodiment, Logic 915 can be used in computer system 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0344] In at least one embodiment, at least one component shown or described with respect to ​ is used to implement the techniques and / or functions described in connection with ​ In at least one embodiment, computer system 1600 performs one or more operations related to a neural network that is used to infer hybrid beamforming parameters and / or transmit power for use by a device to transmit wireless signals described in connection with ​ and as described elsewhere herein.

[0345] ​An exemplary architecture is shown in which multiple GPUs 1710(1)-1710(N) are communicatively coupled to multiple multi-core processors 1705(1)-1705(M) via high-speed links 1740(1)-1740(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1740(1)-1740(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. In at least one embodiment, various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, and their values can vary from figure to figure. In at least one embodiment, one or more of the multiple GPUs 1710(1)-1710(N) include one or more graphics cores (also simply referred to as "cores") 2000 as disclosed in ​ and ​ . In at least one embodiment, one or more graphics cores 2000 can be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where in this context, a slice can refer to a portion of the processing resources in a processing unit (e.g., 16 cores, ray tracing units, thread directors or schedulers).

[0346] Furthermore, in at least one embodiment, two or more GPUs 1710 are interconnected via high-speed links 1729(1)-1729(2), which can be implemented using a protocol / link similar to or different from the protocol / link used for high-speed links 1740(1)-1740(N). Similarly, two or more multi-core processors 1705 can be connected via high-speed link 1728, which can be a symmetric multi-processor (SMP) bus operating at a speed of 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, a similar protocol / link (e.g., via a common interconnect structure) can be used to accomplish ​ all communications between the various system components shown in

[0347] In at least one embodiment, each multi-core processor 1705 is communicatively coupled to processor memories 1701(1)-1701(M) via memory interconnects 1726(1)-1726(M), respectively, and each GPU 1710(1)-1710(N) is communicatively coupled to GPU memories 1720(1)-1720(N) via GPU memory interconnects 1750(1)-1750(N), respectively. In at least one embodiment, the memory interconnects 1726 and 1750 may utilize similar or different memory access technologies. By way of example and not limitation, the processor memories 1701(1)-1701(M) and the GPU memories 1720 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of the processor memory 1701 may be volatile memory while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0348] As described herein, although the respective multi-core processors 1705 and GPUs 1710 may be physically coupled to specific memories 1701, 1720, respectively, and / or a unified memory architecture may be implemented, in which a virtual system address space (also referred to as the "effective address" space) is distributed among the respective physical memories. For example, the processor memories 1701(1)-1701(M) may each include 64 GB of system memory address space, and the GPU memories 1720(1)-1720(N) may each include 32 GB of system memory address space, such that when M = 2 and N = 4, a total of 256 GB of addressable memory results. Other values of N and M are possible.

[0349] ​ Additional details of the interconnection between a multi-core processor 1707 and a graphics acceleration module 1746 are shown. In at least one embodiment, the graphics acceleration module 1746 may include one or more GPU chips integrated on a line card that is coupled to the processor 1707 via a high-speed link 1740 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1746 may alternatively be integrated on a package or chip having the processor 1707.

[0350] In at least one embodiment, the processor 1707 includes multiple cores 1760A - 1760D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1761A - 1761D and one or more caches 1762A - 1762D. In at least one embodiment, cores 1760A - 1760D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, caches 1762A - 1762D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1756 may be included within caches 1762A - 1762D and shared by groups of cores 1760A - 1760D. For example, one embodiment of the processor 1707 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1707 and the graphics acceleration module 1746 are connected to the system memory 1714, which may include ​ processor memories 1701(1) - 1701(M) therein.

[0351] In at least one embodiment, data and instructions stored in respective caches 1762A - 1762D, 1756, and system memory 1714 are maintained consistent via the coherence bus 1764 for inter - core communication. In at least one embodiment, for example, each cache may have cache coherence logic / circuit associated therewith to communicate via the coherence bus 1764 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the coherence bus 1764 to snoop cache accesses.

[0352] In at least one embodiment, the proxy circuit 1725 communicatively couples the graphics acceleration module 1746 to the coherence bus 1764, thereby allowing the graphics acceleration module 1746 to participate in the cache coherence protocol as a peer of cores 1760A - 1760D. In particular, in at least one embodiment, the interface 1735 provides a connection to the proxy circuit 1725 via the high - speed link 1740, and the interface 1737 connects the graphics acceleration module 1746 to the high - speed link 1740.

[0353] In at least one embodiment, the accelerator integrated circuit 1736 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746. In at least one embodiment, each of the graphics processing engines 1731(1)-1731(N) may include a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746 include one or more graphics cores 2000 as discussed in conjunction with ​ and ​ . In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may alternatively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1746 may be a GPU having multiple graphics processing engines 1731(1)-1731(N), or the graphics processing engines 1731(1)-1731(N) may be individual GPUs integrated on a common package, line card, or chip.

[0354] In at least one embodiment, the accelerator integrated circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and also includes a memory access protocol for accessing the system memory 1714. In at least one embodiment, the MMU 1739 may also include a translation lookaside buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, the cache 1738 may store commands and data for efficient access by the graphics processing engines 1731(1)-1731(N). In at least one embodiment, a fetch unit 1744 may be used to keep the data stored in the cache 1738 and the graphics memories 1733(1)-1733(M) consistent with the core caches 1762A-1762D, 1756, and the system memory 1714. As previously described, this may be represented by the cache 1738 and the memories 1733(1)-1733(M) being implemented via the proxy circuit 1725 (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 1762A-1762D, 1756 to the cache 1738 and receiving updates from the cache 1738).

[0355] In at least one embodiment, a set of registers 1745 stores context data of threads executed by the graphics processing engines 1731(1)-1731(N), and the context management circuitry 1748 manages thread contexts. For example, the context management circuitry 1748 may perform save and restore operations to save and restore the contexts of individual threads during a context switch (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, the context management circuitry 1748 may store the current register values to a specified area in memory (e.g., identified by a context pointer) during a context switch. Then, the register values can be restored when returning to the context. In at least one embodiment, the interrupt management circuitry 1747 receives and processes interrupts received from system devices.

[0356] In at least one embodiment, the MMU 1739 converts virtual / valid addresses from the graphics processing engines 1731 to real / physical addresses in the system memory 1714. In at least one embodiment, the accelerator integrated circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1746 may be dedicated to a single application executed on the processor 1707 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented where the resources of the graphics processing engines 1731(1)-1731(N) are shared among multiple applications or virtual machines (VMs). In at least one embodiment, the resources may be subdivided into "slices" based on the processing requirements and priorities associated with the VMs and / or applications, and these slices are allocated to different VMs and / or applications.

[0357] In at least one embodiment, the accelerator integrated circuit 1736 acts as a bridge for the system of the graphics accelerator modules 1746 and provides address translation and system memory cache services. Additionally, in at least one embodiment, the accelerator integrated circuit 1736 may provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engines 1731(1)-1731(N).

[0358] In at least one embodiment, since the hardware resources of the graphics processing engines 1731(1)-1731(N) are explicitly mapped to the real address space seen by the host processor 1707, any host processor can directly address these resources using valid address values. In at least one embodiment, one function of the accelerator integrated circuit 1736 is the physical separation of the graphics processing engines 1731(1)-1731(N) such that they appear as independent units to the system.

[0359] In at least one embodiment, one or more graphics memories 1733(1)-1733(M) are respectively coupled to each graphics processing engine 1731(1)-1731(N), and N = M. In at least one embodiment, the graphics memories 1733(1)-1733(M) store instructions and data being processed by each graphics processing engine 1731(1)-1731(N). In at least one embodiment, the graphics memories 1733(1)-1733(M) can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6) or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-Ram.

[0360] In at least one embodiment, to reduce data traffic on the high-speed link 1740, bias techniques can be used to ensure that the data stored in the graphics memories 1733(1)-1733(M) is the data most frequently used by the graphics processing engines 1731(1)-1731(N), and preferably is data not used (at least not frequently used) by the cores 1760A-1760D. Similarly, in at least one embodiment, the bias mechanism attempts to keep the data needed by the cores (and preferably not needed by the graphics processing engines 1731(1)-1731(N)) in the caches 1762A-1762D, 1756, and the system memory 1714.

[0361] ​ Another exemplary embodiment is shown where the accelerator integrated circuit 1736 is integrated within the processor 1707. In this embodiment, the graphics processing engines 1731(1)-1731(N) communicate directly with the accelerator integrated circuit 1736 via the interface 1737 and the interface 1735 (again, which can be any form of bus or interface protocol) through the high-speed link 1740. In at least one embodiment, the accelerator integrated circuit 1736 can perform operations similar to those described with respect to ​ but may have higher throughput due to its close proximity to the coherence bus 1764 and the caches 1762A-1762D, 1756. In at least one embodiment, the accelerator integrated circuit supports different programming models, which include a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), and the programming models can include a programming model controlled by the accelerator integrated circuit 1736 and a programming model controlled by the graphics acceleration module 1746.

[0362] In at least one embodiment, the graphics processing engines 1731(1)-1731(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application may funnel other application requests to the graphics processing engines 1731(1)-1731(N) to provide virtualization within a VM / partition.

[0363] In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a hypervisor to virtualize the graphics processing engines 1731(1)-1731(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns the graphics processing engines 1731(1)-1731(N). In at least one embodiment, the operating system may virtualize the graphics processing engines 1731(1)-1731(N) to provide access to each process or application.

[0364] In at least one embodiment, the graphics acceleration module 1746 or individual graphics processing engines 1731(1)-1731(N) use a process handle to select process elements. In at least one embodiment, the process elements are stored in the system memory 1714 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engines 1731(1)-1731(N) (i.e., calling the system software to add a process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0365] ​An exemplary accelerator integrated slice 1790 is shown. In at least one embodiment, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1736. In at least one embodiment, an application is a valid address space 1782 in system memory 1714 that stores process elements 1783. In at least one embodiment, the process elements 1783 are stored in response to a GPU call 1781 from an application 1780 executing on a processor 1707. In at least one embodiment, the process element 1783 contains the process state of the corresponding application 1780. In at least one embodiment, the work descriptor (WD) 1784 contained in the process element 1783 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1784 is a pointer to a job request queue in the valid address space 1782 of the application.

[0366] In at least one embodiment, the graphics acceleration module 1746 and / or the individual graphics processing engines 1731(1)-1731(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure can be included for setting the process state and sending the WD 1784 to the graphics acceleration module 1746 to start a job in a virtualized environment.

[0367] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1746 or an individual graphics processing engine 1731. In at least one embodiment, when the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1746 is assigned, the operating system initializes the accelerator integrated circuit 1736 for the owned process.

[0368] In at least one embodiment, in operation, the WD fetch unit 1791 in the accelerator integrated slice 1790 fetches the next WD 1784, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1746. In at least one embodiment, data from the WD 1784 can be stored in the register 1745 and used by the MMU 1739, the interrupt management circuit 1747, and / or the context management circuit 1748, as shown. For example, one embodiment of the MMU 1739 includes a segment / page walk circuit for accessing the segment / page table 1786 within the OS virtual address space 1785. In at least one embodiment, the interrupt management circuit 1747 can process the interrupt event 1792 received from the graphics acceleration module 1746. In at least one embodiment, when performing a graphics operation, the effective address 1793 generated by the graphics processing engines 1731(1)-1731(N) is translated by the MMU 1739 into a real address.

[0369] In at least one embodiment, the register 1745 is replicated for each graphics processing engine 1731(1)-1731(N) and / or the graphics acceleration module 1746, and the register 1745 can be initialized by a hypervisor or an operating system. In at least one embodiment, each of these replicated registers can be included in the accelerator integrated slice 1790. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0370] Table 1 - Registers Initialized by the Hypervisor

[0371]

[0372]

[0373] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0374] Table 2 - Registers Initialized by the Operating System

[0375]

[0376] In at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731(1)-1731(N). In at least one embodiment, it contains all the information required for the graphics processing engines 1731(1)-1731(N) to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0377] ​Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1798 in which a list of process elements 1799 is stored. In at least one embodiment, the hypervisor real address space 1798 can be accessed via a hypervisor 1796 that virtualizes a graphics acceleration module engine for an operating system 1795.

[0378] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1746. In at least one embodiment, there are two programming models in which the graphics acceleration module 1746 is shared by multiple processes and partitions, namely time slice sharing and graphics directed sharing.

[0379] In at least one embodiment, in this model, the hypervisor 1796 owns the graphics acceleration module 1746 and makes its functions available to all operating systems 1795. In at least one embodiment, for the graphics acceleration module 1746 to support virtualization through the hypervisor 1796, the graphics acceleration module 1746 may have to comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., do not need to maintain state between jobs), or the graphics acceleration module 1746 must provide a context save and restore mechanism, (2) the graphics acceleration module 1746 guarantees that the job requests of the application are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1746 provides the ability to preempt job processing, and (3) when operating in a directed sharing programming model, it must be ensured that the graphics acceleration module 1746 is fair among processes.

[0380] In at least one embodiment, the application 1780 is required to use a graphics acceleration module type, a work descriptor (WD), a permission mask register (AMR) value, and a context save / restore area pointer (CSRP) for an operating system 1795 system call. In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1746 and can take the form of a graphics acceleration module 1746 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1746.

[0381] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. In at least one embodiment, if the implementation of accelerator integrated circuit 1736 (not shown) and graphics acceleration module 1746 does not support the user authority mask override register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in a hypervisor call. In at least one embodiment, the hypervisor 1796 may selectively apply the current authority mask override register (AMOR) value before placing the AMR in the process element 1783. In at least one embodiment, the CSRP is one of the registers 1745 that contains the effective address of a region in the effective address space 1782 of the application for the graphics acceleration module 1746 to save and restore the context state. In at least one embodiment, the pointer is optional if it is not necessary to save the state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0382] Upon receiving a system call, the operating system 1795 may verify that the application 1780 has been registered and granted permission to use the graphics acceleration module 1746. Then, in at least one embodiment, the operating system 1795 uses the information shown in Table 3 to call the hypervisor 1796.

[0383] Table 3 - Operating System to Hypervisor Call Parameters

[0384]

[0385]

[0386] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1796 verifies that the operating system 1795 has been registered and granted permission to use the graphics acceleration module 1746. Then, in at least one embodiment, the hypervisor 1796 places the process element 1783 in a linked list of process elements of the corresponding graphics acceleration module 1746 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0387] Table 4 - Process Element Information

[0388]

[0389] In at least one embodiment, the hypervisor initializes multiple accelerator integrated slice 1790 registers 1745.

[0390] As ​As shown, in at least one embodiment, a unified memory is used, which can be addressed via a common virtual memory address space for accessing the physical processor memories 1701(1)-1701(N) and the GPU memories 1720(1)-1720(N). In this implementation, operations executed on the GPUs 1710(1)-1710(N) utilize the same virtual / effective memory address space to access the processor memories 1701(1)-1701(M), and vice versa, thus simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 1701(1), a second portion is allocated to the second processor memory 1701(N), a third portion is allocated to the GPU memory 1720(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of the processor memories 1701 and the GPU memories 1720, allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0391] In at least one embodiment, the bias / coherency management circuits 1794A-1794E within one or more MMUs 1739A-1739E ensure cache coherency between one or more host processors (e.g., 1705) and the caches of the GPUs 1710, and implement a bias technique for physical memory indicating where certain types of data should be stored. In at least one embodiment, although multiple instances of the bias / coherency management circuits 1794A-1794E are shown ​ in, the bias / coherency circuits can be implemented within the MMU of one or more host processors 1705 and / or within the accelerator integrated circuit 1736.

[0392] One embodiment allows the GPU memory 1720 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology without suffering from the performance drawbacks associated with full-system cache coherence. In at least one embodiment, the ability of the GPU memory 1720 to be accessed as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the software of the host processor 1705 to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU memory 1720 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1710. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0393] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page-granularity structure (e.g., controlled at the granularity of memory pages), and this page-granularity structure includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, with or without a bias cache in the GPU 1710 (e.g., for caching frequently / most recently used entries of the bias table), the bias table may be implemented in the stolen memory ranges of one or more GPU memories 1720. Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

[0394] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memory 1720 is accessed, thereby causing the following operations. In at least one embodiment, a local request from the GPU 1710 that finds its page in the GPU bias is directly forwarded to the corresponding GPU memory 1720. In at least one embodiment, a local request from the GPU that finds its page in the host bias is forwarded to the processor 1705 (e.g., via the high-speed link described herein). In at least one embodiment, a request from the processor 1705 that finds the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request pointing to a GPU bias page can be forwarded to the GPU 1710. In at least one embodiment, if the GPU is not currently using a page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed by a software-based mechanism, a software mechanism assisted by hardware, or in a limited set of cases by a purely hardware-based mechanism.

[0395] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and perform a cache flush operation in the host in certain migrations. In at least one embodiment, the cache flush operation is used for migration from the host processor 1705 bias to the GPU bias, but not for the reverse migration.

[0396] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 1705. In at least one embodiment, to access these pages, the processor 1705 can request access from the GPU 1710, and the GPU 1710 may or may not immediately grant access. Thus, in at least one embodiment, to reduce communication between the processor 1705 and the GPU 1710, it is beneficial to ensure that GPU bias pages are pages required by the GPU rather than pages required by the host processor 1705, and vice versa.

[0397] One or more hardware structures 915 are used to implement one or more embodiments. Details regarding one or more hardware structures 915 may be provided herein in conjunction with ​ and / or ​ provide details regarding one or more hardware structures 915.

[0398] Figure 18An exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein are shown, which may be fabricated using one or more IP cores. In addition to those illustrated, in at least one embodiment, other logic and circuitry may also be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0399] Figure 18 is a block diagram of an exemplary system on a chip integrated circuit 1800 that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1800 includes peripheral or bus logic, which includes a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an 2 S / I 2 C controller 1840. In at least one embodiment, integrated circuit 1800 may include a display device 1845 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1850 and a mobile industry processor interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1870.

[0400] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, logic 915 may be in integrated circuit 1800 for inferring or predicting operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0401] In at least one embodiment, at least one component shown or described with respect to Figures 17A - 18 is used to implement the techniques and / or functions described in connection with Figures 1 - 8B In at least one embodiment, SoC 1800 performs one or more operations related to a neural network for inferring hybrid beamforming parameters and / or transmit power for use by a device to transmit in connection with Figure 1Describe a wireless signal as described elsewhere herein.

[0402] Figures 19A - 19B Illustrates an exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein, which may be fabricated using one or more IP cores. In addition to those illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0403] Figures 19A - 19B Is a block diagram illustrating an exemplary graphics processor used within a SoC in accordance with an embodiment described herein. Figure 19A Illustrates an exemplary graphics processor 1910 of a system-on-chip integrated circuit in accordance with at least one embodiment, which may be fabricated using one or more IP cores. Figure 19B Illustrates an additional exemplary graphics processor 1940 of a system-on-chip integrated circuit in accordance with at least one embodiment, which may be fabricated using one or more IP cores. In at least one embodiment, Figure 19A The graphics processor 1910 is a low-power graphics processor core. In at least one embodiment, Figure 19B The graphics processor 1940 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1910, 1940 may be Figure 18 A variant of the graphics processor 1810.

[0404] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A - 1915N (e.g., 1915A, 1915B, 1915C, 1915D to 1915N-1 and 1915N). In at least one embodiment, the graphics processor 1910 may execute different shader programs via separate logic such that the vertex processor 1905 is optimized to execute operations for vertex shader programs, while one or more fragment processors 1915A - 1915N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1905 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, one or more fragment processors 1915A - 1915N use the primitives and vertex data generated by the vertex processor 1905 to produce a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 1915A - 1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0405] In at least one embodiment, the graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A - 1920B, one or more caches 1925A - 1925B, and one or more circuit interconnects 1930A - 1930B. In at least one embodiment, one or more of the MMUs 1920A - 1920B provide virtual - to - physical address mapping for the graphics processor 1910 (including for the vertex processor 1905 and / or the fragment processors 1915A - 1915N), and in addition to vertex or image / texture data stored in one or more of the caches 1925A - 1925B, it can also reference vertex or image / texture data stored in memory. In at least one embodiment, one or more of the MMUs 1920A - 1920B can be synchronized with other MMUs within the system, including one or more MMUs associated with one or more of the application processors 1805, image processors 1815, and / or video processors 1820 of Figure 18 such that each of the processors 1805 - 1820 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more of the circuit interconnects 1930A - 1930B enable the graphics processor 1910 to interface with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0406] In at least one embodiment, the graphics processor 1940 includes one or more shader cores 1955A - 1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F to 1955N - 1, and 1955N) as shown in Figure 19B which provides a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter - core task manager 1945 which acts as a thread dispatcher for dispatching execution threads to one or more of the shader cores 1955A - 1955N and a tiling unit 1958 to accelerate the tiling operations for tile - based rendering, where the rendering operation of the scene is subdivided in the image space, e.g., to take advantage of local spatial coherence within the scene or to optimize the use of internal caches.

[0407] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described in connection with Figure 9A and / or Figure 9BProvide details regarding Logic 915. In at least one embodiment, Logic 915 can be used in Graphics Processor 1910 and / or 1940 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0408] In at least one embodiment, at least one component shown or described is used to implement the techniques and / or functions associated with Figures 19A - 19B described. In at least one embodiment, Graphics Processor 1910 performs one or more operations related to a neural network for inferring hybrid beamforming parameters and / or transmit power for use by a device to transmit wireless signals described in Figures 1 - 8B and elsewhere herein. Figure 1 described and as

[0409] Figures 20A - 20B Shows additional exemplary graphics processor logic according to embodiments described herein. In at least one embodiment, the components shown and described in Figures 20A - 20B are integrated into a single system, such as a graphics processing unit (GPU), a system-on-chip (SoC), or another type of processor. In at least one embodiment, Figures 20A - 20B shown includes Graphics Core 2000 that can be included within Graphics Processor 1810 of Figure 20A and, in at least one embodiment, can be Unified Shader Core 1955A - 1955N as shown in Figure 18 shown. Figure 19B Figure 20B Shows a highly parallel general-purpose graphics processing unit (“GPGPU,” which may also be referred to as a “graphics processing unit”) 2030 suitable for deployment on a multi-chip module in at least one embodiment. In at least one embodiment, Graphics Processing Unit 2030 is a GPGPU that includes a graphics processor. In at least one embodiment, Integrated Circuit 1800 includes Graphics Core 2000, e.g., for forming an integrated circuit and / or forming an SoC, where such integrated circuit and / or such SoC performs the operations described herein.

[0410] ​In at least one embodiment, the graphics core 2000 includes a shared instruction cache 2002, texture units 2018, and cache / shared memory 2020 (e.g., including L1, L2, L3, last-level cache, or other caches), which are shared for execution resources within the graphics core 2000. In at least one embodiment, the graphics core 2000 may include multiple slices 2001A - 2001N or partitions per core, and the graphics processor may include multiple instances of the graphics core 2000. In at least one embodiment, each of the slices 2001A - 2001N refers to the graphics core 2000. In at least one embodiment, the slices 2001A - 2001N have sub-slices that are part of the slices 2001A - 2001N. In at least one embodiment, the slices 2001A - 2001N are independent of or dependent on other slices. In at least one embodiment, the slices 2001A - 2001N may include support logic, which includes local instruction caches 2004A - 2004N, thread schedulers (sequencers) 2006A - 2006N, thread dispatchers 2008A - 2008N, and a set of registers 2010A - 2010N. In at least one embodiment, the slices 2001A - 2001N may include a set of additional functional units (AFU 2012A - 2012N), floating-point units (FPU 2014A - 2014N), integer arithmetic logic units (ALU 2016A - 2016N), address calculation units (ACU 2013A - 2013N), double-precision floating-point units (DPFPU 2015A - 2015N), and matrix processing units (MPU 2017A - 2017N). In at least one embodiment, the MPU 2017A - 2017N is referred to as a matrix engine.

[0411] In at least one embodiment, each of slices 2001A - 2001N includes one or more engines for floating - point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large - data - set workloads. In at least one embodiment, one or more of slices 2001A - 2001N includes one or more vector engines for computing vectors (e.g., performing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16 - bit floating - point (also known as "FP16"), 32 - bit floating - point (also known as "FP32"), or 64 - bit floating - point (also known as "FP64"). In at least one embodiment, one or more of slices 2001A - 2001N includes 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are exposed through matrix expansion. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, e.g., 16 cores and ray - tracing units of a processor or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of a processor. In at least one embodiment, the graphics core 2000 includes one or more matrix engines for computing matrix operations, e.g., when computing tensor operations.

[0412] In at least one embodiment, one or more of slices 2001A - 2001N includes one or more ray - tracing units for computing ray - tracing operations (e.g., 16 ray - tracing units per slice in slices 2001A - 2001N). In at least one embodiment, the ray - tracing units compute ray traversal, triangle intersection, bounding - box intersection, or other ray - tracing operations.

[0413] In at least one embodiment, one or more of slices 2001A - 2001N includes a media slice that encodes, decodes, and / or transcodes data; scales and / or converts the format of data; and / or performs video - quality operations on video data.

[0414] In at least one embodiment, one or more slices 2001A - 2001N are linked to an L2 cache and a memory structure, a link connector, a high - bandwidth memory (HBM) (e.g., HBM2e, HBM3) stack, and a media engine. In at least one embodiment, one or more slices 2001A - 2001N include a plurality of cores (e.g., 16 cores) and a plurality of ray - tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 2001A - 2001N have one or more L1 caches. In at least one embodiment, one or more slices 2001A - 2001N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data corresponding to instructions, for example; one or more samplers for sampling data; one or more ray - tracing units for performing ray - tracing operations; one or more geometry units for performing operations in a geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector - graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical - depth buffers (Hiz) for buffering data; and / or one or more pixel back - ends. In at least one embodiment, slices 2001A - 2001N include a memory structure, such as an L2 cache.

[0415] In at least one embodiment, FPUs 2014A - 2014N can perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while DPFPU 2015A - 2015N performs double - precision (64 - bit) floating - point operations. In at least one embodiment, ALUs 2016A - 2016N can perform variable - precision integer operations with 8 - bit, 16 - bit, and 32 - bit precision and can be configured for mixed - precision operations. In at least one embodiment, MPUs 2017A - 2017N can also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, MPUs 2017A - 2017N can perform various matrix operations to accelerate machine - learning application frameworks, including enabling support for accelerated general matrix - matrix multiplication (GEMM). In at least one embodiment, AFUs 2012A - 2012N can perform additional logical operations not supported by a floating - point unit or an integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0416] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Figure 9A and / or Figure 9B which provide details regarding Logic 915. In at least one embodiment, Logic 915 may be used in Graphics Core 2000 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0417] In at least one embodiment, Graphics Core 2000 includes an interconnect and link structure sub-layer attached to a switch and a GPU-GPU bridge, which enables multiple graphics processors 2000 (e.g., 8) to be interconnected with each other without bonding through the load / store unit (LSU), data transfer unit, and synchronization semantics across multiple graphics processors 2000. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0418] In at least one embodiment, Graphics Core 2000 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where an individual die may be connected to the interconnect (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)). In at least one embodiment, Graphics Core 2000 includes a compute tile, a memory tile (e.g., where the memory tile may be exclusively accessed by different tiles or different chip sets such as Rambo tiles), a base tile, a foundation tile, an HMB tile, a link tile, and an EMIB tile, where all tiles are encapsulated together in Graphics Core 2000 as part of the GPU. In at least one embodiment, Graphics Core 2000 may include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, the compute tile may have 8 Graphics Cores 2000, an L1 cache; and the foundation tile may have a host interface to PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, and 8 ports with an embedded switch. In at least one embodiment, the tiles are connected by face-to-face (F2F) chip-on-chip bonding with fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, Graphics Core 2000 includes a memory structure (which includes memory) and is a tile that can be accessed by multiple tiles. In at least one embo...

Claims

1. A processor, comprising: One or more circuits for generating one or more hybrid beamforming parameters using one or more neural networks to be used in transmitting one or more wireless signals.

2. The processor according to claim 1, wherein: The one or more circuits are configured to use the one or more neural networks to generate the one or more hybrid beamforming parameters by jointly inferring one or more analog beamforming parameters and one or more digital beamforming parameters.

3. The processor according to claim 1, wherein: Generating the one or more hybrid beamforming parameters is based at least in part on optimizing one or more signal characteristics of the one or more wireless signals to be transmitted.

4. The processor according to claim 1, wherein: The one or more hybrid beamforming parameters are to be used to transmit the one or more wireless signals, which exhibit one or more signal-to-noise ratios (SNRs) above a threshold at a base station of a fifth generation new radio 5G NR network.

5. The processor according to claim 1, wherein: The one or more hybrid beamforming parameters include one or more complex values ​​to be used to transmit a wireless baseband signal.

6. The processor of claim 1, wherein: The one or more circuits are configured to generate, using the one or more neural networks, the one or more hybrid beamforming parameters including a representation of one or more phase shifters using one or more one-hot vectors.

7. The processor according to claim 1, wherein: The one or more hybrid beamforming parameters are to be used to modify the operation of one or more analog beamforming components and one or more digital beamforming components of a hybrid beamforming system for transmitting the one or more wireless signals.

8. A system comprising: One or more processors for generating one or more hybrid beamforming parameters using one or more neural networks to be used in transmitting one or more wireless signals.

9. The system according to claim 8, wherein: The one or more processors are configured to generate analog beamforming parameters and digital beamforming parameters in a single inference pass using the one or more neural networks.

10. The system according to claim 8, wherein: Generating the one or more hybrid beamforming parameters is based at least in part on optimizing one or more signal-to-noise ratios (SNRs) of the one or more wireless signals to be transmitted.

11. The system according to claim 8, wherein: The one or more wireless signals will be transmitted by a base station of a fifth generation new radio 5G NR network.

12. The system according to claim 8, wherein: The one or more hybrid beamforming parameters satisfy a unit modulus constraint.

13. The system according to claim 8, wherein: The one or more hybrid beamforming parameters are based at least in part on representing one or more phase shifters with one or more one-hot vectors.

14. The system according to claim 8, wherein: The one or more processors are configured to output the one or more hybrid beamforming parameters as a single vector using the one or more neural networks.

15. A method comprising: One or more neural networks are used to generate one or more hybrid beamforming parameters to be used in transmitting one or more wireless signals.

16. The method according to claim 15, wherein: The one or more neural networks are used to generate the one or more hybrid beamforming parameters with a single forward pass.

17. The method according to claim 15, wherein: Generating the one or more hybrid beamforming parameters is based at least in part on a signal-to-noise ratio formula that uses analog beamforming parameters and digital beamforming parameters as inputs.

18. The method according to claim 15, wherein: Training the one or more neural networks is based at least in part on maximizing a reward function of a reinforcement learning neural network training process.

19. The method according to claim 15, wherein: The one or more hybrid beamforming parameters are output as a single vector to be applied to a uniform linear array of sensors.

20. The method according to claim 15, wherein: The one or more hybrid beamforming parameters include a representation of one or more phase angles using one or more one-hot vectors.

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