Signal processing techniques

Abstract

Devices, systems, and techniques that use a neural network to jointly derive signal parameters for controlling and transmitting wireless signals. In at least one embodiment, one or more neural networks are trained using reinforcement learning techniques to derive hybrid beamforming parameters used by one or more devices for transmitting wireless signals.

Description

CROSS REFERENCE TO RELATED APPLICATIONSThis application also includes for all purposes the complete disclosure of co-filed U.S. Patent Application No. entitled "SIGNAL PROCESSING TECHNIQUES USING SIGNAL INFORMATION" (Attorney docket No. 0112912-746US 0).TECHNICAL FIELDAt least one embodiment relates to processing resources used to perform and facilitate wireless communication. For example, at least one embodiment relates to processors or computer systems that use neural networks to process signals for transmission.BACKGROUNDProcessing signals in wireless communication may require significant memory, time, or computational resources, which limits the effectiveness of each signal. For example, some signal processing techniques may generate suboptimal signals due to computational constraints. Therefore, signal processing techniques in wireless communication can be improved.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a block diagram of a neural network training system that uses deep reinforcement learning techniques, according to at least one embodiment; FIG. 2 shows a block diagram of a system used to train a neural network to derive hybrid beamforming parameters, according to at least one embodiment; FIG. 3 shows a block diagram of a system used to train a neural network to derive hybrid beamforming parameters and transmit powers, according to at least one embodiment; FIG. 4 shows a block diagram of a system for training a neural network using rewards, according to at least one embodiment; FIG. 5 shows a block diagram of a system for training a neural network using rewards, according to at least one embodiment; FIG. 6 illustrates a method for training a neural network to derive hybrid beamforming signal parameters, according to at least one embodiment; FIG. 7 shows a block diagram of a process for training a neural network to derive hybrid beamforming parameters, according to at least one embodiment; FIG. 8A shows a block diagram of a driver and / or runtime that includes APIs used to derive hybrid beamforming parameters, according to at least one embodiment; FIG. 8B shows a block diagram of a processor and modules used to train a neural network to derive hybrid beamforming parameters, according to at least one embodiment; FIG. 9A illustrates the logic according to at least one embodiment; FIG. 9B illustrates the logic according to at least one embodiment; FIG. 10 illustrates training and deployment of a neural network, according to at least one embodiment; FIG. 11 shows an example data center system according to at least one embodiment; FIG. 12A shows an example of an autonomous vehicle, according to at least one embodiment; FIG. 12B shows an example of camera positions and fields of view for the autonomous vehicle of FIG. 12A, according to at least one embodiment; FIG. 12C is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 12A, according to at least one embodiment; FIG. 12D is a diagram illustrating a system for communicating between one or more cloud-based servers and the autonomous vehicle of FIG. 12A, according to at least one embodiment; FIG. 13 is a block diagram illustrating a computer system according to at least one embodiment; FIG. 14 is a block diagram illustrating a computer system according to at least one embodiment; FIG. 15 illustrates a computer system according to at least one embodiment; FIG. 16 illustrates a computer system according to at least one embodiment; FIG. 17A illustrates a computer system according to at least one embodiment; FIG. 17B illustrates a computer system according to at least one embodiment; FIG. 17C illustrates a computer system according to at least one embodiment; FIG. 17D illustrates a computer system according to at least one embodiment; FIGS. 17E and 17F show a common programming model according to at least one embodiment; FIG. 18 illustrates example integrated circuits and associated graphics processors, in accordance with at least one embodiment; FIGS. 19A-19B show example integrated circuits and associated graphics processors, according to at least one embodiment; FIGS. 20A-20B show additional example graphics processor logic, according to at least one embodiment; FIG. 21 illustrates a computer system according to at least one embodiment; FIG. 22A illustrates a parallel processor according to at least one embodiment; FIG. 22B illustrates a partition unit according to at least one embodiment; FIG. 22C illustrates a processing cluster according to at least one embodiment; FIG. 22D illustrates a graphics multiprocessor according to at least one embodiment; FIG. 23 illustrates a multi-graphics processing system (GPU) according to at least one embodiment; FIG. 24 illustrates a graphics processor according to at least one embodiment; FIG. 25 is a block diagram illustrating a processor microarchitecture for a processor, according to at least one embodiment; FIG. 26 illustrates a deep learning application processor according to at least one embodiment; FIG. 27 is a block diagram illustrating an example neuromorphic processor according to at least one embodiment; FIG. 28 illustrates at least portions of a graphics processor, in accordance with one or more embodiments; FIG. 29 illustrates at least portions of a graphics processor according to one or more embodiments; FIG. 30 illustrates at least portions of a graphics processor according to one or more embodiments; FIG. 31 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment; FIG. 32 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment; FIGS. 33A-33B illustrate thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment; FIG. 34 illustrates a parallel processing unit ("PPU") according to at least one embodiment; FIG. 35 illustrates a general processing cluster ("GPC") according to at least one embodiment; FIG. 36 illustrates a memory partition unit of a parallel processing unit ("PPU") according to at least one embodiment; FIG. 37 illustrates a streaming multiprocessor according to at least one embodiment; FIG. 38 is an example dataflow diagram for an advanced computer pipeline, in accordance with at least one embodiment; FIG. 39 is a system diagram for an example system for training, adjusting, instantiating, and providing machine learning models in an advanced computer pipeline, in accordance with at least one embodiment; FIG. 40 includes an example diagram of an advanced computer pipeline 3910A for processing image data, in accordance with at least one embodiment; FIG. 41A includes an example dataflow diagram of a virtual instrument supporting an ultrasound device, in accordance with at least one embodiment; FIG. 41B includes an example dataflow diagram of a virtual instrument supporting a CT scanner, in accordance with at least one embodiment; FIG. 42A illustrates a dataflow diagram for a process for training a machine learning model in accordance with at least one embodiment; FIG. 42B illustrates an example representation of a client-server architecture for enhancing annotation tools with pre-trained annotation models, in accordance with at least one embodiment; and FIG. 43 illustrates components of a system for accessing a large language model, in accordance with at least one embodiment.DETAILED DESCRIPTIONIn the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concepts may be practiced without one or more of these specific details, and that two or more aspects of one or more of the embodiments described herein may be combined.In at least one embodiment, a neural network derives hybrid beamforming parameters and / or transmit powers to be used by devices to transmit wireless signals based on signal data input to that neural network. In at least one embodiment, a neural network is trained using reinforcement learning techniques described further below. In at least one embodiment, a neural network generates hybrid beamforming parameters by jointly deriving analog beamforming parameters and digital beamforming parameters. In at least one embodiment, a neural network jointly derives hybrid beamforming parameters, which refers to analog beamforming parameters and digital beamforming parameters being derived hybrid to each other during a single forward pass, wherein input data is processed by neural network from an input layer to an output layer during training of that neural network. In at least one embodiment, a single forward pass is referred to as a single inference pass or single inference run. In at least one embodiment, a trained neural network jointly derives analog and digital signal parameters used as part of a hybrid beamforming process. In at least one embodiment, derivation of hybrid beamforming parameters is used to optimize signal-to-noise ratio (SNR) of a transmitted signal. In at least one embodiment, optimizing an SNR means increasing this SNR.In at least one embodiment, hybrid beamforming parameters include baseband weights used in digital beamforming and radio frequency (RF) weights used in analog beamforming. In at least one embodiment, baseband and RF weights are values applied to a signal to modify it. In at least one embodiment, baseband weights are complex values, which may also be referred to as complex numbers. In at least one embodiment, baseband weights are applied to a signal to change its magnitude and phase. In at least one embodiment, RF weights are applied to a signal to change phase of signal. In at least one embodiment, phase of a signal is a position of that signal at a particular time in a waveform cycle and is given in degrees (0-360) or degrees of curvature (0-2π). In at least one embodiment, the phase of a signal is referred to as a phase angle.In at least one embodiment, hybrid beamforming parameters are phase values such as phase angles and phase shifts. In at least one embodiment, hybrid beamforming parameters are phase shifts, i.e., values expressed in degrees or radians, that indicate how to modify a phase of a signal. In at least one embodiment, hybrid beamforming parameters are power values, gain values, amplitude values, amplitude values, or a combination thereof. In at least one embodiment, hybrid beamforming parameters are considered coefficients. In at least one embodiment, hybrid beamforming parameters include carrier frequency information. In at least one embodiment, hybrid beamforming parameters include indications of particular signals, devices, cells, or a combination thereof to which hybrid beamforming parameters are to be applied.In at least one embodiment, a neural network identifies a beam direction and / or transmit power to be used by a device to transmit a signal based on information about another signal transmitted or received by another device. In at least one embodiment, identification of a beam direction and / or transmit power based on information about another signal is used to optimize a signal-to-interference-to-noise ratio (SINR) of all signals transmitted in a wireless network, which in turn increases overall data throughput of that network. In at least one embodiment, optimizing a SINR means increasing that SINR.In at least one embodiment, hybrid beamformers are a combination of hardware, firmware, and software that modify signals to be transmitted in a particular direction using multiple antennas as well as constructive and destructive interference. In at least one embodiment, hybrid beamformers use a combination of analog and digital beamformer components and techniques. In at least one embodiment, a beam is a directional signal transmitted by one or more antennas.In at least one embodiment, jointly deriving analog and digital beamforming parameters refers to training a neural network, which includes deriving one or more analog beamforming parameters related to one or more digital beamforming parameters and / or vice versa.In at least one embodiment, a neural network derives hybrid beamforming parameters and / or transmit powers to be used by devices in a wireless network, such as a 5G network. In at least one embodiment, equipment used in a wireless network includes, but is not limited to, beamformers, user equipment (UE), antenna groups, and base stations. In at least one embodiment, transmit powers are referred to as transmit power parameters or power parameters. In at least one embodiment, a transmit power refers to an output of a transmit power amplifier. In at least one embodiment, increasing transmit power of a signal increases the amplitude of that signal.In at least one embodiment, wireless signals are referred to as radio frequency (RF) signals. In at least one embodiment, directed wireless signals are referred to as beams. In at least one embodiment, wireless signals are referred to as radio signals or wireless radio signals. In at least one embodiment, a signal is a wireless signal. In at least one embodiment, a signal is a wired signal. In at least one embodiment, a signal refers to any aspect of a communication signal, including data transmitted by that signal. In at least one embodiment, different wireless communication devices convert a wired signal to a wireless signal and / or vice versa.In at least one embodiment, training a neural network to perform hybrid beamforming described herein provides a larger range of possible directions into which signals may be directed while meeting signal processing latency requirements. In at least one embodiment, a neural network is trained to derive hybrid beamforming parameters and / or transmit powers to increase a sum rate of a portion of wireless network. In at least one embodiment, sum rate refers to total data transmission rate or throughput of all signals in at least a portion or entirety of a wireless network. In at least one embodiment, a portion of a wireless network refers to a cell. In at least one embodiment, a cell refers to a geographic area covered by a base station. In at least one embodiment, a base station is a receiver and transmitter of wireless signals and may serve as a node for wireless devices, a connection to a wired network, a connection to a different wireless network, or a combination thereof.FIG. 1 illustrates a training system for a neural network 100 according to at least one embodiment. In at least one embodiment, neural network training system 100 trains one or more neural networks to derive parameters used to perform hybrid beamforming and / or to derive transmit powers used by wireless signal transmission devices as part of a communication network. In at least one embodiment, one or more aspects of one or more embodiments described herein in connection with FIG. 1 are combined with one or more aspects of one or more embodiments described herein, including those described at least in connection with FIGS. 2-8B. In at least one embodiment, one or more processors perform one or more operations used by neural network training system 100. In at least one embodiment, one or more processors that perform one or more operations used by neural network training system 100 are any processor or combination of processors described herein, including processor(s) 822 described in connection with FIG. 8B, graphics processor 1910 described in connection with FIG. 19A, and parallel processing unit ("PPU") 3400 described in connection with FIG. 34. In at least one embodiment, processor(s) 822 performs (perform) operations used by deep reinforcement learning agent system 104, such as deriving signal parameters using neural network module 114 and calculating a reward function using reward module 122.In at least one embodiment, neural network training system 100 includes input signal(s) 102, deep reinforcement learning agent module 104, actuator module 106, environment module 108, signal preprocessing module 112, neural network module 114, signal parameter module 116, signal characteristic computing module 118, channel state information (CSI) module 120, and reward module 122.In at least one embodiment, terms such as "system" and "module", as well as nominally-bound verbs (e.g., compilers and / or other terms) as used in any implementation described herein refer to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide functionality described herein, unless context dictates otherwise, or expressly stated to the contrary. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions. In at least one embodiment, hardware, alone or in any combination, includes a hardwired circuit, a programmable circuit, a state machine circuit, a fixed function circuit, an execution unit circuit, and / or firmware storing instructions executed by a programmable circuit. In at least one embodiment, modules may be embodied jointly or individually as circuits that are part of a larger system, such as an integrated circuit (IC), a system-on-a-chip (SoC), and so forth.In at least one embodiment, neural network training system 100 uses one or more techniques of reinforcement learning to train a neural network to generate signal parameters used in hybrid beamforming. In at least one embodiment, reinforcement learning is referred to as a type of neural network training, neural network learning, or machine learning. In at least one embodiment, neural network training system 100 uses one or more techniques of reinforcement learning to train a neural network to modify one or more transmit powers of one or more wireless signals. In at least one embodiment, reinforcement learning refers to one or more machine learning operations that include an autonomous agent, further described herein, that generates modifications to data and / or functions to maximize a reward function within a given set of constraints. In at least one embodiment, maximizing a reward function is used to update parameters, such as weights, of a neural network. In at least one embodiment, deep reinforcement learning is referred to as reinforcement learning. In at least one embodiment, each module or combination of modules that perform one or more operations of reinforcement learning is referred to as a reinforcement learning system.In at least one embodiment, input signal(s) 102 comprise one or more wireless communication network signals. In at least one embodiment, input signal(s) 102 is a set of signal parameters used to train a neural network. In at least one embodiment, a set of signal parameters includes data representing frequency values, phase angle values, phase shift values, gain values, transmit power values, or a combination thereof. In at least one embodiment, input signal(s) 102 are simulated signals determined by software for simulating a wireless communication system. In at least one embodiment, input signal(s) 102 are simulated signals that include sets of signal parameters and are not actual signals transmitted by a transmitter. In at least one embodiment, input signal(s) 102 are wireless signals generated by wireless signal generators. In at least one embodiment, input signal(s) 102 are signals of any wireless communication network operating under a current or future protocol or standard, such as fifth generation new radio (5G or 5G NR), sixth generation wireless (6G), IEEE 802, Wi-Fi 7. In at least one embodiment, wireless signals are signals of any wireless communication network operating according to a current or future protocol or standard, for example 5G or 5G NR, 6G, IEEE 802, Wi-Fi 7. In at least one embodiment, wireless signals are wireless signals transmitted and / or received from a base station. In at least one embodiment, a wireless communication network refers to any hardware, firmware, software, architecture, signals, methods, or any combination thereof used in 5G wireless communication.In at least one embodiment, a wireless communication network is referred to as a wireless network or network. In at least one embodiment, input signal or signals 102 are digital signals or a representation thereof. In at least one embodiment, input signal(s) 102 are analog signals or a representation thereof. In at least one embodiment, data includes discrete and / or continuous numerical values. In at least one embodiment, input signal(s) 102 is(are) a set of data representing(s) parameters of a signal, such as magnitude and phase. In at least one embodiment, data includes imaginary numbers and / or real numbers. In at least one embodiment, data includes complex numbers including an imaginary part and a real part. In at least one embodiment, the rate at which data transmitted from any signal is transmitted or received per unit time is referred to as a data transmission rate. In at least one embodiment, the rate at which desired data is transmitted or received per unit time is referred to as effective data rate or throughput. A rate at which all data is transmitted in a part or an entire wireless network is referred to as a sum rate. In at least one embodiment, sum rate refers to total data throughput in a portion or entirety of a wireless network. In at least one embodiment, two or more signals of input signal / signals 102 use different bandwidths within different frequency ranges.In at least one embodiment, deep reinforcement learning agent module 104 uses one or more modules, such as actuator module 106, signal characteristic computation module 118, and reward module 122, to maximize a signal characteristic that includes an input signal and restrictions included in environment module 108. In at least one embodiment, deep reinforcement learning agent module 104 attempts to maximize a signal-to-noise ratio (SNR) of a modified input signal with respect to environmental conditions in the form of channel state information (CSI). In at least one embodiment, deep reinforcement learning agent module 104 attempts to increase SNR of a modified input signal to achieve or exceed a threshold or target value. In at least one embodiment, CSI refers to all characteristics of a communication link between a transmitter and a receiver.In at least one embodiment, deep reinforcement learning agent module 104 performs one or more operations used in reinforcement learning. In at least one embodiment, deep reinforcement learning module 104 includes other modules for performing operations used in reinforcement learning. In at least one embodiment, deep reinforcement learning agent module 104 acts as an agent within a deep reinforcement learning system. In at least one embodiment, an agent is a combination of hardware, firmware, or software that attempts to maximize a reward, as described below. In at least one embodiment, deep reinforcement learning agent module 104 performs data transfers between modules, as depicted by arrows in FIG. 1, including transfer of data output from signal preprocessing module 112 to actuator module 106, where actuator module 106 receives this data as input data. In at least one embodiment, deep reinforcement learning agent module 104 performs data transfers between any two modules depicted in FIG. 1. In at least one embodiment, each module of deep reinforcement learning agent module 104 is communicatively coupled to one or more other modules of deep reinforcement learning agent module 104. In at least one embodiment, one or more modules of deep reinforcement learning agent module 104 are implemented on another module, including reward module 122 implemented on environment module 108, as depicted in FIG. 1. In at least one embodiment, a module implemented on another module refers to hardware, firmware, software, or a combination thereof of a module installed on hardware components, such as a processor and / or memory, of another module. In at least one embodiment, deep reinforcement learning agent module 104 performs one or more operations of other types of neural network training, such as supervised learning, semi-supervised learning, unsupervised learning, or a combination thereof.In at least one embodiment, deep reinforcement learning agent module 104 is referred to as an autonomous agent or an agent. In at least one embodiment, an agent is one or more modules that include algorithms and / or functions that effect modifications to data, such as modifications to wireless signal parameters based on data contained and / or generated by environment module 108. In at least one embodiment, deep reinforcement learning agent module 104 performs modifications to signal parameters by using a neural network included in actuator module 106.In at least one embodiment, actuator module 106 performs data on signal parameters such as hybrid beamforming parameters. In at least one embodiment, one or more data changes made by actuator module 106 are referred to as one or more actions. In at least one embodiment, an action conceptually refers to a decision made by actor module 106 to change a state. In at least one embodiment, a state includes current values of signal parameters to be input to a neural network. In at least one embodiment, a state includes information about an action previously performed by actuator module 106, further described herein. In at least one embodiment, a state includes an SNR for each signal used by a UE. In at least one embodiment, a signal used by a UE refers to a signal received from a UE. In at least one embodiment, a signal used by a UE refers to a signal transmitted by a UE. In at least one embodiment, a state of deep reinforcement learning agent system 104 includes signal parameters output by signal preprocessing module 112. In at least one embodiment, a state includes channel state information provided by environment module 108. In at least one embodiment, a state includes signal parameters previously generated by actuator module 106. In at least one embodiment, an actuator is conceptually used in an actuator critical type of reinforcement learning. In at least one embodiment, an actuator conceptually decides which action to take with respect to a current state. In at least one embodiment, an actuator correlates states with previously performed actions by obtaining and / or otherwise rewarding a reward based on those actions. In at least one embodiment, a reward is an integer. In at least one embodiment, actuator module 106 uses a neural network, such as a neural network, that includes neural network module 114 to derive actions that should be taken. In at least one embodiment, an action is a set of one or more new signal parameters derived from a neural network. In at least one embodiment, at least conceptually, new signal parameters derived from a neural network are considered an action because they change an input signal parameter to a new parameter. In at least one embodiment, actuator module 106 uses a separate neural network to update weights of neural network module 114. In at least one embodiment, an input to a neural network of actuator module 106 is data representing a current state. In at least one embodiment, a neural network output of actuator module 106 is considered a modified state. In at least one embodiment, an output of a neural network of actuator module 106 is one or more indications of actions required to change a state.In at least one embodiment, actuator module 106 performs operations to modify signal parameters of one or more wireless signals to maximize an SNR and / or SINR of these one or more signals as part of a hybrid beamforming process and / or a transmit power modification process. In at least one embodiment, actuator module 106 performs operations to modify signal parameters of one or more wireless signals to cause an SNR and / or SINR of these one or more signals to meet or exceed a threshold. In at least one embodiment, actuator module 106 performs operations to modify signal parameters based on an expected SNR and / or SINR of wireless signals in transmission. In at least one embodiment, an expected SNR and / or SINR is generated by performing mathematical functions using simulated signal parameters. In at least one embodiment, signal parameters are output by signal preprocessing module 112 in actuator module 106. In at least one embodiment, a state includes signal parameters output by signal preprocessing module 112 and / or signal parameters previously output by signal preprocessing module 112.In at least one embodiment, environment module 108 includes parameters related to how a signal is processed and / or transmitted. In at least one embodiment, environment module 108 includes multiple modules that generate and / or otherwise output data used by actuator module 106 to derive measures to take to maximize a signal characteristic such as SNR and / or SINR. In at least one embodiment, environment module 108 includes multiple modules that generate and / or otherwise output data used by actuator module 106 to update neural network weights and / or functions. In at least one embodiment, neural network weights and / or functions are considered part of a strategy that is updated during a reinforcement learning process. In at least one embodiment, actuator module 106 updates a reward maximizing strategy, which is described further herein. In at least one embodiment, environment module 108 includes parameters related to channel state information (CSI). In at least one embodiment, environment module 108 includes parameters related to channel impulse response (CIR) and channel frequency response (CFR). In at least one embodiment, CSI includes information related to scattering, fading, power decay, delay, amplitude, phase, or a combination thereof related to wireless network devices and / or signals.In at least one embodiment, signal preprocessing module 112 processes input signal(s) 102 to be suitable as inputs to a neural network. In at least one embodiment, signal preprocessing module 112 performs a sampling of input signal(s) 102 to convert analog signals to digital signals. In at least one embodiment, signal preprocessing module 112 performs filtering of input signal(s) 102 to remove unwanted aspects such as noise, interference, distortions, or a combination thereof. In at least one embodiment, signal preprocessing module 112 modifies data of input signal(s) 102 to be tensors of particular dimensions so that a neural network can process these tensors as input data. In at least one embodiment, scalars and vectors are types of tensors.In at least one embodiment, neural network module 114 includes one or more neural networks. In at least one embodiment, neural network module 114 derives signal parameters used in hybrid beamforming. In at least one embodiment, neural network module 114 derives transmit powers used for signal transmission. In at least one embodiment, a processor sends signal parameters derived from neural network module 114 to signal parameter module 116. In at least one embodiment, a neural network includes any neural network discussed herein, including those discussed in connection with FIGS. 9 and 10C. In at least one embodiment, a neural network includes processors, data, functions, and parameters of neural network used to draw conclusions based on input data. In at least one embodiment, neural network parameters include neural network weights. In at least one embodiment, neural network parameters are regularly modified based on a reward generated during a training process for a deep learning neural network. In at least one embodiment, neural network parameters are parameters used by actuator module 104 to determine neural network performance characteristics, such as accuracy. In at least one embodiment, neural network parameters include parameters indicative of neural network learning rates, local neural network iterations, neural network aggregation weights, a number of neural network neurons, or a combination thereof.In at least one embodiment, a neural network is a recurrent neural network (RNN), a convolutional neural network (CNN), a generative adversarial network (GAN), a transformer, a graphical neural network (GNN), or a combination thereof. In at least one embodiment, neural network is a CNN, such as a U-net with a 5-level encoder-decoder network architecture with residual blocks at each level. In at least one embodiment, a residue block is a stack of layers of a neural network in which output of one layer is added to another layer deeper in that residue block. In at least one embodiment, a layer is a structure or network topology that includes nodes corresponding to a feature extracted from a dataset. In at least one embodiment, an encoder-decoder network includes two recurrent neural networks, one for encoding input data and another for decoding encoded data. In at least one embodiment, a recurrent network is a neural network that uses sequential data. In at least one embodiment, a training system uses training data to train an untrained neural network to generate a trained neural network using systems and methods such as those described herein. In at least one embodiment, an untrained neural network is a neural network that has partial training and for which further training is to occur. In at least one embodiment, training data is a training data set.In at least one embodiment, signal parameter module 116 includes a memory that stores parameters derived from neural network module 114. In at least one embodiment, parameters include values such as amplitude, phase angle, base bandwidth, number of radio frequency chains (RF), number of resource elements (REs), number of component carriers, transmit power, or a combination thereof, all of which are described in more detail in connection with FIG. 2. In at least one embodiment, signal parameter module 116 stores at least some inferred signal parameters based on prior actions of actuator module 106. In at least one embodiment, signal parameter module 116 performs operations such as F.normalize(), Argmax, P max F.sigmoid(), as described further in connection with FIGS. 2 and 3. In at least one embodiment, signal parameter module 116 converts phase angles to one-hot vectors. In at least one embodiment, one-hot coding is a data format representing integer values as a vector, a value of that vector being binary coded and indicating an integer value. In at least one embodiment, a vector used in one-hot coding is referred to as a one-hot vector. In at least one embodiment, one-hot coding is used to meet a unit module condition. In at least one embodiment, a unit module constraint is used with respect to analog components of a hybrid beamformer system to prevent magnitude of a complex number representing a phase angle from being greater than 1.In at least one embodiment, signal characteristic calculation module 118 calculates a signal characteristic using signal parameters output by neural network module 114 and modified by signal parameter module 116. In at least one embodiment, signal characteristic calculation module 118 calculates a signal characteristic using signal parameters and channel state information output from channel state information module 120. In at least one embodiment, a signal characteristic refers to any property or quality of one or more signals. In at least one embodiment, a signal characteristic refers to SNR, SINR, sum rate, or a combination thereof. In at least one embodiment, signal characteristic calculation module 118 calculates one or more signal characteristics of input signals 102 that have been at least conceptually modified using signal parameters derived from a neural network and CSI. In at least one embodiment, actuator module 106 at least conceptually modifies parameters of a signal, such as input signal(s) 102, in attempting signal characteristic calculation module 118 to output a signal characteristic that is maximized or above a threshold, as indicated by reward module 122. In at least one embodiment, signal processing neural network training system 100 trains a neural network to derive signal parameters that are used in hybrid beamforming and that, when applied to a signal, maximize signal-to-noise ratio of that signal. In at least one embodiment, signal processing neural network training system 100 trains a neural network to derive signal parameters and transmit powers that, when applied to multiple signals within a portion of a wireless communication network, maximize a sum rate of that portion.In at least one embodiment, channel state information (CSI) module 120 stores CSI in memory. In at least one embodiment, CSI module 120 includes CSI for one or a plurality of wireless network situations. In at least one embodiment, CSI module 120 generates hypothetical CSI for use in training a neural network. In at least one embodiment, CSI module 120 stores CSI information recorded in real situations. In at least one embodiment, CSI module 120 stores CSI information recorded from a channel state information (CSI-RS) reference signal. In at least one embodiment, CSI includes information that may be used to estimate a time of arrival difference (TDOA) and angle of arrival (AOA). In at least one embodiment, CSI includes channel frequency response (CFR) information that may be used to estimate effects of a channel on different components (e.g., amplitude, phase) of a signal. In at least one embodiment, CSI includes a channel quality indicator (CQI) that may be used to indicate how well a signal may be received and decoded. In at least one embodiment, CSI information includes parameters such as precoding type indicator (PTI), precoding matrix indicator (PMI), rank indicator (RI), layer indicator (LI), or a combination thereof.In at least one embodiment, reward module 122 uses one or more functions to calculate a reward for actuator module 104. In at least one embodiment, a reward indicates an effectiveness of parameters derived from a neural network in improving a signal property, such as signal-to-noise ratio (SNR) or signal-to-interference-plus-noise ratio (SINR). In at least one embodiment, reward module 122 includes one or more reward functions as described in connection with process 600 of FIG. 6. In at least one embodiment, a reward function is a continuous reward function that changes with change in channel state information. In at least one embodiment, a reward function is a discrete reward function that changes discontinuously with changes in channel state information. In at least one embodiment, a discrete reward function changes with occurring events, for example, when actuator module 114 receives a reward that exceeds a target value. In at least one embodiment, a reward function is a combination of continuous and discrete reward functions.In at least one embodiment, neural network training system 100 includes a computer readable storage medium and / or code stored on that computer readable storage medium in the form of a computer program containing a plurality of computer readable instructions executable by one or more processors. In at least one embodiment, computer readable storage medium is a non-transitory computer readable medium. In at least one embodiment, at least some computer readable instructions usable to perform operations described herein, including operations described in connection with FIGS. 1-8, are stored using transitory signals (e.g., propagating transient electrical or electromagnetic transmission), not exclusively. In at least one embodiment, a non-transitory computer readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within transitory signal transceivers. In at least one embodiment, neural network training system 100 is implemented as a non-transitory computer readable storage medium storing executable instructions that, when executed by one or more processors of a computer system, cause computer system to perform neural network operations that derive hybrid beamforming parameters and / or transmit powers to be used by wireless signal transmission devices.FIG. 2 illustrates a system 200 used for training a neural network to derive signal parameters used in hybrid beamforming, according to at least one embodiment. In at least one embodiment, one or more aspects of one or more embodiments described in connection with FIG. 2 are combined with one or more aspects of one or more embodiments described herein, including those described in connection with at least FIGS. 1 and 3-8B. In at least one FIG embodiment, one or more processors that perform one or more operations used by system 200 is any processor or combination of processors described herein, including processor / processors 822 described in connection with FIG. 8B, graphics processor 1910 described in connection with FIG. 19A, and parallel processing unit ("PPU") 3400 described in connection with FIG. 34. In at least one embodiment, processor(s) 822 performs (perform) operations of actuator 210. In at least one embodiment, processor(s) 822 performs / perform an action 230 to update a state 220 to be input to neural network 214. In at least one embodiment, action 230 is a set of one or more changes to apply to state 220. In at least one embodiment, action 230 is an output of neural network 214. In at least one embodiment, action 230 is signal parameters 219 or a representation thereof. In at least one embodiment, updating state 220 using action 230 refers to replacing signal parameters included in state 220 with signal parameters 219. In at least one embodiment, actuator 210 performs one or more operations, such as changing signal parameters performed by actuator module 106 of FIG. 1. In at least one embodiment, actuator 210 performs one or more operations performed by actuator 310 of FIG. 3, which operations include generating an action to change a transmit power of a signal. In at least one embodiment, actuator 210 is actuator 410 of FIG. 4 and / or actuator 510 of FIG. 5. In at least one embodiment, actuator 210 outputs data, such as signal parameters, to environment 450 of FIG. 4 and / or environment 550 of FIG. 5. In at least one embodiment, actuator 210 performs one or more operations of process 600, such as updating analog and digital precoding vectors with operation 606. In at least one embodiment, actuator 210 performs one or more operations of a training process for a neural network with reinforcement learning, as shown in FIG. 7, which includes generating an action used to update a training module.In at least one embodiment, neural network 214 is a neural network that includes neural network module 114 of FIG. 1. In at least one embodiment, all neural networks appearing in figures, including neural network 214 of FIG. 2, do not represent a particular type or structure of neural network and are included for purposes of illustration only. In at least one embodiment, neural network 214 includes weights W 1 to WL for layers 1 to L. In at least one embodiment, neural network 214 includes biases b 1 to bL. In at least one embodiment, nodes of a neural network are represented by a small written sigma σ within a circle.In at least one embodiment, state 220 is input to neural network 214. In at least one embodiment, state 220 represents signal parameters of a signal transmitted or received by a user device. In at least one embodiment, signal parameters represented by state 220 are signal parameters included in an input data set of signals. In at least one embodiment, signal parameters represented by state 220 are signal parameters updated by actuator 210 as a result of a round of training or an inference run. In at least one embodiment, an input data set of signals is generated based on signals from the real world. In at least one embodiment, an input data set of signals is generated by a simulator. In at least one embodiment, signal parameters represented by state 220 are generated by neural network 214 during a previous round of training.In at least one embodiment, state 220 includes channel state information (CSI) or a channel matrix. In at least one embodiment, state 220 is represented by st, where t represents a particular time step. In at least one embodiment, a stage in a training process of a deep learning enhancing neural network is indicated by a time step. In at least one embodiment, a time step correlates to a forward sweep and / or a number of times actuator 210 at least conceptually performed an action 230. In at least one embodiment, state 220 represents an SNR generated last by an environment module, such as environment module 108 described in FIG. 1. In at least one embodiment, state 220 includes any environment information, such as information indicating characteristics of a wireless network and its environment. In at least one embodiment, environment information includes information about quality of a signal, type of hardware, type of software, architecture, number of devices and / or stations connected, or a combination thereof. In at least one embodiment, state 220 represents any information relevant to output of signal parameters by neural network 214 that would result in a stronger, more reliable signal than without neural network 214. In at least one embodiment, state 220 represents any information about a signal and / or wireless network relevant to neural network 214 that outputs signal parameters that can be used to generate a signal having an SNR that exceeds a threshold. In at least one embodiment, state 220 represents a history of previous state information input to actuator 210, including inputs and outputs of neural network 214. In at least one embodiment, state 220 represents a history of previously calculated SNRs and / or reward values. In at least one embodiment, state 220 represents a history of previously used channel state information.In at least one embodiment, neural network 214 generates signal parameters 216 by inference. In at least one embodiment, signal parameters 216 include real and imaginary portions of baseband parameters to be used in a real or simulated baseband signal, where these parameters are organized in vector form. In at least one embodiment, baseband parameters are referred to as baseband weights. In at least one embodiment, real parts of baseband parameters are represented as real (Wbb) and imaginary parts of baseband parameters are represented as imag (Wbb). In at least one embodiment, signal parameters 216 include phase values represented by.phi.,.phi.. In at least one embodiment, phase values comprise values representing each phase shifter in an analog portion of a hybrid beamforming system and are represented as one-hot vectors of length N. In at least one embodiment, a linear output of signal parameters representing phase angles and / or phase shifts is used instead of one-hot coding to meet a unit module condition. In at least one embodiment, phase values include phase angles corresponding to analog phase shifters. In at least one embodiment, N RF identifies a particular RF chain. In at least one embodiment, N r identifies a particular receive antenna from N number of receive antennas. In at least one embodiment, N c denotes a particular carrier frequency. In at least one embodiment, number N is based on total number of analog components in a hybrid beamformer system that includes an RR chain and an antenna.In at least one embodiment, one or more signal parameters 216 are changed by functions F.normalize() 217 and Argmax 218. In at least one embodiment, F.normal () 217 is a function of an application programming interface (API) library used in machine learning to normalize values in a tensor across one or more dimensions. In at least one embodiment, normalization of values includes scaling values of a vector to fall between 0 and 1. In at least one embodiment, normalization of values includes scaling values of a vector to have an average of 0 and a standard deviation of 1. In at least one embodiment, signal parameters 216 are normalized, at least in part, by techniques or functions other than F.normal(), including min-max scaling and z-score normalization. In at least one embodiment, real and imaginary parts of baseband parameters output from neural network 214 are normalized.In at least one embodiment, Argmax 218 is a function of an API library used in machine learning to generate an index or indices of one or more maximum values based on a function. In at least one embodiment, Argmax 218 is performed on phase values of signal parameters 216. In at least one embodiment, phase values, such as phase angles, of signal parameters 216 are represented using a one-hot encoding format. In at least one embodiment, one-hot coding represents integer values as a binary vector, where a value of a binary vector indicates an integer value. In at least one embodiment, representation of each phase shifter is expressed as a one-hot vector as b={0,1}^N such that ||b||_0=1 is where N is a number of possible discrete phase angles. In at least one embodiment, one or more functions, such as Argmax 218, are performed to convert phase values of signal parameters 216 to a corresponding phase shift. In at least one embodiment, use of one-hot coding enables representation of discrete and / or quantized values.In at least one embodiment, after performing F. normalize( ) 217 and Argmax 218 on signal parameters 216, a resulting set of data is signal parameters 219. In at least one embodiment, signal parameters 219 comprise normalized baseband parameters represented as Real(Wbb) and Imag(Wbb), as shown in FIG. 2. In at least one embodiment, signal parameters 219 comprise phase shifts represented by theta, θ. In at least one embodiment, phase shifts of signal parameters 219 are represented in a one-hot coding format. In at least one embodiment, actuator 210 outputs signal parameters 219 to environment 250.In at least one embodiment, action 230 is represented by a t where t represents a particular time step. In at least one embodiment, a stage in a training process of a deep learning enhancing neural network is indicated by time steps. In at least one embodiment, a time step correlates to a forward sweep and / or a number of times actuator 210 at least conceptually performed an action 230. In at least one embodiment, an action at time step t is a concatenated vector of real (Wbb), imag (Wbb), and one-hot encoded phase angles that are values in signal parameters 219. In at least one embodiment, at least conceptually, a concatenated vector representing an action at time t indicates one or more actions that have already been performed by actuator 210 by using neural network 214 to derive signal parameters that make up this concatenated vector. In at least one embodiment, actions taken by actuator 210 relate, at least in part, to conclusions made by neural network 214. In at least one embodiment, action 230 is also sent to criticism 240 in addition to environment 250.In at least one embodiment, criticism 240 is a module that includes a neural network that provides feedback on quality of action 230 performed by actuator 210. In at least one embodiment, critic 240 includes a value function. In at least one embodiment, a value function estimates future rewards, as further described herein, based on a state and a corresponding action derived based on that state. In at least one embodiment, a value function is based on past rewards and estimates of future rewards for a given state and expected action generated by actuator 210. In at least one embodiment, outputting a value function improves actions generated by actuator 210 over multiple time steps. In at least one embodiment, an output of a value function is referred to as a Q value. In at least one embodiment, a value function is used to continuously improve neural network performance during training.In at least one embodiment, environment 250 shares one or more aspects of environment module 108 described in connection with FIG. 1 and environment 450 described in connection with FIG. 4. In at least one embodiment, environment 250 includes signal characteristic computation module 118, channel state information module 120, and reward module 122, as described in connection with FIG. 1. In at least one embodiment, environment 250 includes signal parameters 419 a- b, channel state information 430, signal-to-noise ratio calculation module 440, reward module 450, and next state module 460 as described in connection with FIG. 4.FIG. 3 shows a system 300 used in a training system for a neural network with reinforcement learning to train a neural network to identify a beam direction and derive transmit powers within a wireless communication network. In at least one embodiment, one or more aspects of one or more embodiments described in connection with FIG. 3 are combined with one or more aspects of one or more embodiments described herein, including at least those described in connection with FIGS. 1-2 and 4-8B. In at least one FIG embodiment, one or more processors that perform one or more operations used by system 300 is any processor or combination of processors described herein, including processor(s) 822 described in connection with FIG. 8B, graphics processor 1910 described in connection with FIG. 19A, and parallel processing unit ("PPU") 3400 described in connection with FIG. 34. In at least one embodiment, processor(s) 822 performs (perform) operations of actuator 310. In at least one embodiment, processor(s) 822 performs / perform action 330 to update a state 320 to be input to neural network 314. In at least one embodiment, actuator 310 performs one or more operations, such as changing signal parameters performed by actuator module 106 of FIG. 1. In at least one embodiment, actuator 310 performs one or more operations performed by actuator 210 of FIG. 2, which operations include generating an action to change a transmit power of a signal. In at least one embodiment, actuator 310 is actuator 410 of FIG. 4 and / or actuator 510 of FIG. 5. In at least one embodiment, actuator 310 outputs data, such as signal parameters, to environment 450 of FIG. 4 and / or environment 550 of FIG. 5. In at least one embodiment, actuator 310 performs one or more operations of process 600, such as updating analog and digital precoding vectors with operation 606. In at least one embodiment, actuator 310 performs one or more operations of reinforcement learning depicted in FIG. 7, such as updating a critical module.In at least one embodiment, neural network 314 is a neural network that includes neural network module 114 of FIG. 1. In at least one embodiment, neural network 314 shares one or more aspects of neural network 214. In at least one embodiment, neural network 314 as shown in FIG. 3 does not represent a particular type or structure of neural network and is included for illustrative purposes only. In at least one embodiment, neural network 314 includes weights W 1 to W L for layers 1 to L. In at least one embodiment, neural network 3 includes bias b 1 to b L. In at least one embodiment, nodes of a neural network are represented by a small written sigma σ within a circle. In at least one embodiment, neural network 314 is trained to identify one or more beam directions used by one or more first user equipment (UEs) to transmit wireless signals based on information about beams used by one or more second UEs. In at least one embodiment, neural network 314 is trained to identify a beam direction based on derivation of signal parameters and / or transmit powers of two or more signals that result in a SINR and / or a sum rate above threshold. In at least one embodiment, a neural network identifies a beam direction to be used by a first device for transmitting a signal by deriving a beam direction that optimizes a total SINR that involves information, such as transmission power and beam direction, of another signal where that signal is or is to be transmitted. In at least one embodiment, after identifying a beam direction to be used by a signal, a neural network derives hybrid beamforming parameters to be used to direct transmission of that signal in that identified direction and in the form of a beam. In at least one embodiment, a beam direction is a direction described by an angle value in which a signal is transmitted. In at least one embodiment, a method for aligning or directing a signal is called a beamformer. In at least one embodiment, beamforming of a signal refers to at least applying signal parameters to that signal to steer it. In at least one embodiment, beamforming includes other modifications of a signal, including modifications that form a signal. In at least one embodiment, UEs include devices such as laptops, tablets, cell phones, portable Internet hotspots, and autonomous vehicles. In at least one embodiment, neural network 314 is trained to identify a beam direction of a signal to be transmitted by a first UE based on information of a beam transmitted by a second UE to reduce total signal interference generated by multiple signals in one or more cells of a wireless network. In at least one embodiment, reducing total signal interference increases data throughput of one or more cells of a wireless network.In at least one embodiment, state 320 is input to neural network 314. In at least one embodiment, state 320 represents signal parameters of two or more signals transmitted or received from two or more user devices connected to a single base station. In at least one embodiment, two or more signals transmitted or received by two or more user devices connected to a single base station describe, in part, a portion of a wireless network. In at least one embodiment, a portion of a wireless network is a cell, each cell comprising a single base station. In at least one embodiment, signal parameters represented by state 320 are signal parameters included in an input data set of signals. In at least one embodiment, signal parameters represented by state 320 are signal parameters updated by actuator 310 as a result of a round of training or an inference pass. In at least one embodiment, an input data set of signals is generated based on computations and / or recordings of signals from real world. In at least one embodiment, signal parameters represented by state 220 are generated by neural network 214 during a previous round of training.In at least one embodiment, state 320 comprises channel state information (CSI) or a channel matrix for two or more signals. In at least one embodiment, state 320 is represented by st, where t represents a particular time step. In at least one embodiment, state 320 represents any information indicative of characteristics of a wireless network and its environment, including information about quality of its signals, type of hardware, type of software, architecture, number of devices and / or stations connected, or a combination thereof. In at least one embodiment, state 320 represents any information relevant to neural network 314 that outputs signal and transmit power parameters that are estimated to result in improved overall data throughput for a portion of a wireless network that includes two or more wireless signals transmitted between user devices and a base station. In at least one embodiment, total data throughput of a portion of a wireless network is referred to as a sum rate. In at least one embodiment, state 320 represents any information about a signal and / or wireless network relevant to neural network 414 that outputs signal parameters that can be used to generate multiple signals that collectively have a SINR that exceeds a threshold, where such a SINR may be referred to as collective SINR, total SINR, or total SINR. In at least one embodiment, a threshold is referred to as a target value. In at least one embodiment, state 420 represents a history of previous state information input to actuator 310, including inputs and outputs of neural network 314. In at least one embodiment, state 320 represents a history of previously calculated SINRs and / or reward values. In at least one embodiment, state 320 represents a history of previously used channel state information.In at least one embodiment, neural network 314 generates signal parameters 316 by inference. In at least one embodiment, signal parameters 316 include types of signal parameters described in connection with signal parameters 216 of FIG. 2. In at least one embodiment, signal parameters 316 include power parameters, represented as p. In at least one embodiment, power parameters are referred to as transmit power parameters or transmit powers. In at least one embodiment, N u indicates a particular user or user equipment.In at least one embodiment, one or more signal parameters 316 are changed by functions F.normalize() 317 and Argmax 318, also described as F.normalize()217 and Argmax 218. In at least one embodiment, one or more signal parameters 316 are modified by a function P max F. Sigmoid() 321, which is a function of an API library used in machine learning. In at least one embodiment, P max represents a maximum value for transmit power, while F. Sigmoid( ) is an activation function. In at least one embodiment, P max F. Sigmoid( ) 321 scales an output of an activation function to adjust transmission powers of two or more signals.In at least one embodiment, after performing F.normalize() 317 and Argmax 318 on signal parameters 316, a set of signal parameters 319 results. In at least one embodiment, signal parameters 319 include normalized baseband parameters represented as real (Wbb) and imag (Wbb), as shown in FIG. 3. In at least one embodiment, signal parameters 319 include phase shifts represented by theta, θ. In at least one embodiment, phase shifts of signal parameters 319 are encoded using one-hot coding. In at least one embodiment, signal parameters include scaled values of transmit power represented by p as shown in FIG. 3. In at least one embodiment, actuator 310 outputs signal parameters 319 to environment 350.In at least one embodiment, action 330 is represented by a t where t represents a particular time step. In at least one embodiment, an action at time step t is a concatenated vector of real (Wbb), imag (Wbb), one-hot encoded phase angles, and transmit powers that are values found in signal parameters 319. In at least one embodiment, at least conceptually, a concatenated vector representing an action at time t indicates one or more actions that have already been performed by actuator 310 by using neural network 314 to derive signal parameters that make up this concatenated vector. In at least one embodiment, actions taken by actuator 2310 relate, at least in part, to conclusions made by neural network 314. In at least one embodiment, action 330 is also sent to criticator 340 in addition to environment 350.In at least one embodiment, critics 340 includes a neural network that provides feedback on quality of action 330 performed by actuator 310. In at least one embodiment, critics 340 includes one or more aspects and performs one or more operations of critics 240 as described in connection with FIG. 2. In at least one embodiment, environment 350 includes one or more aspects and performs one or more operations of environment module 108 as described in connection with FIG. 1, environment 250 as described in connection with FIG. 2, and environment 450 as described in connection with FIG. 4. In at least one embodiment, critic 340 is updated to minimize a gap between values represented as Q (s t, a t) and R t+ γ Q (s t+1, π (s t+1)) described below in connection with FIG. 7. In at least one embodiment, actuator 310 is updated to maximize Q. In at least one embodiment, critic 340 outputs Q (s t, a t).FIG. 4 shows a system 400 used in a training system for a reinforcement learning neural network to use environment 450 to evaluate an action performed by an actuator 410, in accordance with at least one embodiment. In at least one embodiment, one or more aspects of one or more embodiments described in connection with FIG. 4 are combined with one or more aspects of one or more embodiments described herein, including those described in connection with at least FIGS. 1-3 and 5-8. In at least one FIG., one or more processors that perform one or more operations used by system 400 are any processor or combination of processors described herein, including processor / processors 822 described in connection with FIG. 8B, graphics processor 1910 described in connection with FIG. 19A, and parallel processing unit ("PPU") 3400 described in connection with FIG. 34. In at least one embodiment, processor(s) 822 performs (perform) operations of actuator 410. In at least one embodiment, processor(s) 822 performs (perform) operations of SNR calculation module 440 to output data used by reward module 442 to generate a reward value. In at least one embodiment, SNR calculation module 440 performs one or more operations of signal characteristic calculation module 118 of FIG. 1, such as calculation of an SNR. In at least one embodiment, environment 450 performs one or more operations performed by environment 250 of FIG. 2. In at least one embodiment, environment 450 of FIG. 4 is environment 350 of FIG. 3. In at least one embodiment, environment 450 performs one or more operations of environment 550 including computing a next state using next state module 560. In at least one embodiment, environment 450 performs one or more operations of process 600, such as calculating an SNR with operation 608. In at least one embodiment, environment 450 performs one or more operations of a training process shown in FIG. 7 for a reinforcement learning neural network that includes generation of a next state.In at least one embodiment, actuator 410 shares one or more aspects and performs one or more operations of at least actuator module 106 described in FIG. 1, actuator 210 described in FIG. 2, and actuator 310 described in FIG. 3. In at least one embodiment, actuator 410 outputs signal parameters, such as signal parameters 219 described in connection with FIG. 2 or signal parameters 319 described in connection with FIG. 4, received from or otherwise obtained from environment 450. In at least one embodiment, actuator 410 outputs signal parameters depicted as signal parameters 419 a- b. In at least one embodiment, signal parameters 419a are analog beamformers and signal parameters 419b are digital beamformers.In at least one embodiment, signal parameters 419 a- bare input to SNR calculation module 440. In at least one embodiment, channel state information module (CSI) 430 outputs channel state information received from SNR calculation module 440 as input data. In at least one embodiment, CSI module 430 includes one or more aspects or performs one or more operations of CSI module 120 described in connection with FIG. 1.In at least one embodiment, SNR calculation module 440 calculates an SNR of a signal using signal parameters 419 a, signal parameters 419 b, and channel state information of CSI module 430. In at least one embodiment, SNR calculation module 440 calculates an SNR using operations described in connection with operation 608 of FIG. 6.In at least one embodiment, SNR calculation module 440 outputs an SNR value to reward module 442. In at least one embodiment, reward module 442 uses an SNR as input to one or more functions to output a value that indicates how well an action of actuator 410 improves an SNR of a signal. In at least one embodiment, a reward function outputs a positive or negative integer value whose magnitude corresponds to an amount of enhancement or degradation of SNR of a signal. In at least one embodiment, reward module 442 outputs a reward value to actuator 410, target actuator 480, target critics 470, or a combination thereof.In at least one embodiment, next state module 460 outputs a next state represented by s t+1 where t+1indicates a next time step in a training process for a neural network with reinforcement learning. In at least one embodiment, a next state represents an environment that includes an SNR output of SNR calculation module 440 during a next time step. In at least one embodiment, data output by next state module 460 becomes current state data, such as state 220 described in connection with FIG. 2. In at least one embodiment, data output by next state module 460 includes an SNR output of SNR calculation module 440, channel state information of channel state information module 430, signal parameters 419 a, signal parameters 419 b, or a combination thereof. In at least one embodiment, data output by next state module 460 and a reward value output by reward module 442 are used by actuator 410 to update neural network parameters, such as neural network 214 described in connection with FIG. 2. In at least one embodiment, next state module outputs data to target criticism 470.In at least one embodiment, target criticism 470 is a neural network and uses one or more aspects of a neural network architecture used by criticism 240 of FIG. 2 and / or criticism 340 of FIG. 3. In at least one embodiment, weights of target critics 470 are updated less frequently than that of critics such as critic 240 and critic 340. In at least one embodiment, target criticism 470 helps mitigate issues with overestimate values output by value functions and improve stability of weights during training of actuator neural network, such as neural network 314 of FIG. 3. In at least one embodiment, values output by value functions are referred to as Q values.In at least one embodiment, target criterion 470 uses an output of target actuator 480. In at least one embodiment, target actuator 480 is a neural network and uses one or more aspects of a neural network architecture used by an actuator such as actuator 410. In at least one embodiment, weights of target actuator 480 are updated less frequently than that of an actuator such as actuator 410. In at least one embodiment, target actuator 480 helps mitigate issues with overestimate values output by value functions and improve stability of weight adjustments made during training of actuator neural network, such as neural network 314 described in connection with FIG. 3.FIG. 5 illustrates a system 500 used in a training system for a reinforcement learning neural network that, according to at least one embodiment, uses environment 550 to evaluate an action performed by an actuator 510. In at least one embodiment, one or more aspects of one or more embodiments described in connection with FIG. 5 are combined with one or more aspects of one or more embodiments described herein, including those described in connection with at least FIGS. 1-4 and 6-8B. In at least one FIG embodiment, one or more processors that perform one or more operations used by system 500 is any processor or combination of processors described herein, including processor / processors 822 described in connection with FIG. 8B, graphics processor 1910 described in connection with FIG. 19A, and parallel processing unit ("PPU") 3400 described in connection with FIG. 34. In at least one embodiment, processor(s) 822 performs (perform) operations of actuator 410. In at least one embodiment, processor(s) 822 performs (perform) operations of SINR calculation module 540 to output data used by reward module 542 to generate a reward value. In at least one embodiment, SINR calculation module 540 performs one or more operations of signal characteristic calculation module 118 of FIG. 1, such as calculation of an SINR. In at least one embodiment, environment 550 performs one or more operations performed by environment 250 of FIG. 2. In at least one embodiment, environment 550 is environment 350 of FIG. 3. In at least one embodiment, environment 550 performs one or more operations of environment 450, including computing a next state with next state module 460. In at least one embodiment, environment 550 performs one or more operations of process 600, such as calculating an SNR with operation 708. In at least one embodiment, environment 550 performs one or more operations of training process shown in FIG. 7 for a neural network with reinforcement learning, including generation of a next state.In at least one embodiment, actuator 510 shares one or more aspects and performs one or more operations of actuator module 106 described in connection with FIG. 1, actuator 210 described in connection with FIG. 2, and actuator 310 described in connection with FIG. 3. In at least one embodiment, actuator 510 outputs signal parameters, such as signal parameters 219 described in connection with FIG. 2 or signal parameters 319 described in connection with FIG. 3, received or otherwise obtained from environment 550. In at least one embodiment, actuator 510 outputs signal parameters depicted as signal parameters 519 a- c. In at least one embodiment, signal parameters 519 aare analog beamformers and signal parameters 519 bare digital beamformers. In at least one embodiment, signal parameters 519 care transmission power change parameters.In at least one embodiment, signal parameters 519 a- care input to SINR calculation module 540. In at least one embodiment, channel state information (CSI) module 530 outputs channel state information received from SINR calculation module 540 as input data. In at least one embodiment, CSI module 530 includes one or more aspects or performs one or more operations of CSI module 120 described in connection with FIG. 1.In at least one embodiment, SINR calculation module 540 calculates an SINR of a signal using signal parameters 519 a, signal parameters 519 b, signal parameters 519 c, and channel state information of CSI module 530. In at least one embodiment, SINR calculation module 540 calculates an SINR using operations described in connection with operation 708 of FIG. 7.In at least one embodiment, SINR calculation module 540 outputs a SINR value to reward module 542. In at least one embodiment, reward module 542 uses a SINR value as input to one or more functions to output a value that indicates how well an action of actuator 510 improves a SINR value of a signal. In at least one embodiment, a reward function outputs a positive or negative integer value whose magnitude corresponds to an amount of enhancement or degradation of SNR of a signal. In at least one embodiment, reward module 542 outputs a reward value to actuator 510, target actuator 580, target critics 570, or a combination thereof.In at least one embodiment, next state module 560 outputs a next state represented by st+1, where t+1indicates a next time step in a training process of a neural network with reinforcement learning. In at least one embodiment, a next state represents an environment that includes an SINR output of SINR calculation module 540 during a next time step. In at least one embodiment, data output by next state module 560 becomes current state data, such as state 220 described in connection with FIG. 2. In at least one embodiment, data output by SINR calculation module 560 includes an SINR output of SINR calculation module 540, channel state information of channel state information module 530, signal parameters 519 a, signal parameters 519 b, signal parameters 519 c, or a combination thereof. In at least one embodiment, data output by next state module 560 and a reward value output by reward module 542 are used by actuator 510 to update neural network parameters, neural network 214 being described in connection with FIG. 2. In at least one embodiment, next state module outputs data to target criticism 570.In at least one embodiment, target criticism 570 is a neural network and uses one or more aspects of a neural network architecture used by criticism 240 described in connection with FIG. 2 and / or criticism 340 described in connection with FIG. 3. In at least one embodiment, weights of target critics 570 are updated less frequently than that of critics such as critic 240 and critic 340. In at least one embodiment, target criticism 570 helps alleviate issues with overestimate values output by value functions and improve stability of weights taken during training of actuator neural network, such as neural network 314 described in connection with FIG. 3.In at least one embodiment, target criterion 570 uses an output of target actuator 580. In at least one embodiment, target actuator 580 is a neural network and uses one or more aspects of a neural network architecture used by an actuator such as actuator 510. In at least one embodiment, weights of target actuator 580 are updated less frequently than that of an actuator such as actuator 510. In at least one embodiment, target actuator 580 helps mitigate issues with overestimate of values output by value functions and improve stability of weight adjustments made during training of actuator neural network, such as neural network 314 described in connection with FIG. 3.FIG. 6 illustrates a process 600 used by a training system for a reinforcement learning neural network to train a neural network to modify both analog and digital parameters of a signal using hybrid beamforming techniques to achieve an SNR, SINR, a sum rate, or a combination thereof that is above a threshold, according to at least one embodiment. In at least one embodiment, one or more aspects of one or more embodiments described in connection with FIG. 6 are combined with one or more aspects of one or more embodiments described herein, including those described in connection with at least FIGS. 1-5 and 7-8B. In at least one FIG embodiment, one or more processors that perform one or more operations used in process 600 is any processor or combination of processors described herein, including processor / processors 822 described in connection with FIG. 8B, graphics processor 1910 described in connection with FIG. 19A, and parallel processing unit ("PPU") 3400 described in connection with FIG. 34. In at least one embodiment, processor(s) 822 performs (perform) operations of actuator 410. In at least one embodiment, processor(s) 822 performs (perform) operation 608 to calculate an SNR such that SNR calculation module 440 described in connection with FIG. 4 may output an SNR to be used by reward module 442 also described in connection with FIG. 4. In at least one embodiment, reward module 122 described in connection with FIG. 1 performs operation 610 of process 600 to output a reward value. In at least one embodiment, actuator 210 described in connection with FIG. 2 and actuator 310 described in connection with FIG. 3 perform operation 606 of process 600 to update analog and digital precoding vectors. In at least one embodiment, environment 450 described in connection with FIG. 4 and environment 550 described in connection with FIG. 5 perform operation 608 of process 600 to calculate an SNR.In at least one embodiment, process 600 begins with obtaining a signal at operation 602. In at least one embodiment, obtaining a signal refers to a processor receiving as input parameters of one or more wireless signals. In at least one embodiment, such parameters include values related to amplitude, phase angle, and frequency.In at least one embodiment, a signal obtained with operation 602 is part of a 5G wireless network multiple-input multiple-output (MIMO) uplink system. In at least one embodiment, a MIMO uplink system uses a Uniform Linear Array (ULA) control vector to beam a signal using analog components of a hybrid beamformer system. In at least one embodiment, a uniform linear array is a set of sensors equi-spaced along a straight line, wherein a sensor may be an antenna. In at least one embodiment, a ULA control vector is expressed as follows:In at least one embodiment, θ represents angle of arrival of a signal; N represents number of elements in a ULA; d represents distance between individual elements of a ULA; λ represents wavelength of a signal; and e2π(d / λ)sin θ represents a phase shift applied to each element of a ULA to direct a beam in direction θ. In at least one embodiment, a ULA steering vector is a complex valued vector that describes how signals on array elements are to be weighted to form a beam in a particular direction. In at least one embodiment, a complex valued vector is a vector comprising complex values, sometimes also referred to as complex numbers. In at least one embodiment, each element of a ULA control vector corresponds to a different array element.In at least one embodiment, a MIMO uplink system uses a discrete beam propagation model, also known as a geometric channel model, which is a line of sight channel model. In at least one embodiment, a discrete radiation propagation model expresses a channel matrix as follows:In at least one embodiment, a sum is over p, where p is an index of paths in a wireless channel; N p represents a number of paths; α p represents a complex gain of a path p; a(θ p, N r) represents a control vector at a receive antenna for a path p; θ p represents an angle of arrival of a path p; N r represents a number of receive antennas.In at least one embodiment, a discrete beam propagation model expresses a received signal at a hybrid beamformer system as follows:In at least one embodiment, baseband and RF pre-encoders are provided that modify signal parameters. In at least one embodiment, it is used at a transmitter and used to maximize signal quality at a receiver. ρ stands for the transmission power of a signal. In at least one embodiment, H represents a channel matrix, s represents a transmit signal, and n represents noise at receiver.In at least one embodiment, a set of RF precoding matrices used in beamforming is represented as follows:In at least one embodiment, a matrix of size is N r × N RF where N r is a number of receive antennas and N RF is a number of RF chains. In at least one embodiment, a set of phase angles represents. In at least one embodiment, values in precoding (RF or baseband) matrices comprise weights, such as phase and gain, applied to a signal.In at least one embodiment, a set of baseband precoding matrices is expressed as:In at least one embodiment, C NRF×Nu represents a set of matrices of complex numbers. In at least one embodiment, N u refers to a number of data streams being transmitted, i.e., signals transmitting payload data.In at least one embodiment, a processor continues process 600 by performing operation 604 to input received input data to a neural network. In at least one embodiment, a neural network is part of an actuator module as described herein. In at least one embodiment, a neural network is neural network 214 of FIG. 2, neural network 314 of FIG. 3, or a combination thereof. In at least one embodiment, a neural network takes signal parameters, such as values included in Rf and baseband precoding matrices, and derives therefrom new signal parameters to improve SNR of one signal or total SINR of two or more signals.In at least one embodiment, a processor continues process 600 by performing operation 606 to calculate an SNR and / or an SINR based on signal parameters, such as values for precoding matrices output from a neural network. In at least one embodiment, a formula used to calculate SNR is expressed as follows:In at least one embodiment, a formula for calculating SINR is expressed as follows:In at least one embodiment, c refers to a particular cell within a wireless network. In at least one embodiment, h c, (c*, u*) represents an uplink channel from a u*th user equipment (UE) in a c*th cell for a c*th gNB that is a base station. In at least one embodiment, a μ-th UE is in c-th cell (with peak power p max). In at least one embodiment, hybrid beamformers represent (c, u) defined asIn at least one embodiment, a processor continues process 600 by executing operation 608 to output a reward value. In at least one embodiment, a reward value is received or otherwise obtained from an actuator module to be used to evaluate its actions. In at least one embodiment, a reward value, such as an action, for example, updating values of precoding matrices, has increased or decreased a signal property, for example, SNR or SINR, of one or more signals. In at least one embodiment, a signal characteristic refers to a characteristic of a portion of a wireless network as a whole, such as total SINR or a sum rate for that portion. In at least one embodiment, a reward value where target of an actuator module is to maximize or achieve a target SNR is represented as follows: R t= Π u SNR u. In at least one embodiment, a reward value where actuator module goal is to maximize or achieve a SINR goal is represented as R t= +100 χ {SNRt≥target}+ 1 χ {SNRt≥SNRt-1}- ∑ u p u. In at least one embodiment, another reward value based on reaching a SINR target is represented as R t= +100 χ {SNRt≥target}+ 1 χ {SNRt≥SNRt-1}- 10 log 10 ∑ u w u p u, where wurepresents a weight described further herein. In at least one embodiment, a formula for maximizing a total SINR shown jointly by two or more signals is represented as: ∑ c,u log 2(1 + SINR c,u). In at least one embodiment, a reward value where goal of an actor module is to maximize or satisfy a goal sum rate is represented as R t= ∑ (c,u) log 2 log 2(1 + SINR c,u) - ∑ (c,u) p c,u.In at least one embodiment, a reward value is intended to at least conceptually motivate an agent of reinforcement learning to achieve a goal with highest reward. In at least one embodiment, a reward value is +=100 when a currently achieved SNR value>= SNR target (or target throughput). In at least one embodiment, SINR may also be used in forming reward values instead of SNR. In at least one embodiment, a reward value is +=1 when an achieved SNR improves. In at least one embodiment, a reward value -=is a sum of transmit powers in dB. In at least one embodiment, a weighted sum of w_u is used depending on a quality of service (QoS) metric or performance of a UE. In at least one embodiment, a user u with lower power may not provide high transmit power, such that a higher w_u may be substituted into a reward formula to more penalize an action of the actuator. In at least one embodiment, a neural network is trained to cause UEs to minimize transmit power so that a negative penalty is applied to a reward formula that is proportional to transmit power derived from that neural network, and therefore an actor attempts to maximize a reward in part by minimizing transmit power.In at least one embodiment, maximizing a sum rate is represented as maximizing a sum of log 2(1 + SINR c,u). In at least one embodiment, to minimize concentration on a single UE with highest channel gain, a fitness condition is added such that maximizing a sum rate is represented as maximizing a sum of log 2 log 2(1 + SINR c,u).In at least one embodiment, a processor continues process 600 by performing operation 610 to determine whether a signal characteristic has been maximized or satisfied. In at least one embodiment, a reward value output by operation 608 is used to determine whether a signal property has been maximized or satisfied. In at least one embodiment, a signal characteristic is compared to a target signal characteristic set by a user or software to determine whether that characteristic is maximized or satisfied.In at least one embodiment, a processor continues process 600 by performing operation 614 to determine whether additional input signals and their signal parameters are available that can be used to train a neural network as described herein. In at least one embodiment, if additional signals are available that may be used as input data for training a neural network, process 600 repeats beginning with operation 602. In at least one embodiment, if no additional signals are available that can be used as input data for training a neural network, process 600 ends.FIG. 7 shows a block diagram 700 depicting a process flow for aspects of a training system for a reinforcement learning neural network used to train a neural network to modify both analog and digital parameters of a signal using hybrid beamformer techniques to achieve a signal characteristic above a threshold, according to at least one embodiment. In at least one embodiment, one or more aspects of one or more embodiments described in connection with FIG. 7 are combined with one or more aspects of one or more embodiments described herein, including those described in connection with at least FIGS. 1-6 and 8. In at least one FIG., one or more processors that perform one or more operations used in block diagram 700 are any processor or combination of processors described herein, including processor / processors 822 described in connection with FIG. 8B, graphics processor 1910 described in connection with FIG. 19A, and parallel processing unit ("PPU") 3400 described in connection with FIG. 34. In at least one embodiment, processor(s) 822 perform(s) operations to update an actuator to maximize rt, as shown in FIG. 7. In at least one embodiment, processor(s) 822 perform operations correlated with blocks depicted in FIG. 7, such as operations used by a criticism as described in connection with FIG. 3 or FIG. 4, or operations used by a target criticism as described in connection with FIG. 5.In at least one embodiment, a state s t, as shown in block diagram 700, is information that a training agent uses for a neural network with reinforcement learning. In at least one embodiment, state s t includes a prior action a t-1 and individually reached SNRs for all UEs. In at least one embodiment, action at modifies design factors under control of an agent. In at least one embodiment, action a t uses a concatenation of vectors W BB and W RF. In at least one embodiment, action a t is expressed as a signal vector. In at least one embodiment, action atis an output of a neural network, such as neural network 214 of FIG. 2. in at least one embodiment, are for a non-grid of beams (GoB) system of hybrid beamforming, where in at least one embodiment, each θ is represented by a one-hot coding of length N. In at least one embodiment, an environment not shown in FIG. 7 divides an action into W BB and W RF, meaning that an environment divides parameters in an action into parameters used in digital beamforming and parameters used in analog beamforming. In at least one embodiment, smooth updating of neural network parameters is a more gradual combination of current parameters with previously used parameters to achieve greater stability for neural network during training.FIG. 8A shows a block diagram of a driver and / or runtime that includes one or more libraries to provide one or more application programming interfaces (APIs), according to at least one embodiment. In at least one embodiment, any processor or combination of processors executes API(s) 810, including processor / processors 822 of FIG. 8B, graphics processor 1910 described in connection with FIG. 19A, and parallel processing unit ("PPU") 3400 described in connection with FIG. 34. In at least one embodiment, API(s) 810 are described below. In at least one embodiment, a call to API(s) 810 causes one or more operations of one or more modules of FIGS. 1-5 to be performed. In at least one embodiment, API(s) 810 receives as input baseband and RF signal parameters of a transmitted signal. In at least one embodiment, upon receiving input of signal parameters, API(s) 810 cause an actuator module, such as actuator module 106 of FIG. 1, to perform operations that train a neural network to output hybrid beamforming parameters used to form and transmit a directed beam, as further described herein. In at least one embodiment, API(s) 810 cause a neural network trained according to one or more techniques described herein, including those described at least in connection with FIGS. 1-7, to take input of hybrid beamforming signal parameters of a transmitted signal and output other hybrid beamforming signal parameters to cause transmission of a directed beam having a signal characteristic that satisfies a target value, as further described herein.In at least one embodiment, software program 802 is a software module. In at least one embodiment, a software program 802 includes one or more software modules. In at least one embodiment, one or more APIs 810 are sets of software instructions that, when executed, cause one or more processors to perform one or more computational operations. In at least one embodiment, one or more APIs 810 are distributed or otherwise provided as part of one or more libraries 806, runtimes 804, drivers 804, and / or other grouping of software and / or executable code further described herein. In at least one embodiment, one or more APIs 810 perform one or more computing operations in response to being called by software programs 802. In at least one embodiment, software program 802 is a collection of software code, instructions, instructions, or other text sequences to direct a computing device to perform one or more computational operations and / or invoke one or more other sets of instructions, such as APIs 810 or API functions 812, for execution. In at least one embodiment, functionality provided by one or more APIs 810 includes software functions 812 that may be used, for example, to accelerate one or more portions of software programs 802 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, a software program is a compiler.In at least one embodiment, APIs 810 are hardware interfaces to one or more circuits to perform one or more computing operations. In at least one embodiment, one or more software APIs 810 described herein are implemented as one or more circuits to perform one or more techniques described herein. In at least one embodiment, one or more software programs 802 include instructions that, when executed, cause one or more hardware devices and / or circuits to perform one or more techniques further described herein.In at least one embodiment, software programs 802, such as user-implemented software programs, use one or more application programming interfaces (APIs) 810 to perform various computational operations, such as memory reservation, matrix multiplication, arithmetic operations, or any computational operation performed by parallel processing units (PPUs), such as graphics processing units (GPUs), as further described herein. In at least one embodiment, one or more APIs 810 provide a set of callable functions 812, referred to herein as APIs, API functions, and / or functions, that individually perform one or more computational operations, such as parallel data processing related computational operations. For example, in one embodiment, one or more APIs 810 provide functions 812 to cause a scheduler to schedule instructions to be executed by processors based on the latency of interconnects coupled to those processors.In at least one embodiment, one or more software programs 802 interact or communicate with one or more APIs 810 to perform one or more computing operations using one or more PPUs, such as GPUs. In at least one embodiment, one or more computational operations using one or more PPUs include at least one or more groups of computational operations that are accelerated by execution at least partially by one or more PPUs. In at least one embodiment, one or more software programs 802 interact with one or more APIs 810 to enable parallel computing via a remote or local interface.In at least one embodiment, an interface is comprised of software instructions that, when executed, provide access to one or more functions 812 provided by one or more APIs 810. In at least one embodiment, a software program 802 uses a local interface when a software developer compiles one or more software programs 802 in conjunction with one or more libraries 806 that include or otherwise provide access to one or more APIs 810. In at least one embodiment, one or more software programs 802 are statically compiled in conjunction with precompilation libraries 806 or noncompilation source code comprising instructions for executing one or more APIs 810. In at least one embodiment, one or more software programs 802 are dynamically compiled, and one or more software programs use a linker to connect to one or more precompilation libraries 806 that include one or more APIs 810.In at least one embodiment, a software program 802 uses a remote interface when a software developer executes a software program that uses or otherwise communicates with a library 806 comprising one or more APIs 810 over a network or other remote communication medium. In at least one embodiment, one or more libraries 806 comprising one or more APIs 810 are executed by a remote computing service, such as a provider of computing resource services. In another embodiment, one or more libraries 806 comprising one or more APIs 810 are executed by another computer host that provides the one or more APIs 810 to one or more software programs 802.In at least one embodiment, a processor executing or using one or more software programs 802 invokes, uses, executes, or otherwise implements one or more APIs 810 to allocate and otherwise manage memory to be used by software programs 802. In at least one embodiment, one or more software programs 802 use one or more APIs 810 to allocate and otherwise manage memory to be used by one or more portions of software programs 802 to be accelerated using one or more PPUs, such as GPUs or other accelerator or processor further described herein. These software programs 802 may be executed by one or more processors based at least in part on latency of interconnects coupled to one or more processors using functions 812 provided by one or more APIs 810 in one embodiment.In at least one embodiment, an API 810 is an API to facilitate parallel computing. In at least one embodiment, an API 810 is any other API further described herein. In at least one embodiment, an API 810 is provided by a driver and / or runtime 804. In at least one embodiment, an API 810 is provided by a CUDA user mode driver. In at least one embodiment, an API 810 is provided by a CUDA runtime. In at least one embodiment, a driver 804 is comprised of data values and software instructions that, when executed, perform or otherwise facilitate operation of one or more functions 812 of an API 810 during loading and execution of one or more portions of a software program 802. In at least one embodiment, runtime 804 is comprised of data values and software instructions that, when executed, perform or otherwise facilitate operation of one or more functions 812 of an API 810 during execution of a software program 802. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 implemented or otherwise provided by a driver and / or runtime 804 to perform combined arithmetic operations by one or more software programs 802 during execution by one or more PPUs, such as GPUs.In at least one embodiment, one or more software programs 802 use one or more APIs 810 provided by a driver and / or runtime 804 to perform combined arithmetic operations of one or more PPUs, such as GPUs. In at least one embodiment, one or more APIs 810 provide combined arithmetic operations via a driver and / or a runtime 804, as described above. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by a driver and / or runtime 804 to allocate or otherwise reserve one or more storage blocks 814 to one or more PPUs, such as GPUs. In at least one embodiment, one or more software programs 802 utilize one or more APIs 810 provided by a driver and / or runtime 804 to allocate or otherwise reserve storage blocks. In at least one embodiment, one or more APIs 810 perform combined mathematical functions as described herein.In at least one embodiment, to improve utility of software programs 802 and / or optimization of one or more portions of software programs 802 to be accelerated by one or more PPUs, such as GPUs, one or more APIs 810 provide one or more API functions 812 to perform a scheduling system that may be used or is utilized by one or more computing devices as described herein. In at least one embodiment, a processor executes one or more software programs to combine two or more application programming interfaces (APIs) into a single API. In at least one embodiment, a processor uses an API to cause a scheduler to select a thread selection mechanism and / or perform other operations described herein. In at least one embodiment, an API invokes a scheduler to cause resource allocation. In at least one embodiment, a processor uses an example API to schedule one or more instructions to be executed by one or more processors based at least in part on latency of one or more interconnects associated with those one or more processors.In at least one embodiment, memory 814 is system memory 1904 of computer system 1900. In at least one embodiment, memory 814 stores data parameters such as baseband and RF weights of one or more transmitted signals. In at least one embodiment, memory 814 stores data parameters used by various modules of a reinforcement learning system, modules such as actuator module 106 of FIG. 1, actuator module 230 of FIG. 2, actuator module 310 for storing signal parameters 319 of FIG. 3, next state module of FIG. 4, and target critics module 570 of FIG. 5. In at least one embodiment, memory 814 stores SINR values calculated with operation 608. In at least one embodiment, memory 814 stores results of attempts to minimize [Q (s t, a t) - { R t+ γ Q (s t+1, π (s t+1))}]2 by updating a criticism as shown in FIG. 7. In at least one embodiment, memory 814 stores functions such as reward functions and value functions as described herein. In at least one embodiment, memory 814 stores a neural network by at least partially storing neural network parameters such as weights, biases, and activation values of neural network.FIG. 8B shows block diagram 800 including processor(s) 822 that is / are used to perform one or more operations of one or more modules described herein at least in connection with FIGS. 1-7, in accordance with at least one embodiment. In at least one embodiment, processor(s) 822 is / are used to perform training of a neural network using reinforcement learning as further described herein. In at least one embodiment, one or more aspects of one or more embodiments described in connection with FIG. 8B are combined with one or more aspects of one or more embodiments described herein, including at least those described in connection with FIGS. 1-7. In at least one embodiment, processor(s) 822 is(are) any processor or combination of processors described herein, including graphics processor 1910 described in connection with FIG. 19A and parallel processing unit ("PPU") 3400 described in connection with FIG. 34. In at least one embodiment, processor(s) 822 is(are) processor(s) 1902 of computer system 1900.In at least one embodiment, one or more modules described herein, including those described at least in connection with FIGS. 1-5, are installed on processor(s) 822. In at least one embodiment, an example module on processor(s) 822 is actuator module 824. In at least one embodiment, actuator module 824 includes one or more aspects of actuator module 106 of FIG. 1, actuator 210 of FIG. 2, actuator 310 of FIG. 3, actuator 410 of FIG. 4, actuator 510 of FIG. 5, or a combination thereof. In at least one embodiment, actuator module 824 includes one or more of API(s) 810 of FIG. 8A to perform one or more operations with respect to an actuator of a reinforcement learning system, such as jointly deriving signal parameters to be used in a hybrid beam forming system.In at least one embodiment, an example module on processor(s) 822 is environment module 826. In at least one embodiment, environment module 826 includes one or more aspects of environment module 108 of FIG. 1, environment 250 of FIG. 2, environment 350 of FIG. 3, environment 450 of FIG. 4, environment 550 of FIG. 5, or a combination thereof. In at least one embodiment, environment module 824 includes one or more of API(s) 810 of FIG. 8A to perform one or more operations related to an environment module in a system with reinforcement learning, such as calculating a reward indicating how well an action generated by an actuator module has improved a signal property of a transmitted signal.FIG. 8B shows block diagram 800 including processor(s) 822 that is / are used to perform one or more operations of one or more modules described herein at least in connection with FIGS. 1-7, in accordance with at least one embodiment. In at least one embodiment, processor(s) 822 is / are used to perform training of a neural network using reinforcement learning as further described herein. In at least one embodiment, one or more aspects of one or more embodiments described in connection with FIG. 8B are combined with one or more aspects of one or more embodiments described herein, including at least those described in connection with FIGS. 1-7. In at least one embodiment, processor(s) 822 is(are) any processor or combination of processors described herein, including graphics processor 1910 described in connection with FIG. 19A and parallel processing unit ("PPU") 3400 described in connection with FIG. 34. In at least one embodiment, processor(s) 822 is(are) processor(s) 1902 of computer system 1900.In at least one embodiment, one or more modules described herein, including those described at least in connection with FIGS. 1-5, are installed on processor(s) 822. In at least one embodiment, an example module on processor(s) 822 is actuator module 824. In at least one embodiment, actuator module 824 includes one or more aspects of actuator module 106 of FIG. 1, actuator 210 of FIG. 2, actuator 310 of FIG. 3, actuator 410 of FIG. 4, actuator 510 of FIG. 5, or a combination thereof. In at least one embodiment, actuator module 824 includes one or more of API(s) 810 of FIG. 8A to perform one or more operations with respect to an actuator of a reinforcement learning system, such as jointly deriving signal parameters to be used in a hybrid beam forming system.In at least one embodiment, an example module on processor(s) 822 is environment module 826. In at least one embodiment, environment module 826 includes one or more aspects of environment module 108 of FIG. 1, environment 250 of FIG. 2, environment 350 of FIG. 3, environment 450 of FIG. 4, environment 550 of FIG. 5, or a combination thereof. In at least one embodiment, environment module 824 includes one or more of API(s) 810 of FIG. 8A to perform one or more operations related to an environment module in a system with reinforcement learning, such as calculating a reward indicating how well an action generated by an actuator module has improved a signal property of a transmitted signal.LOGICFIG. 9A shows logic 915 that, as described elsewhere herein, may be used in one or more devices to perform operations such as those discussed herein in accordance with at least one embodiment. In at least one embodiment, logic 915 is used to perform inferencing and / or training operations associated with one or more embodiments. In at least one embodiment, logic 915 is inference and / or training logic. Details of logic 915 will be described below in connection with FIGS. 9A and / or 9B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide functionality or operations described herein, where logic may be collectively or individually embodied as circuitry that forms part of a larger system, such as an integrated circuit (IC), system-on-chip (SoC), or one or more processors (e.g., CPU, GPU).In at least one embodiment, logic 915 may include, without limitation, code and / or data storage 901 to store forward and / or output weights and / or input / output data and / or other parameters to configure neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, logic 915 may include or be coupled to code and / or data store 901 to store graph code or other software that controls timing and / or order in which information about weights and / or other parameters is loaded to configure logic, including integer and / or floating point units (collectively: arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, based on a neural network architecture to which such code corresponds loads weights or other parameter information into processor ALUs. In at least one embodiment, code and / or data store 901 stores weight parameters and / or input / output data of each layer of a neural network trained or used in connection with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, each portion of code and / or data store 901 may comprise other on-chip or off-chip data stores, including L1, L2, or L3 cache or system memory of a processor.In at least one embodiment, any portion of code and / or data store 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data store 901 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, selection of whether code and / or code and / or data store 901 is internal or external to a processor, for example, or comprises DRAM, SRAM, flash, or other type of memory may depend on available on-chip memory versus off-chip memory, latency requirements of training and / or inferencing functions performed, batch size of data used in inferencing and / or training a neural network, or a combination of these factors.In at least one embodiment, logic 915 may include, without limitation, code and / or data storage 905 to store backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data store 905 stores weight parameters and / or input / output data of each layer of a neural network trained or used in connection with one or more embodiments during backward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, logic 915 may include or be coupled to code and / or data store 905 to store graph code or other software that controls timing and / or order in which information about weights and / or other parameters is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).In at least one embodiment, code, such as graph code, causes loading information about weights or other parameters into processor ALUs based on a neural network architecture to which that code corresponds. In at least one embodiment, each portion of code and / or memory 905 may include other on-chip or off-chip memories, including L1, L2, or L3 cache or system memory of a processor. In at least one embodiment, any portion of code and / or data store 905 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data store 905 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, selection of whether code and / or data store 905 is internal or external to a processor, for example, or comprises DRAM, SRAM, flash memory, or other type of memory may depend on available on-chip memory versus off-chip memory, latency requirements of training and / or inferencing functions performed, batch size of data used in inferencing and / or training a neural network, or a combination of these factors.In at least one embodiment, code and / or data store 901 and code and / or data store 905 may be separate storage structures. In at least one embodiment, code and / or data store 901 and code and / or data store 905 may be a combined storage structure. In at least one embodiment, code and / or data store 901 and code and / or data store 905 may be partially combined and partially separated. In at least one embodiment, each portion of code and / or data store 901 and code and / or data store 905 may comprise other on-chip or off-chip data stores, including processor's L1, L2, or L3 cache or system memory.In at least one embodiment, logic 915 may include, without limitation, one or more arithmetic logic unit(s) ("ALU(s)") 910, including integer and / or floating point units, to perform logical and / or mathematical operations based at least in part on or indicated by training and / or inference code (e.g., graph code), a result of which may generate activations (e.g., output values of layers or neurons within a neural network) stored in an activation memory 920 that are functions of input / output and / or weight parameter data stored in code and / or data memory 901 and / or code and / or data memory 905. In at least one embodiment, activations stored in activation memory 920 are generated according to linear algebraic and / or matrix-based math executed by ALU(s) 910 in response to execution instructions or other code, wherein weight values stored in code and / or data memory 905 and / or data memory 901 are used as operands along with other values such as bias values, gradient information, pulse values or other parameters or hyperparameters, some or all of which may be stored in code and / or data memory 905 or code and / or data memory 901 or other memory on or off-chip.In at least one embodiment, ALU(s) 910 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, ALU(s) 910 may be external to a processor or other hardware logic device or circuit that uses it (e.g., a co-processor). In at least one embodiment, ALUs 910 may be included in execution units of a processor or otherwise included in a bank of ALUs that may be accessed by execution units of a processor either within same processor or distributed to different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 901, code and / or data storage 905, and activation storage 920 may share a processor or other hardware logic device or circuit, while in another embodiment, they may reside in different processors or other hardware logic devices or circuits, or in a combination of same and different processors or other hardware logic devices or circuits. In at least one embodiment, each portion of activation memory 920 may include other on-chip or off-chip data memories, including L1, L2, or L3 cache memory of a processor or system memory. Moreover, the inference and / or training code may be stored along with other code that may be accessed by a processor or other hardware logic or circuitry and that is retrieved and / or processed using a processor's fetch, decode, scheduling, execute, commit, and / or other logic circuitry.In at least one embodiment, activation memory 920 may be a cache memory, a DRAM, an SRAM, a non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, activation memory 920 may be located wholly or partially within or outside one or more processors or other logic circuitry. In at least one embodiment, selection of whether activation memory 920 is internal or external to a processor, for example, or comprises DRAM, SRAM, flash memory, or other type of memory may depend on available on-chip memory versus off-chip memory, latency requirements of training and / or inferencing functions performed, batch size of data used in inferencing and / or training a neural network, or a combination of these factors.In at least one embodiment, logic 915 shown in FIG. 9A may be used in conjunction with an application specific integrated circuit ("ASIC"), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™ or a Nervana® processor (e.g., "Lake Crest") from Intel Corp. In at least one embodiment, logic 915 shown in FIG. 9A may be used in conjunction with hardware of central processing unit ("CPU"), graphics processing unit ("GPU"), or other hardware, such as field programmable gate arrays ("FPGAs").FIG. 9B illustrates logic 915, in accordance with at least one embodiment. In at least one embodiment, logic 915 is inference and / or training logic. In at least one embodiment, logic 915 may include, without limitation, hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, logic 915 shown in FIG. 9B may be used in conjunction with an application specific integrated circuit (ASIC), such as Google's TensorFlow® processing unit, Graphcore™ inference processing unit (IPU), or Intel Corp's Nervana® processor (e.g., Lake Crest). In at least one embodiment, logic 915 shown in FIG. 9B may be used in conjunction with Central Processing Unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as Field Programmable Gate Arrays (FPGAs). In at least one embodiment, logic 915 includes, without limitation, code and / or data store 901 and code and / or data store 905, which may be used to store code (e.g., diagram code), weight values, and / or other information, including bias values, gradient information, pulse values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 9B, each of code and / or data stores 901 and code and / or data stores 905 are connected to a dedicated computing resource, such as computer hardware 902 and computer hardware 906, respectively. In at least one embodiment, each of computing hardware 902 and computer hardware 906 includes one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and / or data store 901 and code and / or data store 905, respectively, as a result of which is stored in activation memory 920.In at least one embodiment, code and / or data stores 901 and 905 and corresponding computer hardware 902 and 906 correspond to different layers of a neural network, respectively, such that activation resulting from a memory / compute pair 901 / 902 of code and / or data store 901 and computer hardware 902 is provided as input to a next memory / compute pair 905 / 906 of code and / or data store 905 and computer hardware 906 to reflect a conceptual organization of a neural network. In at least one embodiment, each of memory / compute pairs 901 / 902 and 905 / 906 may correspond to more than one layer of neural network. In at least one embodiment, additional memory / compute pairs (not shown) following or parallel to memory / compute pairs 901 / 902 and 905 / 906 may be included in logic 915.TRAINING AND DEPLOYMENT OF NEURAL NETWORKFIG. 10 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an trained neural network 1006 is trained using a training dataset 1002. In at least one embodiment, training framework 1004 is a PyTor framework, while in other embodiments, training framework 1004 is a TensorFlow, Boost, Coffee, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, training framework 1004 trains an untrained neural network 1006 and enables training thereof with processing resources described herein to generate a trained neural network 1008. In at least one embodiment, weights may be selected randomly or by pretraining using a deep belief network. In at least one embodiment, training may be performed in either monitored, partially monitored, or unsupervised fashion.In at least one embodiment, non-trained neural network 1006 is trained using supervised learning, wherein training dataset 1002 includes input paired with a desired output for input, or wherein training dataset 1002 has input with a known output and output of neural network 1006 is manually evaluated. In at least one embodiment, trained neural network 1006 is trained and processes inputs from training dataset 1002 in a supervised manner and compares resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then tracked back by non-trained neural network 1006. In at least one embodiment, training framework 1004 adjusts weights that control non-trained neural network 1006. In at least one embodiment, training framework 1004 includes tools for monitoring how well non-trained neural network 1006 converges to a model, such as trained neural network 1008, that is capable of generating correct responses based on input data, such as new dataset 1012, such as result 1014. In at least one embodiment, training framework 1004 trains untrained neural network 1006 repeatedly while adjusting weights to refine an output of untrained neural network 1006 using a loss function and an adjustment algorithm such as stochastic gradient descent. In at least one embodiment, training framework 1004 trains untrained neural network 1006 until untrained neural network 1006 reaches a desired accuracy. In at least one embodiment, trained neural network 1008 may then be deployed to implement any number of machine learning operations.In at least one embodiment, untrained neural network 1006 is trained using unsupervised learning, where untrained neural network 1006 attempts to train itself with unlabeled data. In at least one embodiment, unsupervised learning training dataset 1002 includes input data without associated output data or "Grundwahrheitsdaten". In at least one embodiment, non-trained neural network 1006 may learn groupings within training dataset 1002 and determine how individual inputs are related to non-trained dataset 1002. In at least one embodiment, unsupervised training may be used to generate a self-organizing map in a trained neural network 1008 that is capable of performing operations useful for reducing dimensionality of new dataset 1012. In at least one embodiment, unsupervised training may also be used to detect anomalies, which allows identification of data points in new dataset 1012 that deviate from normal patterns of new dataset 1012.In at least one embodiment, semi-supervised learning may be used, i.e., a technique in which training dataset 1002 includes a mixture of labeled and unlabeled data. In at least one embodiment, training framework 1004 may be used to perform incremental learning, for example, through transmitted learning techniques. In at least one embodiment, incremental learning allows trained neural network 1008 to adapt to a new dataset 1012 without forgeting knowledge that was shot to trained neural network 1008 during initial training.In at least one embodiment, training framework 1004 is a framework that is processed in conjunction with a software development toolkit, such as an Open Visual Inference and Neural Network Optimization (OpenVINO) toolkit. In at least one embodiment, an OpenVINO toolkit is a toolkit as developed by Intel Corporation of Santa Clara, CA. In at least one embodiment, OpenVINO includes logic 915 or uses logic 915 to perform operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform operations described herein.In at least one embodiment, OpenVINO is a toolkit to facilitate development of applications, particularly neural network applications, for various tasks and operations such as human vision emulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variants thereof.In at least one embodiment, OpenINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face detection, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image transmission, style transfer, action detection, colorization, and / or variations thereof.In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as model optimizers. In at least one embodiment, a model optimizer is a command line tool that facilitates transitions between training and deployment of neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and / or processing units, such as a GPU, CPU, PPU, GPGPU, and / or variations thereof. In at least one embodiment, a model optimizer generates an internal representation of a model and optimizes model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces a number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model used for training. In at least one embodiment, a model optimizer performs various operations of a neural network, such as changing inputs to a model (e.g., changing magnitude of inputs to a model), changing magnitude of inputs to a model (e.g., changing stack size of a model), changing a model structure (e.g., changing layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as integer), and / or variations thereof.In at least one embodiment, OpenVINO includes one or more software libraries for inferencing, also referred to as an inference engine.In at least one embodiment, inference engine is a C++ library or other suitable library in a programming language. In at least one embodiment, an inference engine is used to derive input data. In at least one embodiment, an inference engine implements various classes for deriving input data and generating one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, set input and / or output formats, and / or execute a model on one or more devices.In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or computation refers to one or more computing processes and / or systems that use one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions to execute, for example, a first portion of code on a CPU and a second portion of code on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).In at least one embodiment, OpenVINO includes various functionalities similar to functionalities associated with a CUDA programming model, for example, various neural network model operations associated with frameworks such as TensorFlow, PyTor, and / or variants thereof. In at least one embodiment, one or more CUDA programming model operations are performed with OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO.DATACENTERFIG. 11 shows an example of a data center 1100 in which at least one embodiment may be used. In at least one embodiment, data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.In at least one embodiment, as shown in FIG. 11, data center infrastructure layer 1110 may include resource orchestrator 1112, grouped compute resources 1114, and node compute resources ("node C.R.s") 1116( 1)- 1116(N), where "N" represents a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, nodes C.R.s 1116( 1)- 1116(N) may include any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), storage devices 1118( 1)- 1118(N) (e.g., dynamic read only memory, solid state memory, or hard disk drives), network input / output devices ("NW I / O"), network switches, virtual machines ("VMs"), Power modules and cooling modules, etc. In at least one embodiment, one or more node C.R.s among node C.R.s 1116( 1)- 1116(N) may be a server having one or more of the computing resources mentioned above.In at least one embodiment, grouped computing resources 1114 may include separate groupings of node C.R.s residing in one or more racks (not shown) or multiple racks residing in data centers at different geographic locations (also not shown). In at least one embodiment, separate groupings of node C.R.s within grouped computing resources 1114 may include grouped computing, network, storage, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, multiple node C.R.s comprising CPUs or processors may be grouped into one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.In at least one embodiment, resource orchestrator 1112 may configure or otherwise control one or more nodes C.R.s 1116( 1)- 1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource orchestrator 1112 may include a software design infrastructure ("SDI") manager for data center 1100. In at least one embodiment, resource orchestrator 912 may comprise hardware, software, or a combination thereof.In at least one embodiment, as shown in FIG. 11, framework layer 1120 includes a job scheduler 1122, a configuration manager 1124, a resource manager 1126, and a distributed file system 1128. In at least one embodiment, framework layer 1120 may include a framework to support software 1132 of software layer 1130 and / or one or more application(s) 1142 of application layer 1140. In at least one embodiment, software 1132 or application(s) 1142 may include web-based service software or applications such as provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1120 may be any type of free and open source software web application framework such as Apache Spark™ (hereinafter "Spark"), which may utilize a distributed file system 1128 for large volume data processing (e.g., "Big Data"). In at least one embodiment, job scheduler 1122 may include a spark driver to facilitate scheduling workloads supported by different layers of data center 1100. In at least one embodiment, configuration manager 1124 may be capable of configuring different layers, such as software layer 1130 and framework layer 1120, including spark and distributed file system 1128, to support large volume processing. In at least one embodiment, resource manager 1126 may be capable of managing clustered or grouped computing resources associated with supporting distributed file system 1128 and job scheduler 1122. In at least one embodiment, clustered or grouped computing resources may include grouped computing resources 1114 at data center infrastructure layer 1110. In at least one embodiment, resource manager 1126 may coordinate with resource orchestrator 1112 to manage these allocated or allocated computing resources.In at least one embodiment, software 1132 included in software layer 1130 may include software used by at least portions of nodes C.R.s 1116( 1)-1116(N), grouped computing resources 1114, and / or distributed file system 1128, of framework layer 1120. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scan software, database software, and streaming video content software.In at least one embodiment, application(s) 1142 included in application layer 1140 may include one or more types of applications used by at least portions of nodes C.R.s 1116( 1)- 1116(N), grouped computing resources 1114, and / or distributed file system 1128 of framework layer 1120. In at least one embodiment, one or more types of applications may include any number of a genomic application, a cognitive computing application, and a machine learning application, including, but not limited to, training or inferencing software, machine learning framework software (e.g., PyTor, TensorFlow, Coffee, etc.), or other machine learning applications used in connection with one or more embodiments.In at least one embodiment, configuration manager 1124, resource manager 1126, and resource orchestrator 1112 may implement any number and type of self-modifying actions based on any amount and type of data captured in any technically feasible manner. In at least one embodiment, self-modifying actions may offload a data center operator of data center 1100 from making potentially bad configuration decisions and may avoid unutilized and / or malfunctioning portions of a data center.In at least one embodiment, data center 1100 may include tools, services, software, or other resources to train one or more machine learning models or predict or derive information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by computing weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 1100. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to derive or predict information using resources described above with respect to data center 1100 by using weighting parameters calculated by one or more training techniques described herein.In at least one embodiment, data center may use CPUs, application specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using resources described above. Moreover, one or more of the software and / or hardware resources described above may be configured as a service to enable users to train or inferencing information such as image recognition, speech recognition, or other artificial intelligence services.Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 in data center 1100 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, at least one component shown or described in FIGS. 9A-11 is used to implement techniques and / or functions described in connection with FIGS. 1-6. In at least one embodiment, logic 915 performs one or more aspects of scaling values according to differential order and as otherwise further described herein, including at least in connection with FIG. 1.AUTONOMOUS VEHICLEFIG. 12A shows an example of an autonomous vehicle 1200, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1200 (alternatively referred to herein as "vehicle 1200") may be, without limitation, a passenger car, such as a passenger car, truck, bus, and / or other type of vehicle that receives one or more passengers. In at least one embodiment, vehicle 1200 may be a semi-trailer used for transporting goods. In at least one embodiment, vehicle 1200 may be an aircraft, robotic vehicle, or other type of vehicle.Autonomous vehicles may be described in terms of automation levels defined by the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Ministry of Traffic, and the Society of Automotive Engineers ("SAE") "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806 published June 15, 1718 Standard No. J3016-20169 published September 27, 1716 as well as earlier and future versions of this standard). In at least one embodiment, vehicle 1200 may be capable of performing functions according to one or more of autonomous driving levels 1 through 5. For example, in at least one embodiment, vehicle 1200 may be capable of conditional automated (stage 3), highly automated (stage 4), and / or fully automated (stage 5), depending on the embodiment.In at least one embodiment, vehicle 1200 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 15, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1200 may include, without limitation, a propulsion system 1250, such as an internal combustion engine, a hybrid electric power plant, a pure electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1250 may be connected to a powertrain of vehicle 1200, which may include, without limitation, a transmission to enable propulsion of vehicle 1200. In at least one embodiment, propulsion system 1250 may be controlled in response to receiving signals from accelerator pedal / accelerator(s) 1252.In at least one embodiment, a steering system 1254, which may include, without limitation, a steering wheel, is used to steer vehicle 1200 (e.g., along a desired path or route) when drive system 1250 is operating (e.g., when vehicle 1200 is in motion). In at least one embodiment, steering system 1254 may receive signals from steering actuator(s) 1256. At least in one embodiment, a steering wheel for full automation (Level 5) may be optional. In at least one embodiment, a brake sensor system 1246 may be used to actuate vehicle brakes in response to receiving signals from brake actuator(s) 1248 and / or brake sensors.In at least one embodiment, controllers 1236 which may include, without limitation, one or more system-on-chips ("SoCs") (not shown in FIG. 12A ) and / or graphics processing units ("GPUs") provide signals (e.g., representative of commands) to one or more components and / or systems of vehicle 1200. For example, in at least one embodiment, controller 1236 may send signals to actuate vehicle brakes via brake actuator(s) 1248; actuate steering system 1254 via steering actuator(s) 1256, and actuate propulsion system 1250 via accelerator pedal / accelerator device(s) 1252. In at least one embodiment, controller(s) 1236 may include one or more onboard (e.g., integrated) computing devices that process sensor signals and issue operating commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving vehicle 1200. In at least one embodiment, controller(s) 1236 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence (e.g., computer vision) functions, a fourth controller for infotainment functions, a fifth controller for redundancy in emergency cases, and / or other controllers. In at least one embodiment, a single controller may perform two or more of the above-mentioned functions, two or more controllers may perform a single function, and / or any combination thereof.In at least one embodiment, controller(s) 1236 provide signals to control one or more components and / or systems of vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be transmitted, for example and without limitation, to (a) global navigation satellite system ("GNSS") sensor(s) 1258 (e.g., global positioning system sensor(s)), (a) RADAR sensor(s) 1260, (an) ultrasonic sensor(s) 1262, (a) LIDAR sensor(s) 1264, (a) inertial measurement unit ("IMU") sensor(s) 1266 (e.g., accelerometer, gyroscope(s), magnetic compass or magnetic compass, magnetometer, etc.), microphone(s) 1296, stereo camera(s) 1268, wide angle camera(s) 1270 (e.g., fish eye cameras), infrared camera(s) 1272, Environmental camera(s) 1274 (e.g., 330 degree cameras), remote cameras (not shown in FIG. 12A ), mid-range camera(s) (not shown in FIG. 12A ), speed sensor(s) 1244 (e.g., for measuring the speed of the vehicle 1200), vibration sensor(s) 1242, steering sensor(s) 1240, brake sensor(s) (e.g., as part of the brake sensor system 1246), and / or other types of sensors.In at least one embodiment, one or more controllers 1236 may receive input (e.g., in the form of input data) from an instrument cluster 1232 of vehicle 1200 and provide output (e.g., in the form of output data, display data, etc.) via a human-machine interface ("HMI") display 1234, an acoustic detector, a speaker, and / or via other components of vehicle 1200. In at least one embodiment, outputs may include information such as vehicle speed, speed, time, map data (e.g., a high resolution map (not shown in FIG. 12A )), location data (e.g., location of vehicle 1200 such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects, and status of objects as perceived by controller(s) 1236, etc. For example, in at least one embodiment, HMI display 1234 may display information about presence of one or more objects (e.g., a road sign, a warning sign, a changing traffic light, etc.) and / or information about driving maneuvers that vehicle has performed, performed, or will perform (e.g., lane change now, two-miles exit 31B, etc.).In at least one embodiment, vehicle 1200 further includes a network interface 1224 that may use wireless antenna(s) 1226 and / or modem(s) for communication over one or more networks. For example, in at least one embodiment, network interface 1224 may be capable of communicating via long-term evolution ("LTE"), wideband code division multiple access ("WCDMA"), universal mobile telecommunications system ("UMTS"), global system for mobile communication ("GSM"), IMT-CDMA multi-carrier ("CDMA2000") networks, etc. In at least one embodiment, wireless antenna(s) 1226 may also enable communication between objects in environment (e.g., vehicles, mobile devices, etc.) by using local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or Low Power Wide Area Networks ("LPWANs") such as LoRaWAN, SigOx, etc.Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 in vehicle 1200 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, at least one component shown or described in FIG. 12A is used to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, wireless antenna(s) 1226 is(are) used to transmit and / or receive one or more wireless signals using hybrid beamforming parameters and / or transmit powers derived from a neural network as described in connection with FIG. 1 and as otherwise described herein.FIG. 12B shows an example of camera positions and fields of view for the autonomous vehicle 1200 of FIG. 12A, according to at least one embodiment. In at least one embodiment, cameras and respective fields of view represent an example embodiment and are not to be considered limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be disposed at different locations of vehicle 1200.In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of vehicle 1200. In at least one embodiment, camera(s) may operate at Automotive Safety Integrity Level ("ASIL") B and / or on another ASIL. In at least one embodiment, camera types may achieve any image capture rate, such as 60 images per second (fps), 920 fps, 210 fps, etc., depending on embodiment. In at least one embodiment, cameras may use rolling shutters, global shutters, another type of shutter, or a combination thereof. In at least one embodiment, color filter array may include a red-clear-clear color filter array ("RCCC"), a red-clear-blue color filter array ("RCCB"), a red-blue-green-clear color filter array ("RBGC"), a Foveon X3 color filter array, a Bayer sensor color filter array ("RGGB"), a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, RCCB, and / or RBGC color filter array, may be used to increase photosensitivity.In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). Thus, in at least one embodiment, a multi-function monocamera may be installed that includes functions such as lane keeping assist, road sign assist, and smart headlight control. In at least one embodiment, one or more of cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).In at least one embodiment, one or more cameras may be mounted in a mounting device, such as a custom designed (three-dimensional ("3D") printed) device, to eliminate stray light and reflections within vehicle 1200 (e.g., reflections from dashboard reflected in windshield mirrors), which may interfere with camera image capture capability. In at least one embodiment, exterior mirror assemblies may be custom 3D printed such that a camera mounting plate is in the form of an exterior mirror. At least in one embodiment, camera(s) may be integrated into the exterior mirrors. In at least one embodiment, in side cameras, camera(s) may also be integrated into four columns at each corner of the cabin.In at least one embodiment, cameras having a field of view that includes portions of an environment in front of vehicle 1200 (e.g., front facing cameras) may be used for surround vision to help identify front facing paths and obstacles, and to provide information relevant to creating an occupancy grid and / or determining preferred vehicle paths using one or more controllers 1236 and / or control SoCs. In at least one embodiment, forward facing cameras may be used to perform many similar ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, forward-facing cameras may also be used for ADAS functions and systems including, without limitation, lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or other functions such as road sign recognition.In at least one embodiment, a plurality of cameras may be used in a forward-facing configuration, including, for example, a monocular camera platform that includes a complementary metal oxide semiconductor (CMOS) color imager. In at least one embodiment, a wide-angle camera 1270 may be used to detect objects that are in field of view from periphery (e.g., pedestrians, crossing traffic, or bicycles). Although only one wide-angle camera 1270 is shown in FIG. 12B, in other embodiments, the vehicle 1200 may include any number (including zero) of wide-angle cameras. In at least one embodiment, any number of long-range cameras 1298 (e.g., a wide-angle stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, wide-angle camera(s) 1298 may also be used for object detection and classification as well as for basic object tracking.In at least one embodiment, any number of stereo camera(s) 1268 may also include in a forward-facing configuration. In at least one embodiment, one or more of stereo camera(s) 1268 may include an integrated control unit including a scalable processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with a controller area network ("CAN") or Ethernet integrated interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of vehicle 1200 environment that includes a distance estimate for all points in an image. In at least one embodiment, one or more of stereo camera(s) 1268 may include, without limitation, compact stereo vision sensor(s) that may / may include, without limitation, two camera lenses (one left and right each) and an image processing chip that may measure distance between vehicle 1200 and target object and use generated information (e.g., metadata) to enable autonomous emergency braking and lane keeping warning functions. In at least one embodiment, other types of stereo cameras ( 1568) may also be used in addition to or as an alternative to stereo cameras described herein.In at least one embodiment, cameras having a field of view that includes portions of environment at sides of vehicle 1200 (e.g., side cameras) may be used for environment view and provide information used to create and update an occupancy grid as well as to generate collision warnings upon side impact. In at least one embodiment, for example, surround camera(s) 1274 (e.g., four surround cameras as shown in FIG. 12B ) could be positioned on vehicle 1200. In at least one embodiment, surround camera(s) 1274 may include, without limitation, any number and combination of wide-angle cameras, fish-eye cameras, 330-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fish eye cameras may be positioned at the front, rear, and sides of vehicle 1200. In at least one embodiment, vehicle 1200 may use three surround camera(s) 1274 (e.g., left, right, and rear) and utilize one or more other camera(s) (e.g., a front facing camera) as a fourth surround view camera.In at least one embodiment, at least one component shown or described in FIGS. 12A-12B is used to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, wireless antenna(s) 1226 transmit and / or receive signals using hybrid beamforming parameters and / or transmit powers derived from a neural network described in connection with FIG. 1, and as described elsewhere herein.In at least one embodiment, one or more methods, systems, or processes depicted in FIG. 12B are used to use one or more neural networks to blend two or more images based on one or more confidence values below a first threshold, using various algorithms, formulas, and processes as described in connection with FIG. 1, and / or to perform other operations described herein. In at least one embodiment, one or more systems depicted in FIG. 12B are used to implement one or more systems and / or processes as described in connection with FIGS. 1-11.FIG. 12C is a block diagram illustrating an example system architecture for the autonomous vehicle 1200 of FIG. 12A, according to at least one embodiment. In at least one embodiment, each of vehicle 1200 components, features, and systems is shown connected via a bus 1202 in FIG. 12C. In at least one embodiment, bus 1202 may include, without limitation, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, a CAN may be a network within vehicle 1200 used to assist in controlling various features and functions of vehicle 1200, such as actuation of brakes, acceleration, brakes, steering, windshield wipers, etc. In at least one embodiment, bus 1202 may be configured to include dozens or even hundreds of nodes, each having its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1202 may be read to determine steering wheel angle, vehicle speed, engine speed per minute (RPM), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1202 may be a CAN bus that is ASIL B compliant.In at least one embodiment, FlexRay and / or Ethernet protocols may also be used in addition to or as an alternative to CAN. In at least one embodiment, there may be any number of buses forming bus 1202, which may include, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses with different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for the collision avoidance functionality and a second bus may be used for the actuation control. In at least one embodiment, each bus of bus 1202 may communicate with any components of vehicle 1200, and two or more buses of bus 1202 may communicate with corresponding components. In at least one embodiment, any of any number of system(s) on chip(s) ("SoC(s)") 1204 (such as SoC 1204(A) and SoC 1204(B)), each of controllers 1236, and / or each computer within vehicle may have access to same input data (e.g., inputs from sensors of vehicle 1200), and may be connected to a common bus, such as CAN bus.In at least one embodiment, vehicle 1200 may include one or more controller(s) 1236 as described herein with respect to FIG. 12A. In at least one embodiment, controller(s) 1236 may be used for a plurality of functions. In at least one embodiment, controller(s) 1236 may be coupled to various other components and systems of vehicle 1200 and used for control of vehicle 1200, artificial intelligence of vehicle 1200, infotainment for vehicle 1200, and / or other functions.In at least one embodiment, vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of SoCs 1204 may include, without limitation, central processing units ("CPU(s)") 1206, graphics processors ("GPU(s)") 1208, processor(s) 1210, cache(s) 1212, accelerators 1214, data storage 1216, and / or other components and features not shown. In at least one embodiment, SoC(s) 1204 may be used to control vehicle 1200 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1204 may be combined in a system (e.g., vehicle 1200 system) with a high definition ("HD") map 1222, which may receive map refreshes and / or updates via network interface 1224 from one or more servers (not shown in FIG. 12C ).In at least one embodiment, CPU(s) 1206 may comprise a CPU cluster or complex (alternatively referred to herein as "CCPLEX"). In at least one embodiment, CPU(s) 1206 may include multiple cores and / or level two ("L2") caches. In at least one embodiment, CPU(s) 1206 may include, for example, eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU(s) 1206 may include four dual core clusters, each cluster having a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, CPU(s) 1206 (e.g., CCPLEX) may be configured to support concurrent clustering operations such that any combination of clusters of CPU(s) 1206 may be active at a particular time.In at least one embodiment, one or more of CPU(s) 1206 may implement power management functions that include, without limitation, one or more of following functions, individual hardware blocks may be automatically idle clocked to conserve dynamic power; each core clock may be clocked when such a core is not actively executing instructions due to execution of wait for interrupt ("WFI") / wait for event ("WFE") instructions; each core may be independently power controlled; each core cluster may be independently clock controlled when all cores are clock controlled or power controlled; and / or each core cluster may be independently power controlled when all cores are power controlled. In at least one embodiment, CPU(s) 1206 may further implement an enhanced power state management algorithm where allowed power states and expected wake-up times are specified and hardware / microcode determines which power state is most suitable for core, cluster, and CCPLEX. In at least one embodiment, processor cores may support simplified sequences for power state entry in software, offloading work to microcode.In at least one embodiment, GPU(s) 1208 may include an integrated GPU (alternatively referred to herein as "iG"). In at least one embodiment, GPU(s) 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU(s) 1208 may use an extended tensor instruction set. In at least one embodiment, GPU(s) 1208(s) may include one or more streaming microprocessors, where each streaming microprocessor may include a level one ("L1") cache (e.g., an L1 cache having a storage capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having a storage capacity of 512 KB). In at least one embodiment, GPU(s) 1208 may include at least eight streaming microprocessors. In at least one embodiment, GPU(s) 1208 may use one or more application programming interfaces (API(s)) for computations. In at least one embodiment, GPU(s) 1208 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).In at least one embodiment, one or more of GPU(s) 1208 may be energy optimized for best performance in automotive and embedded use cases. In at least one embodiment, GPU(s) 1208 may be fabricated on fin field effect transistor ("FinFET") circuits, for example. In at least one embodiment, each streaming microprocessor may include a number of mixed precision computing cores divided into multiple blocks. For example, 64 PF32 cores and 32 FP64 cores could be divided into four processing blocks. In at least one embodiment, each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 13 INT32 cores, two mixed precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero ("L0") instruction cache, a scheduler (e.g., warp scheduler) or sequencer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating point data paths to enable efficient execution of workloads with a mixture of computations and addressing computations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capabilities to enable finer grain synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may include a combined L1 data cache and a shared memory unit to improve performance while simplifying programming.In at least one embodiment, one or more of GPU(s) 1208 may include high bandwidth memory ("HBM") and / or a 13 GB HBM2 memory subsystem to provide a peak memory bandwidth of about 900 GB / second, in some examples. In at least one embodiment, in addition to or as an alternative to HBM memory, synchronous graphics random access memory ("SGRAM") may be used, such as dual data rate synchronous random access memory type 5 ("GDDR5").In at least one embodiment, GPU(s) 1208 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow GPU(s) 1208 to directly access page tables of CPU(s) 1206. In at least one embodiment, an address translation request may be sent to CPU(s) 1206 if a GPU of GPU(s) 1208 memory management unit ("MMU") fails. In response, the CPU of the CPU(s) 1206 may search in its page tables for a virtual physical mapping for an address and transmit the translation back to the GPU(s) 1208, in at least one embodiment. In at least one embodiment, unified memory technology may enable a single unified virtual address space for memory of both CPU(s) 1206 and GPU(s) 1208, thereby facilitating programming of GPU(s) 1208 and porting applications to GPU(s) 1208.In at least one embodiment, GPU(s) 1208 may include any number of access counters that may track frequency of GPU(s) 1208 accessing other processor memory. In at least one embodiment, access counters may help move memory pages into physical memory of a processor that most frequently accesses pages, thereby improving efficiency of memory areas shared by processors.In at least one embodiment, one or more of SoC(s) 1204 may include any number of cache(s) 1212, including those described herein. In at least one embodiment, cache(s) 1212 may include, for example, a level 3 cache ("L3") available to both CPU(s) 1206 and GPU(s) 1208 (e.g., coupled to CPU(s) 1206 and GPU(s) 1208). In at least one embodiment, cache(s) 1212 may include a write back cache that may track states of lines, for example, by using a cache coherency protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache may include 4 MB memory or more, depending on embodiment, although smaller cache sizes may also be used.In at least one embodiment, one or more of SoC(s) 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC(s) 1204 may include a hardware accelerator cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB SRAM) may allow a hardware accelerator cluster to accelerate neural networks and other computations. In at least one embodiment, a hardware accelerator cluster may be used to supplement GPU(s) 1208 and offload some tasks of GPU(s) 1208 (e.g., to enable more cycles of GPU(s) 1208 to perform other tasks). In at least one embodiment, accelerator(s) 1214 could be used for targeted workloads (e.g., perception, convolutional neural networks ("CNNs"), recurrent neural networks ("RNNs"), etc.) that are stable enough to be suitable for acceleration. In at least one embodiment, a CNN may include a region-based or regional neural network ("RCNNs") and fast RCNNs (e.g., for object detection) or other type of CNN.In at least one embodiment, accelerator(s) 1214 (e.g., hardware accelerator clusters) may include one or more deep learning accelerators ("DLA"). In at least one embodiment, DLA(s) may include, without limitation, one or more tensor processing units ("TPUs"), which may be configured to provide an additional ten billion operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured and optimized for performing image processing functions (e.g., CNNs, RCNNs, etc.). In at least one embodiment, DLA(s) may be further optimized for a particular set of neural network types and floating point operations, as well as for inferencing. In at least one embodiment, DLA(s) design can provide more performance per millimeter than a typical general purpose GPU and typically far outfits performance of a CPU. In at least one embodiment, TPU(s) may perform multiple functions, including a single instance convolution function that supports, for example, INT8, INT16, and FP16 data types for both features and weights, as well as postprocessor functions. In at least one embodiment, DLA(s) may quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for a variety of functions including, for example and without limitation: a CNN for identifying and recognizing objects using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for detecting and identifying emergency vehicles and recognition using data from microphones; a CNN for face recognition and identifying vehicle owners using data from camera sensors; and / or a CNN for safety-related and / or safety-related events.In at least one embodiment, DLA(s) may execute each function of GPU(s) 1208, and by using an inference accelerator, for example, a developer may provide either DLA(s) or GPU(s) 1208 for each function. For example, in at least one embodiment, a developer may focus processing CNNs and floating point operations on DLA(s) and leave other functions GPU(s) 1208 and / or accelerator(s) 1214.In at least one embodiment, accelerator(s) 1214 may include a programmable image processing accelerator ("PVA"), which may also be referred to herein as a computer vision accelerator. In at least one embodiment, PVA may be designed and configured to speed up computer vision algorithms for advanced driver assistance systems ("ADAS") 1238, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, PVA may provide a balance between performance and flexibility. In at least one embodiment, each PVA may include, for example and without limitation, any number of reduced instruction set computing cores ("RISC"), direct memory access ("DMA"), and / or any number of vector processors.In at least one embodiment, RISC cores may cooperate with image sensors (e.g., image sensors of cameras described herein), image signal processors, etc. In at least one embodiment, each RISC core may comprise any amount of memory. In at least one embodiment, RISC cores may use any number of protocols depending on embodiment. In at least one embodiment, RISC cores may execute a real-time operating system ("RTOS"). In at least one embodiment, RISC cores may be implemented with one or more integrated circuits, application specific integrated circuits ("ASICs"), and / or memory devices. In at least one embodiment, RISC cores could include, for example, an instruction cache and / or a close coupled RAM.In at least one embodiment, DMA may allow components of PVA to access system memory independent of CPU(s) 1206. In at least one embodiment, DMA may support any number of features used to optimize a PVA, including, but not limited to, support multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block locking, vertical block locking, and / or depth locking.In at least one embodiment, vector processors may be programmable processors that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, a vector processing subsystem may operate as a primary processing unit of a PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, VPU core may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), and very long instruction words ("VLIW") digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may increase throughput and speed.In at least one embodiment, each of vector processors may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each of vector processors may be configured to operate independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to use data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may concurrently execute different image processing algorithms for an image, or even different algorithms for successive images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, among other things, and each PVA may include any number of vector processors. In at least one embodiment, PVA may include additional error correction code ("ECC") memory to increase overall system security.In at least one embodiment, accelerator(s) 1214 may include an on-chip computer vision network and a static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to accelerator(s) 1214. In at least one embodiment, on-chip memory may include at least 4 MB SRAM, for example and without limitation, eight array configurable memory blocks that may be accessed by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an extended peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, a PVA and a DLA may access memory via a backbone that allows a PVA and a DLA to access memory at high speed. In at least one embodiment, a backbone may include an on-chip computer vision network that connects a PVA and a DLA to memory (e.g., using APB).In at least one embodiment, a computer vision network on chip may include an interface that determines that both a PVA and a DLA provide ready and valid signals prior to transmission of control signals / addresses / data. In at least one embodiment, an interface may provide separate phases and separate channels for transmission of control signals / addresses / data, as well as burst communication for continuous data transmission. In at least one embodiment, an interface may comply with International Organization for Standardization ("ISO") 23262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may also be used.In at least one embodiment, one or more of SoC(s) 1204 may include a real-time ray tracing hardware accelerator. In at least one embodiment, real-time ray tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model), to generate real-time visualization simulations, for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for purposes of localization and / or for other functions and / or for other purposes.In at least one embodiment, accelerator / accelerators 1214 may include a wide range of uses for autonomous driving. In at least one embodiment, a PVA may be used for important processing steps in ADAS and autonomous vehicles. In at least one embodiment, PVA capabilities are well suited for algorithmic areas requiring predictable processing at low power and low latency. In other words, a PVA lends itself well to semi-dense or dense regular computations, even for small data sets requiring predictable low latency, low power consumption runtimes. In at least one embodiment, such as in vehicle 1200, PVAs may be configured to execute classical computer vision algorithms because they are efficient in object detection and processing integer mathematical data.For example, according to at least one embodiment of the technology, a PVA is used to perform computer stereo vision. In at least one embodiment, in some examples, a semi-global matching based algorithm may be used, although this is not intended to be limiting. In at least one embodiment, in autonomous driving applications of stages 3 through 5, a flying motion estimation / stereo matching is used (e.g., structure of motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras.In at least one embodiment, a PVA may be used to perform a dense optical flow. In at least one embodiment, a PVA could process raw RADAR data (e.g., using a 4D fast Fourier transform) to provide processed RADAR data, for example. In at least one embodiment, a PVA is used for time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data, for example.In at least one embodiment, a DLA may be used to operate any type of network to improve control and driving safety, including, for example and without limitation, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as a relative "weight" of each recognition as compared to other recognitions. In at least one embodiment, a confidence measure allows system to make further decisions about which detections should be considered true positive detections and which should be considered false positive detections. In at least one embodiment, a system may set a threshold for confidence measure and consider only detections exceeding threshold as true positive detections. In an embodiment where an automatic emergency braking system ("AEB") is used, false positive detections would result in the vehicle automatically performing emergency braking, which is, of course, undesirable. In at least one embodiment, very secure detections may be considered triggers for AEB. In at least one embodiment, a DLA may employ a neural network to regression confidence value. In at least one embodiment, neural network may use as input at least a subset of parameters, such as bounding box dimensions, ground plane estimate obtained (e.g., from another subsystem), output of IMU sensor / s 1266 correlated with vehicle 1200 orientation, distance, object 3D position estimates obtained from neural network and / or other sensors (e.g., LIDAR sensor(s) 1264 or RADAR sensor(s) 1260), and others.In at least one embodiment, one or more SoC(s) 1204 may include one or more data stores 1216 (e.g., memory). In at least one embodiment, data store(s) 1216 may be an on-chip memory of SoC(s) 1204, which may (may) store neural network(s) to be executed on GPU(s) 1208 and / or a DLA. In at least one embodiment, data store(s) 1216 may be large enough to store multiple instances of neural networks for redundancy and security. In at least one embodiment, data store(s) 1216 may include L2 or L3 cache(s).In at least one embodiment, one or more of SoC(s) 1204 may include any number of processor(s) 1210 (e.g., embedded processors). In at least one embodiment, processor(s) 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and associated security enforcement. In at least one embodiment, a boot and power management processor may be part of a boot sequence of SoC(s) 1204 and provide runtime power management services. In at least one embodiment, a boot power supply and management processor may provide clock and voltage programming, support for low power system transitions, management of SoC(s) 1204 temperatures and temperature sensors, and / or management of SoC(s) 1204 power supply states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and SoC(s) 1204 may use ring oscillators to sense temperatures of CPU(s) 1206, GPU(s) 1208, and / or accelerator(s) 1214. In at least one embodiment, if temperatures are determined to exceed a threshold, a boot and power management processor may enter a temperature fault routine and place SoC(s) 1204 in a lower power state and / or place vehicle 1200 in a chauffeur-to-safe stop mode (e.g., place vehicle 1200 in a safe stop).In at least one embodiment, processor(s) 1210 may further include a series of embedded processors that may serve as an audio processing engine, which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces as well as a wide and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processor core with a dedicated RAM digital signal processor.In at least one embodiment, processor(s) 1210 may further include an "ways on" processor engine that may provide necessary hardware functions to support low power sensor management and wake-use cases. In at least one embodiment, an "ways on" processor engine may include, without limitation, a processor core, close coupled memory, supporting peripherals (e.g., timers and interrupt controllers), various peripherals of I / O controller, and routing logic.In at least one embodiment, processor(s) 1210 may further include a security cluster engine that includes, without limitation, a dedicated processor subsystem for handling security management for automotive applications. In at least one embodiment, a security cluster engine may include, without limitation, two or more processor cores, close coupled memory, supporting peripheral devices (e.g., timers, interrupt control, etc.), and / or routing logic. In a safety mode, in at least one embodiment, two or more cores may operate in a lockstep mode and function as a single core with compare logic to detect any differences between their operations. In at least one embodiment, processor(s) 1210 may further include a real-time camera engine, which may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor(s) 1210 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline.In at least one embodiment, processor(s) 1210 may comprise a video image combiner, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions needed by a video playback application to generate a final image for a player window. In at least one embodiment, a video image combiner may make a lens distortion correction at wide-angle camera(s) 1270, at surround camera(s) 1274, and / or at monitoring camera(s) sensors in cabin. In at least one embodiment, monitoring camera(s) sensor(s) in cabin is / are preferably monitored by a neural network running on another instance of SoC 1204 and configured to detect and respond to events in cabin. In at least one embodiment, an in-vehicle system may perform lipread without limitation to activate cellular service and place a call, dictate EMails, change destination, activate or change infotainment system and vehicle settings, or enable voice-controlled browsing on Internet. In at least one embodiment, certain features are available to driver when a vehicle is operating in an autonomous mode and are otherwise disabled.In at least one embodiment, a video image compositor may include improved temporal noise suppression for both spatial and temporal noise suppression. For example, in at least one embodiment in which motion occurs in a video, noise suppression appropriately weights spatial information, thereby reducing weight of information provided by adjacent frames. In at least one embodiment where an image or portion of an image does not include motion, temporal noise suppression performed by the video image compositor may use information from a previous image to reduce noise in the current image.In at least one embodiment, a video image combiner may also be configured to perform stereo rectification on input stereo objective images. In at least one embodiment, a video image compositor may be further used for user interface compilation when an operating system desktop is in use and GPU(s) 1208 are not required to continuously render new surfaces. In at least one embodiment, a video image compositor may be used to offload GPU(s) 1208 to improve performance and responsiveness when GPU(s) 1208 are turned on and actively perform 3D rendering.In at least one embodiment, one or more SoC of SoC(s) 1204 may further include a MIPI serial camera interface for receiving video and inputs from cameras, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functions. In at least one embodiment, one or more of SoC(s) 1204 may further include one or more input / output controllers that may be controlled by software and used to receive I / O signals that are not associated with a particular role.In at least one embodiment, one or more SoC of SoC(s) 1204 may further include a wide range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, SoC(s) 1204 may be used to obtain data from cameras (e.g., via gigabit multimedia serial link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1264, RADAR sensor(s) 1260, etc., which may be connected via Ethernet channels), data from bus 1202 (e.g., vehicle speed 1200, steering wheel position, etc.), data from GNSS sensor(s) 1258 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more SoC of SoC(s) 1204 may further comprise dedicated high-performance mass storage controllers, which may include their own DMA engines and which may be used, This is to free the CPU(s) 1206 from routine data management tasks.In at least one embodiment, SoC(s) 1204(s) may be an end-to-end platform with a flexible architecture spanning automation levels 3-5, thereby providing a comprehensive functional safety architecture that uses computer vision and ADAS techniques for diversity and redundancy and provides a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, SoC(s) 1204 may be faster, more reliable, and even more energy and space saving than conventional systems. For example, in at least one embodiment, accelerators 1214, in combination with CPU(s) 1206, GPU(s) 1208, and data store(s) 1216, may form a fast, efficient level 3-5 autonomous vehicle platform.In at least one embodiment, computer vision algorithms can be executed on CPUs that can be configured with a high-level language such as C to execute a plurality of processing algorithms for a plurality of visual data. However, in at least one embodiment, CPUs are often unable to meet performance requirements of many image processing applications, such as execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real-time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.The embodiments described herein enable multiple neural networks to be executed simultaneously and / or sequentially and the results combined together to enable the level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., GPU(s) 1220) may have text and word recognition that enables reading and understanding traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network capable of identifying, interpreting, and semantically understanding a character and passing this semantic understanding to path planning modules running on a CPU complex.In at least one embodiment, multiple neural networks may run simultaneously, such as when driving level 3, 4, or 5. For example, in at least one embodiment, a warning sign may be interpreted independently or jointly with an electrical light from multiple neural networks, titled "Caution: Flashing lights indicate Smoothis.". At least in one embodiment, such a warning sign itself may be identified as traffic signs by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate ice smoothness" may be interpreted by a second deployed neural network that informs a vehicle's path planning software (preferably executed on a CPU complex) that when flashing lights are detected, ice smoothness is present. In at least one embodiment, a turn signal may be identified by operation of a third neural network over multiple frames informing path planning software of a vehicle of presence (or absence) of turn signals. In at least one embodiment, all three neural networks may run simultaneously, for example within a DLA and / or on GPU(s) 1208.In at least one embodiment, a CNN for face recognition and vehicle owner identification may use data from camera sensors to identify presence of an authorized driver and / or owner of vehicle 1200. In at least one embodiment, an "ways on" sensor processing engine may be used to unlock a vehicle when an owner approaches a driver door and turns lights on, and to disable such a vehicle in a security mode when an owner leaves such a vehicle. In this way, the SoC(s) 1204 provide security against theft and / or carjacking.In at least one embodiment, a emergency vehicle detection and identification CNN may use data from microphones 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s) 1204 use a CNN to classify environmental and urban sounds as well as to classify visual data. In at least one embodiment, a CNN running on a DLA is trained to detect a relative approach speed of a emergency vehicle (e.g., using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is in progress as identified by GNSS sensors 1258. In at least one embodiment, a CNN when used in Europe will attempt to identify European sirens, and when used in North America, a CNN will attempt to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slow a vehicle, drive to roadside, park a vehicle, and / or idle a vehicle using ultrasonic sensors 1262 until emergency vehicles pass.In at least one embodiment, vehicle 1200 may include one or more CPU(s) 1218 (e.g., discrete CPU(s) or dCPU(s)), which may be connected to SoC(s) 1204 via a high-speed link (e.g., PCIe). In at least one embodiment, CPU(s) 1218 may include, for example, an X86 processor. The CPU(s) 1218 may / may be used to perform a variety of functions, including arbitration for potentially conflicting results between ADAS sensors and SoC(s) 1204, and / or monitoring the status and state of the controller(s) 1236 and / or an infotainment system on a chip ("Infotainment SoC") 1230, for example. In at least one embodiment, SoC (SoCs) 1204 includes one or more interconnects, and an interconnect may include a peripheral component interconnect express (PCIe).In at least one embodiment, vehicle 1200 may include GPU(s) 1220 (e.g., discrete GPU(s) or dG(s)), which may be coupled to SoC(s) 1204 via a high-speed link (e.g., NVIDIAs NVLINK channel). In at least one embodiment, GPU(s) 1220 may provide additional artificial intelligence functionality, for example, by executing redundant and / or different neural networks, and may be used (may) to train and / or update neural networks based at least in part on input data (for example, sensor data) from sensors of a vehicle 1200.In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include, without limitation, one or more wireless antennas 1226 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1224 may be used to enable wireless connectivity to Internet cloud services (e.g., with servers and / or other network devices), other vehicles, and / or computing devices (e.g., passenger client devices). In at least one embodiment, a direct connection between vehicle 1200 and another vehicle and / or an indirect connection (e.g., via networks and Internet) may be established for communication with other vehicles. In at least one embodiment, direct connections may be established via a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles proximate vehicle 1200 (e.g., vehicles in front of, beside, and / or behind vehicle 1200). In at least one embodiment, this aforementioned functionality may be part of a cooperative adaptive cruise control function of vehicle 1200.In at least one embodiment, network interface 1224 may include a SoC that provides modulation and demodulation functions and enables controller(s) 1236 to communicate over wireless networks. In at least one embodiment, network interface 1224 may include a radio frequency front end for up-converting from baseband to radio frequency and down-converting from radio frequency to baseband. In at least one embodiment, frequency transformations may be performed in any technically possible manner. For example, frequency transformations can be performed by known methods and / or using super heterodyne methods. In at least one embodiment, radio frequency front-end functionality may be provided by a separate chip. In at least one embodiment, network interfaces may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWA, and / or other wireless protocols.In at least one embodiment, vehicle 1200 may further include one or more data stores 1228, which may include, without limitation, off-chip memory (e.g., off-SoC(s) 1204). In at least one embodiment, data store(s) 1228 may include, without limitation, one or more memory elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, hard drives, and / or other components and / or devices capable of storing at least one bit of data.In at least one embodiment, vehicle 1200 may further include GNSS sensor(s) 1258 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid creation, and / or path planning. In at least one embodiment, any number of GNSS sensor(s) 1258 may be used, including, for example and without limitation, a GPS using a USB port with an Ethernet-to-serial bridge (e.g., RS-202).In at least one embodiment, vehicle 1200 may further include RADAR sensors 1260. In at least one embodiment, RADAR sensor(s) 1260 from vehicle 1200 may be used by vehicle 1200 for detecting long range vehicles, even in darkness and / or bad weather conditions. In at least one embodiment, functional RADAR security levels may be ASIL B. In at least one embodiment, RADAR sensor(s) 1260 may use a CAN bus and / or bus 1202 (e.g., to transmit data generated by RADAR sensor(s) 1260) to control and access object tracking data, in some examples, access to raw data via Ethernet channels. In at least one embodiment, a wide range of RADAR sensors may be used. For example, and without limitation, RADAR sensor(s) 1260 may be suitable for use as front, rear, and side RADARs. In at least one embodiment, one or more sensors of RADAR sensor / sensors 1260 is a pulse-doppler RADAR sensor.In at least one embodiment, RADAR sensor(s) 1260 may include various configurations, such as narrow field of view long range, wide field of view short range, side close range coverage, etc. In at least one embodiment, long range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long range RADAR systems may provide a wide field of view realized by two or more independent scans, for example, within a range of 220 m (meters). In at least one embodiment, RADAR sensor(s) 1260 may aid in distinguishing between static and moving objects and may be used by ADAS system 1238 for emergency brake assist and forward collision warning. In at least one embodiment, sensor(s) 1260 included in a long range RADAR system(s) may (are) include, without limitation, a monostatic multimode RADAR having multiple (e.g., six or more) fixed RADAR antennas and a high speed CAN and FlexRay interface. In at least one embodiment with six antennas, four antennas in the center may generate a focused beam pattern that serves to sense the environment of the vehicle at higher speeds with minimal interference from traffic in the adjacent lanes. In at least one embodiment, two other antennas may extend field of view so that vehicles entering or leaving a lane of vehicle 1200 may be quickly detected.In at least one embodiment, medium range RADAR systems may include, for example, a range of up to 130 m (forward) or 80 m (rearward) and a field of view of up to 39 degrees (forward) or 120 degrees (rearward). In at least one embodiment, short range RADAR systems may include, without limitation, any number of RADAR sensors 1260 that may be installed at both ends of a rear bumper. In at least one embodiment, a RADAR sensor system, when installed at both ends of a rear bumper, may generate two beams that continuously monitor blind spots in a rearward direction and adjacent a vehicle. In at least one embodiment, short range RADAR systems may be used in ADAS system 1238 to detect blind spot and / or to assist in lane changing.In at least one embodiment, vehicle 1200 may further include ultrasonic sensor(s) 1262. In at least one embodiment, ultrasonic sensor(s) 1262, which may(s) be disposed at a front, rear, and / or lateral location of vehicle 1200, may(s) be used to assist parking and / or to create and update an occupancy grid. In at least one embodiment, a plurality of ultrasonic sensors 1262 may be used, and different ultrasonic sensors 1262 may be used for different sensing ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensor(s) 1262 may(s) operate at ASIL B functional safety levels.In at least one embodiment, vehicle 1200 may include one or more LIDAR sensors 1264. In at least one embodiment, LIDAR sensor(s) 1264 may be(can) used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor(s) 1264 may(s) operate at ASIL B functional security level. In at least one embodiment, vehicle 1200 may include multiple LIDAR sensors 1264 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to provide data to a gigabit Ethernet switch).In at least one embodiment, LIDAR sensor(s) 1264 may / may be capable of providing a list of objects and their distances for a 330 degree field of view. In at least one embodiment, commercially available LIDAR sensor(s) 1264 may / may have an advertised range of about 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protrusion LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1264 may / may comprise a small device that may be embedded in a front, rear, side, and / or corner position of the vehicle 1200. In at least one embodiment, in such an embodiment, LIDAR sensor(s) 1264 may provide a horizontal field of view of up to 90 degrees and a vertical field of view of up to 32 degrees with a range of 170 m even for low reflectivity objects. In at least one embodiment, front mounted LIDAR sensor(s) 1264 may / may be configured for a horizontal field of view between 42 degrees and 105 degrees.In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate environment of vehicle 1200 to a distance of about 170 meters. In at least one embodiment, flash LIDAR unit includes, without limitation, a receptor that records laser pulse travel time and reflected light at each pixel, which in turn corresponds to a distance from vehicle 1200 to objects. In at least one embodiment, flash LIDAR may allow highly accurate and distortion-free images of environment to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be employed, one on each side of vehicle 1200. In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid state 3D star array LIDAR camera that does not have moving parts other than a blower (e.g., a non-scanning LIDAR device). In at least one embodiment, flash LIDAR device may use a 5 nanosecond class I (eye safe) laser pulse per image and acquire reflected laser light as a 3D range point cloud and co-registered intensity data.In at least one embodiment, vehicle 1200 may further include one or more IMU sensors 1266. In at least one embodiment, IMU sensor(s) 1266 may / may be disposed in the center of a rear axle of vehicle 1200. In at least one embodiment, IMU sensor(s) 1266 may include, for example and without limitation, one or more accelerometers, magnetometers, gyroscope(s), magnetic compass, magnetic compass, and / or other types of sensors. In at least one embodiment, for example in six-axis applications, IMU sensor(s) 1266 may / may include accelerometers and gyroscopes without limitation. In at least one embodiment, such as in nine-axis applications, IMU sensor(s) 1266 may / may include, without limitation, accelerometers, gyroscopes, and magnetometers.In at least one embodiment, IMU sensor(s) 1266 may be implemented as a miniaturized, high performance GPS-based inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and location. In at least one embodiment, IMU sensors 1266 may enable vehicle 1200 to estimate its heading without requiring inputs from a magnetic sensor by directly observing changes in speed from a GPS and correlating with IMU sensors 1266. In at least one embodiment, IMU sensor(s) 1266 and GNSS sensor(s) 1258 may be combined into a single integrated unit.In at least one embodiment, vehicle 1200 may include one or more microphones 1296 disposed in and / or around vehicle 1200. In at least one embodiment, microphone(s) 1296 may be used to identify emergency vehicles, among other things.In at least one embodiment, vehicle 1200 may further include any number of camera types, including stereo camera(s) 1268; wide-angle camera(s) 1270; infrared camera(s) 1272; surround camera(s) 1274; long-range camera(s) 1298; mid-range camera(s) 1276, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire perimeter of vehicle 1200. In at least one embodiment, vehicle 1200 depends on which types of cameras are used. In at least one embodiment, any combination of camera types may be used to ensure required coverage around vehicle 1200. In at least one embodiment, the number of cameras used may vary depending on the embodiment. In at least one embodiment, vehicle 1200 may include, for example, six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, cameras may support gigabit multimedia serial link ("GMSL") and / or gigabit Ethernet communication, for example and without limitation. In at least one embodiment, each camera may be as described in more detail above in FIGS. 12A and 12B.In at least one embodiment, vehicle 1200 may further include one or more vibration sensors 1242. In at least one embodiment, vibration sensor(s) 1242 may (may) measure vibrations of components of vehicle 1200, such as axle(s). In at least one embodiment, changes in vibrations may indicate a change in road surface, for example. In at least one embodiment, when two or more vibration sensors 1242 are used, differences between vibrations may be used to determine friction or slip of road surface (e.g., when there is a difference in vibration between a driven axle and a free-rotating axle).In at least one embodiment, vehicle 1200 may include ADAS system 1238. In at least one embodiment, ADAS system 1238 may include, without limitation, a SoC in some examples. In at least one embodiment, ADAS system 1238 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control ("ACC") system, a cooperative adaptive cruise control ("CACC") system, a forward crash warning ("FCW") system, an automatic emergency braking ("AEB") system, a lane departure warning ("LDW") system, a lane keeping assist ("LKA") system, a blind spot warning ("BSW") system, a rear cross traffic warning ("RCTW") system, a collision warning ("CW") system, a track centering ("LC") system and / or other systems, features and / or functions.In at least one embodiment, ACC system may use RADAR sensor(s) 1260, LIDAR sensor(s) 1264, and / or any number of cameras. In at least one embodiment, ACC system may include a longitudinal ACC system and / or a transverse ACC system. In at least one embodiment, an ACC system monitors and controls distance to another vehicle immediately in front of vehicle 1200 in a longitudinal direction and automatically adjusts speed of vehicle 1200 to maintain a safe distance to preceding vehicles. In at least one embodiment, a lateral ACC system takes over distance keeping and advises vehicle 1200 to change lanes as necessary. In at least one embodiment, a lateral ACC system is connected to other ADAS applications, such as LC and CW.In at least one embodiment, a CACC system uses information from other vehicles that may be received via network interface 1224 and / or wireless antenna(s) 1226 from other vehicles via a wireless connection or indirectly via a network connection (e.g., via Internet). In at least one embodiment, direct connections may be provided through a vehicle-to-vehicle communication link ("V2V"), while indirect connections may be provided through an infrastructure-to-vehicle communication link ("I2V"). Generally, the V2V communication provides information about immediately preceding vehicles (e.g., vehicles that are immediately in front of and on the same lane as vehicle 1200), while the I2V communication provides information about the traffic ahead. In at least one embodiment, a CACC system may include either or both I2V and V2V information sources. In at least one embodiment, a CACC system may be more reliable given information about vehicles in front of vehicle 1200, and has potential to improve traffic flow and reduce road jams.In at least one embodiment, an FCW system is designed to warn a driver of a risk so that that driver may correctively intervene. In at least one embodiment, an FCW system uses a front-facing camera and / or RADAR sensor(s) 1260 that is / are coupled to a dedicated processor, DSP, FPGA, and / or ASIC that / are electrically coupled to provide feedback to driver, such as a display, speaker, and / or vibrating component. In at least one embodiment, an FCW system may provide a warning, such as in the form of a sound, a visual warning, a vibration, and / or a rapid brake pulse.In at least one embodiment, an AEB system detects an imminent forward collision with another vehicle or object and can automatically apply brakes if a driver does not correctively engage within a particular time or distance parameter. In at least one embodiment, AEB system may use forward facing camera(s) and / or RADAR sensor(s) 1260 coupled to a special purpose processor, DSP, FPGA, and / or ASIC. In at least one embodiment, if an AEB system detects a risk, it will typically first warn a driver to take corrective action to avoid a collision, and if that driver does not take corrective action, AEB system may automatically apply brakes to prevent or at least mitigate effects of a predicted collision. In at least one embodiment, an AEB system may include techniques such as dynamic brake assist and / or crash-intrinsic braking.In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to warn driver when vehicle 1200 crosses lane markings. In at least one embodiment, an LDW system is not activated when a driver indicates an intentional lane departure, such as by actuating a turn signaler. In at least one embodiment, an LDW system may use front-facing cameras coupled to a special purpose processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide feedback to driver, such as via a display, speaker, and / or vibrating component. In at least one embodiment, an LKA system is a variant of an LDW system. In at least one embodiment, an LKA system provides steering intervention or braking to correct vehicle 1200 when vehicle 1200 begins to exit its lane.In at least one embodiment, a BSW system detects and alerts driver to vehicles in the blind spot of vehicle. In at least one embodiment, a BSW system may issue a visual, audible, and / or tactile warning to indicate that lane merging or changing is uncertain. In at least one embodiment, a BSW system may issue an additional warning when a driver actuates a turn signal. In at least one embodiment, a BSW system(s) may use rear-facing camera(s) and / or RADAR sensor(s) 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to feedback of driver, such as a display, speaker, and / or vibrating component.In at least one embodiment, an RCTW system may provide visual, audible, and / or tactile notification when an object outside range of rear camera is detected when vehicle 1200 is backing. In at least one embodiment, an RCTW system includes an AEB system to ensure that vehicle brakes are applied to avoid an accident. In at least one embodiment, an RCTW system may use one or more rear-facing RADAR sensor(s) 1260, which is / are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is / are electrically coupled to provide feedback to driver, for example, via a display, speaker, and / or vibrating component.In at least one embodiment, conventional ADAS systems may lead to false positive results that, while annoying and distracted to driver, are generally not catastrophic because conventional ADAS systems warn the driver and allow him to decide whether a safety condition is true and act accordingly. In at least one embodiment, vehicle 1200 itself decides, in the case of conflicting results, whether to observe the result of a primary computer or a secondary computer (for example, a first control unit or a second control unit of control units 1236). In at least one embodiment, ADAS system 1238 may be, for example, a backup and / or secondary computer that provides perception information to a rationality module of backup computer. In at least one embodiment, a backup computer rationality monitor may run redundant various software on hardware components to detect perception and dynamic driving task errors. In at least one embodiment, outputs of ADAS system 1238 may be passed to a higher level MCU. In at least one embodiment, a parent MCU determines how to resolve conflict to ensure safe operation when outputs of a primary computer and outputs of a secondary computer conflict with each other.In at least one embodiment, a primary computer may be configured to provide a parent MCU with a confidence value that indicates primary computer's confidence in a selected result. In at least one embodiment, if this confidence value exceeds a threshold, monitoring MCU may follow primary computer instruction, regardless of whether secondary computer provides an conflicting or inconsistent result. In at least one embodiment, in cases where a confidence value does not reach a threshold and where primary and secondary computers indicate different results (e.g., conflict), a monitoring MCU may mediate between computers to determine an appropriate result.In at least one embodiment, a monitoring MCU may be configured to execute one or more neural networks trained and configured to determine, based at least in part on primary computer outputs and secondary computer outputs, conditions under which that secondary computer provides false alarms. In at least one embodiment, neural network(s) may (may) learn in a monitoring MCU when output of a secondary computer can be trusted and when not. In at least one embodiment, if secondary computer is a RADAR-based FCW system, a neural network or networks may learn in that parent MCU when an FCW system identifies metallic objects that are not actually hazardous, such as a drain grid or channel cap that triggers an alarm. In at least one embodiment, a neural network in a monitoring MCU may learn to override lane keeping assist when a secondary computer is a camera-based lane keeping assist system and lane departure is actually the safest maneuver. In at least one embodiment, a monitoring MCU may include at least one DLA or GPU suitable for executing neural networks with associated memory. In at least one embodiment, a monitoring MCU may include and / or be included as a component of SoC(s) 1204.In at least one embodiment, ADAS system 1238 may include a secondary computer that performs ADAS functions using conventional rules of computer vision. In at least one embodiment, this secondary computer may use classic computer vision rules (if-then), and presence of a neural network(s) in a parent MCU may improve reliability, security, and performance. At least in one embodiment, the overall system becomes more fault tolerant, particularly to faults caused by software functions (or software-hardware interfaces), through the differential implementation and intentional non-identity. For example, in at least one embodiment, if a software fault occurs in software running on a primary computer and non-identical software code runs on a secondary computer that provides a consistent overall result, then a monitoring MCU may have a greater confidence that an overall result is correct and a fault in software or hardware on that primary computer does not cause a significant fault.In at least one embodiment, an output of ADAS system 1238 may be fed to host perception block and / or host dynamic driving task block. For example, in at least one embodiment, if ADAS system 1238 indicates a forward crash warning due to an object immediately ahead, a perception block may use this information in identifying objects. In at least one embodiment, a secondary computer may have its own neural network that is trained and thus reduces risk of false alarms, as described herein.In at least one embodiment, vehicle 1200 may further include an infotainment SoC 1230 (e.g., an on-board infotainment system (IVI)). Although illustrated and described as SoC, in at least one embodiment, infotainment system SoC 1230 may not be a SoC and may include, without limitation, two or more discrete components. In at least one embodiment, infotainment SoC 1230 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, a personal digital assistant, navigation instructions, messages, radio, etc.), video (e.g., television, movies, streaming, etc.), telephone (e.g., (e.g., hands-free kit), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation systems, rear parking assist, a radio data system, vehicle related information such as fuel level, total distance travelled, brake fuel level, oil level, door open / close, air filter information, etc.) to vehicle 1200. The infotainment SoC 1230 could include, for example, radios, disk players, navigation systems, video players, USB and Bluetooth connectivity, carputers, in-car entertainment, WiFi, steering wheel audio controls, hands-free kit, heads-up display ("HUD"), HMI display 1234, telematics device, control panel (e.g., for control and / or interaction with various components, functions, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1230 may be further used to provide information (e.g., visual and / or audible) to vehicle 1200 users, such as information from ADAS system 1238, autonomous driving information, such as scheduled vehicle maneuvers, trajectories, environmental information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.In at least one embodiment, infotainment SoC 1230 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1230 may communicate with other devices, systems, and / or components of vehicle 1200 via bus 1202. In at least one embodiment, infotainment SoC 1230 may be coupled to a monitoring MCU such that a GPU of an infotainment system may perform some self-driving functions if primary controller(s) 1236 (e.g., vehicle 1200 primary and / or backup computers) fail. In at least one embodiment, infotainment SoC 1230 may place vehicle 1200 in a chauffeur-to-safe stop mode, as described herein.In at least one embodiment, vehicle 1200 may further include an instrument cluster 1232 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 1232 may include, without limitation, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, instrument group 1232 may include, without limitation, any number and combination of instruments, such as tachometer, fuel level, oil pressure, tachometer, odometer, turn signal, shift position indicator, seatbelt warning light(s), parking brake warning light(s), engine malfunction light(s), additional restraint system information (e.g., airbags), lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared by infotainment SoC 1230 and instrument group 1232. In at least one embodiment, instrument cluster 1232 may include a portion of infotainment SoC 1230, or vice versa.In at least one embodiment, at least one component shown or described in FIG. 12C is used to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, data is transmitted from data store(s) 1216 via wireless antenna(s) 1226, with signals using hybrid beamforming parameters and / or transmit powers derived by a neural network as described in connection with FIG. 1 and as described elsewhere herein.FIG. 12D is a diagram of a system for communication between one or more cloud-based servers and the autonomous vehicle 1200 of FIG. 12A, according to at least one embodiment. In at least one embodiment, system may include, without limitation, server / s 1278 network(s) 1290, and any number and type of vehicle, including vehicle 1200. In at least one embodiment, server(s) 1278 may include, without limitation, a plurality of GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(D) (collectively referred to herein as PCIe switches 1282) and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected with high speed links, such as, for example and without limitation, NVLink interfaces 1288 and / or PCIe links 1286 developed by NVIDIA. In at least one embodiment, GPUs 1284 are connected via an NVLink and / or NVSwitch SoC, and GPUs 1284 and PCIe switches 1282 are connected via PCIe connections. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not to be understood as limiting. In at least one embodiment, each of servers 1278 may include, without limitation, any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282, in any combination. For example, in at least one embodiment, server(s) 1278 could each include eight, sixteen, thirty-two, and / or more GPUs 1284.In at least one embodiment, server(s) 1278 may receive, via network(s) 1290 and from vehicles, image data representative of images showing unexpected or altered road conditions, such as recently initiated road operations. In at least one embodiment, server / s 1278 may transmit, via network(s) 1290 and to vehicles, updated or other neural networks 1292 and / or map information 1294 including, but not limited to, traffic and road conditions information. In at least one embodiment, updates to map information 1294 may include, without limitation, updates to HD map 1222, such as information about worksites, holes, diversions, floods, and / or other obstacles. In at least one embodiment, neural networks 1292 and / or map information 1294 may result from new training and / or experiences represented in data received from any number of vehicles in an environment and / or based at least in part on training performed at a data center (e.g., using server(s) 1278 and / or other servers).In at least one embodiment, server / s 1278 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data may be generated from vehicles and / or in a simulation (e.g., using a game engine). In at least one embodiment, any set of training data is marked (e.g., when associated neural network benefits from supervised learning) and / or subjected to other preprocessing. In at least one embodiment, any set of training data is not marked and / or preprocessed (e.g., if associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, vehicle machine learning models may be used (e.g., transmitted to vehicles via network(s) 1290) and / or machine learning models may be used by server(s) 1278 to remotely monitor vehicles.In at least one embodiment, server(s) 1278 may receive data from vehicles and apply data to current neural networks in real-time to draw smart conclusions in real-time. In at least one embodiment, server / servers 1278 may include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) 1284, such as DGX and DGX station machines developed by NVIDIA. However, in at least one embodiment, server / servers 1278 may also include a deep learning infrastructure that uses CPU-powered data centers.In at least one embodiment, deep learning infrastructure of server(s) 1278 may be capable of performing fast real-time inferencing and utilize this capability to assess and verify status of processors, software, and / or associated hardware in vehicle 1200. For example, in at least one embodiment, deep learning infrastructure may receive periodic updates from vehicle 1200, such as a sequence of images and / or objects that vehicle 1200 has located in that sequence of images (e.g., via computer vision and / or other machine object classification techniques). In at least one embodiment, deep learning infrastructure may run its own neural network to identify objects and compare them to objects identified by vehicle 1200, and if results do not match and deep learning infrastructure concludes that AI in vehicle 1200 is malfunctioning, then server / s 1278 may send a signal to vehicle 1200 instructing a vehicle 1200 fail-safe computer to take control of notifying passengers and performing a safe parking maneuver.In at least one embodiment, server / s 1278 may include GPU(s) 1284 and one or more programmable inference accelerators (e.g., NVIDIAs TensorRT 3 devices). In at least one embodiment, a combination of GPU-based servers and inferencing acceleration may enable real-time responsiveness. In at least one embodiment, for example, when performance is less critical, servers with CPUs, FPGAs, and other processors may be used for inferencing. In at least one embodiment, hardware structure(s) 915 are used to perform one or more embodiments. Details of the hardware structure(s) 915 are described herein in connection with FIGS. 9A and / or 9B.COMPUTER SYSTEMSFIG. 13 is a block diagram illustrating an example computer system, which may be a system including interconnected devices and components, a system on a chip (SOC), or a combination thereof, formed with a processor that may include execution units for executing an instruction, in accordance with at least one embodiment. In at least one embodiment, computer system 1300 may include, without limitation, a component such as processor 1302 to employ execution units including logic to perform algorithms for processing data in accordance with present disclosure, as in embodiment described herein. In at least one embodiment, computer system 1300 may include processors such as PENTIUM® family of processors, Xeon™ Itanium® XScale™ and / or StrongARM™ Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, and the like) may also be used. In at least one embodiment, computer system 1300 may execute a version of WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, network computers ("NetPCs"), set-top boxes, network hubs, wide area network switches ("WAN"), or any other system capable of executing one or more instructions according to at least one embodiment.In at least one embodiment, computer system 1300 may include, without limitation, a processor 1302, which may include, without limitation, one or more execution units 1308 to perform machine learning model training and / or inferencing according to techniques described herein. In at least one embodiment, computer system 1300 is a desktop or server system having a processor, but in another embodiment, computer system 1300 may be a multiprocessor system. In at least one embodiment, processor 1302 may include, without limitation, a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other computing device such as a digital signal processor. In at least one embodiment, processor 1302 may be connected to a processor bus 1310 that may transmit data signals between processor 1302 and other components in computer system 1300.In at least one embodiment, processor 1302 may include, without limitation, an internal cache memory ("cache") 1304 level 1 ("L1"). In at least one embodiment, processor 1302 may include a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1302. Other embodiments may also include a combination of internal and external caches depending on the particular implementation and needs. In at least one embodiment, a register file 1306 may store different types of data in different registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.In at least one embodiment, execution unit 1308, which includes, without limitation, logic to perform integer and floating point operations, is also located in processor 1302. In at least one embodiment, processor 1302 may also include microcode ("ucode") read-only memory ("ROM") that stores microcode for certain microinstruction. In at least one embodiment, execution unit 1308 may include logic to handle a packed instruction set 1309. In at least one embodiment, by including a packed instruction set 1309 in an instruction set of a general purpose processor along with associated circuitry for executing instructions, operations used by many multimedia applications may be performed using packed data in processor 1302. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by utilizing full width of processor's data bus for performing packed data operations, thereby eliminating the need to transfer smaller units of data across processor's data bus to perform one or more operations with one data element each.In at least one embodiment, execution unit 1308 may also be used in microcontrollers, embedded processors, graphics processors, DSPs, and other types of logic circuitry. In at least one embodiment, computer system 1300 may include, without limitation, memory 1320. In at least one embodiment, memory 1320 may be dynamic random access memory ("DRAM"), static random access memory ("SRAM"), flash memory, or other memory. In at least one embodiment, memory 1320 may store instructions 1319 and / or data 1321 represented by data signals executable by processor 1302.In at least one embodiment, a system logic chip may be connected to processor bus 1310 and memory 1320. In at least one embodiment, a system logic chip may include, without limitation, a memory controller hub ("MCH") 1316, and processor 1302 may communicate with MCH 1316 via processor bus 1310. In at least one embodiment, MCH 1316 may provide a high bandwidth storage path 1318, to memory 1320 for storing instructions and data stores, as well as for storing graphics instructions, data, and textures. In at least one embodiment, MCH 1316 may route data signals between processor 1302, memory 1320, and other components in computer system 1300, and may bypass data signals between processor bus 1310, memory 1320, and a system I / O interface 1322. In at least one embodiment, a system logic chip may provide a graphics port for connection to a graphics controller. In at least one embodiment, MCH 1316 may be coupled to memory 1320 via a high bandwidth memory path 1318, and a graphics / video card 1312 may be coupled to MCH 1316 via an accelerated graphics port ("AGP") link 1314.In at least one embodiment, computer system 1300 may use system I / O interface 1322 as a proprietary hub interface bus to connect MCH 1316 to an I / O control hub ("ICH") 1330. In at least one embodiment, ICH 1330 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high speed I / O bus for connecting peripherals to memory 1320, a chipset, and processor 1302. Examples may include, without limitation, an audio controller 1329, a firmware hub ("flash BIOS") 1328, a wireless transceiver 1326, a data storage 1324, a legacy I / O controller 1323 having user input and keyboard interfaces 1325, a serial expansion port 1327 such as a universal serial bus ("USB") port, and a network controller 1334. In at least one embodiment, data storage 1324 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.In at least one embodiment, FIG. 13 illustrates a system including interconnected hardware devices or "chips", while in other embodiments, FIG. 13 may illustrate an example SoC. In at least one embodiment, devices shown in FIG. 13 may be connected to proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of computer system 1300 are interconnected via compute express link (CXL) connections.Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details of logic 915 are described herein in connection with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in computer system 1300 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, one or more methods, systems, or processes depicted in FIG. 13 are used to use one or more neural networks to blend two or more images based on one or more confidence values below a first threshold, using various algorithms, formulas, and processes such as those described in connection with FIG. 1, and / or otherwise performing operations described herein. In at least one embodiment, one or more systems depicted in FIG. 13 are used to implement one or more systems and / or processes as described in connection with FIGS. 1-11.In at least one embodiment, at least one component shown or described in FIGS. 12D-13 is used to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, processor 1302 performs one or more operations related to a neural network to derive hybrid beamforming parameters and / or transmit powers to be used by wireless signal transmission devices as described in connection with FIG. 1 and as otherwise described herein.In at least one embodiment, electronic device 1400 may include, without limitation, a processor 1410 communicatively coupled to any number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1410 is coupled via a bus or interface, such as an I2C bus, a system management ("SMBus") bus, a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high definition audio ("HDA") bus, a serial advance technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, FIG. 14 illustrates a system including interconnected hardware devices or "chips", while in other embodiments, FIG. 14 may illustrate an example SoC. In at least one embodiment, devices shown in FIG. 14 may be interconnected via proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of FIG. 14 are interconnected via compute express link (CXL) connections.In at least one embodiment, FIG. 14 may include a display 1424, a touch screen 1425, a touchpad 1430, a near field communications ("NFC") unit 14 42, a sensor hub 1440, a thermal sensor 1446, an express chipset ("EC") 1435, a trusted platform module ("TPM") 1438, BIOS / firmware / flash memory ("BIOS, FW Flash") 1422, a DSP 1460, a drive 1420 such as a solid state disk ("SSD") or a hard disk drive ("HDD"), a wireless local area network ("WLAN") unit 1 420, a Bluetooth unit 1 422, a wireless wide area network ("WWAN") unit 1 426, a global positioning system (GPS) unit 1 425, a camera ("USB 3.0 camera") 1 424 such as a USB 3.0 camera, and / or a low power double data rate ("LPDDR") storage unit ("LPDDR3") 1415 implemented according to an LPDDR3 standard, for example.These components may each be implemented in any suitable manner.In at least one embodiment, other components may be communicatively connected to processor 1410 via components described herein. In at least one embodiment, an accelerometer 1441, an ambient light sensor ("ALS") 1442, a compass 1443, and a gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, a thermal sensor 1439, a fan 1437, a keyboard 1436, and a touchpad 1430 may be communicatively connected to EC 1435. In at least one embodiment, speaker 1463, earphone 1464, and microphone 1465 may be communicatively coupled to an audio unit ("audio codec and class D amplifier") 1462, which in turn may be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1462 may include, for example and without limitation, an audio coder / decoder ("codec") and a class D amplifier. In at least one embodiment, a SIM card ("SIM") 1 427 may be communicatively coupled to WWAN unit 1 426. In at least one embodiment, components such as WLAN unit 1 420 and Bluetooth unit 1 422 and WWAN unit 1 426 may be implemented in a next generation form factor ("NGFF").Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 in electronic device 1400 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, at least one component shown or described in FIG. 14 is used to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, processor 1415 performs one or more operations related to a neural network to derive hybrid beamforming parameters and / or transmit powers to be used by wireless signal transmission devices as described in connection with FIG. 1 and as described elsewhere herein.FIG. 15 illustrates a computer system 1500, according to at least one embodiment. In at least one embodiment, computer system 1500 is configured to implement various processes and methods described in this disclosure.In at least one embodiment, computer system 1500 includes, without limitation, at least one central processing unit ("CPU") 1502 connected to a communication bus 1510 implemented using any suitable protocol, such as peripheral component interconnect (PCI); peripheral component interconnect express ("PCI-Express"); accelerated graphics port (AGP); hypertransport; or any other bus or point-to-point communication protocol(s). In at least one embodiment, computer system 1500 includes, without limitation, main memory 1504 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1504, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface ("network interface") subsystem 1522 provides an interface to other computing devices and networks to receive data from other systems and transmit it to other systems with computer system 1500.In at least one embodiment, computer system 1500 includes, without limitation, input devices 1508, a parallel processing system 1512, and display devices 1506 that may be implemented with a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light emitting diode display ("LED"), a plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices 1508 such as keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may be packaged on a single semiconductor platform to form a processing system.Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details of inference and / or training logic 915 are described herein in connection with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in computer system 1500 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, at least one component shown or described in FIG. 15 is used to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, computer system 1500 performs one or more operations related to a neural network to derive hybrid beamforming parameters and / or transmit powers used by wireless signal transmission devices as described in connection with FIG. 1 and as described elsewhere herein.FIG. 16 illustrates a computer system 1600, according to at least one embodiment. In at least one embodiment, computer system 1600 includes, without limitation, a computer 1610 and a USB stick 1620. In at least one embodiment, computer 1610 may include, without limitation, any number and type of processor(s) (not shown) and memory (not shown). In at least one embodiment, computer 1610 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.In at least one embodiment, USB stick 1620 includes, without limitation, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, processing unit 1630 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1630 may include, without limitation, any number and type of compute cores (not shown). In at least one embodiment, processing unit 1630 includes an application specific integrated circuit ("ASIC") that is optimized for performing any number and type of machine learning related operations. In at least one embodiment, processing unit 1630 is, for example, a tensor processing unit ("TPC") that is optimized for performing machine learning inference operations. In at least one embodiment, processing unit 1630 is a Image Processing Unit ("VPU") that is optimized for performing image processing and machine learning operations.In at least one embodiment, USB interface 1640 may be any type of USB plug or jack. For example, in at least one embodiment, USB interface 1640 is a USB 3.0 type C socket for data and power. In at least one embodiment, USB interface 1640 is a USB 3.0 type A connector. In at least one embodiment, USB interface logic 1650 may include any amount and type of logic that enables processing unit 1630 to communicate with devices (e.g., computer 1610) via USB port 1640.Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are provided herein in connection with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in computer system 1600 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, at least one component shown or described in FIG. 16 is used to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, computer system 1600 performs one or more operations related to a neural network to derive hybrid beamforming parameters and / or transmit powers to be used by wireless signal transmission devices as described in connection with FIG. 1 and as otherwise described herein.FIG. 17A illustrates an example architecture in which a plurality of GPUs 1710( 1)- 2010(N) are communicatively coupled to a plurality of multi-core processors 1705( 1)- 2005(M) via high-speed links 1740( 1)- 2040(N) (e.g., buses, point-to-point links, etc.). In at least one embodiment, high speed links 1740( 1)- 2040(N) support communication throughput of 4 GB / s, 27 GB / s, 80 GB / s, or more. In at least one embodiment, various link protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, "N" and "M" represent positive integers whose values may vary from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1710( 1)- 2010(N) includes one or more graphics cores (also referred to simply as "cores") 2000 as disclosed in FIGS. 20A and 20B. In at least one embodiment, one or more graphics cores 2000 may be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., 13 cores, a ray tracing unit, a thread director, or scheduler).Additionally, and in at least one embodiment, two or more GPUs 1710 are interconnected via high-speed links 1729( 1)- 2029( 2), which may be implemented using similar or different protocols / links than those used for high-speed links 1740( 1)- 2040(N). Similarly, two or more multi-core processors 1705 may be connected via a high speed link 1728, which may be symmetric multiprocessor buses (SMPs) operating at 17 GB / s, 27 GB / s, 90 GB / s, or more. Alternatively, all communication between the various system components shown in FIG. 17A may be accomplished using similar protocols / connections (e.g., via a common connection structure).In at least one embodiment, each multi-core processor 1705 is communicatively coupled to a processor memory 1701( 1)- 2001(M) via memory links 1726( 1)- 2026(M), and each GPU 1710( 1)- 2010(N) is communicatively coupled to GPU memory 1720( 1)- 2020(N) via GPU memory links 1750( 1)- 2050(N). In at least one embodiment, memory interconnects 1726 and 1750 may use similar or different memory access technologies. For example, the processor memories 1701( 1)- 2001(M) and the GPU memories 1720 may be volatile memories, such as dynamic random access memories (DRAMs) (including stacked DRAMs), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be nonvolatile memories, such as 3D XPoint or nano-Ram. In at least one embodiment, one portion of processor memory 1701 may be volatile memory and another portion may be nonvolatile memory (e.g., using a two-stage memory hierarchy (2LM)).As described herein, while different multi-core processors 1705 and GPUs 1710 may be physically coupled to a particular memory 1701 and 1720, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as "effective address space") is distributed among different physical memories. For example, processor memories 1701(1)-2001(M) may each comprise 64 GB system address space and GPU memories 1720(1)-2020(N) may each comprise 32 GB system address space, resulting in a total of 226 GB addressable memories at M=2 and N=4. Other values for N and M are possible.FIG. 17B shows additional details for a connection between a multi-core processor 1707 and a graphics acceleration module 1746, in accordance with an example embodiment. In at least one embodiment, graphics acceleration module 1746 may include one or more GPU chips integrated on a line card connected to processor 1707 via a high-speed link 1740 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1746 may alternatively be integrated on a package or chip with processor 1707.In at least one embodiment, processor 1707 includes a plurality of cores 1760A- 2060D (which may be referred to as "execution units") each having a translation lookaside buffer ("TLB") 1761A- 2061D and one or more caches 1762A- 2062D. In at least one embodiment, cores 1760A- 2060D may include various other components for executing instructions and processing data, not shown. In at least one embodiment, caches 1762A- 2062D may include level 1 (L1) and level 2 (L2) caches. Moreover, one or more shared caches 1756 may be included in caches 1762A- 2062D and shared by multiple cores 1760A- 2060D. For example, one embodiment of processor 1707 includes 21 cores, each with a dedicated L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1707 and graphics acceleration module 1746 are coupled to system memory 1714, which may include processor memories 1701( 1)- 2001( M) of FIG. 17A.In at least one embodiment, coherency is maintained for data and instructions stored in various caches 1762A- 2062D, 1756 and system memory 1714 via inter-core communication via a coherency bus 1764. For example, in at least one embodiment, each cache may include associated cache coherency logic / circuitry to communicate over coherency bus 1764 in response to detected reads or writes in particular cache lines. In at least one embodiment, a cache coherency protocol is implemented over coherency bus 1764 to snoop cache accesses.In at least one embodiment, proxy circuit 1725 communicatively couples graphics acceleration module 1746 to coherency bus 1764, thereby enabling graphics acceleration module 1746 to participate in a cache coherency protocol as peers of cores 1760A- 2060D. In particular, in at least one embodiment, an interface 1735 provides connectivity to proxy circuit 1725 via high speed link 1740 and an interface 1737 connects graphics acceleration module 1746 to high speed link 1740.In at least one embodiment, circuitry 1736 provides cache management, memory access, context management, and interrupt management services to a plurality of graphics processing engines 1731(1)-2031(N) of graphics acceleration module 1746. In at least one embodiment, graphics processing engines 1731(1)-2031(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, multiple graphics processing engines 1731(1)-2031(N) of graphics acceleration module 1746 include one or more graphics cores 2000, as discussed in connection with FIGS. 20A and 20B. In at least one embodiment, graphics processing engines 1731(1)-2031(N) may alternatively include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1746 may be a GPU having a plurality of graphics processing engines 1731(1)-2031(N), or graphics processing engines 1731(1)-2031(N) may be individual GPUs integrated on a common package, line card, or chip.In at least one embodiment, accelerator integration circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual to physical memory translations (also referred to as effective to real memory translations) and memory access protocols for accessing system memory 1714. In at least one embodiment, MMU 1739 may also include a translation lookaside buffer (TLB) (not shown) to cache virtual / effective to physical / real address translations. In at least one embodiment, a cache 1738 may store instructions and data for efficient access by graphics processing engines 1731(1)-2031(N). In at least one embodiment, data stored in cache 1738 and graphics memories 1733(1)-2033(M) is maintained coherent with core caches 1762A- 2062D, 1756 and system memory 1714, possibly using fetch unit 1744. As mentioned, this may be via proxy circuitry 1725 in the name of cache 1738 and memories 1733(1)-2033(M) (e.g., sending updates to cache 1738 regarding changes / accesses to cache lines in processor caches 1762A- 2062D, 1756, and receiving updates from cache 1738).In at least one embodiment, a set of registers 17 42 store context data for threads executed by graphics processing engines 1731(1)-2031(N), and context management circuitry 1748 manages thread contexts. For example, context management circuitry 1748 may perform store and restore operations to store and restore contexts of different threads upon context switches (e.g., when a first thread is stored and a second thread is stored to allow a second thread to be executed by a graphics processing engine). For example, upon a context change, context management circuitry 1748 may store the current register values in a particular area of memory (e.g., identified by a context pointer). The register values may then be restored upon return to a context. In at least one embodiment, interrupt management circuitry 1747 receives and processes interrupts received from system devices.In at least one embodiment, virtual / effective addresses from a graphics processing engine 1731 are translated by MMU 1739 to real / physical addresses in system memory 1714. In at least one embodiment, accelerator integration circuit 1736 supports multiple (e.g., 4, 8, 13) graphics acceleration modules 1746 and / or other accelerometers. In at least one embodiment, graphics acceleration module 1746 may be dedicated to a single application executing on processor 1707, or shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which graphics processing engines 1731(1)-2031(N) resources are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be divided into "slices" assigned to different VMs and / or applications based on processing requests and priorities associated with VMs and / or applications.In at least one embodiment, accelerator integration circuit 1736 bridges a system for graphics acceleration module 1746, and provides address translation and system memory cache services. Moreover, in at least one embodiment, accelerator integration circuit 1736 may provide virtualization facilities for a host processor to manage virtualization of graphics processing engines 1731( 1)- 2031( N), interrupts, and memory management.In at least one embodiment, because hardware resources of graphics processing engines 1731(1)-2031(N) are explicitly mapped to a real address space seen by host processor 1707, each host processor can address these resources directly via an effective address value. In at least one embodiment, a function of accelerator integration circuit 1736 is to physically separate graphics processing engines 1731(1)-2031(N) so that they appear as independent units for a system.In at least one embodiment, one or more graphics memories 1733(1)-2033(M) are connected to each of graphics processing engines 1731(1)-2031(N), where N=M. In at least one embodiment, graphics memories 1733(1)-2033(M) store instructions and data processed by each of graphics processing engines 1731(1)-2031(N). In at least one embodiment, graphics memories 1733(1)-2033(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be nonvolatile memories such as 3D XPoint or nano-Ram.In at least one embodiment, to reduce data traffic over high speed link 1740, biasing techniques may be used to ensure that data stored in graphics memories 1733(1)-2033(M) is data most frequently used by graphics processing engines 1731(1)-2031(N), and preferably not by cores 1760A-2060D (at least not frequently). Similarly, in at least one embodiment, a bias mechanism attempts to keep data required by cores (and preferably not graphics processing engines 1731(1)-2031(N)) in caches 1762A- 2062D, 1756 and system memory 1714.FIG. 17C shows another example embodiment in which the accelerator integration circuit 1736 is integrated with the processor 1707. In this embodiment, graphics processing engines 1731(1)-2031(N) communicate directly over high speed link 1740 to accelerator integration circuit 1736 via interface 1737 and interface 1735 (which in turn may be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuit 1736 may perform similar operations as described in FIG. 17B, but possibly with a higher throughput because it is in close proximity to coherency bus 1764 and caches 1762A- 2062D, 1756. In at least one embodiment, accelerator integration circuitry supports various programming models, including a dedicated process programming model (without virtualization of graphics acceleration module) and shared programming models (with virtualization), which may include programming models controlled by accelerator integration circuitry 1736, and programming models controlled by graphics acceleration module 1746.In at least one embodiment, graphics processing engines 1731(1)-2031(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application may pass other application requests to graphics processing engines 1731(1)-2031(N), thereby enabling virtualization within a VM / partition.In at least one embodiment, graphics processing engines 1731(1)-2031(N) may be shared among multiple VM / application partitions. In at least one embodiment, shared models may use a system supervisor to virtualize graphics processing engines 1731(1)-2031(N) to enable access by each operating system. In at least one embodiment, graphics processing engines 1731(1)-2031(N) are owned by an operating system in systems with a partition without a hypervisor. In at least one embodiment, an operating system may virtualize graphics processing engines 1731(1)-2031(N) to enable access to each process or application.In at least one embodiment, graphics acceleration module 1746 or a single graphics processing engine 1731(1)-2031(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1714 and are addressable from effective addresses to real addresses using a translation technique described herein. In at least one embodiment, a process handle may be an implementation specific value provided to a host process when it registers its context to graphics processing engine 1731(1)-2031(N) (i.e., when it invokes system software to add a process element to a linked process element list). In at least one embodiment, lower 16 bits of a process handle may be an offset of a process element within a linked process element list.FIG. 17D shows an example accelerator integration slice 1790. In at least one embodiment, a "slice" includes a particular portion of processing resources of accelerator integration circuit 1736. In at least one embodiment, an application stores process elements 1783 in effective address space 1782 of system memory 1714. In at least one embodiment, process elements 1783 are stored in response to GPU calls 1781 from applications 1780 executing on processor 1707. In at least one embodiment, a process element 1783 includes a process status for corresponding application 1780. In at least one embodiment, a work descriptor (WD) 1784 included in process element 1783 may be a single job requested by an application or may include a pointer to a queue of jobs. In at least one embodiment, WD 1784 is a pointer to a job request queue in effective address space 1782 of an application.In at least one embodiment, graphics acceleration module 1746 and / or individual graphics processing engines 1731(1)-2031(N) may be shared among all or a subset of processes in a system. In at least one embodiment, an infrastructure for establishing process conditions and sending a WD 1784 to a graphics acceleration module 1746 for starting a job in a virtualized environment may be included.In at least one embodiment, a programming model for dedicated processes is implementation specific. In at least one embodiment, in this model, a single process has graphics acceleration module 1746 or an individual graphics processing engine 1731. In at least one embodiment, when graphics acceleration module 1746 belongs to a single process, a hypervisor initializes accelerator integration circuit 1736 for a owned partition and an operating system initializes accelerator integration circuit 1736 for a owned process when graphics acceleration module 1746 is assigned.In operation, in at least one embodiment, a WD fetch unit 1791 in accelerator integration slice 1790 fetches next WD 1784 that includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module 1746. In at least one embodiment, data from WD 1784 may be stored in registers 17 42 and used by MMU 1739, interrupt management circuitry 1747, and / or context management circuitry 1748, as shown. For example, one embodiment of MMU 1739 includes segment / page run circuitry for accessing segment / page tables 1786 within a virtual address space 1785 of the operating system. In at least one embodiment, circuitry 1747 may process interrupt events 1792 received from graphics acceleration module 1746. In at least one embodiment, when performing graphics operations, an effective address 1793 generated by a graphics processing engine 1731(1)-2031(N) is translated by MMU 1739 to a real address.In at least one embodiment, registers 17 42 are duplicated for each graphics processing engine 1731(1)-2031(N) and / or graphics acceleration module 1746, and may be initialized by a hypervisor or operating system. In at least one embodiment, each of these duplicated registers may include an accelerator integration slice 1790. Example registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Initialized Hypervisor Registers Table 1 - Initialized Hypervisor Registers1Slice Control Registers (Slice Control Registers)2Real Address (RA) Pointer to Scheduled Process Area3Authority Mask Override Registers4Interrupt Vector Table Entry Offset5Interrupt Vector Table Entry Boundary6Status Register7Partition Logical ID8Real Address (RA) Pointer to Hypervisor Accelerator Utilization Record9Memory Description RegisterExample registers that may be initialized by an operating system are shown in Table 2. Table 2 - Initialized Registers of the Operating System Table 2 - Initialized Registers of the Operating System1Process and Thread Identification2Effective Address (EA) Context Store / Restore Pointer3Virtual Address (VA) Pointer for the Accelerator Load Set4Virtual Address (VA) Pointer to Memory Segment Table5Authority Mask6Working DescriptionIn at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engines 1731(1)-2031(N). In at least one embodiment, it contains all information needed by a graphics processing engine 1731(1)-2031(N) to perform work, or it may be a pointer to a storage location where an application has set up a command queue of work to be performed.FIG. 17E shows additional details for an example embodiment of a common model. This embodiment includes a hypervisor real address space 1798 in which a process element list 1799 is stored. In at least one embodiment, hypervisor real address space 1798 is accessible via a hypervisor 1796 that virtualizes graphics acceleration module engines for operating system 1795.In at least one embodiment, common programming models allow all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1746. In at least one embodiment, there are two programming models in which graphics acceleration module 1746 is shared among multiple processes and partitions, namely, time-shared sharing and graphic-directed sharing.In at least one embodiment, in this model, system supervisor 1796 has graphics acceleration module 1746, and provides its function to all operating systems 1795. In at least one embodiment, a graphics acceleration module 1746 to support virtualization by system supervisor 1796 may meet certain requirements, such as (1) task request of an application must be autonomous (i.e., state need not be maintained between tasks), or graphics acceleration module 1746 must provide a mechanism for storing and restoring context, (2) graphics acceleration module 1746 guarantees that task request of an application will complete in a certain amount of time, including any translation errors, or graphics acceleration module 1746 provides ability to prefer processing of a task, and (3) graphics acceleration module 1746 must guarantee fitness between processes when operating in a directed shared programming model.In at least one embodiment, application 1780 needs to perform a system call of operating system 1795 with a graphics acceleration module type, a work description (WD), an authority mask register (AMR) value, and a context store / restore pointer (CSRP). In at least one embodiment, type of graphics acceleration module describes a targeted acceleration function for a system call. In at least one embodiment, type of graphics acceleration module may be a system specific value. In at least one embodiment, WD is specially formatted for graphics acceleration module 1746, and may be in the form of a command from graphics acceleration module 1746, a pointer to effective address of a user-defined structure, a pointer to effective address of a command queue, or other data structure describing work to be performed by graphics acceleration module 1746.In at least one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is similar to setting of an AMR by an application. In at least one embodiment, if accelerator integration circuit 1736 (not shown) and graphics acceleration module 1746 do not support an authority mask override register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1796 may optionally apply a current value of authority mask override register (AMOR) before placing an AMR in process element 1783. In at least one embodiment, CSRP is one of registers 17 42 that contains an effective address of an area in effective address space 1782 of an application for graphics acceleration module 1746 to store and restore context status. In at least one embodiment, this pointer is optional when no state needs to be stored between jobs or when a job is terminated prematurely. In at least one embodiment, context storage / recovery area may be resident in system memory.Upon receiving a system call, the operating system 1795 may verify whether the application 1780 has received and obtained permission to use the graphics acceleration module 1746. In at least one embodiment, operating system 1795 then invokes hypervisor 1796 with information listed in Table 3. Table 3 - Parameters for Calling the Operating System to the Hypervisor Table 3 - Parameters for Calling the Operating System to the Hypervisor1A Working Description (WD)2An authority mask register value (AMR) (possibly masked)3An effective address (EA) context store / restore pointer (CSRP)4A process ID (PID) and optionally a thread ID (TID)5A Virtual Address (VA) Accelerator Load Set Pointer (AURP)6Virtual Address of Pointer to Memory Segment Table (SSCP)7A Logical Interrupt Service Number (LISN)In at least one embodiment, upon receiving a hypervisor call, hypervisor 1796 checks whether operating system 1795 has and is receiving permission to use graphics acceleration module 1746. In at least one embodiment, hypervisor 1796 then inserts process element 1783 into a process element list for a corresponding type of graphics acceleration module 1746. In at least one embodiment, a process element may include information shown in Table 4. Table 4 - Process Element Information Table 4 - Process Element Information1A Working Description (WD)2An authority mask register (AMR) value (possibly masked).3An effective address (EA) context store / restore pointer (CSRP)4A process ID (PID) and optionally a thread ID (TID)5A Virtual Address (VA) Accelerator Load Set Pointer (AURP)6Virtual Address of Pointer to Memory Segment Table (SSCP)7A Logical Interrupt Service Number (LISN)8Interrupt Vector Table Derived from Hypervisor Call Parameters9A state register value (SR)10A logical partition ID (LPID)11A Real Address (RA) Accelerator Utilization Set pointer of the Hypervisor12Memory Description Register (SDR)In at least one embodiment, hypervisor initializes a plurality of registers 17 42 for accelerator integration slices 1790.As shown in FIG. 17F, in at least one embodiment, unified memory is used that is addressable via a common virtual memory address space used for accessing physical processor memories 1701( 1)- 2001(N) and GPU memories 1720( 1)- 2020(N). In this implementation, the operations performed on the GPUs 1710( 1)- 2010(N) use the same virtual / effective address space to access the processor memories 1701( 1)- 2001(M) and vice versa, which simplifies the programability. In at least one embodiment, a first portion of a virtual / effective address space is allocated to processor memory 1701(1), a second portion is allocated to second processor memory 1701(N), a third portion is allocated to GPU memory 1720(1), etc. In at least one embodiment, this distributes an entire virtual / effective memory space (sometimes referred to as an effective address space) across each of processor memories 1701 and GPU memories 1720 so that each processor or GPU can access each physical memory with a virtual address associated with that memory.In at least one embodiment, bias / coherency management circuit 1794A- 2094E within one or more MMUs 1739A- 2039E ensures cache coherency between caches of one or more host processors (e.g., 1705) and GPUs 1710, and implements bias techniques that indicate in which physical memories certain types of data should be stored. In at least one embodiment, while multiple instances of bias / coherence management circuitry 1794A- 2094E are shown in FIG. 17F, bias / coherence circuitry may be implemented within an MMU of one or more host processors 1705 and / or within accelerator integration circuitry 1736.In one embodiment, GPU memory 1720 may be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without experiencing performance disadvantages associated with full system cache coherency. In at least one embodiment, the ability to access GPU memory 1720 as system memory without inconvenient cache coherency overhead provides an advantageous operating environment for GPU offload. In at least one embodiment, this arrangement allows host processor 1705 software to adjust operands and access computation results without overhead of traditional I / O DMA copies of data. In at least one embodiment, such conventional copies are associated with driver calls, interrupts, and memory mapping I / O accesses (MMIO), all of which are inefficient compared to simple memory accesses. In at least one embodiment, ability to access GPU memory 1720 without cache coherency overheads may be critical to execution time of an offloaded computation. In at least one embodiment, cache coherency overhead, for example, in cases with substantial streaming write memory traffic, may substantially reduce effective write bandwidth of a GPU 1710. In at least one embodiment, operand construction efficiency, result access efficiency, and GPU calculation efficiency may play a role in determining GPU offload effectiveness.In at least one embodiment, selection of GPU bias and host processor bias is controlled by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page granular structure (e.g., controlled at granularity of a memory page) that includes 1 or 2 bits per GPU-connected memory page. In at least one embodiment, a bias table may be implemented in a stolen memory area of one or more GPU memories 1720, with or without bias cache in a GPU 1710 (e.g., to cache frequently / recently used entries of a bias table). Alternatively, in at least one embodiment, an entire bias table may be maintained in a GPU.In at least one embodiment, a bias table entry associated with each access to a memory 1720 coupled to GPU is accessed prior to actual access to a GPU memory, causing following operations. In at least one embodiment, local requests from a GPU 1710 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 1720. In at least one embodiment, local requests from a GPU that find their page in host bias are forwarded to processor 1705 (e.g., via a high-speed link as described herein). In at least one embodiment, requests from processor 1705 that find a requested page in host processor bias concludes a request such as a normal memory read. Alternatively, requests directed to a page with GPU bias may be forwarded to a GPU 1710. In at least one embodiment, a GPU may then transition a page to a host processor bias if it is not currently using page. In at least one embodiment, bias state of a page may be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited number of instances, a purely hardware-based mechanism.In at least one embodiment, a mechanism for changing bias state uses an API call (e.g., OpenCL) that in turn calls graphics processor's device driver, which in turn sends a message to a graphics processor (or queues a command descriptor) to instruct it to change bias state and perform a cache flushing operation in a host at some transitions. In at least one embodiment, a cache flushing operation is used for a transition from host processor 1705 bias to GPU bias, but not for an opposite transition.In at least one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by host processor 1705. In at least one embodiment, to access these pages, processor 1705 may request access from GPU 1710, which may or may not immediately grant access. Thus, in at least one embodiment, to reduce communication between processor 1705 and GPU 1710, it is advantageous to ensure that GPU-biased pages are those required by a GPU but not host processor 1705, and vice versa.Hardware structure(s) 915 are used to perform one or more embodiments. Details of a hardware structure (or multiple hardware structures) 915 may be provided herein in connection with FIGS. 9A and / or 9B.FIG. 18 illustrates example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to the embodiments shown, other logic and circuitry may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.FIG. 18 is a block diagram illustrating an example integrated circuit 1800 that may be fabricated using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, integrated circuit 1800 includes one or more application processor(s) 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, each of which may be a modular IP core. In at least one embodiment, integrated circuit 1800 includes peripheral or bus logic including a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an I22S / I22C controller 1840. In at least one embodiment, integrated circuit 1800 may include a display device 18 42 coupled to one or more of the following interfaces: a high-definition multimedia interface (HDMI) controller 1850 and a mobile industry processor interface (MIPI) 1855. In at least one embodiment, memory may be provided by a flash memory subsystem 1860 that includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1870.Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 in integrated circuit 1800 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, at least one component shown or described in FIGS. 17A-18 is used to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, SOC 1800 performs one or more operations related to a neural network to derive hybrid beamforming parameters and / or transmit powers to be used by wireless signal transmission devices as described in connection with FIG. 1 and as described elsewhere herein.FIGS. 19A-19B show example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to the embodiments shown, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.FIGS. 19A-19B are block diagrams illustrating example graphics processors for use in a SoC, in accordance with embodiments described herein. FIG. 19A illustrates an example graphics processor 1910 of an integrated circuit for a system-on-a-chip system that may be fabricated using one or more IP cores, in accordance with at least one embodiment. FIG. 19B illustrates another example graphics processor 1940 of an integrated circuit that may be fabricated with one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, graphics processor 1910 of FIG. 19A is a low power graphics processor core. In at least one embodiment, graphics processor 1940 of FIG. 19B is a higher power graphics processor core. In at least one embodiment, each of graphics processors 1910, 1940 may be a variant of graphics processor 1810 of FIG. 18.In at least one embodiment, graphics processor 1910 includes a vertex processor 1905, and one or more fragment processors 1915A- 1915N (e.g., 1915A, 1915B, 1915C, 1915D, through 1915N- 1, and 1915N). In at least one embodiment, graphics processor 1910 may execute different shader programs via separate logic such that vertex processor 1905 is optimized for executing operations for vertex shader programs, while one or more fragment processor(s) 1915A- 1915N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1905 executes a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s) 1915A- 1915N use primitive and vertex data generated by vertex processor 1905 to generate a frame buffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 1915A- 1915N is / are optimized for executing fragment shader programs as provided in an OpenGL API that can be used to perform operations similar to a pixel shader program as provided in a Direct 3D API.In at least one embodiment, graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A- 1920B, cache(s) 1925A- 1925B, and circuit interconnect(s) 1930A- 1930B. In at least one embodiment, one or more MMU(s) 1920A- 1920B provide virtual to physical address mapping for graphics processor 1910, including vertex processor 1905, and / or fragment processor(s) 1915A- 1915N, which may / may refer to vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 1925A- 1925B. In at least one embodiment, one or more MMU(s) 1920A- 1920B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s) 1805, image processors 1815, and / or video processors 1820 of FIG. 18, such that each processor 1805-1820 may participate in a shared or unified virtual storage system. In at least one embodiment, one or more circuit connection(s) 1930A- 1930B enable graphics processor 1910 to interface to other IP cores within SoC, either via an internal bus of SoC or via a direct connection.In at least one embodiment, graphics processor 1940 includes one or more shader cores 1955A- 1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F, through 1955N- 1, and 1955N) as shown in FIG. 19B, which provides a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, number of shader cores may vary. In at least one embodiment, graphics processor 1940 includes an inter-core task manager 19 42 that functions as a thread dispatcher to dispatch execution threads to one or more shader cores 1955A- 1955N, and a tiling unit 1958 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are divided into image space, for example, to exploit local spatial coherence within a scene or to optimize utilization of internal caches.Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 may be used in graphics processor 1910 and / or 1940 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, at least one component shown or described in FIGS. 19A-19B is used to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, graphics processor 1910 performs one or more operations related to a neural network to derive hybrid beamforming parameters and / or transmit powers to be used by wireless signal transmission devices as described in connection with FIG. 1 and as described elsewhere herein.FIGS. 20A-20B show additional example graphics processor logic according to embodiments described herein. In at least one embodiment, components illustrated and described in FIGS. 20A-20B are integrated into a single system, such as a graphics processing unit (GPU), a SoC, or other type of processor. FIG. 20A illustrates a graphics core 2000, which in at least one embodiment may include graphics processor 1810 of FIG. 18, and in at least one embodiment may be a uniform shader core 1955A- 1955N as in FIG. 19B. FIG. 20B illustrates a highly parallel general purpose graphics processing unit ("GPGPU", which may also be referred to as a "graphics processing unit") 2030 suitable for use on a multi-chip module in at least one embodiment. In at least one embodiment, graphics processing unit 2030 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 1800 includes graphics core 2000, for example to form an integrated circuit and / or a SoC, where such an integrated circuit and / or a SoC perform operations described herein.In at least one embodiment, graphics core 2000 includes a shared instruction cache 2002, a texture unit 2018, and a cache / shared memory 2020 (e.g., L1, L2, L3, last level cache, or other caches) that are shared with execution resources within graphics core 2000. In at least one embodiment, graphics core 2000 may include multiple slices 2001A- 2001N or a partition for each core, and a graphics processor may include multiple instances of graphics core 2000. In at least one embodiment, each slice 2001A- 2001N refers to graphics core 2000. In at least one embodiment, slices 2001A- 2001N include sub-slices that are part of a slice 2001A- 2001N. In at least one embodiment, slices 2001A- 2001N are independent of other slices or dependent on other slices. In at least one embodiment, slices 2001A- 2001N may include support logic including local instruction cache 2004A- 2004N, thread scheduler (sequencer) 2006A- 2006N, thread dispatcher 2008A- 2008N, and set of registers 2010A- 2010N. In at least one embodiment, slices 2001A- 2001N may include a set of additional functional units (AFUs 2012A- 2012N), floating point units (FPUs 2014A- 2014N), integer arithmetic logic units (ALUs 2016A- 2016N), address calculation units (ACUs 2013A- 2013N), double-precision floating point units (DPFPUs 2015A- 2015N), and matrix processing units (MPUs 2017A- 2017N). In at least one embodiment, MPUs 2017A- 2017N are referred to as matrix engines.In at least one embodiment, each slice 2001A- 2001N includes one or more engines for floating point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large data sets. In at least one embodiment, one or more slices 2001A- 2001N include one or more vector engines for computing a vector (e.g., for computing mathematical operations for vectors). In at least one embodiment, a vector engine may compute a vector operation in 16-bit floating point (also referred to as "FP16"), 32-bit floating point (also referred to as "FP32"), or 64-bit floating point (also referred to as "FP64"). In at least one embodiment, one or more slices 2001A- 2001N include 13 vector engines paired with 16 matrix math units to compute matrix / tensor operations, where vector engines and math units are accessible via matrix extensions. In at least one embodiment, a slice includes a particular portion of processing resources of a processing unit, such as 13 cores and a ray tracing unit or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, graphics core 2000 includes one or more matrix engines for calculating matrix operations, for example, in calculating tensor operations.In at least one embodiment, one or more slices 2001A- 2001N includes one or more ray tracing units for computing ray tracing operations (e.g., 13 ray tracing units per slice 2001A- 2001N). In at least one embodiment, a ray tracing unit calculates ray crossings, triangle crossings, bounding box intersections, or other ray tracing operations.In at least one embodiment, one or more slices 2001A- 2001N includes a media slice that encodes, decodes, and / or transcodes, scales and / or formats data, and / or performs video quality operations on video data.In at least one embodiment, one or more slices 2001A- 2001N are connected to L2 cache and memory structure, interconnect ports, HBM stacks (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 2001A- 2001N include multiple cores (e.g., 13 cores) and multiple ray tracing units (e.g., 13) coupled to each core. In at least one embodiment, one or more slices 2001A- 2001N includes one or more L1 caches. In at least one embodiment, one or more slices 2001A- 2001N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data, e.g., corresponding to instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in geometry pipelines and / or for applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., shape) and converting it into a raster image (e.g., a series of pixels, dots, or lines that together result in an image being represented by shapes when displayed); one or more hierarchical depth buffers (hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, slice 2001A- 2001N includes a memory structure, for example, an L2 cache.In at least one embodiment, FPUs 2014A- 2014N may perform single precision (32 bits) and half precision (16 bits) floating point operations while DPFPUs 2015A- 2015N may perform double precision (64 bits) floating point operations. In at least one embodiment, ALUs 2016A- 2016N may perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision and be configured for mixed precision operations. In at least one embodiment, MPUs 2017A- 2017N may also be configured for mixed precision matrix operations that include semi-accurate floating point and 8-bit integer operations. In at least one embodiment, MPUs 2017-2017N may perform a plurality of matrix operations to speed up machine learning application frameworks, including support for speeded up general matrix-matrix multiplication (GEMM). In at least one embodiment, AFUs 2012A- 2012N may perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 in graphics core 2000 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, graphics core 2000 includes an interconnect and a link fabric sublayer coupled to a switch and a GPU GPU bridge that enables multiple graphics processors 2000 (e.g., 8) to be bonded together without adhesive, with load / store units (LSUs), communication units, and synchronization semantics across multiple graphics processors 2000. In at least one embodiment, interconnects include standardized interconnects (e.g., PCIe) or a combination thereof.In at least one embodiment, graphics core 2000 includes multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, where individual dies may be connected to an interconnect (e.g., embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 2000 includes a compute tile, a memory tile (e.g., when a memory tile excluding different tiles or different chipsets can be accessed, such as a rambo tile), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, where all tiles are packaged together in graphics core 2000 as part of a GPU. In at least one embodiment, graphics core 2000 may include multiple tiles in a single packet (also referred to as a "multi-tile packet"). In at least one embodiment, a compute tile may include 8 graphics cores 2000, an L1 cache, and a base tile, a host interface including PCIe 5.0, HBM2e, MDFI, and EMIB, and a link tile including 8 links, 8 ports, and an embedded switch. In at least one embodiment, tiles are connected to face-to-face (F2F) chip-on-chip bonding via fine graded 33 micron microbumps (e.g., copper pillars). In at least one embodiment, graphics core 2000 includes a memory structure including memory and a tile accessible by multiple tiles. In at least one embodiment, graphics core 2000 accesses or loads its own hardware contexts in memory, where a hardware context is a set of data that is loaded from registers prior to resumption of a process, and where a hardware context may indicate a state of hardware (e.g., a GPU's state).In at least one embodiment, graphics core 2000 includes a serializing / deserialization circuit (SERDES) that converts a serial data stream into a parallel data stream or a parallel data stream into a serial data stream.In at least one embodiment, graphics core 2000 includes a high speed unified coherent fabric (GPU to GPU), load / store units, mass transfer, and sync semantics, and GPUs connected via an embedded switch, where a GPU-GPU bridge is controlled by a controller.In at least one embodiment, graphics core 2000 executes an API, where API abstracts graphics core 2000 hardware and accesses libraries of instructions to perform mathematical operations (e.g., math core library), deep neural network operations (e.g., deep neural network library), vector operations, collective communication, thread building blocks, video processing, data analytics library, and / or ray tracing operations.In at least one embodiment, at least one component shown or described in FIG. 20A is used to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, graphics core 2000 performs one or more operations related to a neural network to derive hybrid beamforming parameters and / or transmit powers to be used by wireless signal transmission devices as described in connection with FIG. 1 and as described elsewhere herein.FIG. 20B illustrates the GPGPU 2030 that may be configured to enable highly parallel computational operations by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU 2030 may be directly connected to other instances of GPGPU 2030 to form a multi-GPU cluster and improve training speed for deep neural networks. In at least one embodiment, GPGPU 2030 includes a host interface 2032 to enable connection to a host processor. In at least one embodiment, host interface 2032 is a PCI Express interface. In at least one embodiment, host interface 2032 may be a proprietary interface or communication structure. In at least one embodiment, GPGPU 2030 receives instructions from a host processor and uses a global scheduler 2034 (which may be referred to as a thread sequencer and / or asynchronous compute engine) to distribute execution threads associated with these instructions to a series of compute clusters 2036A- 2036H. In at least one embodiment, compute clusters 2036A- 2036H share a cache memory 2038. In at least one embodiment, cache 2038 may serve as a parent cache for caches within compute clusters 2036A- 2036H. In at least one embodiment, compute clusters 2036A- 2036H comprise a slice or are referred to as "slices.". In at least one embodiment, GPGPU 2030 is part of a SoC, such as part of integrated circuit 1800 (FIG. 18 ).In at least one embodiment, GPGPU 2030 includes memory 2044A- 2044B coupled to compute clusters 2036A- 2036H via a series of memory controllers 2042A- 2042B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 2044A- 2044B may include various types of memory devices, including dynamic random access memory (DRAM), or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics dual data rate memory (GDDR).In at least one embodiment, compute clusters 2036A- 2036H each include a set of graphics cores, such as graphics core 2000 of FIG. 20A, which may include multiple types of integer and floating point logic units that may perform computational operations at a number of precisions that are also suitable for machine learning computations. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters 2036A- 2036H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units may be configured to perform 64-bit floating point operations.In at least one embodiment, multiple instances of GPGPU 2030 may be configured to operate as compute clusters. In at least one embodiment, communication used by compute clusters 2036A- 2036H for synchronization and data exchange varies among embodiments. In at least one embodiment, multiple instances of GPGPU 2030 communicate via host interface 2032. In at least one embodiment, GPGPU 2030 includes an I / O hub 2039 that couples GPGPU 2030 to a GPU link 2040 that enables direct connection to other instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is connected to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a high-speed link to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple GPGPU instances 2030 are located in separate computing systems and communicate over a network interface accessible via host interface 2032. In at least one embodiment, GPU link 2040 may be configured to enable a connection to a host processor in addition to or alternatively to host interface 2032.In at least one embodiment, GPGPU 2030 may be configured to train neural networks. In at least one embodiment, GPGPU 2030 may be used within an inferencing platform. In at least one embodiment where GPGPU 2030 is used for inferencing, GPGPU 2030 may include fewer compute clusters 2036A- 2036H than when GPGPU 2030 is used for neural network training. In at least one embodiment, memory technology associated with memory 2044A- 2044B may be different between inference and training configurations, where training configurations are assigned higher bandwidth memory technologies. In at least one embodiment, an inferencing configuration of GPGPU 2030 may support inferencing specific commands. For example, in at least one embodiment, an inference configuration may provide support for one or more 8-bit integer dot product instructions that may be used during inference operations for deployed neural networks.Logic 915 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 915 are described herein in connection with FIGS. 9A and / or 9B. In at least one embodiment, logic 915 in GPGPU 2030 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, at least one component shown or described in FIG. 20B is used to implement techniques and / or functions described in connection with FIGS. 1-8. In at least one embodiment, GPGPU 2030 performs one or more operations related to a neural network to derive hybrid beamforming parameters and / or transmit powers to be used by wireless signal transmission devices as described in connection with FIG. 1 and as described elsewhere herein.FIG. 21 is a block diagram illustrating a computer system 2100, according to at least one embodiment. In at least one embodiment, computer system 2100 includes a processing subsystem 2101 having one or more processor(s) 2102 and a system memory 2104 that communicate via an interconnect path that may include a memory hub 2105. In at least one embodiment, memory hub 2105 may be a separate component within a chipset component or integrated into one or more processor(s) 2102. In at least one embodiment, storage hub 2105 is connected to an I / O subsystem 2111 via a communication link 2106. In at least one embodiment, I / O subsystem 2111 includes an I / O hub 2107 that may allow computer system 2100 to receive input from one or more input device(s) 2108. In at least one embodiment, I / O hub 2107 may enable a display controller, which may include one or more processor(s) 2102, to provide output to one or more display device(s) 2110A. In at least one embodiment, one or more display device(s) 2110A coupled to I / O hub 2107 may include a local, internal, or embedded display device.In at least one embodiment, processing subsystem 2101 includes one or more parallel processor(s) 2112 that is / are connected to memory hub 2105 via bus or other communication link 2113. In at least one embodiment, communication link 2113 may use any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or a proprietary communication interface or communication fabric. In at least one embodiment, one or more parallel processor(s) 2112 form a computational-enhanced parallel or vector processing system, which may include a large number of computational cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, some or all of parallel processors 2112 form a graphics processing subsystem that can output pixels to one or more display device(s) 2110A coupled via I / O hub 2107. In at least one embodiment, parallel processor(s) 2112 may also include a display controller and display interface (not shown) to enable direct connection to one or more display device(s) 2110B. In at least one embodiment, parallel(s) processor(s) 2112 include one or more cores, such as graphics cores 2000 discussed herein.In at least one embodiment, a system storage unit 2114 may be coupled to I / O hub 2107 to provide a storage mechanism for computer system 2100. In at least one embodiment, an I / O switch 2116 may be used to provide an interface that enables connections between I / O hub 2107 and other components, such as a network adapter 2118 and / or a wireless network adapter 2119 that may be integrated into platform and various other devices that may be added via one or more add-in devices 2120. In at least one embodiment, network adapter 2118 may be an Ethernet adapter or other wired network adapter. In at least one embodiment, wireless network adapter 2119 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or another network device including one or more wireless radios.In at least one embodiment, computer system 2100 may include other components not explicitly shown, including USB or other connector connections, optical storage drives, video capture devices, and the like, which may also be connected to I / O hub 2107. In at least one embodiment, communication paths interconnecting various components in FIG. 21 may be implemented using any suitable protocols, such as peripheral component interconnect (PCI)-based protocols (e.g., PCI Express), or other bus or point-to-point communication interfaces and / or protocols, such as high speed NV-link connection or interconnect protocols.In at least one embodiment, parallel processor(s) 2112 include circuitry optimized for graphics and video processing, such as video output circuitry, and form a graphics processing unit (GPU), such as parallel processor(s) 2112 includes graphics core 2000. In at least one embodiment, parallel(s) processor(s) 2112 includes(s) general processing optimized circuitry. In at least one embodiment, components of computer system 2100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor(s) 2112, memory hub 2105, processor(s) 2102, and I / O hub 2107 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of computer system 2100 may be integrated into a s...

Claims

A processor comprising: one or more circuits for using one or more neural networks to generate one or more hybrid beamforming parameters used to transmit one or more wireless signals.The processor of claim 1, wherein the one or more circuits are to use the one or more neural networks to generate the one or more hybrid beamforming parameters by jointly deriving one or more analog beamforming parameters and one or more digital beamforming parameters.The processor of claim 1, wherein the generation of the one or more hybrid beamforming parameters is based at least in part on the optimization of one or more signal characteristics of the one or more radio signals to be transmitted.The processor of claim 1, wherein the one or more hybrid beamforming parameters are to be used to transmit the one or more wireless signals having one or more signal-to-noise ratios (SNRs) above a threshold at a base station of a new fifth generation radio network (5G NR).The processor of claim 1, wherein the one or more hybrid beamforming parameters comprise one or more complex values to be used for transmission of a wireless baseband signal.The processor of claim 1, wherein the one or more circuits are to use the one or more neural networks to generate the one or more hybrid beamforming parameters comprising a representation of one or more phase shifters using one or more one-hot vectors.The processor of claim 1, wherein the one or more hybrid beamforming parameters are to be used to modify the operation of one or more analog beamforming components and one or more digital beamforming components of a hybrid beamforming system used to transmit the one or more wireless signals.A system comprising: one or more processors to use one or more neural networks to generate one or more hybrid beamforming parameters used to transmit one or more wireless signals.The system of claim 8, wherein the one or more processors use the one or more neural networks to generate analog and digital beamforming parameters in a single inference pass.The system of claim 8, wherein the generation of the one or more hybrid beamforming parameters is based at least in part on the optimization of one or more signal-to-noise ratios (SNRs) of the one or more radio signals to be transmitted.The system of claim 8, wherein the one or more wireless signals are to be transmitted from a base station of a new fifth generation radio network (5G NR).The system of claim 8, wherein the one or more hybrid beamforming parameters satisfy a unit module constraint.The system of claim 8, wherein the one or more hybrid beamforming parameters are based at least in part on the representation of one or more phase shifters with one or more one-hot vectors.The system of claim 8, wherein the one or more processors are to use the one or more neural networks to output the one or more hybrid beamforming parameters as a single vector.A method comprising: using one or more neural networks to generate one or more hybrid beamforming parameters to be used to transmit one or more wireless signals.The method of claim 15, wherein the one or more neural networks are to generate the one or more hybrid beamforming parameters with a single forward pass.The method of claim 15, wherein the generation of the one or more hybrid beamforming parameters is based at least in part on a signal-to-noise ratio formula that uses analog beamforming parameters and digital beamforming parameters as inputs.The method of claim 15, wherein training the one or more neural networks is based at least in part on maximizing a reward function of a training process of a neural network with reinforcement learning.The method of claim 15, wherein the one or more hybrid beamforming parameters are output as a single vector to be applied to a uniform linear array of sensors.The method of claim 15, wherein the one or more hybrid beamforming parameters comprise a representation of one or more phase angles using one or more one-hot vectors.

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