Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises at least one transistor, and the transistor comprises a first source drain electrode, a second source drain electrode, a channel region and a gate structure. The channel region is located between the first source and drain electrode and the second source and drain electrode; the gate structure comprises a gate dielectric layer, a gate conductive layer and a first threshold voltage adjusting layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer is in contact with the channel region; wherein the first threshold voltage adjusting layer is used for adjusting the threshold voltage of the transistor.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As the integration density of memories develops towards a higher level, higher requirements are imposed on the arrangement manner of transistors and the size of transistors in the array structure of memories.

[0003] Currently, the structure of memories needs to be further improved. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof.

[0005] To achieve the above object, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, embodiments of the present disclosure provide a semiconductor device, where the semiconductor device includes at least one transistor, and the transistor includes: a first source / drain, a second source / drain, a channel region, and a gate structure;

[0007] The channel region is located between the first source / drain and the second source / drain;

[0008] The gate structure includes a gate dielectric layer, a gate conductive layer, and a first threshold voltage adjustment layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer is in contact with the channel region; wherein, the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor.

[0009] In some embodiments, the gate structure further includes a second threshold voltage adjustment layer located between the first threshold voltage adjustment layer and the gate conductive layer; wherein, the work function of the second threshold voltage adjustment layer is less than the work function of the first threshold voltage adjustment layer.

[0010] In some embodiments, each transistor includes a transistor column, and the transistor column sequentially includes the first source / drain, the channel region, and the second source / drain along an extending direction;

[0011] The gate structure covers at least one sidewall of the transistor column.

[0012] In some embodiments, the semiconductor device includes a plurality of transistors arranged in an array along a first direction and a second direction, and each transistor includes a transistor column extending along a third direction; wherein, any two of the first direction, the second direction, and the third direction are perpendicular to each other; the semiconductor device further includes:

[0013] A plurality of word lines extending in the first direction, and the word lines are connected to gate structures of a plurality of transistors arranged in the first direction;

[0014] A plurality of bit lines extending in the second direction, and the bit lines are connected to a plurality of first source / drain electrodes arranged in the second direction;

[0015] A plurality of storage capacitors, and the storage capacitors are connected to the second source / drain electrodes.

[0016] In some embodiments, the work function range of the first threshold voltage adjustment layer is from 4.6 eV to 6.9 eV.

[0017] In some embodiments, the thickness range of the first threshold voltage adjustment layer is from 0.25 nm to 4 nm.

[0018] In some embodiments, the transistor includes a junctionless field-effect transistor and a P-type transistor.

[0019] In some embodiments, the first threshold voltage adjustment layer includes molybdenum trioxide; and / or, the second threshold voltage adjustment layer includes molybdenum nitride; and / or, the gate conductive layer includes molybdenum.

[0020] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the semiconductor device including at least one transistor, the method including:

[0021] Providing at least one transistor pillar; the transistor pillar sequentially includes a first source / drain electrode, a channel region, and a second source / drain electrode along an extending direction;

[0022] Forming a gate dielectric layer covering at least one sidewall of the transistor pillar;

[0023] Forming a first metal material layer covering the gate dielectric layer;

[0024] Performing an oxidation treatment on the first metal material layer to form a first threshold voltage adjustment layer;

[0025] Forming a gate conductive layer covering the first threshold voltage adjustment layer; wherein, the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor.

[0026] In some embodiments, before forming the gate conductive layer covering the first threshold voltage adjustment layer, the method further includes:

[0027] Forming a second threshold voltage adjustment layer covering the first threshold voltage adjustment layer; wherein, the work function of the second threshold voltage adjustment layer is less than the work function of the first threshold voltage adjustment layer.

[0028] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. The semiconductor device includes at least one transistor, and the transistor includes: a first source / drain, a second source / drain, a channel region, and a gate structure; the channel region is located between the first source / drain and the second source / drain; the gate structure includes a gate dielectric layer, a gate conductive layer, and a first threshold voltage adjustment layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer contacts the channel region; wherein, the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor. In the embodiments of the present disclosure, a first threshold voltage adjustment layer is provided between the gate dielectric layer and the gate conductive layer. By using the first threshold voltage adjustment layer with a high work function, the difference between the work functions of the gate structure and the channel region material is increased, thereby increasing the threshold voltage of the transistor, and further improving the electrical performance of the semiconductor device by adjusting the threshold voltage of the transistor. Description of the Drawings

[0029] Figure 1 Schematic cross-sectional structure diagram of a semiconductor device provided for an example;

[0030] Figure 2 Schematic cross-sectional structure diagram of a semiconductor device provided for another example;

[0031] Figure 3 Schematic cross-sectional structure diagram of a semiconductor device provided for yet another example;

[0032] Figure 4 Schematic top view structure diagram of a semiconductor device provided for yet another example;

[0033] Figure 5 Schematic flow chart of the manufacturing method of the semiconductor device provided by the embodiments of the present disclosure;

[0034] Figures 6A to 6E Schematic top view structure diagram of the semiconductor device provided by the embodiments of the present disclosure during manufacturing. Detailed Embodiments

[0035] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present disclosure.

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of actual embodiments are described herein, and well-known functions and structures are not described in detail.

[0037] In the drawings, for the sake of clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Like reference numerals throughout the drawings denote like elements.

[0038] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings of the present disclosure. And when a second element, component, region, layer, or section is discussed, it does not necessarily imply that a first element, component, region, layer, or section exists in the present disclosure.

[0039] Spatial relationship terms such as “under,” “below,” “beneath,” “underneath,” “above,” “over,” etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, then an element or feature described as “under” or “beneath” or “underneath” another element or feature will be oriented “over” the other element or feature. Thus, the exemplary terms “under” and “beneath” can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0041] To fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0042] As the integration density of Dynamic Random Access Memory (DRAM) develops towards a higher level, higher requirements are imposed on the arrangement manner of transistors and the size of transistors in the DRAM array structure. Transistors with a Gate All Around (GAA) structure, as transistors in DRAM, can achieve a smaller size, which is beneficial to improving the integration density of DRAM.

[0043] However, the threshold voltage of the Gate All Around transistor is relatively low. Therefore, there is a current need to further improve the structure of transistors in the memory to adjust the threshold voltage of the transistors.

[0044] In view of this, embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof.

[0045] Referring to Figure 1 , Figure 1 is a schematic cross-sectional structure diagram of a semiconductor device provided as an example. As Figure 1 shown, embodiments of the present disclosure provide a semiconductor device. The semiconductor device 100 includes at least one transistor 102 (such as Figure 1As shown by the dashed box in the figure, the transistor 102 includes: a first source / drain 106, a second source / drain 108, and a channel region 110 disposed in a substrate 104; wherein, the channel region 110 is located between the first source / drain 106 and the second source / drain 108; a gate structure 112 disposed on the substrate 104, the gate structure 112 includes a gate dielectric layer 114, a gate conductive layer 116, and a first threshold voltage adjustment layer 118 located between the gate dielectric layer 114 and the gate conductive layer 116; the gate dielectric layer 114 is in contact with the channel region 110; wherein, the first threshold voltage adjustment layer 118 is used to adjust the threshold voltage of the transistor 102.

[0046] In the embodiments of the present disclosure, a first threshold voltage adjustment layer is provided between the gate dielectric layer and the gate conductive layer. By increasing the work function of the first threshold voltage adjustment layer, the difference between the work function of the gate structure and the work function of the channel region material is increased, thereby increasing the threshold voltage of the transistor, that is, the purpose of using the first threshold voltage adjustment layer to adjust the threshold voltage of the transistor to improve the electrical performance of the semiconductor device is achieved.

[0047] Here, the substrate may be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (such as a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. It may also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, and a silicon-germanium substrate, etc.

[0048] Exemplarily, the substrate can be doped to form the first source / drain and the second source / drain; wherein, the first source / drain and the second source / drain are doped regions. Exemplarily, the substrate can also be doped to form the channel region.

[0049] In some embodiments, when the first source / drain serves as the source of the transistor, the second source / drain serves as the drain of the transistor. In other embodiments, when the first source / drain serves as the drain of the transistor, the second source / drain serves as the source of the transistor.

[0050] In some embodiments, the type of doping ions in the doped region may be different from the type of doping ions in the channel region. For example, for a P-type Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the doping ions in the doped region are N-type ions, and the doping ions in the channel region are P-type ions; among them, the N-type ions can be, for example, arsenic ions, phosphorus ions or antimony ions; the P-type ions can be, for example, boron ions, indium ions or gallium ions.

[0051] In other embodiments, the type of doping ions in the doped region may be the same as the type of doping ions in the channel region. For example, a Junctionless Field Effect Transistor (JLT) can be formed.

[0052] Here, the material of the gate dielectric layer may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride.

[0053] Exemplarily, silicon oxide can be formed on a substrate made of silicon by a thermal oxidation process.

[0054] In some embodiments, the process of forming the gate dielectric layer may include but is not limited to Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD) or any combination thereof.

[0055] Here, the material of the gate conductive layer may include but is not limited to metal materials and semiconductor materials. Among them, the metal materials can be, for example, gold, aluminum, copper, tungsten or molybdenum, etc.; the semiconductor materials can be, for example, polysilicon.

[0056] In some embodiments, the process of forming the gate conductive layer may include but is not limited to CVD, PVD, ALD or any combination thereof.

[0057] In some embodiments, the work function range of the first threshold voltage adjustment layer 118 is from 4.6 eV to 6.9 eV. Optionally, the work function range of the first threshold voltage adjustment layer 118 is from 6 eV to 6.9 eV.

[0058] In the embodiments of the present disclosure, a first threshold voltage adjustment layer is provided between the gate dielectric layer and the gate conductive layer in the gate structure. By increasing the work function of the first threshold voltage adjustment layer, the difference between the work function of the gate structure and the material of the channel region is increased, thereby increasing the threshold voltage of the transistor.

[0059] In some embodiments, the material of the first threshold voltage adjustment layer may be molybdenum trioxide (MoO 3 ).

[0060] Here, molybdenum trioxide is an indirect bandgap material with a bandgap of about 3.0 eV. At the same time, it is an excellent semiconductor oxide material with a high work function and is the most stable oxide of molybdenum. Specifically, the work function of molybdenum trioxide can reach 6.9 eV.

[0061] Exemplarily, molybdenum can be formed on the gate dielectric layer by ALD process, and molybdenum trioxide can be obtained after multiple oxidation treatments of molybdenum using oxygen (O 2 ) or ozone (O 3 ).

[0062] In some embodiments, the thickness range of the first threshold voltage adjustment layer 118 is from 0.25 nm to 4 nm.

[0063] Here, when the material of the first threshold voltage adjustment layer is the same, the thickness is one of the factors affecting the work function of the first threshold voltage adjustment layer.

[0064] Taking the material of the first threshold voltage adjustment layer as molybdenum trioxide as an example, as the thickness of the first threshold voltage adjustment layer increases, the work function of the first threshold voltage adjustment layer first increases and then remains basically unchanged. When the thickness of the first threshold voltage adjustment layer 118 is greater than 0.25 nm, the work function of the first threshold voltage adjustment layer is greater than 6.0 eV. However, as the thickness of the first threshold voltage adjustment layer increases, the size of the semiconductor device also increases, which is not conducive to improving the integration density of the semiconductor device.

[0065] In the above embodiments, by limiting the thickness of the first threshold voltage adjustment layer within the above range, high work function and high integration density can be taken into account at the same time.

[0066] In some embodiments, the transistor 102 includes a junctionless field effect transistor and a P-type transistor.

[0067] Here, since the threshold voltages of the junctionless vertical channel transistor (Vertical Channel Transistor, VCT) and the P-type transistor are relatively low, therefore, it is more necessary to improve the structures of the junctionless vertical channel transistor and the P-type transistor to increase the threshold voltages of the junctionless vertical channel transistor and the P-type transistor.

[0068] Refer to Figure 2 , Figure 2 which is a schematic cross-sectional structure diagram of a semiconductor device provided for another example. As Figure 2As shown, in some embodiments, the gate structure 112 further includes a second threshold voltage adjustment layer 120 located between the first threshold voltage adjustment layer 118 and the gate conductive layer 116; wherein, the work function of the second threshold voltage adjustment layer 120 is less than that of the first threshold voltage adjustment layer 118.

[0069] In the embodiments of the present disclosure, a second threshold voltage adjustment layer is further provided between the first threshold voltage adjustment layer and the gate conductive layer in the gate structure. By increasing the work function of the second threshold voltage adjustment layer and utilizing the high work functions of the first threshold voltage adjustment layer and the second threshold voltage adjustment layer, the difference between the work function of the gate structure and the work function of the channel region material is increased, thereby increasing the threshold voltage of the transistor.

[0070] In addition, the work function of the second threshold voltage adjustment layer is less than that of the first threshold voltage adjustment layer. The second threshold voltage adjustment layer can not only increase the threshold voltage of the transistor but also reduce the resistance of the gate structure.

[0071] In some embodiments, the material of the second threshold voltage adjustment layer can be molybdenum nitride.

[0072] Here, the work function of molybdenum nitride varies with different nitrogen contents. Compared with MoN, the nitrogen content in Mo 2 N is lower, and the work function of Mo 2 N is smaller; the work function of Mo 2 N is about 4.47 eV, and the work function of MoN is greater than 5 eV.

[0073] In some embodiments, the process for forming the second threshold voltage adjustment layer may include, but is not limited to, ALD.

[0074] In some embodiments, the first threshold voltage adjustment layer 118 includes molybdenum trioxide; and / or, the second threshold voltage adjustment layer 120 includes molybdenum nitride; and / or, the gate conductive layer 116 includes molybdenum.

[0075] Exemplarily, molybdenum can be formed on the gate dielectric layer by ALD process, and the molybdenum is oxidized to form molybdenum trioxide as the first threshold voltage adjustment layer; then, molybdenum nitride can be formed on the first threshold voltage adjustment layer by ALD process, and the molybdenum nitride is used as the second threshold voltage adjustment layer; alternatively, molybdenum nitride can be used as the seed layer, and molybdenum is continuously grown on the second threshold voltage adjustment layer by ALD process as the gate conductive layer.

[0076] As mentioned above, the gate structure provided by the embodiments of the present disclosure is particularly used for vertical channel transistors and P-type transistors. Refer to Figure 3 and Figure 4 , Figure 3 which is a schematic cross-sectional structure diagram of a semiconductor device provided as another example. Figure 4A top view structural schematic diagram of a semiconductor device provided for another example. The following will be combined with Figure 3 and Figure 4 , taking the semiconductor device as a vertical channel transistor as an example for detailed description.

[0077] Before introducing the vertical channel transistor, each direction of the semiconductor device is defined first. The extending direction of the transistor column in the vertical channel transistor is defined as the third direction, that is, the Z direction. In the plane perpendicular to the third direction, the intersecting first direction and second direction are defined, that is, the X direction and the Y direction. Alternatively, the semiconductor device includes a plurality of transistors arranged in an array, and the arranging direction of the plurality of transistors is defined as the intersecting first direction and second direction, that is, the X direction and the Y direction. In some embodiments, any two of the X direction, the Y direction, and the Z direction are perpendicular to each other.

[0078] In some embodiments, the semiconductor device 200 includes a plurality of transistors 202 arranged in an array along the first direction (i.e., the X direction) and the second direction (i.e., the Y direction), and each transistor 202 includes a transistor column 204 extending along the third direction (i.e., the Z direction).

[0079] Figure 3 Schematically shows a YZ plane cross-sectional view of the semiconductor device, Figure 4 Schematically shows an XY plane top view of the semiconductor device. As Figure 3 and Figure 4 shown, in some embodiments, the semiconductor device 200 includes at least one transistor 202 (as shown by the dotted circular frame in Figure 4 ), each transistor 202 includes a transistor column 204, and the transistor column 204 sequentially includes a first source-drain 206, a channel region 210, and a second source-drain 208 along the extending direction; the gate structure 212 covers at least one sidewall of the transistor column 204.

[0080] In some embodiments, the positive projection of the transistor column on the XY plane may be a quadrilateral, and the transistor column includes four sidewalls, wherein, two sidewalls are oppositely arranged along the X direction, and the other two sidewalls are oppositely arranged along the Y direction. In other embodiments, the positive projection of the transistor column on the XY plane may also be circular, elliptical, etc., and the present disclosure has no special limitation on the shape of the positive projection of the transistor column on the XY plane.

[0081] In some embodiments, the gate structure covers one sidewall of the transistor column, that is, a single-gate transistor is formed.

[0082] In some embodiments, the gate structure covers two sidewalls of the transistor column, that is, a double-gate transistor is formed.

[0083] In some embodiments, the gate structure covers three sidewalls of the transistor column, that is, a triple-gate transistor is formed.

[0084] In some embodiments, the gate structure covers four sidewalls of the transistor pillar, i.e., a fully-depleted surround gate transistor is formed. Figure 3 and Figure 4 illustrates a fully-depleted surround gate transistor.

[0085] Here, the gate structure 212 sequentially includes a gate dielectric layer 214, a first threshold voltage adjustment layer 218, a second threshold voltage adjustment layer 220, and a gate conductive layer 216; wherein, the gate dielectric layer 214 surrounds the channel region 210 of the transistor pillar 204, the first threshold voltage adjustment layer 218 surrounds the gate dielectric layer 214, the second threshold voltage adjustment layer 220 surrounds the first threshold voltage adjustment layer 218, and the gate conductive layer 216 surrounds the second threshold voltage adjustment layer 220.

[0086] As Figure 4 shown, in some embodiments, the semiconductor device 200 further includes: a plurality of word lines 222 extending along the X direction (as Figure 4 shown by the center dash-dotted square), and the word lines 222 are connected to the gate structures 212 of a plurality of transistors 202 arranged along the X direction; a plurality of bit lines extending along the Y direction, and the bit lines are connected to a plurality of first source / drain electrodes 206 arranged along the Y direction; a plurality of storage capacitors, and the storage capacitors are connected to the second source / drain electrode 208.

[0087] Here, the semiconductor device includes a plurality of word lines 222 extending along the X direction and arranged in sequence along the Y direction, and a plurality of bit lines extending along the Y direction and arranged in sequence along the X direction. Among them, adjacent word lines 222 are separated by a first isolation layer 224.

[0088] In some embodiments, when the transistor pillar sequentially includes a first source / drain electrode, a channel region, and a second source / drain electrode along the extending direction, a bit line connected to the first source / drain electrode can be formed on the front surface of the substrate, the back surface of the substrate is thinned to expose the second source / drain electrode, and a storage capacitor connected to the second source / drain electrode is formed on the back surface of the substrate.

[0089] In other embodiments, when the transistor pillar sequentially includes a first source / drain electrode, a channel region, and a second source / drain electrode along the extending direction, a buried bit line connected to the second source / drain electrode can be formed on the front surface of the substrate, and a storage capacitor connected to the first source / drain electrode is formed on the front surface of the substrate.

[0090] In still other embodiments, when the transistor pillar sequentially includes a first source / drain electrode, a channel region, and a second source / drain electrode along the extending direction, a storage capacitor connected to the first source / drain electrode can be formed on the front surface of the substrate, the back surface of the substrate is thinned to expose the second source / drain electrode, and a bit line connected to the second source / drain electrode is formed on the back surface of the substrate.

[0091] In some embodiments, the material of the bit line may include, but is not limited to, metals, metal compounds, or alloys. Among them, the metal may be, for example, copper, aluminum, tungsten, gold, or silver; the metal compound may be, for example, tantalum nitride or titanium nitride; the alloy may be an alloy formed by at least two of the metal elements of copper, aluminum, tungsten, gold, or silver.

[0092] Reference Figure 5 , Figure 5 is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure. As Figure 5 shown, an embodiment of the present disclosure also provides a method for manufacturing a semiconductor device. The semiconductor device includes at least one transistor, and the method includes:

[0093] Step S501: Provide at least one transistor pillar; the transistor pillar sequentially includes a first source-drain, a channel region, and a second source-drain along the extending direction;

[0094] Step S502: Form a gate dielectric layer covering at least one sidewall of the transistor pillar;

[0095] Step S503: Form a first metal material layer covering the gate dielectric layer;

[0096] Step S504: Perform an oxidation treatment on the first metal material layer to form a first threshold voltage adjustment layer;

[0097] Step S505: Form a gate conductive layer covering the first threshold voltage adjustment layer; wherein, the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor.

[0098] In the embodiment of the present disclosure, a first threshold voltage adjustment layer is provided between the gate dielectric layer and the gate conductive layer. By increasing the work function of the first threshold voltage adjustment layer, the difference between the work function of the gate structure and the material of the channel region is increased, thereby increasing the threshold voltage of the transistor, that is, the purpose of adjusting the threshold voltage of the transistor by using the first threshold voltage adjustment layer to improve the electrical performance of the semiconductor device is achieved.

[0099] Reference Figures 6A to 6E , Figures 6A to 6E is a schematic top view structure diagram of a semiconductor device provided by an embodiment of the present disclosure during manufacturing. The manufacturing process of the semiconductor device will be described in detail below with reference to Figure 5 and Figures 6A to 6E .

[0100] In the embodiment of the present disclosure, in step S501, at least one transistor pillar 204 is provided; the transistor pillar 204 sequentially includes a first source-drain 206, a channel region 210, and a second source-drain 208 along the extending direction.

[0101] As Figure 6AAs shown, transistor columns 204 are formed on a substrate and arranged in an array along the X direction and the Y direction.

[0102] Exemplarily, forming the transistor columns may include: providing a substrate; etching the substrate to form a plurality of first grooves extending along the Y direction and a plurality of semiconductor strips extending along the Y direction, and filling the isolation material in the first grooves; etching the substrate to form a plurality of second grooves extending along the X direction and a plurality of semiconductor columns (i.e., transistor columns) arranged in an array along the X direction and the Y direction, and filling the isolation material in the second grooves.

[0103] In some embodiments, after forming the semiconductor columns, the semiconductor columns may be doped to form doped regions (i.e., the first source / drain and the second source / drain) and channel regions.

[0104] Exemplarily, after forming the semiconductor columns, the semiconductor columns may be doped by ion implantation or thermal diffusion processes. Alternatively, after doping the substrate, the substrate is etched to form a plurality of semiconductor columns arranged in an array, such that the semiconductor columns have channel regions and the first source / drain and the second source / drain located on both sides of the channel regions.

[0105] As Figure 6A shown, in some embodiments, before forming the gate dielectric layer, it further includes: forming a first isolation layer 224 and a second isolation layer 226, the second isolation layer 226 is located between adjacent transistor columns 204, and the first isolation layer 224 penetrates the second isolation layer 226 between adjacent transistor columns 204 along the X direction; wherein, the first isolation layer 224 is used to isolate adjacent word lines formed subsequently and prevent electrical interference between adjacent conductive structures.

[0106] In some embodiments, the materials of the first isolation layer and the second isolation layer may include but are not limited to silicon nitride.

[0107] In the embodiments of the present disclosure, in step S502, a gate dielectric layer 214 covering at least one sidewall of the transistor column 204 is formed.

[0108] As Figure 6B shown, the second isolation layer 226 is removed to form a word line groove 230 exposing the sidewalls of the transistor column 204 (as Figure 6B shown by the dashed square); a gate dielectric layer 214 surrounding the sidewalls of the transistor column 204 and covering the sidewalls of the word line groove 230 is formed.

[0109] Exemplarily, silicon oxide may be formed as the gate dielectric layer by an ALD process or an in-situ steam generation (ISSG) process.

[0110] In the embodiments of the present disclosure, in step S503, a first metal material layer 228 covering the gate dielectric layer 214 is formed.

[0111] As Figure 6B shown, a first metal material layer 228 is formed surrounding the gate dielectric layer 214 on the sidewall of the transistor pillar 204 and covering the sidewall of the word line groove 230.

[0112] Exemplarily, molybdenum can be formed as the first metal material layer by an ALD process.

[0113] In the embodiments of the present disclosure, in step S504, the first metal material layer 228 is oxidized to form a first threshold voltage adjustment layer 218.

[0114] As Figure 6C shown, the first metal material layer 228 is oxidized to form a first threshold voltage adjustment layer 218. Wherein, the first threshold voltage adjustment layer 218 surrounds the gate dielectric layer 214 on the sidewall of the transistor pillar 204 and covers the sidewall of the word line groove 230.

[0115] Exemplarily, the first metal material layer can be formed by an ALD process, such as molybdenum; the first metal material layer is oxidized using oxygen or ozone to form a first threshold voltage adjustment layer, such as molybdenum trioxide. The first metal material layer can be formed multiple times, and oxidized multiple times to form the first threshold voltage adjustment layer.

[0116] In some embodiments, before step S505, the method further includes: forming a second threshold voltage adjustment layer 220 covering the first threshold voltage adjustment layer 218; wherein, the work function of the second threshold voltage adjustment layer 220 is less than the work function of the first threshold voltage adjustment layer 218.

[0117] As Figure 6D shown, a second threshold voltage adjustment layer 220 is formed surrounding the first threshold voltage adjustment layer 218 on the sidewall of the transistor pillar 204 and covering the sidewall of the word line groove 230.

[0118] In the embodiments of the present disclosure, in step S505, a gate conductive layer 216 covering the first threshold voltage adjustment layer 218 is formed; wherein, the first threshold voltage adjustment layer 218 is used to adjust the threshold voltage of the transistor 202. Here, after forming the second threshold voltage adjustment layer 220, a gate conductive layer 216 covering the second threshold voltage adjustment layer 220 is formed.

[0119] As Figure 6EAs shown, a gate conductive layer 216 is formed to surround the second threshold voltage adjustment layer 220 on the sidewall of the transistor pillar 204 and cover the sidewall of the word line groove 230; wherein, the gate dielectric layer 214, the first threshold voltage adjustment layer 218, the second threshold voltage adjustment layer 220, and the gate conductive layer 216 surrounding the sidewall of the transistor pillar 204 together form a gate structure 212.

[0120] Exemplarily, the second threshold voltage adjustment layer can be formed by an ALD process, such as molybdenum nitride; using molybdenum nitride as a seed layer to grow and form a gate conductive layer, such as molybdenum.

[0121] As Figure 6E shown, in the embodiments of the present disclosure, the method further includes: forming a plurality of word lines 222 extending in the X direction (as Figure 6E shown by the mid-dashed box), and the word lines 222 are connected to the gate structures of a plurality of transistors 202 arranged in the X direction; forming a plurality of bit lines extending in the Y direction, and the bit lines are connected to a plurality of first source / drain electrodes arranged in the Y direction; forming a plurality of storage capacitors, and the storage capacitors are connected to the second source / drain electrodes.

[0122] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. The semiconductor device includes at least one transistor, and the transistor includes: a first source / drain electrode, a second source / drain electrode, a channel region, and a gate structure; the channel region is located between the first source / drain electrode and the second source / drain electrode; the gate structure includes a gate dielectric layer, a gate conductive layer, and a first threshold voltage adjustment layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer is in contact with the channel region; wherein, the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor. In the embodiments of the present disclosure, a first threshold voltage adjustment layer is provided between the gate dielectric layer and the gate conductive layer. By using the first threshold voltage adjustment layer with a high work function, the difference between the work function of the gate structure and the work function of the channel region material is increased, thereby increasing the threshold voltage of the transistor, and further improving the electrical performance of the semiconductor device by adjusting the threshold voltage of the transistor.

[0123] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the sequence numbers of the above processes do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The sequence numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0124] The above are only the preferred embodiments of the present disclosure, and do not limit the patent scope of the present disclosure. Any equivalent structural transformation made under the inventive concept of the present disclosure by using the content of the specification and drawings of the present disclosure, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, the semiconductor device includes at least one transistor, and the transistor includes: a first source-drain, a second source-drain, a channel region, and a gate structure; the channel region is located between the first source-drain and the second source-drain; the gate structure includes a gate dielectric layer, a gate conductive layer, and a first threshold voltage adjustment layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer contacts the channel region; wherein, the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor.

2. The semiconductor device according to claim 1, characterized in that, the gate structure further includes a second threshold voltage adjustment layer located between the first threshold voltage adjustment layer and the gate conductive layer; wherein, the work function of the second threshold voltage adjustment layer is less than the work function of the first threshold voltage adjustment layer.

3. The semiconductor device according to claim 1 or 2, characterized in that, each transistor includes a transistor column, and the transistor column sequentially includes the first source-drain, the channel region, and the second source-drain along the extending direction; the gate structure covers at least one sidewall of the transistor column.

4. The semiconductor device according to claim 3, characterized in that, the semiconductor device includes a plurality of transistors arranged in an array along a first direction and a second direction, and each transistor includes a transistor column extending along a third direction; wherein, any two of the first direction, the second direction, and the third direction are perpendicular to each other; the semiconductor device further includes: a plurality of word lines extending along the first direction, and the word lines are connected to the gate structures of the plurality of transistors arranged along the first direction; a plurality of bit lines extending along the second direction, and the bit lines are connected to the plurality of first source-drains arranged along the second direction; a plurality of storage capacitors, and the storage capacitors are connected to the second source-drains.

5. The semiconductor device according to claim 1, characterized in that, the work function range of the first threshold voltage adjustment layer is 4.6 eV to 6.9 eV.

6. The semiconductor device according to claim 1, characterized in that, the thickness range of the first threshold voltage adjustment layer is 0.25 nm to 4 nm.

7. The semiconductor device according to claim 1, characterized in that, the transistor includes a junctionless field effect transistor and a P-type transistor.

8. The semiconductor device according to claim 2, characterized in that, the first threshold voltage adjustment layer includes molybdenum trioxide; and / or, the second threshold voltage adjustment layer includes molybdenum nitride; and / or, the gate conductive layer includes molybdenum.

9. A manufacturing method of a semiconductor device, characterized in that, the semiconductor device includes at least one transistor, and the method includes: providing at least one transistor column; the transistor column sequentially includes a first source-drain, a channel region, and a second source-drain along the extending direction; forming a gate dielectric layer covering at least one sidewall of the transistor column; forming a first metal material layer covering the gate dielectric layer; The first metal material layer is oxidized to form a first threshold voltage adjustment layer; A gate conductive layer covering the first threshold voltage adjustment layer is formed; wherein, the first threshold voltage adjustment layer is used to adjust the threshold voltage of the transistor.

10. The manufacturing method of the semiconductor device according to claim 9, characterized in that, Before forming the gate conductive layer covering the first threshold voltage adjustment layer, the method further includes: Forming a second threshold voltage adjustment layer covering the first threshold voltage adjustment layer; wherein, the work function of the second threshold voltage adjustment layer is less than the work function of the first threshold voltage adjustment layer.

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