Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. The semiconductor device comprises at least one transistor, the transistor comprising: a first source / drain, a second source / drain, a channel region, and a gate structure; the channel region is located between the first source / drain and the second source / drain; the gate structure comprises a gate dielectric layer, a gate conductive layer, and a first threshold voltage adjusting layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer is in contact with the channel region; wherein the first threshold voltage adjusting layer is used to adjust the threshold voltage of the transistor.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to the technical field of semiconductor technology, in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] With the development of the integration density of the memory towards higher direction, higher requirements are generated for the arrangement mode of the transistor and the size of the transistor in the array structure of the memory.

[0003] At present, the structure of the memory needs to be further improved. SUMMARY

[0004] Therefore, the embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof.

[0005] To achieve the above object, the technical scheme of the present disclosure is as follows:

[0006] In a first aspect, the embodiment of the present disclosure provides a semiconductor device, comprising at least one transistor, the transistor comprising: a first source / drain, a second source / drain, a channel region and a gate structure.

[0007] The channel region is located between the first source / drain and the second source / drain.

[0008] The gate structure comprises a gate dielectric layer, a gate conductive layer and a first threshold voltage adjusting layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer is in contact with the channel region; wherein the first threshold voltage adjusting layer is used to adjust the threshold voltage of the transistor.

[0009] In some embodiments, the gate structure further comprises a second threshold voltage adjusting layer located between the first threshold voltage adjusting layer and the gate conductive layer; wherein the work function of the second threshold voltage adjusting layer is smaller than the work function of the first threshold voltage adjusting layer.

[0010] In some embodiments, each transistor comprises a transistor column, the transistor column comprising the first source / drain, the channel region and the second source / drain in sequence along an extension direction.

[0011] The gate structure covers at least one sidewall of the transistor column.

[0012] In some embodiments, the semiconductor device comprises a plurality of transistors arranged in an array along a first direction and a second direction, each transistor comprising a transistor column extending along a third direction; wherein any two of the first direction, the second direction and the third direction are perpendicular to each other; the semiconductor device further comprises:

[0013] a plurality of word lines extending along the first direction, and the word lines are connected with gate structures of a plurality of the transistors arranged along the first direction;

[0014] a plurality of bit lines extending along the second direction, and the bit lines are connected with a plurality of the first source-drains arranged along the second direction;

[0015] a plurality of storage capacitors, and the storage capacitors are connected with the second source-drains.

[0016] In some embodiments, a work function of the first threshold voltage adjusting layer ranges from 4.6 eV to 6.9 eV.

[0017] In some embodiments, a thickness of the first threshold voltage adjusting layer ranges from 0.25 nm to 4 nm.

[0018] In some embodiments, the transistor includes a junctionless field effect transistor and a P-type transistor.

[0019] In some embodiments, the first threshold voltage adjusting layer includes molybdenum trioxide; and / or, the second threshold voltage adjusting layer includes molybdenum nitride; and / or, the gate conductive layer includes molybdenum.

[0020] In a second aspect, the embodiments of the present disclosure provide a manufacturing method of a semiconductor device including at least one transistor, the method comprising:

[0021] providing at least one transistor column; the transistor column includes, in sequence along an extending direction, a first source-drain, a channel region, and a second source-drain;

[0022] forming a gate dielectric layer covering at least one sidewall of the transistor column;

[0023] forming a first metal material layer covering the gate dielectric layer;

[0024] performing an oxidation treatment on the first metal material layer to form a first threshold voltage adjusting layer;

[0025] forming a gate conductive layer covering the first threshold voltage adjusting layer; wherein the first threshold voltage adjusting layer is used to adjust a threshold voltage of the transistor.

[0026] In some embodiments, before the forming of the gate conductive layer covering the first threshold voltage adjusting layer, the method further comprises:

[0027] forming a second threshold voltage adjusting layer covering the first threshold voltage adjusting layer; wherein a work function of the second threshold voltage adjusting layer is less than a work function of the first threshold voltage adjusting layer.

[0028] The semiconductor device provided by the embodiment of the present disclosure comprises at least one transistor, and the transistor comprises a first source / drain, a second source / drain, a channel region and a gate structure. The channel region is located between the first source / drain and the second source / drain. The gate structure comprises a gate dielectric layer, a gate conductive layer and a first threshold voltage adjusting layer located between the gate dielectric layer and the gate conductive layer. The gate dielectric layer is in contact with the channel region. The first threshold voltage adjusting layer is used to adjust the threshold voltage of the transistor. In the embodiment of the present disclosure, the first threshold voltage adjusting layer is arranged between the gate dielectric layer and the gate conductive layer. The first threshold voltage adjusting layer with high work function is used to increase the difference between the work function of the gate structure and the work function of the channel region, thereby increasing the threshold voltage of the transistor. The electrical performance of the semiconductor device is improved by adjusting the threshold voltage of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 A cross-sectional structure schematic diagram of a semiconductor device provided for an example is shown in the figure.

[0030] Figure 2 A cross-sectional structure schematic diagram of a semiconductor device provided for another example is shown in the figure.

[0031] Figure 3 A cross-sectional structure schematic diagram of a semiconductor device provided for another example is shown in the figure.

[0032] Figure 4 A top view structure schematic diagram of a semiconductor device provided for another example is shown in the figure.

[0033] Figure 5 A flowchart of a manufacturing method of a semiconductor device provided by the embodiment of the present disclosure is shown in the figure.

[0034] Figures 6A to 6E A top view structure schematic diagram of a semiconductor device in a manufacturing process provided by the embodiment of the present disclosure is shown in the figure. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in combination with the embodiments of the present disclosure and the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present disclosure.

[0036] In the following description, numerous specific details are given to provide a thorough understanding of the disclosure. However, it will be apparent that the disclosure can be practiced without one or more of the specific details. In other instances, well-known features are not described in order to avoid obscuring the disclosure. Unless otherwise specifically defined herein, all terms are to be given their broadest possible interpretation including modifi cations and variants thereof. For example, the terms "including" and "comprising" should be given their broadest interpretative meanings, that is, "including", but not limited to.

[0037] In the drawings, the size of layers, regions, elements, and the like, can be exaggerated for clarity. Like reference numerals in different drawings denote like elements.

[0038] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, then there are no intervening elements or layers present. It will be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Conversely, a second element, component, region, layer or section discussed need not necessarily be termed a first element, component, region, layer or section.

[0039] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0042] As the integration density of Dynamic Random Access Memory (DRAM) continues to increase, higher demands are placed on the arrangement and size of transistors in the DRAM array structure. Gate-All-Around (GAA) transistors, used in DRAM, can achieve smaller sizes, which is beneficial for improving the integration density of DRAM.

[0043] However, the threshold voltage of all-around gate transistors is relatively low. Therefore, further improvements to the transistor structure in memory are needed to adjust the threshold voltage of the transistors.

[0044] In view of the above, this disclosure provides a semiconductor device and a method for manufacturing the same.

[0045] refer to Figure 1 , Figure 1 This is a schematic cross-sectional view of a semiconductor device as an example. Figure 1 As shown, this disclosure provides a semiconductor device 100, which includes at least one transistor 102 (e.g., ...). Figure 1As shown in the middle dashed box, the transistor 102 comprises: a first source-drain 106 and a second source-drain 108 and a channel region 110 disposed in a substrate 104, wherein the channel region 110 is located between the first source-drain 106 and the second source-drain 108; a gate structure 112 disposed on the substrate 104, the gate structure 112 comprising a gate dielectric layer 114, a gate conductive layer 116, and a first threshold voltage adjusting layer 118 located between the gate dielectric layer 114 and the gate conductive layer 116; the gate dielectric layer 114 is in contact with the channel region 110; wherein the first threshold voltage adjusting layer 118 is used to adjust the threshold voltage of the transistor 102.

[0046] In the embodiments of the present disclosure, the first threshold voltage adjusting layer is disposed between the gate dielectric layer and the gate conductive layer, and the work function of the first threshold voltage adjusting layer is increased to increase the difference between the work function of the gate structure and the work function of the channel region material, so as to increase the threshold voltage of the transistor, that is, to achieve the purpose of adjusting the threshold voltage of the transistor by the first threshold voltage adjusting layer to improve the electrical performance of the semiconductor device.

[0047] Here, the substrate can be a semiconductor substrate; specifically including at least one single-element semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (such as a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art, and can also include other semiconductor-containing substrates, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, and a silicon germanium substrate, etc.

[0048] Exemplarily, the substrate can be doped to form the first source-drain and the second source-drain; wherein the first source-drain and the second source-drain are doped regions. Exemplarily, the substrate can also be doped to form the channel region.

[0049] In some embodiments, the first source-drain serves as the source of the transistor, and the second source-drain serves as the drain of the transistor. In other embodiments, the first source-drain serves as the drain of the transistor, and the second source-drain serves as the source of the transistor.

[0050] In some embodiments, the type of the doping ions in the doping region can be different from the type of the doping ions in the channel region. For example, for a P-type Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), the doping ions in the doping region can be N-type ions, and the doping ions in the channel region can be P-type ions. The N-type ions can be, for example, arsenic ions, phosphorus ions, or antimony ions. The P-type ions can be, for example, boron ions, indium ions, or gallium ions.

[0051] In some other embodiments, the type of the doping ions in the doping region can be the same as the type of the doping ions in the channel region. For example, a Junctionless Field Effect Transistor (JLT) can be formed.

[0052] Here, the material of the gate dielectric layer can include, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride.

[0053] Exemplarily, the silicon oxide can be formed on a substrate with a material of silicon by a thermal oxidation process.

[0054] In some embodiments, the process of forming the gate dielectric layer can include, but is not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

[0055] Here, the material of the gate conductive layer can include, but is not limited to, a metal material and a semiconductor material. The metal material can be, for example, gold, aluminum, copper, tungsten, or molybdenum, etc. The semiconductor material can be, for example, polysilicon.

[0056] In some embodiments, the process of forming the gate conductive layer can include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0057] In some embodiments, the work function of the first threshold voltage adjusting layer 118 ranges from 4.6 eV to 6.9 eV. Optionally, the work function of the first threshold voltage adjusting layer 118 ranges from 6 eV to 6.9 eV.

[0058] In the embodiments of the present disclosure, the first threshold voltage adjusting layer is arranged between the gate dielectric layer and the gate conductive layer in the gate structure. By increasing the work function of the first threshold voltage adjusting layer, the difference between the work function of the gate structure and the work function of the channel region material is increased, so as to increase the threshold voltage of the transistor.

[0059] In some embodiments, the material of the first threshold voltage adjusting layer can be molybdenum trioxide (MoO3).

[0060] Here, molybdenum trioxide is an indirect bandgap material with a bandgap of about 3.0 eV, and is also a good semiconductor oxide material with a high work function, and is the most stable oxide of molybdenum. Specifically, the work function of molybdenum trioxide can reach 6.9 eV.

[0061] Exemplarily, molybdenum can be formed on the gate dielectric layer by an ALD process, and molybdenum trioxide can be obtained after multiple oxidation treatments of molybdenum using oxygen (O2) or ozone (O3).

[0062] In some embodiments, the thickness of the first threshold voltage adjusting layer 118 ranges from 0.25 nm to 4 nm.

[0063] Here, in the case where the material of the first threshold voltage adjusting layer is the same, the thickness is one of the factors affecting the work function of the first threshold voltage adjusting layer.

[0064] Taking molybdenum trioxide as the material of the first threshold voltage adjusting layer as an example, as the thickness of the first threshold voltage adjusting layer increases, the work function of the first threshold voltage adjusting layer first increases and then remains basically unchanged. When the thickness of the first threshold voltage adjusting layer 118 is greater than 0.25 nm, the work function of the first threshold voltage adjusting layer is greater than 6.0 eV. However, as the thickness of the first threshold voltage adjusting layer increases, the size of the semiconductor device also increases, which is not conducive to improving the integration density of the semiconductor device.

[0065] In the above embodiments, by limiting the thickness of the first threshold voltage adjusting layer within the above range, high work function and high integration density can be simultaneously considered.

[0066] In some embodiments, the transistor 102 includes a junctionless field effect transistor and a P-type transistor.

[0067] Here, since the threshold voltage of the junctionless vertical channel transistor (VCT) and the P-type transistor is low, it is more necessary to improve the structure of the junctionless vertical channel transistor and the P-type transistor to increase the threshold voltage of the junctionless vertical channel transistor and the P-type transistor.

[0068] Reference Figure 2 , Figure 2 A cross-sectional structure schematic diagram of a semiconductor device provided for another example is shown in FIG. 2. As shown in FIG. 2, the semiconductor device includes a substrate 202, a gate dielectric layer 204, a first threshold voltage adjusting layer 206, a gate electrode layer 208, a source electrode layer 210, and a drain electrode layer 212. Figure 2As shown, in some embodiments, the gate structure 112 further includes a second threshold voltage adjustment layer 120 located between the first threshold voltage adjustment layer 118 and the gate conductive layer 116; wherein the work function of the second threshold voltage adjustment layer 120 is less than the work function of the first threshold voltage adjustment layer 118.

[0069] In this embodiment of the present disclosure, a second threshold voltage adjustment layer is further provided between the first threshold voltage adjustment layer and the gate conductive layer in the gate structure. By increasing the work function of the second threshold voltage adjustment layer, and simultaneously utilizing the high work functions of the first threshold voltage adjustment layer and the second threshold voltage adjustment layer, the difference between the work functions of the gate structure and the channel region material is increased, thereby increasing the threshold voltage of the transistor.

[0070] Furthermore, the work function of the second threshold voltage adjustment layer is smaller than that of the first threshold voltage adjustment layer. The second threshold voltage adjustment layer can not only increase the threshold voltage of the transistor but also reduce the resistance of the gate structure.

[0071] In some embodiments, the material of the second threshold voltage regulating layer may be molybdenum nitride.

[0072] Here, the work function varies depending on the nitrogen content in molybdenum nitride. Compared to MoN, Mo2N has a lower nitrogen content and a smaller work function; the work function of Mo2N is approximately 4.47 eV, while that of MoN is greater than 5 eV.

[0073] In some embodiments, the process for forming the second threshold voltage regulation layer may include, but is not limited to, ALD.

[0074] In some embodiments, the first threshold voltage adjustment layer 118 comprises molybdenum trioxide; and / or, the second threshold voltage adjustment layer 120 comprises molybdenum nitride; and / or, the gate conductive layer 116 comprises molybdenum.

[0075] For example, molybdenum can be formed on the gate dielectric layer by ALD process, and the molybdenum can be oxidized to form molybdenum trioxide as a first threshold voltage adjustment layer; molybdenum nitride can then be formed on the first threshold voltage adjustment layer by ALD process, and the molybdenum nitride can be used as a second threshold voltage adjustment layer; alternatively, molybdenum nitride can be used as a seed layer, and molybdenum can be grown on the second threshold voltage adjustment layer by ALD process as a gate conductive layer.

[0076] As previously described, the gate structure provided in the embodiments of this disclosure is particularly suitable for vertical channel transistors and P-type transistors. Reference Figure 3 and Figure 4 , Figure 3 This is a cross-sectional structural diagram of a semiconductor device, provided as another example. Figure 4 This is a top view of a semiconductor device, providing another example. The following will combine... Figure 3and Figure 4 The semiconductor device is taken as a vertical channel transistor for detailed description.

[0077] Before introducing the vertical channel transistor, the directions of the semiconductor device are defined. The extending direction of the transistor column in the vertical channel transistor is defined as the third direction, i.e., the Z direction. The first direction and the second direction, i.e., the X direction and the Y direction, are defined in the plane perpendicular to the third direction. Alternatively, the semiconductor device includes a plurality of transistors arranged in an array, and the directions in which the plurality of transistors are arranged are defined as the first direction and the second direction, i.e., the X direction and the Y direction. In some embodiments, any two of the X direction, the Y direction and the Z direction are perpendicular to each other.

[0078] In some embodiments, the semiconductor device 200 includes a plurality of transistors 202 arranged in an array along the first direction (i.e., the X direction) and the second direction (i.e., the Y direction), and each transistor 202 includes a transistor column 204 extending along the third direction (i.e., the Z direction).

[0079] Figure 3 The YZ plane sectional view of the semiconductor device is schematically shown, Figure 4 The XY plane top view of the semiconductor device is schematically shown. As shown in Figure 3 and Figure 4 As shown in some embodiments, the semiconductor device 200 includes at least one transistor 202 (as shown in the dashed circle frame in Figure 4 Each transistor 202 includes a transistor column 204, which includes a first source / drain 206, a channel region 210 and a second source / drain 208 in sequence along the extending direction; and a gate structure 212 covering at least one sidewall of the transistor column 204.

[0080] In some embodiments, the orthogonal projection of the transistor column on the XY plane can be quadrilateral, and the transistor column includes four sidewalls, of which two are oppositely arranged along the X direction, and the other two are oppositely arranged along the Y direction. In other embodiments, the orthogonal projection of the transistor column on the XY plane can also be circular, elliptical, etc., and the present disclosure does not have special limitation on the shape of the orthogonal projection of the transistor column on the XY plane.

[0081] In some embodiments, the gate structure covers one sidewall of the transistor column, i.e., a single-gate transistor is formed.

[0082] In some embodiments, the gate structure covers two sidewalls of the transistor column, i.e., a double-gate transistor is formed.

[0083] In some embodiments, the gate structure covers three sidewalls of the transistor column, i.e., a triple-gate transistor is formed.

[0084] In some embodiments, the gate structure covers four sidewalls of the transistor pillar, i.e. a full-surround gate transistor is formed. Figure 3 and Figure 4 A full-surround gate transistor is shown.

[0085] Here, the gate structure 212 includes, in sequence, a gate dielectric layer 214, a first threshold voltage adjusting layer 218, a second threshold voltage adjusting layer 220, and a gate conductive layer 216; wherein the gate dielectric layer 214 surrounds the channel region 210 of the transistor pillar 204, the first threshold voltage adjusting layer 218 surrounds the gate dielectric layer 214, the second threshold voltage adjusting layer 220 surrounds the first threshold voltage adjusting layer 218, and the gate conductive layer 216 surrounds the second threshold voltage adjusting layer 220.

[0086] As shown in Figure 4 In some embodiments, the semiconductor device 200 further includes: a plurality of word lines 222 extending along the X direction (as shown by the dotted box in the middle of Figure 4 ), and the word lines 222 are connected with the gate structures 212 of the plurality of transistors 202 arranged along the X direction; a plurality of bit lines extending along the Y direction, and the bit lines are connected with the first source-drain electrodes 206 arranged along the Y direction; and a plurality of storage capacitors, and the storage capacitors are connected with the second source-drain electrodes 208.

[0087] Here, the semiconductor device includes a plurality of word lines 222 extending along the X direction and arranged along the Y direction in sequence, and a plurality of bit lines extending along the Y direction and arranged along the X direction in sequence. Wherein, the adjacent word lines 222 are separated by the first isolation layer 224.

[0088] In some embodiments, when the transistor pillar includes, in sequence from top to bottom along the extending direction, the first source-drain electrode, the channel region, and the second source-drain electrode, a bit line connected with the first source-drain electrode can be formed on the front surface of the substrate, the back surface of the substrate is thinned to expose the second source-drain electrode, and a storage capacitor connected with the second source-drain electrode is formed on the back surface of the substrate.

[0089] In other embodiments, when the transistor pillar includes, in sequence from top to bottom along the extending direction, the first source-drain electrode, the channel region, and the second source-drain electrode, a buried bit line connected with the second source-drain electrode can be formed on the front surface of the substrate, and a storage capacitor connected with the first source-drain electrode is formed on the front surface of the substrate.

[0090] In yet other embodiments, when the transistor pillar includes, in sequence from top to bottom along the extending direction, the first source-drain electrode, the channel region, and the second source-drain electrode, a storage capacitor connected with the first source-drain electrode can be formed on the front surface of the substrate, the back surface of the substrate is thinned to expose the second source-drain electrode, and a bit line connected with the second source-drain electrode is formed on the back surface of the substrate.

[0091] In some embodiments, the material of the bit line can include, but is not limited to, a metal, a metal compound or an alloy. The metal can be, for example, copper, aluminum, tungsten, gold or silver, etc.; the metal compound can be, for example, tantalum nitride or titanium nitride; and the alloy can be an alloy formed by at least two metal elements of copper, aluminum, tungsten, gold or silver.

[0092] Reference Figure 5 , Figure 5 A flowchart of a manufacturing method of a semiconductor device is provided in the embodiments of the present disclosure. As shown in Figure 5 , the embodiments of the present disclosure also provide a manufacturing method of a semiconductor device including at least one transistor, which comprises the following steps:

[0093] Step S501: providing at least one transistor column; the transistor column sequentially includes a first source / drain, a channel region and a second source / drain along an extension direction;

[0094] Step S502: forming a gate dielectric layer covering at least one sidewall of the transistor column;

[0095] Step S503: forming a first metal material layer covering the gate dielectric layer;

[0096] Step S504: performing an oxidation treatment on the first metal material layer to form a first threshold voltage adjusting layer;

[0097] Step S505: forming a gate conductive layer covering the first threshold voltage adjusting layer; wherein the first threshold voltage adjusting layer is used to adjust the threshold voltage of the transistor.

[0098] In the embodiments of the present disclosure, the first threshold voltage adjusting layer is arranged between the gate dielectric layer and the gate conductive layer, and the work function of the first threshold voltage adjusting layer is increased to increase the difference between the work function of the gate structure and the work function of the channel region material, so as to increase the threshold voltage of the transistor, i.e. to achieve the purpose of adjusting the threshold voltage of the transistor by the first threshold voltage adjusting layer to improve the electrical performance of the semiconductor device.

[0099] Reference Figures 6A to 6E , Figures 6A to 6E A top view structural schematic diagram of a semiconductor device in a manufacturing process is provided in the embodiments of the present disclosure. The manufacturing process of the semiconductor device will be described in detail below with reference to Figure 5 and Figures 6A to 6E .

[0100] In the embodiments of the present disclosure, at least one transistor column 204 is provided in step S501; the transistor column 204 sequentially includes a first source / drain 206, a channel region 210 and a second source / drain 208 along an extension direction.

[0101] As Figure 6AAs shown, transistor pillars 204 are formed on the substrate in an array along the X and Y directions.

[0102] For example, forming a transistor pillar may include: providing a substrate; etching the substrate to form a plurality of first grooves extending along the Y direction and a plurality of semiconductor strips extending along the Y direction, and filling the first grooves with an isolation material; etching the substrate to form a plurality of second grooves extending along the X direction and a plurality of semiconductor pillars (i.e., transistor pillars) arranged in an array along the X and Y directions, and filling the second grooves with an isolation material.

[0103] In some embodiments, after the semiconductor pillars are formed, they can be doped to form doped regions (i.e., first source / drain and second source / drain) and channel regions.

[0104] For example, after forming the semiconductor pillars, they can be doped by ion implantation or thermal diffusion processes. Alternatively, after doping the substrate, the substrate can be etched to form multiple semiconductor pillars arranged in an array, such that each semiconductor pillar has a channel region and a first source / drain electrode and a second source / drain electrode located on both sides of the channel region.

[0105] like Figure 6A As shown, in some embodiments, before forming the gate dielectric layer, the method further includes forming a first isolation layer 224 and a second isolation layer 226, wherein the second isolation layer 226 is located between adjacent transistor pillars 204, and the first isolation layer 224 penetrates the second isolation layer 226 between adjacent transistor pillars 204 along the X direction; wherein the first isolation layer 224 is used to isolate adjacent word lines formed subsequently to prevent electrical interference between adjacent conductive structures.

[0106] In some embodiments, the materials of the first isolation layer and the second isolation layer may include, but are not limited to, silicon nitride.

[0107] In this embodiment of the present disclosure, in step S502, a gate dielectric layer 214 is formed covering at least one sidewall of the transistor pillar 204.

[0108] like Figure 6B As shown, the second isolation layer 226 is removed to form a word line recess 230 that exposes the sidewalls of the transistor pillar 204 (as shown). Figure 6B (As shown in the dashed box in the middle); a gate dielectric layer 214 is formed that surrounds the sidewalls of the transistor pillar 204 and covers the sidewalls of the word line groove 230.

[0109] For example, silicon oxide can be formed as a gate dielectric layer using an ALD process or an in-situ steam generation (ISSG) process.

[0110] In step S503, a first metal material layer 228 is formed to cover the gate dielectric layer 214.

[0111] As shown in FIG. 2B, the first metal material layer 228 is formed to cover the sidewall of the gate dielectric layer 214 and cover the sidewall of the word line recess 230. Figure 6B

[0112] Exemplarily, the first metal material layer can be formed by ALD process, for example, molybdenum.

[0113] In step S504, the first metal material layer 228 is oxidized to form a first threshold voltage adjusting layer 218.

[0114] As shown in FIG. 2C, the first metal material layer 228 is oxidized to form the first threshold voltage adjusting layer 218. The first threshold voltage adjusting layer 218 is formed to cover the sidewall of the gate dielectric layer 214 and cover the sidewall of the word line recess 230. Figure 6C

[0115] Exemplarily, the first metal material layer can be formed by ALD process, for example, molybdenum; the first metal material layer is oxidized by oxygen or ozone to form the first threshold voltage adjusting layer, for example, molybdenum trioxide. The first metal material layer can be formed for multiple times, and the first threshold voltage adjusting layer can be formed by multiple oxidizing processes.

[0116] In some embodiments, before step S505, the method further comprises: forming a second threshold voltage adjusting layer 220 to cover the first threshold voltage adjusting layer 218; wherein the work function of the second threshold voltage adjusting layer 220 is less than the work function of the first threshold voltage adjusting layer 218.

[0117] As shown in FIG. 2D, the second threshold voltage adjusting layer 220 is formed to cover the first threshold voltage adjusting layer 218. Figure 6D

[0118] In step S505, a gate conductive layer 216 is formed to cover the first threshold voltage adjusting layer 218; wherein the first threshold voltage adjusting layer 218 is used to adjust the threshold voltage of the transistor 202. Here, the gate conductive layer 216 is formed to cover the second threshold voltage adjusting layer 220 after the second threshold voltage adjusting layer 220 is formed.

[0119] As shown in FIG. 2E, the gate conductive layer 216 is formed to cover the first threshold voltage adjusting layer 218 and cover the second threshold voltage adjusting layer 220. Figure 6E ​​​As shown, a gate conductive layer 216 is formed around the sidewall of the transistor column 204 and covers the sidewall of the word line groove 230; wherein the gate dielectric layer 214, the first threshold voltage adjusting layer 218, the second threshold voltage adjusting layer 220 and the gate conductive layer 216 together form the gate structure 212.

[0120] Exemplarily, the second threshold voltage adjusting layer can be formed by an ALD process, for example, molybdenum nitride; and the gate conductive layer can be formed by growing using the molybdenum nitride as a seed layer, for example, molybdenum.

[0121] As shown, in the embodiment of the present disclosure, the method further comprises: forming a plurality of word lines 222 extending along the X direction (as shown in the dotted box in the middle of FIG. 2B), and the word lines 222 are connected with the gate structures of the plurality of transistors 202 arranged along the X direction; forming a plurality of bit lines extending along the Y direction, and the bit lines are connected with the first source / drain electrodes arranged along the Y direction; and forming a plurality of storage capacitors, and the storage capacitors are connected with the second source / drain electrodes. Figure 6E Figure 6E As shown, in the embodiment of the present disclosure, the method further comprises: forming a plurality of word lines 222 extending along the X direction (as shown in the dotted box in the middle of FIG. 2B), and the word lines 222 are connected with the gate structures of the plurality of transistors 202 arranged along the X direction; forming a plurality of bit lines extending along the Y direction, and the bit lines are connected with the first source / drain electrodes arranged along the Y direction; and forming a plurality of storage capacitors, and the storage capacitors are connected with the second source / drain electrodes.

[0122] The embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises at least one transistor, the transistor comprising: a first source / drain electrode, a second source / drain electrode, a channel region and a gate structure; the channel region is located between the first source / drain electrode and the second source / drain electrode; the gate structure comprises a gate dielectric layer, a gate conductive layer and a first threshold voltage adjusting layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer is in contact with the channel region; wherein the first threshold voltage adjusting layer is used to adjust the threshold voltage of the transistor. In the embodiment of the present disclosure, the first threshold voltage adjusting layer is arranged between the gate dielectric layer and the gate conductive layer, and the first threshold voltage adjusting layer with high work function is used to increase the difference between the work function of the gate structure and the work function of the channel region material, thereby increasing the threshold voltage of the transistor, and further adjusting the threshold voltage of the transistor to improve the electrical performance of the semiconductor device.

[0123] It should be understood that every feature, structure, or characteristic mentioned in the specification, whether explicitly mentioned or not, is considered to be part of at least one embodiment of the present disclosure. Therefore, the appearance of a phrase in various places in the specification is not necessarily intended to refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the size of the sequence numbers of the above processes in various embodiments of the present disclosure does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence numbers of the above embodiments of the present disclosure are only for description, not representing the advantages or disadvantages of the embodiments.​

[0124] The above merely provides the preferred embodiments of the present disclosure, and is not intended to limit the patent scope of the present disclosure. Any equivalent structure variations made according to the present disclosure, or direct / indirect application in other related technical fields, shall fall within the patent protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises at least one transistor, the transistor comprising a first source / drain, a second source / drain, a channel region and a gate structure; each transistor further comprises a transistor column, the transistor column comprising the first source / drain, the channel region and the second source / drain in sequence along an extension direction; the gate structure covers at least one sidewall of the transistor column; The channel region is located between the first source / drain and the second source / drain; The gate structure comprises a gate dielectric layer, a gate conductive layer and a first threshold voltage adjusting layer located between the gate dielectric layer and the gate conductive layer; the gate dielectric layer is in contact with the channel region; wherein the first threshold voltage adjusting layer is used to adjust the threshold voltage of the transistor.

2. The semiconductor device according to claim 1, wherein The gate structure further comprises a second threshold voltage adjusting layer located between the first threshold voltage adjusting layer and the gate conductive layer; wherein the work function of the second threshold voltage adjusting layer is less than the work function of the first threshold voltage adjusting layer.

3. The semiconductor device of claim 1, wherein The semiconductor device comprises a plurality of transistors arranged in an array along a first direction and a second direction, each transistor comprising a transistor column extending along a third direction; wherein any two of the first direction, the second direction and the third direction are perpendicular to each other; the semiconductor device further comprises: a plurality of word lines extending along the first direction, and the word lines are connected with the gate structures of the plurality of transistors arranged along the first direction; a plurality of bit lines extending along the second direction, and the bit lines are connected with the first source / drains arranged along the second direction; a plurality of storage capacitors, and the storage capacitors are connected with the second source / drains.

4. The semiconductor device of claim 1, wherein The work function of the first threshold voltage adjusting layer ranges from 4.6eV to 6.9eV.

5. The semiconductor device of claim 1, wherein The thickness of the first threshold voltage adjusting layer ranges from 0.25nm to 4nm.

6. The semiconductor device of claim 1, wherein The transistor comprises a junctionless field effect transistor and a P-type transistor.

7. The semiconductor device of claim 2, wherein The first threshold voltage adjusting layer comprises molybdenum trioxide; and / or, the second threshold voltage adjusting layer comprises molybdenum nitride; and / or, the gate conductive layer comprises molybdenum.

8. A method of manufacturing a semiconductor device, characterized by The semiconductor device comprises at least one transistor, the method comprises: providing at least one transistor column; the transistor column comprises a first source / drain, a channel region and a second source / drain in sequence along an extension direction; forming a gate dielectric layer covering at least one sidewall of the transistor column; forming a first metal material layer covering the gate dielectric layer; performing oxidation treatment on the first metal material layer to form a first threshold voltage adjusting layer; forming a gate conductive layer covering the first threshold voltage adjusting layer; wherein the first threshold voltage adjusting layer is used to adjust the threshold voltage of the transistor.

9. The method of manufacturing a semiconductor device according to claim 8, wherein Before forming the gate conductive layer covering the first threshold voltage adjusting layer, the method further comprises: forming a second threshold voltage adjusting layer covering the first threshold voltage adjusting layer; wherein the work function of the second threshold voltage adjusting layer is less than the work function of the first threshold voltage adjusting layer.

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