Memory and electronic equipment

Abstract

The invention relates to a memory and electronic equipment, which are used for improving the reliability of the memory. The memory comprises a plurality of layers of memory cell arrays which are stacked along a direction vertical to a substrate, and each memory cell array comprises a plurality of memory cells which are arranged along a first direction and a second direction which are parallel to the substrate; the first direction is intersected with the second direction; the storage unit comprises at least one transistor; the isolation shielding structure penetrates through each layer of storage unit array and is positioned between the two transistors of the two adjacent storage units along the second direction; the isolation shielding structure comprises an isolation layer and a conductive shielding layer; the isolation layer penetrates through each layer of the memory cell array and is at least located between channel regions of the two transistors in each layer of the memory cell array; and the conductive shielding layer penetrates through each layer of storage unit array and is insulated from the two transistors through the isolating layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a memory and an electronic device. Background Art

[0002] The memory in a semiconductor device usually includes memory cells. Exemplarily, each memory cell includes at least one transistor. For example, a 1T1C memory cell or a 2T memory cell. As the integration degree of the memory increases, the size of the memory cell is further reduced, resulting in an increase in signal interference between memory cells, which is not conducive to improving the reliability of the memory. Summary of the Invention

[0003] Based on this, embodiments of the present disclosure provide a memory and an electronic device, which are beneficial to improving the reliability of the memory.

[0004] According to some embodiments, on the one hand, the present disclosure provides a memory, including:

[0005] A multi-layer memory cell array, stacked along the vertical direction of the substrate. The memory cell array includes a plurality of memory cells arranged along a first direction and a second direction parallel to the substrate; the first direction and the second direction intersect; the memory cell includes at least one transistor;

[0006] An isolation and shielding structure, penetrating through each layer of the memory cell array and located between two transistors of two adjacent memory cells along the second direction; the isolation and shielding structure includes an isolation layer and a conductive shielding layer:

[0007] The isolation layer, penetrating through each layer of the memory cell array, at least located between the channel regions of the two transistors in each layer of the memory cell array;

[0008] The conductive shielding layer, penetrating through each layer of the memory cell array, insulated from the two transistors through the isolation layer.

[0009] In some embodiments, it further includes: a reference electrode located between the substrate and each memory cell array, the reference electrode extending on the substrate; wherein,

[0010] The conductive shielding layer extending towards the substrate extends to the reference electrode and is electrically connected to the reference electrode, and the reference electrode is connected to a voltage terminal that can provide a constant potential.

[0011] In some embodiments, it includes a plurality of the isolation and shielding structures located between different memory cells of the memory cell array, and each isolation and shielding structure extends towards the substrate and is connected to the same reference electrode.

[0012] In some embodiments, the storage unit includes a first transistor, and the first transistor includes a ring-shaped first semiconductor layer extending in a direction perpendicular to the substrate; the memory further includes: a plurality of first bit lines;

[0013] Each of the first bit lines extends in the second direction and is electrically connected to the sidewalls of the first semiconductor layers in the corresponding column of the storage units;

[0014] The isolation and shielding structure is located between the outer sidewalls of two adjacent first semiconductor layers in a column of the storage units and extends to the sidewall of the bit line in the first direction.

[0015] In some embodiments, it further includes: a plurality of first word lines;

[0016] The first word line extends in a direction perpendicular to the substrate; the first semiconductor layer surrounds the outer sidewall of the first word line;

[0017] The outer sidewall of the first semiconductor layer is in contact with the isolation layer, and the isolation layer is in contact with the conductive shielding layer.

[0018] In some embodiments, the storage unit further includes: a capacitor;

[0019] The capacitor includes: a first electrode electrically connected to the first semiconductor layer, and a dielectric layer and a second electrode sequentially disposed on a side of the first electrode facing away from the first semiconductor layer;

[0020] The first bit line, the first semiconductor layer, and the first electrode are sequentially arranged in the first direction;

[0021] Wherein, the isolation and shielding structure extends in the first direction from an end close to the first bit line to between two adjacent first electrodes.

[0022] In some embodiments, the storage unit further includes: a second transistor electrically connected to the storage node of the first transistor; the second transistor includes a ring-shaped second semiconductor layer extending in a direction perpendicular to the substrate and insulated from the storage node; the memory further includes: a plurality of second bit lines; wherein,

[0023] The second bit line extends in the second direction in a plane parallel to the substrate and is electrically connected to the second semiconductor layer in the corresponding column of the storage units; the first bit line, the first transistor of the storage unit, the storage node, the second transistor, and the second bit line are sequentially arranged in the first direction;

[0024] Wherein, the isolation and shielding structure extends from the first bit line to the storage node and is located between two adjacent storage nodes along the second direction.

[0025] In some embodiments, the storage node is the main gate of the second transistor, or,

[0026] The second transistor further includes a main gate and a back gate. The main gate is located in a through hole surrounded by the second semiconductor layer, insulated from the second bit line, and connected to the second word line; the storage node is the back gate of the second transistor.

[0027] In some embodiments, the isolation and shielding structure extends in a first direction from an end close to the first bit line to between two adjacent storage nodes.

[0028] In some embodiments, the isolation layer is a hollow annular film layer extending toward the substrate, and the conductive shielding layer is located within the hollow annular film layer.

[0029] According to some embodiments, another aspect of the present disclosure provides an electronic device, including the memory as described above.

[0030] Embodiments of the present disclosure may / at least have the following advantages:

[0031] In embodiments of the present disclosure, an isolation and shielding structure penetrating through the storage cell array of each layer is provided between two transistors of two storage cells adjacent in a second direction. The isolation and shielding structure includes: an isolation layer penetrating through the storage cell array of each layer and at least located in the channel regions of the two transistors in the storage cell array of each layer, and a conductive shielding layer penetrating through the storage cell array of each layer and located in the isolation layer and insulated from the two transistors through the isolation layer. Based on this, the isolation and shielding structure in embodiments of the present disclosure can effectively reduce the influence of signals between the transistor channels in two adjacent storage cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain the drawings of other embodiments without creative efforts based on these drawings.

[0033] Figure 1 It is a schematic structural diagram of a memory provided in some embodiments; wherein, Figure 1 Figure (a) therein is a top view structural diagram of the shown memory, Figure 1 Figure (b) therein is Figure 1 Figure (a) therein Figure 1 a cross-sectional structural diagram along the A-A direction, Figure 1 Figure (c) therein is Figure 1 Figure (a) therein Figure 1A sectional structure diagram along the B-B direction;

[0034] Figure 2 is Figure 1 The equivalent circuit diagram of a storage cell in the shown memory;

[0035] Figure 3 is Figure 1 The principle comparison diagram of the equivalent circuits of the shown memory before and after setting the isolation shielding structure; among them, Figure 3 Figure (a) in Figure 1 is the equivalent circuit schematic diagram of the shown memory before setting the isolation shielding structure, Figure 3 Figure (b) in Figure 1 is the equivalent circuit schematic diagram of the shown memory after setting the isolation shielding structure;

[0036] Figure 4 is the structure schematic diagram of another memory provided in some embodiments; among them, Figure 4 Figure (a) in Figure 4 is Figure 4 Figure (a) in Figure 1 a sectional structure diagram along the A-A direction, Figure 4 Figure (c) in Figure 4 Figure (a) in Figure 1 a sectional structure diagram along the B-B direction, Figure 4 Figure (d) in Figure 4 Figure (a) in Figure 1 a sectional structure diagram along the C-C direction;

[0037] Figure 5 is Figure 4 The equivalent circuit diagram of a storage cell in the shown memory;

[0038] Figure 6 is Figure 4 The principle comparison diagram of the equivalent circuits of the shown memory before and after setting the isolation shielding structure; among them, Figure 6 Figure (a) in Figure 4 is the equivalent circuit schematic diagram of the shown memory before setting the isolation shielding structure, Figure 6 Figure (b) in Figure 4 is the equivalent circuit schematic diagram of the shown memory after setting the isolation shielding structure;

[0039] Figure 7 is the structure schematic diagram of another memory provided in some embodiments; among them, Figure 7 Figure (a) in Figure 7 is Figure 7 Figure (a) in Figure 1 a sectional structure diagram along the A-A direction,Figure 7 Figure (c) in Figure 7 is (a) in Figure 1 a sectional structure diagram along the B-B direction, Figure 7 Figure (d) in Figure 7 is (a) in Figure 1 a sectional structure diagram along the C-C direction;

[0040] Figure 8 is Figure 7 an equivalent circuit diagram of a storage cell of an n-type read transistor in the memory shown;

[0041] Figure 9 is Figure 7 a principle comparison diagram of the equivalent circuits before and after setting the isolation shielding structure in the memory shown; among them, Figure 9 Figure (a) in Figure 7 is the equivalent circuit schematic diagram before setting the isolation shielding structure in the memory shown, Figure 9 Figure (b) in Figure 7 is the equivalent circuit schematic diagram after setting the isolation shielding structure in the memory shown. Description of the drawings:

[0043] U - storage cell, T1 - first transistor, T2 - second transistor, C1 - capacitor, C2 - voltage regulating capacitor, BL and WBL - first bit line, RBL - second bit line, WL and WWL - first word line, RWL - second word line, GND - ground wire, SN - storage node, S1 - intermediate area, S2 - bent area;

[0044] 1 - substrate, 2 - isolation shielding structure, 21 - isolation layer, 22 - conductive shielding layer, 3 - reference electrode, 41 - first semiconductor layer, 42 - first gate dielectric layer, 51 - first isolation structure, 52 - second isolation structure, 53 - third isolation structure, 61 - first electrode, 62 - dielectric layer, 63 - second electrode, 71 - second semiconductor layer, 72 - second gate dielectric layer, 73 - third gate dielectric layer, 81 - first dielectric layer, 82 - second dielectric layer. Detailed implementation manners

[0045] For ease of understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used in the description of the present disclosure herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure.

[0047] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0048] Spatial relationship terms such as “under,” “below,” “beneath,” “underneath,” “above,” “over,” etc. may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “under” or “beneath” or “underneath” another element or feature will be oriented “over” the other element or feature. Thus, the exemplary terms “under” and “beneath” can include both an upper and a lower orientation. Additionally, the device may also assume other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0049] As used herein, the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms “comprises / comprising” or “has / including” etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term “and / or” includes any and all combinations of the related listed items.

[0050] Currently, with the rapid development of integrated circuit manufacturing processes, the physical distance between devices is getting smaller and smaller, and signal interference is likely to occur between adjacent two storage units. For example, signal interference is likely to occur between the channels of transistors of adjacent two storage units, or between the capacitors of adjacent two 1T1C storage units, or between the storage nodes (SNs) of adjacent two 2T storage units. These interferences are likely to affect the reliability of the memory.

[0051] In the application scenario of 2T memory cells, when the memory cells in the memory are in the standby state, the storage nodes are in a floating state, and the capacitive coupling effect between the storage nodes and the storage nodes of other memory cells easily affects the capacitance of the storage nodes, thereby affecting the reliability of the memory.

[0052] Based on this, embodiments of the present disclosure provide a memory to facilitate improving the reliability of the memory of a two-dimensional memory cell array or a three-dimensional memory cell array.

[0053] The following takes a three-dimensional memory cell array as an example to illustrate the present application.

[0054] Please refer to Figure 1 and Figure 2 In some embodiments, the memory includes a multi-layer memory cell array and a plurality of isolation shielding structures 2.

[0055] Exemplarily, the multi-layer memory cell array is stacked along the direction perpendicular to the substrate 1 (for example, the Z direction), and the memory cell array includes a plurality of memory cells U arranged in rows along the first direction parallel to the substrate 1 (for example, the X direction) and arranged in columns along the second direction parallel to the substrate 1 (for example, the Y direction). The first direction (for example, the X direction) and the second direction (for example, the Y direction) intersect, for example, orthogonally. That is, the plurality of memory cells U can be arranged in an array in a plane parallel to the substrate 1 and stacked periodically from bottom to top along the direction perpendicular to the substrate 1 to obtain a three-dimensional memory.

[0056] Exemplarily, the substrate 1 is a supporting substrate, and the substrate has at least one base, such as a silicon substrate. Whether there are other functional devices on the base is not limited in the present application. For example, the substrate 1 can include a base composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including a stack such as Si and SiGe, a stack of Si and SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0057] Exemplarily, the memory cell U can be a 1T or 2T memory cell, and whether the memory cell has a capacitor is not specifically limited in the present application. Exemplarily, the memory cell can be a 1T1C memory cell or a 2T0C memory cell.

[0058] In some embodiments, please continue to refer to Figure 1 andFigure 2 , the storage unit U adopts a 1T1C structure, including a first transistor T1 and a capacitor C1 which are electrically connected. The isolation and shielding structure 2 is located between two first transistors T1 of two adjacent storage units U along the second direction (for example, the Y direction). The isolation and shielding structure 2 includes an isolation layer 21 and a conductive shielding layer 22. The isolation layer 21 penetrates through each layer of the storage cell array and is at least located between the channel regions of two adjacent first transistors T1 in each layer of the storage cell array. The conductive shielding layer 22 penetrates through each layer of the storage cell array and is insulated from the two transistors through the isolation layer.

[0059] In some embodiments, the conductive shielding layer 22 has a constant potential to shield signal interference between storage units.

[0060] In some embodiments, the conductive shielding layer 22 can be provided with a constant potential by a voltage terminal to play a role in shielding interference signals.

[0061] The conductive shielding layer 22 can be insulated from the two transistors through two independent isolation layers respectively, or through an insulating layer. The two isolation layers can be formed of the same material or different materials.

[0062] Exemplarily, the isolation layer is a hollow annular film layer extending towards the substrate, and the conductive shielding layer 22 is located inside the hollow annular film layer. At this time, the isolation layer is an isolation layer that insulates from the two transistors at the same time.

[0063] In some embodiments, two adjacent storage units U in the second direction (column direction) are connected to the same bit line or different bit lines.

[0064] Exemplarily, the isolation layer 21 is formed of an insulating material, such as a low-K dielectric layer such as silicon oxide.

[0065] Exemplarily, the conductive shielding layer 22 is formed of a conductive material, such as a metal material or a doped semiconductor material (such as conductive polysilicon).

[0066] Exemplarily, the isolation layer is a hollow annular film layer extending towards the substrate. It can be understood that there are holes or gaps extending towards the substrate on the isolation layer 21, and the holes or gaps are provided on the upper and lower surfaces of the isolation layer 21 relative to the substrate. For example, when the isolation layer 21 is an annular thin film, the isolation layer 21 can be provided with holes penetrating through each layer of the storage cell array. Or, for another example, when the isolation layer 21 is a block structure extending along the row direction (for example, the X direction), the holes can be provided on the side surfaces between the main surfaces; and it is also allowed that the block structure is only located between two adjacent storage units U or between two adjacent rows of storage units U.

[0067] Exemplarily, the isolation layer 21 may form vias or slits on the insulating layer between the semiconductor layers. Moreover, the isolation layer 21 contacts the channel region of the first transistor T1, and the conductive shielding layer within the vias or slits completely covers the channel regions of the two transistors to achieve a better signal shielding effect.

[0068] In some examples, please refer to Figure 1 Figures (a) and (b) in, the memory further includes: a plurality of first word lines WL. The first word line WL is a linear structure extending along the direction perpendicular to the substrate 1 (e.g., the Z direction). The first transistor T1 includes: a first semiconductor layer 41 insulatingly surrounding the periphery of the first word line WL. That is, the first semiconductor layer 41 may be annular and extend along the direction perpendicular to the substrate 1 (e.g., the Z direction), and a first gate dielectric layer 42 may be provided between the first semiconductor layer 41 and the first word line WL. The capacitor C1 includes: a first electrode 61 electrically connected to the first semiconductor layer 41, and a dielectric layer 62 and a second electrode 63 sequentially provided on the side of the first electrode 61 facing away from the first semiconductor layer 41.

[0069] As described above, in the embodiments of the present disclosure, an isolation and shielding structure 2 penetrating through each layer of the memory cell array is provided between two first transistors T1 of two adjacent memory cells U along the second direction (e.g., the Y direction). Combining the related description of the isolation and shielding structure 2, the isolation and shielding structure 2 in the embodiments of the present disclosure can effectively reduce the signal interference between the channel regions (i.e., the first semiconductor layer 41) of two first transistors T1 in adjacent memory cells U, so as to improve the reliability of the memory.

[0070] In some embodiments, please refer to Figure 1 Figure (c) in, the memory further includes: a reference electrode 3 configured to provide a constant potential to the conductive shielding layer 22, and the reference electrode 3 may be located at the top or bottom of each memory cell array. When the reference electrode 3 is located at the bottom of each memory cell array, it may be located on the substrate 1. The number of the reference electrodes 3 may be at least one. The conductive shielding layer 22 extends in the direction towards the substrate 1, and the reference electrode 3 extends on the substrate. The conductive shielding layer 22 extends to the reference electrode 3 and is electrically connected to the reference electrode 3.

[0071] In some embodiments, please refer to Figure 1 Figures (b) and (c) in, the number of the isolation and shielding structures 2 is multiple, and they are respectively located between adjacent first transistors T1 at different positions. Exemplarily, in each memory cell connected by a bit line, an isolation and shielding structure 2 is provided between any two adjacent transistors of the memory cells.

[0072] The conductive shielding layers 22 in each isolation shielding structure 2 are electrically connected to the same reference electrode 3. That is, the conductive shielding layers 22 of the isolation shielding structures 2 in the memory can share the same reference electrode 3. The same reference electrode 3 can be a planar common electrode or a common electrode connected integrally in a grid pattern.

[0073] Exemplarily, the reference electrode 3 is a ground electrode connected to a ground terminal. This ground electrode can be simultaneously connected to the ground electrode in the capacitor of the 1T1C in the storage unit U. For example, in the 1T1C storage unit U, the outer plate (i.e., the second electrode 63) of the capacitor is connected to the reference electrode 3.

[0074] It should be added that in the example where the reference electrode 3 is a ground electrode, this ground electrode can also be correspondingly and electrically connected to other components in the memory that need to be grounded.

[0075] It is worth mentioning that in some embodiments, the memory further includes: a voltage terminal ( Figure 1 not shown in the figure) electrically connected to the reference electrode 3. The voltage terminal refers to a voltage terminal that can provide a constant voltage, but the voltage value output to the storage unit can be adjusted according to requirements. The reference electrode 3 is regulated to provide different constant potentials to tune the threshold voltage Vth of the corresponding first transistor T1. In this way, by adjusting the constant potential of the reference electrode 3 through the voltage terminal, it is beneficial to adjust the threshold voltage Vth of the first transistor T1 to ensure that the threshold voltage of the transistor operates within the normal range.

[0076] In some embodiments, please continue to refer to Figure 1 , the memory further includes: a plurality of first bit lines BL and a plurality of first isolation structures 51. Among them, each first bit line BL extends in a second direction (e.g., the Y direction) in the plane parallel to the substrate 1 and is electrically connected to the side walls of the first semiconductor layers 41 in the corresponding column of storage units U. Each first isolation structure 51 is located between the outer side walls of two adjacent first semiconductor layers 41 in a column of storage units U and extends to isolate the first bit line BL from this first bit line through an insulating layer.

[0077] Exemplarily, as shown in Figure 1 , every two adjacent storage units U along the row direction (e.g., the X direction) are mirror-symmetrical with respect to the first isolation structure 51. For example, along the direction away from the first isolation structure 51, the capacitor C1 in the storage unit U is located on the side of the corresponding first transistor T1 facing away from the first bit line BL.

[0078] Exemplarily, please refer to Figure 1, the capacitor C1 can be obtained by first laterally etching the target layer material to form a capacitor preset groove, and then sequentially forming a first electrode 61, a dielectric layer 62, and a second electrode 63 in the capacitor preset groove. Correspondingly, in two adjacent memory cells U on the same side of the first isolation structure 51 in the row direction (e.g., the X direction), the second electrodes 63 of the capacitors C1 are electrically connected as an integral structure, and two adjacent memory cells U on the same side of the first isolation structure 51 in the row direction (e.g., the X direction) can share the same isolation shielding structure 2, which is beneficial to simplifying the structure and manufacturing process of the memory.

[0079] Exemplarily, the first bit line BL, the first semiconductor layer 41, and the first electrode 61 are arranged in sequence in a first direction (e.g., the X direction). The isolation shielding structure 2 extends from the first bit line BL to the first electrode 61 and is located between two adjacent first electrodes 61 in a second direction (e.g., the Y direction).

[0080] As described above, for Figure 1 the shown memory, Figure 3 Fig. shows a principle comparison diagram of the equivalent circuits of the memory before and after the isolation shielding structure 2 is provided; among them, as shown in Fig. (a) in Figure 3 , before the isolation shielding structure 2 is provided in the memory, there may be parasitic capacitance between the first semiconductor layers 41 of two first transistors T1 of adjacent memory cells U connected to the same bit line, resulting in signal interference; Figure 3 The dotted line below the gate of the transistor in Fig. (a) in Figure 3 represents the position of the channel, and there is a parasitic capacitance indicated between the two dotted lines. Figure 6 The dotted lines below the gates in Fig. (b) in Figure 3 and Fig. have a similar meaning. The dotted lines below the gates do not represent logic circuits but indication lines. As shown in Fig. (b) in

[0081] In some other embodiments, please refer to Figures 4 - 9, the storage unit U adopts a 2T0C structure, including a first transistor T1 and a second transistor T2 electrically connected to the first transistor T1 at the storage node SN. The second transistor T2 includes an annular second semiconductor layer 71 that is insulated from the storage node SN and extends along the vertical substrate 1 direction (e.g., the Z direction). The isolation shielding structure 2 is located between two adjacent storage units U along the second direction (e.g., the Y direction). For example, the first transistor T1 and the second transistor T2 in any storage unit U are arranged in the first direction (e.g., the X direction), and the isolation shielding structure 2 is located between the corresponding two first transistors T1 and between the corresponding two second transistors T2 respectively. The isolation shielding structure 2 includes an isolation layer 21 and a conductive shielding layer 22. The isolation layer 21 is at least located between the channel regions of two adjacent first transistors T1 in each layer of the storage cell array. The conductive shielding layer 22 is located in the isolation layer 21 and is insulated from the transistors in two adjacent storage units U through the isolation layer 21.

[0082] In some embodiments, the conductive shielding layer has a constant potential to shield signal interference.

[0083] Exemplarily, the first transistor T1 is a write transistor, and the second transistor T2 is a read transistor.

[0084] In some examples, please refer to Figure 4 Figure (d) in Figure 5 for understanding. The storage node SN is the main gate of the second transistor T2. The storage node SN is in sidewall contact with the first semiconductor layer 41 in the first transistor T1 and is insulated from the second semiconductor layer 71 of the second transistor T2 through the second gate dielectric layer 72.

[0085] In other examples, please refer to Figure 7 Figure (d) in Figure 8 for understanding. The storage node SN is the back gate of the second transistor T2. The dashed line connected to SN in this figure represents the back gate. The storage node SN is in sidewall contact with the first semiconductor layer 41 in the first transistor T1 and is insulated from the second semiconductor layer 71 of the second transistor T2 through the second gate dielectric layer 72. The second transistor T2 further includes a main gate, which is located in the through hole surrounded by the second semiconductor layer 71 and is insulated from the second bit line RBL and connected to the second word line RWL. The main gate of the second transistor T2 is, for example, an integral structure with the second word line RWL and is insulated from the second semiconductor layer 71 of the second transistor T2 through the third gate dielectric layer 73.

[0086] In some embodiments, please refer to Figures 4 - 9The memory further includes: a plurality of first bit lines WBL, a plurality of first isolation structures 51, a plurality of second bit lines RBL, and a plurality of second isolation structures 52. The first bit lines WBL and the second bit lines RBL extend respectively along the second direction (e.g., the Y direction) in a plane parallel to the substrate 1, the first bit lines WBL are electrically connected to the side walls of the first semiconductor layers 41 in the corresponding column of memory cells U, the second bit lines RBL are electrically connected to the side walls of the second semiconductor layers 71 in the corresponding column of memory cells U, and the memory cells U are located in the interval between the first bit lines WBL and the second bit lines RBL.

[0087] For example, Figures 4 - 9 As shown in , the first isolation structure 51 and the second isolation structure 52 extend respectively along the second direction (e.g., the Y direction). Each first isolation structure 51 is located between the outer side walls of two adjacent first semiconductor layers 41 in a column of memory cells, extends to the first bit line WBL in the first direction and is isolated from the first bit line by an insulating layer. Every two adjacent memory cells U along the row direction (e.g., the X direction) can be mirror-symmetrical with the first isolation structure 51 or the second isolation structure 52 as the center. For example, every two adjacent memory cells U along the row direction (e.g., the X direction) are mirror-symmetrical with the first isolation structure 51 as the center, and along the direction away from the first isolation structure 51, the second transistor T2 in the memory cell U is located on the side of the corresponding first transistor T1 away from the first bit line WBL.

[0088] Accordingly, if Figures 4 - 9 As shown in the figure, a column of memory cells U is electrically connected to a first bit line WBL and a second bit line RBL, respectively. The first isolation structure 51 is located between two first bit lines WBL electrically connected to adjacent columns of memory cells U, and covers the sidewalls of the first bit lines WBL. The second isolation structure 52 is located between two second bit lines RBL electrically connected to adjacent columns of memory cells U, and covers the sidewalls of the second bit lines RBL. The isolation shielding structure 2 is located on the side of the first bit line WBL away from the first isolation structure 51, the side of the second bit line RBL away from the second isolation structure 52, between two first semiconductor layers 41 adjacent along the second direction (e.g., Y direction), and between two storage nodes SN adjacent along the second direction (e.g., Y direction). That is, the first bit line WBL, the first transistor T1, the storage node SN, the second transistor T2, and the second bit line RBL can be arranged in sequence in the first direction (e.g., X direction). The isolation shielding structure 2 extends from the first bit line WBL to the storage node SN, and is located between two storage nodes SN adjacent along the second direction (e.g., Y direction).

[0089] Exemplarily, the first semiconductor layer 41 in the first transistor T1 is a fully surrounding semiconductor layer. There is an opening in the sidewall of the second semiconductor layer 71 in the second transistor T2. The second bit line RBL is connected to the opening region of the second semiconductor layer 71. For example, the second bit line RBL can be connected to the third isolation structure 53 within the opening region of the second semiconductor layer 71 (as shown in Figure 4 ); or, for another example, the second bit line RBL can be connected to the third gate dielectric layer 73 that coats the second word line RWL within the opening region of the second semiconductor layer 71 (as shown in Figure 7 ).

[0090] In some embodiments, which are the same as the embodiment where the aforementioned storage cell U has a 1T1C structure, please refer to the (c) figure in Figure 4 and the (c) figure in Figure 7 . The memory further includes: at least one reference electrode 3 located between the substrate 1 and the storage cell array. The conductive shielding layer 22 extends along the direction perpendicular to the substrate 1, and the reference electrode 3 extends along the direction parallel to the substrate 1. The conductive shielding layer 22 in the isolation shielding structure 2 extends to the reference electrode 3 and is electrically connected to the reference electrode 3, and the reference electrode 3 is configured to provide a constant potential to the conductive shielding layer 22.

[0091] Exemplarily, as shown in the (c) figure in Figure 4 and the (c) figure in Figure 7 , the number of the isolation shielding structures 2 is multiple, which are respectively located between transistors at different positions. The conductive shielding layers 22 in each isolation shielding structure 2 are electrically connected to the same reference electrode 3. That is, the conductive shielding layers 22 of each isolation shielding structure 2 in the memory can share the same reference electrode 3. The same reference electrode 3 can be a planar common electrode or a common electrode connected integrally in a grid shape.

[0092] Exemplarily, the reference electrode 3 is a ground electrode. And, in some examples, this ground electrode can also be electrically connected correspondingly to other components in the memory that need to be grounded.

[0093] It should be noted that, in some embodiments, the memory further includes: a voltage terminal (not shown in Figures 4 - 9 ) that is electrically connected to the reference electrode 3. The voltage terminal is configured to: regulate the reference electrode 3 to provide different constant potentials to tune the threshold voltage of the corresponding first transistor T1. Thus, by adjusting the constant potential of the reference electrode 3 by the voltage terminal, the threshold voltage Vth of the first transistor T1 in the storage cell U is regulated.

[0094] It should be added that Figure 4 and Figure 7Two different storage cells U with a 2T0C structure are respectively shown. It can be understood that, matching the internal components and connection relationships of the storage cell U, the structure of the storage cell U is not limited to the relevant descriptions in the foregoing embodiments, and there may be other variations and applications, which are not limited in the embodiments of the present disclosure.

[0095] As described above, in the embodiments of the present disclosure, an isolation shielding structure 2 is provided between two adjacent storage cells U along the second direction (e.g., the Y direction). Combining the relevant descriptions of the isolation shielding structure 2 above, a part of the isolation shielding structure 2 is located between two adjacent first semiconductor layers 41 along the second direction (e.g., the Y direction), which is not only beneficial to shielding the influence of external signals on the first semiconductor layer 41 (i.e., the channel of the first transistor T1) through the isolation shielding structure 2, but also can tune the threshold voltage Vth of the first transistor T1 by adjusting the constant potential provided by the reference electrode 3, so as to effectively improve the performance and reliability of the first transistor T1; another part of the isolation shielding structure 2 is located between two adjacent storage nodes SN along the second direction (e.g., the Y direction), which can effectively reduce the coupling effect between adjacent storage nodes SN through the isolation shielding structure 2 on the basis of ensuring the isolation effect between adjacent storage nodes SN, so as to improve the stability of the storage node SN. In this way, the embodiments of the present disclosure can effectively weaken the influence of external signals (e.g., adjacent storage cells U) on the storage cell U, and correspondingly improve the performance and stability of the first transistor T1, so as to be beneficial to improving the performance and reliability of the memory. The embodiments of the present disclosure are particularly applicable to the standby state of the storage cells in the memory.

[0096] In some embodiments, the structure of the storage cell U is as Figure 4 described, and the memory further includes: a plurality of first word lines WWL, a plurality of second word lines RWL, and a plurality of third isolation structures 53. Please combine Figure 4 and Figure 5 to understand that both the first word line WWL and the second word line RWL extend along the direction perpendicular to the substrate 1 (e.g., the Z direction). The first semiconductor layer 41 is insulated and surrounds the periphery of the first word line WWL, and a first gate dielectric layer 42 is provided between the first semiconductor layer 41 and the first word line WWL. The outer sidewall of the first semiconductor layer 41 is in contact with the isolation layer 21, and the isolation layer 21 is in contact with the conductive shielding layer 22. The second semiconductor layer 71 surrounds the second word line RWL and is electrically connected to the second word line RWL. The isolation shielding structure 2 is also in contact with the outer sidewall of the second semiconductor layer 71. The third isolation structure 53 is located between the second word line RWL and the second bit line RBL corresponding to the electrically connected storage cell U.

[0097] Exemplarily, the storage node SN includes a film layer extending along the direction of the vertical substrate 1 (e.g., the Z direction) and surrounding the outer sidewall of the second semiconductor layer 71; the isolation shielding structure extends in the first direction from one end close to the first bit line to between two adjacent storage nodes.

[0098] The film layer includes an intermediate region S1 and a bent region S2 bent along the intermediate region S1 toward the second bit line RBL direction. The two side surfaces of the intermediate region S1 are respectively connected to the first semiconductor layer 41 and connected to the second semiconductor layer 71 through a gate insulating layer (e.g., the second gate dielectric layer 72). The bent region S2 extends along the first direction (e.g., the X direction) and surrounds two opposite sidewalls of the second semiconductor layer 71.

[0099] Correspondingly, the isolation shielding structure 2 is in contact with the outer sidewall of the second semiconductor layer 71.

[0100] Thus, for Figure 4 the shown memory, Figure 6 a principle comparison diagram of the equivalent circuits of the memory before and after the isolation shielding structure 2 is provided; among them, as shown in FIG. (a) in Figure 6 , before the isolation shielding structure 2 is provided in the memory, there may be parasitic capacitance between two storage nodes SN of adjacent storage cells U, resulting in signal interference; as shown in FIG. (b) in Figure 6 , after the isolation shielding structure 2 is provided in the memory, parasitic capacitances with an externally fixed voltage (i.e., having a constant potential) can be formed between two storage nodes SN of adjacent storage cells U and the exposed sidewalls of the semiconductor layers of each transistor and the isolation shielding structure 2, thereby improving the reliability of the memory to ensure that each storage node SN and the channel regions of each transistor are not affected by external signal changes, and further ensuring the stability of the performance parameters of each transistor and storage node SN, especially ensuring the stability of the threshold voltage of each first transistor T1.

[0101] In some other embodiments, the structure of the storage cell U is as described in Figure 7 , and the memory further includes: a plurality of first word lines WWL, a plurality of ground lines GND, and a plurality of second word lines RWL. Please refer to Figure 7 and Figure 8It is understood that the first word line WWL, the ground wire GND, and the second word line RWL all extend along the direction perpendicular to the substrate 1 (e.g., the Z direction). The first semiconductor layer 41 is insulating and surrounds the circumferential side of the first word line WWL. A first gate dielectric layer 42 is provided between the first semiconductor layer 41 and the first word line WWL. The outer sidewall of the first semiconductor layer 41 is in contact with the isolation layer 21, and the isolation layer 21 is in contact with the conductive shielding layer 22. The second semiconductor layer 71 surrounds the ground wire GND and is electrically connected to the ground wire GND. The second word line RWL is located between the ground wire GND and the second bit line RBL and is insulated from the ground wire GND, the second bit line RBL, and the second semiconductor layer 71; for example, the surface of the second word line RWL is coated with a third gate dielectric layer 73. The isolation shielding structure 2 is also in contact with the outer sidewall of the second semiconductor layer 71.

[0102] Exemplarily, the storage node SN includes a film layer that extends along the direction perpendicular to the substrate 1 (e.g., the Z direction) and surrounds the outer sidewall of the second semiconductor layer 71; the film layer includes an intermediate region S1 and a bent region S2 that bends along the direction of the intermediate region S1 toward the second bit line RBL. The two side surfaces of the intermediate region S1 are respectively connected to the first semiconductor layer 41 and connected to the second semiconductor layer 71 through a gate insulating layer (e.g., the second gate dielectric layer 72). The bent region S2 extends along the first direction (e.g., the X direction) and surrounds the two opposite sidewalls of the second semiconductor layer 71.

[0103] Correspondingly, the isolation shielding structure 2 is in contact with the outer sidewall of the second semiconductor layer 71.

[0104] Exemplarily, the reference electrode 3 is a ground electrode, and the ground wire GND is also electrically connected to the reference electrode 3.

[0105] Thus, for Figure 7 the shown memory, Figure 9 a principle comparison diagram of the equivalent circuits of the memory before and after the isolation shielding structure 2 is provided; wherein, as Figure 9 shown in the (a) figure of Figure 9 , before the isolation shielding structure 2 is provided in the memory, there may be parasitic capacitance between the two storage nodes SN of adjacent storage cells U, resulting in signal interference; as

[0106] Figure 9 shown in the (b) figure of , after the isolation shielding structure 2 is provided in the memory, the parasitic capacitance with an externally fixed voltage (i.e., a constant potential) can be formed between the two storage nodes SN of adjacent storage cells U and the exposed sidewalls of the semiconductor layers of each transistor and the isolation shielding structure 2, thereby improving the reliability of the memory to ensure that each storage node SN and the channel regions of each transistor are not affected by external signal changes, and further ensuring the stability of the performance parameters of each transistor and storage node SN, especially ensuring the stability of the threshold voltage of each first transistor T1.In [the figure], the dashed line below the main gate of the read transistor is the back gate connected to the SN. The dashed line below the gate of the write transistor does not represent any circuit structure, but is used to illustrate that the parasitic capacitance gives an indication line of the channel position below the channel.

[0107] It should be added that, in some embodiments, in any layer of memory cell U arrays arranged along the direction parallel to the substrate 1, each first bit line BL or WBL and the memory node SN can be patterned based on the same conductive material layer. Correspondingly, the conductive material layer can be alternately stacked with the first dielectric layer 81 matching the number of distributed layers and the target number of layers of the memory cell U for manufacturing to obtain the memory. In addition, a second dielectric layer 82 can be provided on the surface of the top first dielectric layer 81. The second dielectric layer 82 can be, for example, a hard mask layer to protect the underlying layer structure during the patterning of the conductive material layer and the first dielectric layer 81 and ensure the pattern topography after etching. The materials of the first dielectric layer 81 and the second dielectric layer 82 can be selected and set according to requirements.

[0108] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a photocopier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other devices with data storage functions. The electronic device can include the memory described in some of the foregoing embodiments. The technical advantages possessed by the foregoing memory are also possessed by the electronic device, which will not be elaborated herein.

[0109] In some embodiments, the electronic device includes a housing, a circuit board disposed in the housing, and a memory integrated on the circuit board. The structure of the memory can refer to the relevant descriptions in some of the foregoing embodiments. Other necessary elements or components can also be included in the electronic device, which are not limited in the embodiments of the present disclosure.

[0110] In some embodiments, an external control device such as a processor or an actuator coupled to the memory can also be integrated on the circuit board. For example, the electronic device further includes a processor integrated on the circuit board. The processor is coupled to the memory, and the processor can control the read and write operations of the memory.

[0111] In some embodiments, the memory can be a dynamic random access memory.

[0112] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0113] The above-described embodiments merely represent several implementation manners of the present disclosure. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the appended claims.

Claims

1. A memory device, characterized in that, it includes: A multi-layer memory cell array, stacked in the direction perpendicular to the substrate. The memory cell array includes a plurality of memory cells arranged in a first direction and a second direction parallel to the substrate; the first direction and the second direction intersect; the memory cell includes at least one transistor; An isolation and shielding structure, penetrating through each layer of the memory cell array and located between two transistors of two adjacent memory cells along the second direction; the isolation and shielding structure includes an isolation layer and a conductive shielding layer: The isolation layer, penetrating through each layer of the memory cell array, is at least located between the channel regions of the two transistors in each layer of the memory cell array; The conductive shielding layer, penetrating through each layer of the memory cell array, is insulated from the two transistors through the isolation layer.

2. The memory device according to claim 1, characterized in that, it further includes: A reference electrode located between the substrate and each memory cell array, the reference electrode extending on the substrate; wherein, The conductive shielding layer extending towards the substrate extends to the reference electrode and is electrically connected to the reference electrode, and the reference electrode is connected to a voltage terminal that can provide a constant potential.

3. The memory device according to claim 2, characterized in that, it includes a plurality of the isolation and shielding structures located between different memory cells of the memory cell array, and each isolation and shielding structure extends towards the substrate and is connected to the same reference electrode.

4. The memory device according to any one of claims 1 to 3, characterized in that, The memory cell includes a first transistor, and the first transistor includes a ring-shaped first semiconductor layer extending in the direction perpendicular to the substrate; the memory device further includes: a plurality of first bit lines; Each of the first bit lines extends in the second direction and is electrically connected to the side walls of the first semiconductor layers in the corresponding column of memory cells; The isolation and shielding structure is located between the outer side walls of two adjacent first semiconductor layers in a column of memory cells and extends to the side wall of the bit line in the first direction.

5. The memory device according to claim 4, characterized in that, it further includes: A plurality of first word lines; The first word lines extend in the direction perpendicular to the substrate; the first semiconductor layer surrounds the outer side wall of the first word line; The outer side wall of the first semiconductor layer contacts the isolation layer, and the isolation layer contacts the conductive shielding layer.

6. The memory device according to claim 4, characterized in that, The memory cell further includes: a capacitor; The capacitor includes: a first electrode electrically connected to the first semiconductor layer, and a dielectric layer and a second electrode sequentially arranged on the side of the first electrode away from the first semiconductor layer; The first bit line, the first semiconductor layer, and the first electrode are arranged in sequence in the first direction; wherein, the isolation and shielding structure extends from one end close to the first bit line to between two adjacent first electrodes in the first direction.

7. The memory device according to claim 4, characterized in that, The memory cell further includes: a second transistor electrically connected to the memory node with the first transistor; the second transistor includes a ring-shaped second semiconductor layer extending along a direction perpendicular to the substrate and insulated from the memory node; the memory further includes: a plurality of second bit lines; wherein, the second bit lines extend along the second direction in a plane parallel to the substrate and are electrically connected to the second semiconductor layers in the corresponding columns of the memory cells; the first bit line, the first transistor of the memory cell, the memory node, the second transistor and the second bit lines are arranged in sequence in the first direction; wherein, the isolation and shielding structure extends from the first bit line to the memory node and is located between two adjacent memory nodes along the second direction.

8. The memory according to claim 7, wherein, the memory node is the main gate of the second transistor, or, the second transistor further includes a main gate and a back gate, the main gate is located in a through hole surrounded by the second semiconductor layer and is insulated from the second bit line and connected to the second word line; the memory node is the back gate of the second transistor.

9. The memory according to claim 7, wherein, the isolation and shielding structure extends in the first direction from one end close to the first bit line to between two adjacent memory nodes.

10. The memory according to claim 1, wherein, the isolation layer is a hollow annular film layer extending towards the substrate, and the conductive shielding layer is located inside the hollow annular film layer.

11. An electronic device, wherein, comprises the memory according to any one of claims 1-10.

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