Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate including a memory cell region and a peripheral circuit region, the memory cell region having a first active region and the peripheral circuit region having a second active region; a capacitor structure formed in the memory cell region and including a lower electrode connected to the first active region, an upper electrode surrounding the lower electrode, and a capacitor dielectric film disposed therebetween; a lower insulating film disposed in the memory cell region and the peripheral circuit region and covering the capacitor structure; a first interlayer insulating film including a first lower interlayer insulating film and a first upper interlayer insulating film sequentially stacked on the lower insulating film; and a wiring line disposed in the first interlayer insulating film and electrically connected to the capacitor structure, in which the first upper interlayer insulating film includes a first material including a benzene ring.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0180098, filed with the Korean Intellectual Property Office on December 12, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including metal wiring and a method of manufacturing the same. Background art

[0004] With the development of the electronics industry and user demands, semiconductor devices have become increasingly compact and lightweight through rapid development in miniaturization and high integration. As the high integration of semiconductor devices continues to increase and the size of semiconductor devices is correspondingly significantly reduced, the reliability of semiconductor devices may decrease. However, in order to meet the growing demands of the electronics industry for semiconductor devices with high performance and high reliability, a great deal of research has been conducted to improve the reliability of semiconductor devices. Summary of the invention

[0005] The present inventive concept provides a semiconductor device and a method of manufacturing the same having improved electrical characteristics and reliability.

[0006] According to an embodiment of the present inventive concept, there is provided a semiconductor device including: a substrate including a memory cell region and a peripheral circuit region, the memory cell region having a first active region and the peripheral circuit region having a second active region; a capacitor structure including a lower electrode connected to the first active region in the memory cell region, an upper electrode surrounding the lower electrode in the memory cell region, and a capacitor dielectric film disposed between the lower electrode and the upper electrode; a lower insulating film disposed on the substrate in the memory cell region and the peripheral circuit region and covering the capacitor structure in the memory cell region; a first interlayer insulating film including a first lower interlayer insulating film and a first upper interlayer insulating film sequentially stacked on the lower insulating film; and a wiring line disposed in the first interlayer insulating film and electrically connected to the capacitor structure, wherein the first upper interlayer insulating film includes a first material containing a benzene ring.

[0007] According to an embodiment of the inventive concept, a method of manufacturing a semiconductor device is provided. The method includes: providing a substrate including a memory cell region and a peripheral circuit region, the memory cell region having a first active region and the peripheral circuit region having a second active region; forming a capacitor structure connected to the first active region in the memory cell region; forming a lower insulating film covering the substrate and the capacitor structure; forming a plurality of cell contacts penetrating the lower insulating film in the memory cell region and forming peripheral circuit contacts penetrating the lower insulating film over the peripheral circuit region; forming a first interlayer insulating film including a first lower interlayer insulating film and a first upper interlayer insulating film sequentially stacked on the lower insulating film; and forming a wiring line disposed in the first interlayer insulating film and electrically connected to the capacitor structure, wherein the first upper interlayer insulating film includes a first material including a benzene ring.

[0008] According to an embodiment of the inventive concept, a semiconductor device is provided, including: a substrate including a memory cell region and a peripheral circuit region, the memory cell region having a first active region and the peripheral circuit region having a second active region; a capacitor structure including a lower electrode connected to the first active region in the memory cell region, an upper electrode surrounding the lower electrode in the memory cell region, and a capacitor dielectric film disposed between the lower electrode and the upper electrode; a lower insulating film disposed on the substrate in the memory cell region and the peripheral circuit region and covering the capacitor structure in the memory cell region; a first interlayer insulating film disposed on the lower insulating film and including a first upper interlayer insulating film and a first lower interlayer insulating film, the first upper interlayer insulating film including a first material including a benzene ring, the first lower interlayer insulating film including a low-k dielectric material of the same type as the first material; and a wiring line disposed in the first interlayer insulating film and electrically connected to the capacitor structure and including sidewalls coplanar in a region adjacent to a boundary where the first lower interlayer insulating film and the first upper interlayer insulating film are in contact with each other, wherein the first upper interlayer insulating film is represented by Chemical Formula 1 below:

[0009] [Chemical Formula 1]

[0010]

[0011] In Chemical Formula 1, R represents an alkyl group, and O—Si— represents Chemical Formula 1 repeatedly connected by an SiO bond to Chemical Formula 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a layout diagram showing a semiconductor device according to an embodiment of the inventive concept;

[0014] Figure 2 is Figure 1 an enlarged view of a portion Ex1 of

[0015] Figure 3 is a cross-sectional view taken along line A-A' in Figure 2 ;

[0016] Figures 4 to 14 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the inventive concept; and

[0017] Figure 15 is a cross-sectional view of a semiconductor device taken along line A-A' of Figure 2 according to an embodiment of the inventive concept.

[0018] Since Figures 1 to 15 the figures in are intended for illustrative purposes, the elements in the figures are not necessarily drawn to scale. For example, some of the elements may be enlarged or exaggerated for clarity.

[0019] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and their descriptions are omitted.

[0020] Figure 1 is a layout diagram showing a semiconductor device 10 according to an embodiment of the inventive concept. Figure 2 is Figure 1 an enlarged view of a portion Ex1 of Figure 3 is a cross-sectional view taken along line A-A' in Figure 2 ;

[0021] Referring to Figures 1 to 3 , the semiconductor device 10 may include a substrate 110 having a memory cell area MCA and a peripheral circuit area PCA surrounding the memory cell area MCA.

[0022] The memory cell area MCA may be a memory cell area of a dynamic random access memory (DRAM). The memory cell area MCA may include a plurality of unit memory cells each having a transistor and a capacitor. The peripheral circuit area PCA may be a core area or a peripheral circuit area of the DRAM. The peripheral circuit area PCA may be an area where peripheral circuits required to drive the memory cells in the memory cell area MCA are provided. For example, the peripheral circuit area PCA may include peripheral circuit transistors PG for transmitting signals and / or power to the memory cells included in the memory cell area MCA. In an embodiment of the inventive concept, the peripheral circuit transistors PG may configure various circuits, such as a command decoder, a control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.

[0023] Device isolation trenches 112T may be formed in the substrate 110, and a device isolation film 112 may be formed within the device isolation trenches 112T. The device isolation film 112 may include, for example, an oxide film, a nitride film, or a combination thereof. A plurality of first active regions AC1 are defined in the memory cell area MCA on the substrate 110 by the device isolation film 112, and a second active region AC2 is defined in the peripheral circuit area PCA on the substrate 110. For example, the device isolation trenches 112T may be arranged on the substrate 110 to surround the plurality of first active regions AC1 in each memory cell area MCA and the plurality of second active regions AC2 in each peripheral circuit area PCA.

[0024] In the memory cell area MCA, the plurality of first active regions AC1 may be arranged to have a major axis diagonally with respect to a first horizontal direction (X direction) and a second horizontal direction (Y direction). Thus, the second horizontal direction (Y direction) is orthogonal to the first horizontal direction (X direction). As shown, the plurality of first active regions AC1 may be provided in a diagonal or slanted strip form, and by depositing the plurality of first active regions AC1 in the diagonal or slanted direction, the maximum possible distance between contacts may be provided for the semiconductor device 10. A plurality of word lines WL may be spaced apart from each other in the second horizontal direction (Y direction) and extend parallel to each other across the plurality of first active regions AC1 in the first horizontal direction (X direction). The plurality of word lines WL may be arranged at a uniform pitch. A plurality of bit lines BL may extend parallel to each other in the second horizontal direction (Y direction) on the plurality of word lines WL and may be arranged at a uniform pitch. The plurality of bit lines BL may be connected to the plurality of first active regions AC1 through a plurality of direct contacts DC. In a plan view, the direct contacts DC may each be arranged on a central region of the first active region AC1.

[0025] A plurality of buried contacts BC may be respectively formed between two adjacent bit lines BL among a plurality of bit lines BL, and may be disposed at both ends of a plurality of first active regions AC1. In an embodiment of the inventive concept, the plurality of buried contacts BC may be arranged in a line in a first horizontal direction (X direction) and a second horizontal direction (Y direction). A plurality of landing pads LP may be disposed on the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of landing pads LP may connect a lower electrode 182 of a capacitor structure 180 formed on the plurality of bit lines BL to the plurality of first active regions AC1. For example, the plurality of landing pads LP may be disposed between the plurality of buried contacts BC and the lower electrode 182 of the capacitor structure 180. At least a part of each of the plurality of landing pads LP may overlap with the buried contacts BC in a vertical direction (Z direction).

[0026] The substrate 110 may include at least one selected from, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium antimonide (InSb), lead telluride (PbTe), gallium phosphide (GaP), gallium antimonide (GaSb), or indium phosphide (InP). The substrate 110 may include a conductive (conductive) region, for example, a well doped with impurities or a structure doped with impurities.

[0027] In a memory cell region MCA, a plurality of word line trenches extending in a first horizontal direction (X direction) may be formed in the substrate 110, and a plurality of gate dielectric layers, a plurality of gate electrodes, and a plurality of capping insulating films may be formed in the plurality of word line trenches. The plurality of gate electrodes may correspond to Figure 1 the plurality of word lines WL shown in. The plurality of gate dielectric films may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), oxide / nitride / oxide (ONO), or a high-k dielectric material having a dielectric constant higher than that of silicon oxide (SiO 2 ). The high-k dielectric material may include, for example, hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO 3 ), tantalum oxide (Ta 2 O 3 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO 3 ), zirconium oxide (ZrO 2 ), yttrium oxide (Y 2 O3 ) or titanium oxide (TiO 2 ), but the inventive concept is not limited thereto. The plurality of gate electrodes may include, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or any combination thereof. The plurality of capping insulating films may include silicon oxide (SiO 2 ) film, silicon nitride (Si 3 N 4 ) film, silicon oxynitride (SiON) film, or any combination thereof.

[0028] The buffer film 114 may be disposed on the substrate 110 in the memory cell region MCA. The buffer film 114 may include, for example, an oxide film, a nitride film, or any combination thereof.

[0029] A plurality of direct contacts DC may be formed in a plurality of direct contact holes DCH of the substrate 110. The direct contacts DC may extend to a level higher than the upper surface of the substrate 110. The plurality of direct contacts DC may be connected to the plurality of first active regions AC1. Each of the plurality of direct contacts DC may include, for example, silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or any combination thereof. In an embodiment of the inventive concept, each of the plurality of direct contacts DC may include doped polysilicon (p-Si). For example, the plurality of direct contacts DC may include polysilicon (p-Si) containing a relatively high concentration of impurities such as phosphorus (P), arsenic (As), bismuth (Bi), and / or antimony (Sb).

[0030] A plurality of bit lines BL extending parallel to each other in the second horizontal direction (Y direction) may be disposed on the substrate 110 and on each of the plurality of direct contacts DC. The plurality of bit lines BL may each be connected to the plurality of first active regions AC1 through the plurality of direct contacts DC. Each of the plurality of bit lines BL may include a lower conductive layer 132A, an intermediate conductive layer 134A, and an upper conductive layer 136A sequentially stacked on the substrate 110. The upper surface of the lower conductive layer 132A may be located at the same vertical level as the upper surface of the direct contact DC, and the lower surface of the intermediate conductive layer 134A may be in contact with the upper surface of the direct contact DC.

[0031] The lower conductive layer 132A may include, for example, doped polysilicon (p-Si). The intermediate conductive layer 134A and the upper conductive layer 136A may each include, for example, titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi x) Tungsten silicon nitride (WSi x N y ), ruthenium (Ru), or any combination thereof. For example, the intermediate conductive layer 134A may include a film containing, for example, titanium nitride (TiN) and / or titanium silicon nitride (TiSiN), and the upper conductive layer 136A may include a film containing, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tungsten silicon nitride (WSi x N y ), ruthenium (Ru), or any combination thereof.

[0032] In Figure 3 , each of the plurality of bit lines BL is illustrated as having a triple conductive layer structure, including a lower conductive layer 132A, an intermediate conductive layer 134A, and an upper conductive layer 136A, but the inventive concept is not limited thereto. For example, each of the plurality of bit lines BL may be formed of a single conductive layer, or formed in a stacked structure of a plurality of conductive layers (such as a double conductive layer, or a quadruple conductive layer or more).

[0033] The upper surfaces of each of the plurality of bit lines BL may be respectively covered with a plurality of insulating capping layers 140A. The plurality of insulating capping layers 140A may be disposed on the upper conductive layer 136A of the plurality of bit lines BL. The plurality of insulating capping layers 140A may each extend over each of the plurality of bit lines BL in the second horizontal direction (Y direction). Each of the plurality of insulating capping layers 140A may include silicon nitride (Si 3 N 4 ) film.

[0034] Insulating spacers 150A may be disposed on two sidewalls of each of the plurality of insulating capping layers 140A and the plurality of bit lines BL. The insulating spacers 150A may extend over two sidewalls of each of the plurality of bit lines BL in the second horizontal direction (Y direction). Some of the insulating spacers 150A may further extend into the direct contact hole DCH and cover two sidewalls of the direct contact DC formed in the direct contact hole DCH.

[0035] The plurality of recessed spaces RS formed in the first active region AC1 in some regions of the substrate 110 may be filled with a plurality of contact plugs 152. Each of the plurality of contact plugs 152 may extend in the vertical direction (Z direction) from the recessed space RS. Each of the plurality of contact plugs 152 may contact the first active region AC1. The plurality of contact plugs 152 may be arranged in a row in the second horizontal direction (Y direction) between each of the plurality of bit lines BL. For example, each of the plurality of contact plugs 152 may be disposed between two adjacent insulating spacers 150A, and the upper sides of each of the plurality of contact plugs 152 may contact two adjacent insulating spacers 150A. The lower sides of each of the plurality of contact plugs 152 may extend into the substrate 110. The plurality of contact plugs 152 may be formed Figure 2A plurality of embedded contacts BC as shown. The plurality of contact plugs 152 may include a semiconductor pattern doped with impurities, such as doped polysilicon (p-Si), but the inventive concept is not limited thereto.

[0036] A plurality of insulating fences may each be disposed between two adjacent contact plugs among the plurality of contact plugs 152 arranged in a row in the second horizontal direction (Y direction). The plurality of contact plugs 152 may be insulated from each other by the plurality of insulating fences. Each of the plurality of insulating fences may have a columnar shape extending in the vertical direction (Z direction) between the plurality of bit lines BL. In an embodiment of the inventive concept, the plurality of insulating fences may include, for example, silicon nitride (Si 3 N 4 ) film.

[0037] A plurality of landing pads LP may be disposed on the plurality of contact plugs 152. Each of the plurality of landing pads LP may extend in the vertical direction (Z direction) on the contact plug 152. Each of the plurality of landing pads LP may include a conduction blocking film 162A and a landing pad conductive layer 164A. In an embodiment of the inventive concept, the conduction blocking film 162A may include, for example, titanium (Ti), titanium nitride (TiN), or any combination thereof, and the landing pad conductive layer 164A may include, for example, a metal, a metal nitride, conductive polysilicon (p-Si), or any combination thereof. In a plan view, the plurality of landing pads LP may have an island pattern shape. The plurality of landing pads LP may be electrically insulated from each other by an insulating pattern 166 surrounding each of the plurality of landing pads LP. The insulating pattern 166 may include, for example, at least one of silicon nitride (Si 3 N 4 )、silicon oxide (SiO 2 )、or silicon oxynitride (SiON).

[0038] A metal silicide film may be further disposed between the plurality of contact plugs 152 and the plurality of landing pads LP. The metal silicide film may include, for example, cobalt silicide (CoSi 2 )、nickel silicide (NiSi 2 )、titanium silicide (TiSi 2 )、tantalum silicide (TaSi 2 )、or manganese silicide (MnSi 2 ).

[0039] In the peripheral circuit area PCA, a peripheral circuit transistor PG may be disposed on the second active area AC2. The peripheral circuit transistor PG may include a gate dielectric film 116, a gate electrode PGS, and a gate capping layer 140B sequentially stacked on the second active area AC2.

[0040] The gate dielectric film 116 may include at least one selected from the following: silicon oxide (SiO2 ) Silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a high-k dielectric material having a dielectric constant higher than that of silicon dioxide (SiO 2 ). The high-k dielectric material may include, for example, hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO 3 ), tantalum oxide (Ta 2 O 3 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO 3 ), zirconium oxide (ZrO 2 ), yttrium oxide (Y 2 O 3 ), or titanium oxide (TiO 2 ), but the inventive concept is not limited thereto.

[0041] The gate electrode PGS may include a lower conductive layer 132B, an intermediate conductive layer 134B, and an upper conductive layer 136B. The materials constituting the lower conductive layer 132B, the intermediate conductive layer 134B, and the upper conductive layer 136B may be substantially the same as the materials constituting the lower conductive layer 132A, the intermediate conductive layer 134A, and the upper conductive layer 136A included in the bit line BL in the memory cell region MCA. For example, the gate electrode PGS may be formed simultaneously during the formation of the bit line BL. However, the inventive concept is not limited thereto.

[0042] In an embodiment of the inventive concept, the gate capping layer 140B may include silicon nitride (Si 3 N 4 ).

[0043] In an embodiment of the inventive concept, two sidewalls of the gate electrode PGS may be covered with gate spacers 150B. The gate spacers 150B may include, for example, silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or any combination thereof.

[0044] The peripheral circuit transistor PG may be covered with a first insulating film 142. A second insulating film 144 may be disposed on the first insulating film 142. In the peripheral circuit area PCA, a contact plug CP may be formed in a contact hole CPH that penetrates the first insulating film 142 and the second insulating film 144 in the vertical direction (Z direction). The contact plug CP may include a conduction blocking film 162B and a plug conductive layer 164B. The conduction blocking film 162B and the plug conductive layer 164B of the contact plug CP may each have a structure that is substantially the same as or similar to the conduction blocking film 162A and the landing pad conductive layer 164A of the plurality of landing pads LP formed in the memory cell area MCA, and may include substantially the same materials. As Figure 3 shown, the contact plug CP may be formed in the contact holes CPH that penetrate the first insulating film 142 and the second insulating film 144 in the vertical direction (Z direction) in the peripheral circuit area PCA, respectively, to connect to the substrate 110. For example, the contact plug CP may be disposed adjacent to the gate electrode PGS and connected to the source and drain regions of the substrate 110.

[0045] In the memory cell area MCA, an upper insulating pattern 170 may be disposed on the insulating pattern 166. The upper insulating pattern 170 may include a material having an etching selectivity with respect to the second insulating film 144 and the insulating pattern 166. For example, the upper insulating pattern 170 may include silicon nitride (Si 3 N 4 ).

[0046] In the memory cell area MCA, a capacitor structure 180 may be disposed on the upper insulating pattern 170 and the landing pad LP to store charges in, for example, a semiconductor memory element. For example, the capacitor structure 180 may be connected to a portion of the upper surface of each landing pad LP that is not blocked by the upper insulating pattern 170. The capacitor structure 180 may include a plurality of lower electrodes 182, a capacitor dielectric film 184, and an upper electrode 186. The capacitor structure 180 may be formed only in the memory cell area MCA. That is, the plurality of lower electrodes 182, the capacitor dielectric film 184, and the upper electrode 186 of the capacitor structure 180 may not be formed in the peripheral circuit area PCA.

[0047] Multiple lower electrodes 182 may be disposed on the multiple landing pads LP. The multiple lower electrodes 182 may extend in a vertical direction (Z direction) on the multiple landing pads LP through the upper insulating pattern 170. The lower surface of one of the multiple lower electrodes 182 may contact one landing pad LP selected from the multiple landing pads LP. One of the multiple lower electrodes 182 may contact and be connected to the one landing pad LP. Each of the multiple lower electrodes 182 may include, for example, a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal oxynitride, or any combination thereof. In an embodiment of the inventive concept, the multiple lower electrodes 182 may include at least one selected from the following: metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), etc., conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), tungsten nitride (WN), etc., and conductive metal oxides such as iridium oxide (IrO 2 ), ruthenium oxide (RuO 2 ), strontium ruthenate (SrRuO 3 ), etc.

[0048] Multiple support layers SPT may be disposed on sidewalls of the multiple lower electrodes 182. The multiple support layers SPT may maintain a constant distance between two adjacent lower electrodes 182 and prevent the multiple lower electrodes 182 from tilting or collapsing. The multiple support layers SPT may be located at different vertical levels on the sidewalls of the multiple lower electrodes 182.

[0049] A capacitor dielectric film 184 may be disposed on the multiple lower electrodes 182. The capacitor dielectric film 184 may cover sidewalls of the multiple lower electrodes 182, upper and lower surfaces of the support layers SPT, and an upper surface of the upper insulating pattern 170. The capacitor structure 180 may store charges in the capacitor dielectric film 184 through a potential difference generated between the lower electrode 182 and the upper electrode 186. The capacitor dielectric film 184 may include, for example, zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), titanium oxide (TiO 2 ), niobium oxide (Nb 2 O 5 ), tantalum oxide (Ta 2 O 3 ), yttrium oxide (Y 2 O 3 ), strontium titanate (SrTiO 3 ), barium strontium titanate (BaSrTi 2 O 6 ), scandium oxide (Sc 2 O 3 ), lanthanum oxide (La2 O 3 ) or any combination thereof.

[0050] A plurality of upper electrodes 186 may be arranged to cover a capacitor dielectric film 184 on a plurality of lower electrodes 182. Each of the plurality of upper electrodes 186 may include, for example, a metal, a conductive metal oxide, a conductive metal nitride, a conductive metal oxynitride, or any combination thereof. In an embodiment of the inventive concept, the plurality of upper electrodes 186 may include at least one selected from the following: metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), etc., conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), tungsten nitride (WN), etc., or conductive metal oxides such as iridium oxide (IrO 2 ), ruthenium oxide (RuO 2 ), strontium ruthenate (SrRuO 3 ), etc.

[0051] A lower insulating film 192 may be disposed on a substrate in a memory cell region MCA and a peripheral circuit region PCA. The lower insulating film 192 may cover a capacitor structure 180 in the memory cell region MCA. The lower insulating film 192 may be disposed on a contact plug CP and a second insulating film 144 in the peripheral circuit region PCA. The lower insulating film 192 may cover the second insulating film 144 and the contact plug CP. The lower insulating film 192 may fill a space between capacitor structures 180 of two adjacent memory cell regions MCA.

[0052] In an embodiment of the inventive concept, the lower insulating film 192 may include an oxide. For example, the lower insulating film 192 may include tetraethyl orthosilicate (TEOS), low deposition-tetraethylorthosilicate (LD-TEOS), plasma enhanced-tetraethylorthosilicate (PE-TEOS), or any combination thereof.

[0053] A plurality of cell contacts MC may extend in a vertical direction (Z direction) through the lower insulating film 192 in the memory cell region MCA. A bottom surface of each of the plurality of cell contacts MC may be connected to an upper electrode 186 of the capacitor structure 180. Each of the plurality of cell contacts MC may include a cell conduction blocking film MCL and a cell contact conductive layer MCC. In a plan view, the plurality of cell contacts MC may have a circular shape.

[0054] The peripheral circuit contact PC can extend in the vertical direction (Z direction) through the lower insulating film 192 in the peripheral circuit region PCA. In a plan view, the peripheral circuit contact PC can have a circular shape. The bottom surface of the peripheral circuit contact PC can contact the contact plug CP and be connected to the contact plug CP. The peripheral circuit contact PC can be connected to the second active region AC2 through the contact plug CP. The peripheral circuit contact PC can include a peripheral circuit conduction blocking film PCL and a peripheral circuit contact conductive layer PCC.

[0055] A plurality of wiring lines 193 and a first interlayer insulating film 194 covering the plurality of wiring lines 193 can be disposed on the plurality of unit contacts MC, the peripheral circuit contact PC, and the lower insulating film 192. The bottom surface of the plurality of wiring lines 193 can contact the upper surfaces of the plurality of unit contacts MC and the peripheral circuit contact PC.

[0056] Each of the plurality of wiring lines 193 can include a wiring line conductive layer 193C and a wiring line blocking layer 193L. In an embodiment of the inventive concept, the wiring line conductive layer 193C can include tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or any combination thereof. For example, the wiring line conductive layer 193C can include a copper (Cu) film. The wiring line blocking layer 193L can include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or any combination thereof, but the inventive concept is not limited thereto.

[0057] In an embodiment of the inventive concept, the first interlayer insulating film 194 can include a first lower interlayer insulating film 194L and a first upper interlayer insulating film 194U sequentially stacked on the lower insulating film 192.

[0058] In an embodiment of the inventive concept, the vertical direction (Z direction) thickness (i.e., the vertical thickness) of the first upper interlayer insulating film 194U can be less than the vertical direction (Z direction) thickness (i.e., the vertical thickness) of the first lower interlayer insulating film 194L. However, the inventive concept is not limited thereto, and the thickness of the first upper interlayer insulating film 194U in the vertical direction (Z direction) can be greater than or equal to the vertical (Z direction) thickness of the first lower interlayer insulating film 194L.

[0059] In an embodiment of the inventive concept, the first lower interlayer insulating film 194L can include a low-k material. For example, the first lower interlayer insulating film 194L can include a low dielectric constant k in the range of about 2.2 to about 3.0. For example, the first lower interlayer insulating film 194L can include, for example, a silicon oxycarbide (SiOC) film or a carbon-doped silicon oxide (SiCOH) film.

[0060] In an embodiment of the inventive concept, the first upper interlayer insulating film 194U may include a low-k dielectric material including a benzene ring. For example, the first upper interlayer insulating film 194U may include a material represented by Chemical Formula 1 below.

[0061] [Chemical Formula 1]

[0062]

[0063] In Chemical Formula 1, R represents an alkyl group (e.g., a C1 to C30 (C1 to C20, or C1 to C10) alkyl group), and O-Si- represents Chemical Formula 1 that is repeatedly connected to Chemical Formula 1 through an SiO bond, i.e., a connection site to another Chemical Formula 1.

[0064] The first upper interlayer insulating film 194U includes a low-k dielectric material including a benzene ring, and thus, it is possible to prevent the escape (exhaust) of impurities (e.g., H 2 O, H + ) generated in the interlayer insulating film (e.g., including TEOS) during the manufacturing process of a conventional semiconductor device. If the escape of impurities occurs in the interlayer insulating film, defects may occur in the upper contact, and as a result, the reliability of the semiconductor device may be reduced.

[0065] The first upper interlayer insulating film 194U of the semiconductor device 10 according to the inventive concept includes a material represented by Chemical Formula 1, and since the material does not generate impurities, the escape phenomenon can be prevented. By preventing the escape phenomenon of the first upper interlayer insulating film 194U, the formation of defects in the upper contact 195 can be prevented, and the productivity and reliability of the semiconductor device 10 can be improved.

[0066] In an embodiment of the inventive concept, the first upper interlayer insulating film 194U may include a material having a dielectric constant lower than that of the lower insulating film 192. For example, the first upper interlayer insulating film 194U may include a material having a dielectric constant lower than that of TEOS, PE-TEOS, LD-TEOS, or any combination thereof. For example, the lower insulating film 192 may include a material having a dielectric constant greater than that of the material of the first upper interlayer insulating film.

[0067] The first upper interlayer insulating film 194U includes a material having a dielectric constant lower than that of TEOS, PE-TEOS, LD-TEOS, or any combination thereof, and thus, deterioration between the wiring lines 193 is prevented, and the electrical performance and integration of the semiconductor device 10 can be improved.

[0068] In an embodiment of the inventive concept, the first lower interlayer insulating film 194L may include a material having a dielectric constant different from that of the first upper interlayer insulating film 194U. The first lower interlayer insulating film 194L may include a material having a dielectric constant lower than that of the lower insulating film 192. For example, the first lower interlayer insulating film 194L may include a material having a dielectric constant lower than that of TEOS, PE-TEOS, LD-TEOS, or any combination thereof.

[0069] In an embodiment of the inventive concept, the first lower interlayer insulating film 194L and the first upper interlayer insulating film 194U may include the same type of low-k dielectric material. The same type of low-k dielectric material described herein may include, for example, silicon oxycarbide (SiOC), carbon-doped silicon oxide (SiCOH), and the material represented by Chemical Formula 1. In an embodiment of the inventive concept, the first lower interlayer insulating film 194L and the first upper interlayer insulating film 194U may include the same material. Since the first lower interlayer insulating film 194L and the first upper interlayer insulating film 194U include the same low-k dielectric material, sidewalls of the wiring line 193 may be coplanar in a region adjacent to a boundary where the first lower interlayer insulating film 194L contacts the first upper interlayer insulating film 194U. For example, sidewalls of the wiring line 193 may extend as a straight line (or plane) passing through (through) a boundary between the first lower interlayer insulating film 194L and the first upper interlayer insulating film 194U. Sidewalls of the wiring line 193 may be located on an inclined plane. Since the first lower interlayer insulating film 194L and the first upper interlayer insulating film 194U include the same low-k dielectric material, voids may not be generated in the wiring line 193 during an operation of forming the wiring line 193. Since voids are removed from the wiring line 193, electrical properties and integration of the semiconductor device 10 may be improved. In an embodiment of the inventive concept, the first lower interlayer insulating film 194L of the semiconductor device 10 of the inventive concept may also include the material represented by Chemical Formula 1. However, the inventive concept is not limited thereto.

[0070] The interlayer capping layer 196 may be disposed on the plurality of wiring lines 193 and the first interlayer insulating film 194. The interlayer capping layer 196 may include a lower capping layer 196L covering the first interlayer insulating film 194 and an upper capping layer 196U covering the lower capping layer 196L. A bottom surface of the lower capping layer 196L may contact upper surfaces of the plurality of wiring lines 193 and the first interlayer insulating film 194, respectively. The lower capping layer 196L is disposed between the upper capping layer 196U and the first interlayer insulating film 194, thereby improving adhesion between the upper capping layer 196U and the first interlayer insulating film 194.

[0071] In an embodiment of the inventive concept, the interlayer capping layer 196 may include, for example, silicon nitride (Si 3 N 4 ) or silicon carbonitride (SiCN). For example, the upper capping layer 196U may include silicon nitride (Si 3 N 4 ), and the lower capping layer 196L may include silicon carbonitride (SiCN).

[0072] The second interlayer insulating film 198 may be disposed on the interlayer capping layer 196. In an embodiment of the inventive concept, the second interlayer insulating film 198 may include a material having a dielectric constant higher than that of the first upper interlayer insulating film 194U. For example, the second interlayer insulating film 198 may include, for example, TEOS, PE-TEOS, LD-TEOS, or any combination thereof.

[0073] A plurality of upper contacts 195 may be disposed to penetrate the interlayer capping layer 196 and the second interlayer insulating film 198 in a vertical direction (Z direction). The plurality of upper contacts 195 may each be electrically connected to respective ones of the plurality of wiring lines 193 through the second interlayer insulating film 198 and the interlayer capping layer 196, respectively.

[0074] In an embodiment of the inventive concept, each of the plurality of upper contacts 195 may include an upper contact conductive layer 195C and an upper contact barrier layer 195L. In an embodiment of the inventive concept, the upper contact conductive layer 195C may include, for example, tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or any combination thereof. For example, the upper contact conductive layer 195C may include, for example, a copper (Cu) film. The upper contact barrier layer 195L may include, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or any combination thereof, but the inventive concept is not limited thereto.

[0075] Figures 4 to 14 is a cross-sectional view for explaining a method of manufacturing the semiconductor device 10 according to an embodiment of the inventive concept. For example, Figures 4 to 14 is a cross-sectional view for explaining each operation of a method of manufacturing the semiconductor device 10 according to an embodiment of the inventive concept.

[0076] Referring to Figure 4, a plurality of device isolation trenches 112T may be formed in a substrate 110 having a memory cell area MCA and a peripheral circuit area PCA. Subsequently, a plurality of device isolation films 112 may be formed by filling the plurality of device isolation trenches 112T with an insulating material. By forming the plurality of device isolation films 112, a plurality of first active regions AC1 may be defined in the memory cell area MCA of the substrate 110, and a second active region AC2 may be defined in the peripheral circuit area PCA. In a plan view, the plurality of first active regions AC1 may extend in a diagonal direction inclined at a predetermined angle with respect to a first horizontal direction (X direction) and a second horizontal direction (Y direction) (see Figure 2 ). Additionally, the plurality of first active regions AC1 may be in the form of a plurality of stripes extending parallel to each other, and a substantially central portion of one of the plurality of first active regions AC1 may be disposed adjacent to an end portion of another first active region AC1.

[0077] Subsequently, a buffer film 114 may be formed in the memory cell area MCA of the substrate 110, and a gate dielectric film 116 may be formed in the peripheral circuit area PCA of the substrate 110.

[0078] Subsequently, a direct contact hole DCH may be formed by removing a portion of the substrate 110 using a mask pattern. The direct contact hole DCH may expose the first active region AC1. The mask pattern may include, for example, an oxide film, a nitride film, or any combination thereof, but the inventive concept is not limited thereto. After removing the mask pattern, a direct contact DC may be formed by filling the direct contact hole DCH with a conductive material. For example, the direct contact holes DCH may each be formed at a substantially central portion of each of the first active regions AC1.

[0079] Subsequently, a lower conductive layer 132A, an intermediate conductive layer 134A, an upper conductive layer 136A, and an insulating capping layer 140A are sequentially formed on the buffer film 114 in the memory cell area MCA, and the intermediate conductive layer 134A, the upper conductive layer 136A, and the insulating capping layer 140A are sequentially formed on the direct contact DC, and a lower conductive layer 132B, an intermediate conductive layer 134B, an upper conductive layer 136B, and an insulating capping layer 140B are sequentially formed on the gate dielectric film 116 in the peripheral circuit area PCA.

[0080] Next, in the memory cell array region MCA, a plurality of bit lines BL are formed as follows: using the insulating capping layer 140A as an etching mask, a part of each of the direct contact DC, the lower conductive layer 132A, the intermediate conductive layer 134A, and the upper conductive layer 136A is etched, and in the peripheral circuit region PCA, the gate electrode PGS can be formed as follows: using the insulating capping layer 140B as an etching mask, a part of each of the lower conductive layer 132B, the intermediate conductive layer 134B, and the upper conductive layer 136B is etched. For example, after the patterning process, the bit lines BL and the direct contact DC can be formed on the substrate 110 and connected to the substrate 110, and extend in the second horizontal direction (Y direction) in the memory cell array region MCA.

[0081] Next, a gate spacer 150B can be formed on the sidewalls of the gate electrode PGS, and a first insulating film 142 covering the gate electrode PGS can be formed.

[0082] Next, an insulating spacer 150A can be formed on the sidewalls of each of the plurality of bit lines BL and the insulating capping layer 140A in the memory cell array region MCA, and a plurality of insulating barriers can be formed between the plurality of bit lines BL. For example, a plurality of insulating barriers can be formed using an insulating material at the intersection of the spaces between two adjacent bit lines BL. The insulating spacer 150A can conformally cover the sidewalls of each of the plurality of bit lines BL and the insulating capping layer 140A.

[0083] Next, a plurality of recessed spaces RS exposing the first active region AC1 can be formed between the plurality of bit lines BL as follows: a part of the bottom of the contact space provided between the plurality of bit lines BL and between the plurality of insulating barriers on the substrate 110 is removed. In an embodiment of the inventive concept, an anisotropic etching process or a combination of an anisotropic etching process and an isotropic etching process can be used to form the plurality of recessed spaces RS.

[0084] Next, a plurality of contact plugs 152 can be formed by filling a part of the plurality of recessed spaces RS and the contact space with a conductive material.

[0085] Next, in the peripheral circuit region PCA, a plurality of contact holes CPH exposing the second active region AC2 can be formed by etching the first insulating film 142.

[0086] Next, in the memory cell array region MCA and the peripheral circuit region PCA, a conduction blocking film and a conductive layer are formed to cover the exposed surface of the substrate 110. Thereafter, the conduction blocking film and the conductive layer are patterned to form a plurality of landing pads LP including a conduction blocking film 162A and a landing pad conductive layer 164A in the memory cell array region MCA, and a plurality of contact plugs CP including a conduction blocking film 162B and a plug conductive layer 164B may be formed in the peripheral circuit region PCA. Then, each of the plurality of landing pads LP may be disposed on a part of the upper surface of the insulating capping layer 140A and on the upper surface of the contact plug 152. Like the contact plug 152, the landing pads LP may form a plurality of isolated regions spaced apart from each other.

[0087] Next, an insulating pattern 166 surrounding the sidewalls of the plurality of landing pads LP and a second insulating film 144 covering the sidewalls of the contact plugs CP may be formed. For example, the insulating pattern 166 may separate the landing pads LP from each other, and the second insulating film 144 may separate the contact plugs CP from each other.

[0088] Referring to Figure 5 , an upper insulating pattern 170 may be formed on the insulating pattern 166 in the memory cell array region MCA of the substrate 110. Next, a mold structure may be formed on the upper insulating pattern 170. The mold structure may include a first mold layer, a second mold layer, and a third mold layer sequentially stacked on the upper insulating pattern 170.

[0089] In an embodiment of the inventive concept, a support layer SPT may be selectively formed between the first mold layer and the second mold layer, between the second mold layer and the third mold layer, and on the third mold layer. Although three support layers SPT are shown as being formed in Figure 5 , the inventive concept is not limited thereto, and the number of support layers SPT may vary depending on the height of the plurality of lower electrodes 182.

[0090] In an embodiment of the inventive concept, the support layer SPT may be formed by using a material having an etching selectivity with respect to the material constituting the mold structure. In this case, under selected etching conditions, the etching rate of the material constituting the mold structure may be significantly higher than the etching rate of the material of the support layer SPT. For example, the first to third mold layers may be formed using silicon oxide (SiO 2 ), and the support layer SPT may be formed using silicon nitride (Si 3 N 4 ). However, the inventive concept is not limited thereto.

[0091] Next, a mask pattern is formed on the mold structure body, openings are formed through the mold structure body using the mask pattern as an etching mask, and a plurality of lower electrodes 182 can be formed by filling the openings with a conductive material. Each of the plurality of lower electrodes 182 can contact the upper surface of the conductive landing pad LP at the bottom surface.

[0092] Next, the mold structure body can be removed from the memory cell region MCA, and the mold structure body and the support layer SPT can be removed from the peripheral circuit region PCA. In an embodiment of the inventive concept, a combination of an anisotropic etching process and an isotropic etching process can be used to remove the mold structure body and the support layer SPT. In the memory cell region MCA, the mold structure body can be removed to expose at least a part of two sidewalls of the plurality of lower electrodes 182, the upper surface and the lower surface of the support layer SPT, and the upper surface of the upper insulating pattern 170. In the peripheral circuit region PCA, the mold structure body and the support layer SPT can be removed to expose the upper surface of the second insulating film 144 and the upper surface of the contact plug CP.

[0093] Referring to Figure 6 , a capacitor dielectric film 184 can be formed on the upper insulating pattern 170, the plurality of lower electrodes 182, and the support layer SPT. The capacitor dielectric film 184 can conformally cover the upper surface of the upper insulating pattern 170, at least a part of two sidewalls of the plurality of lower electrodes 182, and the upper surface and the lower surface of the support layer SPT. For example, the capacitor dielectric film 184 can be conformally formed on all exposed surfaces after the mold structure body is removed in the memory cell region MCA. Next, a preliminary upper electrode layer 186P can be formed to cover the capacitor dielectric film 184, the upper surface of the second insulating film 144, and the upper surface of the contact plug CP.

[0094] Referring to Figure 7 , a mask pattern is formed on the upper surface of the preliminary upper electrode layer 186P, and the preliminary upper electrode layer 186P located in the peripheral circuit region PCA can be removed by using the mask pattern as an etching mask (see Figure 6portion of (). For example, the mask pattern may be a photoresist pattern including a layer of photoresist material. The mask pattern may be formed on the upper surface of a portion of the preliminary upper electrode layer 186P located in the memory cell region MCA, but may not be formed on the upper surface of the remaining portion of the preliminary upper electrode layer 186P located in the peripheral circuit region PCA. A portion of the preliminary upper electrode layer 186P located in the peripheral circuit region PCA may be removed to expose the upper surface of the second insulating film 144 and the upper surface of the contact plug CP. The portion of the preliminary upper electrode layer 186P located in the peripheral circuit region PCA may be removed using the photoresist pattern as an etch mask by an anisotropic etching process. Additionally, the remaining portion of the preliminary upper electrode layer 186P that is not removed and remains in the memory cell region MCA may form the upper electrode 186 of the capacitor structure 180.

[0095] Referring to Figure 8 , a first insulating material layer 192P may be formed to cover the capacitor structure 180 in the memory cell region MCA and to cover the second insulating film 144 and the contact plug CP in the peripheral circuit region PCA. The first insulating material layer 192P may be formed by a deposition process. In an embodiment of the inventive concept, the first insulating material layer 192P may include, for example, TEOS, PE-TEOS, LD-TEOS, or any combination thereof.

[0096] Referring to Figure 9 , the upper surface of the insulating material layer 192P (see Figure 8 ) may be flattened by a planarization process. The planarization process may be, for example, a chemical mechanical polishing (CMP) process. The portion of the insulating material layer 192P that remains and is not removed after the planarization process may be the lower insulating film 192.

[0097] Next, a plurality of metal contact holes may be formed through the lower insulating layer 192 in the memory cell region MCA, and peripheral circuit contact holes may be formed through the lower insulating film 192 in the peripheral circuit region PCA. The plurality of metal contact holes and the peripheral circuit contact holes may be formed by an etching process.

[0098] Next, a conduction blocking film MCL may be formed to conformally cover the inner walls of the plurality of metal contact holes, and a conduction blocking film PCL may be formed to conformally cover the inner walls of the peripheral circuit contact holes. The conduction blocking film MCL and the conduction blocking film PCL may include, for example, titanium (Ti), titanium nitride (TiN), or any combination thereof, but the inventive concept is not limited thereto.

[0099] Next, a contact conductive layer MCC filling the plurality of metal contact holes and a peripheral circuit contact conductive layer PCC filling the peripheral circuit contact holes may be formed, and a plurality of unit contacts MC and peripheral circuit contacts PC may be formed as follows: polishing the upper surfaces of the conductive barrier films MCL and PCL and the upper surfaces of the contact conductive layer MCC and the peripheral circuit contact conductive layer PCC. For example, a CMP process may be used to polish the upper surfaces of the conductive barrier films MCL and PCL and the upper surfaces of the contact conductive layer MCC and the peripheral circuit contact conductive layer PCC.

[0100] Referring to Figure 10 , a first preliminary interlayer insulating film 194P may be formed. A first preliminary lower interlayer insulating film 194LP may be formed on the plurality of unit contacts MC, peripheral circuit contacts PC, and the lower insulating film 192. In an embodiment of the inventive concept, the first preliminary lower interlayer insulating film 194LP may include a low-k material. For example, the first preliminary lower interlayer insulating film 194LP may include a low-k dielectric film having a low dielectric constant k in the range of about 2.2 to about 3.0. For example, the first preliminary lower interlayer insulating film 194LP may include a silicon oxycarbide (SiOC) film or a carbon-doped silicon oxide (SiCOH) film.

[0101] Next, a first preliminary upper interlayer insulating film 194UP may be formed on the first preliminary lower interlayer insulating film 194LP. The first preliminary upper interlayer insulating film 194UP and the first preliminary lower interlayer insulating film 194LP may constitute the first preliminary interlayer insulating film 194P. In an embodiment of the inventive concept, the first preliminary upper interlayer insulating film 194UP may include a low-k dielectric material containing a benzene ring. For example, the first preliminary upper interlayer insulating film 194UP may include a material represented by the following Chemical Formula 1.

[0102] [Chemical Formula 1]

[0103]

[0104] In Chemical Formula 1, R represents an alkyl group, and O—Si— represents Chemical Formula 1 repeatedly connected by an SiO bond to Chemical Formula 1.

[0105] Referring to Figure 11, Next, a plurality of trenches TH penetrating the first preliminary interlayer insulating film 194P may be formed. The plurality of trenches TH may be formed by an etching process. The first preliminary lower interlayer insulating film 194LP and the first preliminary upper interlayer insulating film 194UP may include the same material. Since the first preliminary lower interlayer insulating film 194LP and the first preliminary upper interlayer insulating film 194UP include the same low-k dielectric material, the sidewalls of the trenches TH may be coplanar in a region adjacent to the boundary where the first preliminary lower interlayer insulating film 194LP contacts the first preliminary upper interlayer insulating film 194UP. For example, the sidewalls of the trenches TH may extend as a straight line (or plane) passing through the boundary between the first preliminary lower interlayer insulating film 194LP and the first preliminary upper interlayer insulating film 194UP. The sidewalls of the trenches TH may be located on an inclined plane. Since the first preliminary lower interlayer insulating film 194LP and the first preliminary upper interlayer insulating film 194UP include the same low-k dielectric material, the etching profile at the boundary may be constant.

[0106] Referring to Figure 12 , a preliminary wiring line barrier film 193LP may be conformally formed to cover the inner walls of the plurality of trenches TH and the upper surface of the first preliminary upper interlayer insulating film 194UP. The preliminary wiring line barrier film 193LP may include, for example, titanium (Ti), titanium nitride (TiN), or a combination thereof, but the inventive concept is not limited thereto.

[0107] Next, a preliminary wiring line conductive layer 193CP may be formed to fill the plurality of trenches TH and cover the preliminary wiring line barrier film 193LP. The preliminary wiring line conductive layer 193CP may include, for example, tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or any combination thereof. For example, the preliminary wiring line conductive layer 193CP may include a copper (Cu) film.

[0108] Referring to Figure 13 , a plurality of wiring lines 193 may be formed as follows: removing a part of the preliminary wiring line conductive layer 193CP, a part of the preliminary wiring line barrier film 193LP, and a part of the first preliminary upper interlayer insulating film 194UP. The upper surfaces of the plurality of wiring lines 193 and the first upper interlayer insulating film 194U may be planarized by a planarization process. The planarization process may be, for example, a CMP process. For example, after the planarization process, the upper surfaces of the plurality of wiring lines 193 and the upper surface of the first upper interlayer insulating film 194U may be coplanar.

[0109] Referring to Figure 14, a preliminary interlayer capping layer 196P and a second preliminary interlayer insulating film 198P may be formed on a plurality of wiring lines 193 and a first interlayer insulating film 194. The preliminary interlayer capping layer 196P may include a preliminary lower capping layer 196LP and a preliminary upper capping layer 196UP. The preliminary lower capping layer 196LP, the preliminary upper capping layer 196UP, and the second preliminary interlayer insulating film 198P may be stacked in sequence. In an embodiment of the inventive concept, the preliminary upper capping layer 196UP may include silicon nitride (Si 3 N 4 ), and the preliminary lower capping layer 196LP may include silicon carbonitride (SiCN). In an embodiment of the inventive concept, the second preliminary interlayer insulating film 198P may include, for example, TEOS, PE-TEOS, LD-TEOS, or any combination thereof.

[0110] Since the first lower interlayer insulating film 194L and the first upper interlayer insulating film 194U include the same low-k dielectric material, sidewalls of the plurality of wiring lines 193 may be coplanar in a region adjacent to a boundary where the first lower interlayer insulating film 194L contacts the first upper interlayer insulating film 194U. Since the first lower interlayer insulating film 194L and the first upper interlayer insulating film 194U include the same low-k dielectric material, voids may not be generated in the wiring lines 193 during the formation operation of the wiring lines 193.

[0111] Referring again to Figure 3 , then, a plurality of metal contact holes penetrating the preliminary interlayer capping layer 196P and the second preliminary interlayer insulating film 198P may be formed. The plurality of metal contact holes may be formed by an etching process.

[0112] Then, an upper contact barrier layer 195L conformally covering inner walls of the plurality of metal contact holes may be formed. The upper contact barrier layer 195L may include, for example, titanium (Ti), titanium nitride (TiN), or any combination thereof, but the inventive concept is not limited thereto.

[0113] Then, an upper contact conductive layer 195C may be formed to fill the plurality of metal contact holes and cover the upper contact barrier layer 195L, and a plurality of upper contacts 195 may be formed by polishing upper portions of the upper contact barrier layer 195L and upper portions of the upper contact conductive layer 195C.

[0114] Figure 15 is a cross-sectional view taken along line A-A' of a semiconductor device 20 according to an embodiment of the inventive concept. Figure 2 of the semiconductor device 20.

[0115] Referring to Figure 15 , the semiconductor device 20 according to the inventive concept may include an interlayer insulating film 294 including a single layer.Figure 15 The semiconductor device 20 is substantially the same as Figure 3 the semiconductor device 10, except as follows: Figure 15 the semiconductor device 20 includes a first interlayer insulating film 294 including a single layer instead of the first upper interlayer insulating film 194U and the first lower interlayer insulating film 194L included in Figure 3 the semiconductor device 10, and thus, the description given with reference to Figure 3 is omitted.

[0116] In an embodiment of the inventive concept, the first interlayer insulating film 294 may include a low-k dielectric material including a benzene ring. For example, the first interlayer insulating film 294 may include a material represented by the following Chemical Formula 1.

[0117] [Chemical Formula 1]

[0118]

[0119] In Chemical Formula 1, R represents an alkyl group, and O—Si— represents Chemical Formula 1 repeatedly connected to Chemical Formula 1 through an SiO bond.

[0120] In an embodiment of the inventive concept, the first interlayer insulating film 294 may include a material having a dielectric constant lower than that of the lower insulating film 192. For example, the first interlayer insulating film 294 may include a material having a dielectric constant lower than that of TEOS, PE-TEOS, LD-TEOS, or any combination thereof.

[0121] The first interlayer insulating film 294 includes a low-k dielectric material including a benzene ring, and thus, it is possible to prevent the escape of impurities (e.g., H 2 O, H + ) generated in the interlayer insulating film (e.g., including TEOS) during the manufacturing process of a conventional semiconductor device. If the escape of impurities occurs in the interlayer insulating film, defects may occur in the upper contact, and as a result, the reliability of the semiconductor device may be reduced. The first interlayer insulating film 294 of the semiconductor device 20 of the inventive concept includes a material represented by Chemical Formula 1, and since the material does not generate impurities, the escape phenomenon can be prevented. Since the escape phenomenon of the first interlayer insulating film 294 is prevented, the formation of defects in the upper contact 195 can be prevented, and the productivity and reliability of the semiconductor device 20 can be improved.

[0122] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept defined by the appended claims.

Claims

1. Semiconductor devices, including: a substrate including a memory cell region and a peripheral circuit region, the memory cell region having a first active region and the peripheral circuit region having a second active region; a capacitor structure including a lower electrode connected to the first active region in the memory cell region, an upper electrode surrounding the lower electrode in the memory cell region, and a capacitor dielectric film disposed between the lower electrode and the upper electrode; a lower insulating film provided on the substrate in the memory cell region and the peripheral circuit region and covering the capacitor structure in the memory cell region; a first interlayer insulating film including a first lower interlayer insulating film and a first upper interlayer insulating film sequentially stacked on the lower insulating film; as well as a wiring line provided in the first interlayer insulating film and electrically connected to the capacitor structure, The first upper interlayer insulating film includes a first material including a benzene ring.

2. The semiconductor device according to claim 1, wherein the first material is represented by the following Chemical Formula 1: [Chemical formula 1] In Chemical Formula 1, R represents an alkyl group, and O—Si— represents Chemical Formula 1 repeatedly connected to Chemical Formula 1 through a SiO bond. 3 . The semiconductor device according to claim 1 , wherein the lower insulating film includes a material having a dielectric constant larger than that of the first material. 4 . The semiconductor device according to claim 1 , wherein the first lower interlayer insulating film includes a second material having a dielectric constant different from that of the first material. 5 . The semiconductor device of claim 1 , wherein the first lower interlayer insulating film comprises a low-k dielectric material of the same type as the first material. 6 . The semiconductor device according to claim 1 , wherein the first lower interlayer insulating film and the first material comprise the same material.

7. The semiconductor device according to claim 1, further comprising: an interlayer capping layer, comprising a lower capping layer covering the first interlayer insulating film and an upper capping layer covering the lower capping layer; a second interlayer insulating film covering the interlayer capping layer; as well as An upper contact is electrically connected to the wiring line through the second interlayer insulating film and the interlayer capping layer.

8. The semiconductor device according to claim 7, wherein The lower capping layer includes silicon carbonitride, and The upper capping layer includes silicon nitride.

9. The semiconductor device according to claim 7, wherein the second interlayer insulating film includes a material having a dielectric constant larger than that of the first material.

10. The semiconductor device according to claim 1, wherein side walls of the wiring line are coplanar in a region adjacent to a boundary where the first lower interlayer insulating film and the first upper interlayer insulating film are in contact with each other. 11 . The semiconductor device according to claim 1 , wherein a vertical thickness of the first upper interlayer insulating film is smaller than a vertical thickness of the first lower interlayer insulating film.

12. A method for manufacturing a semiconductor device, the method comprising: providing a substrate including a memory cell region and a peripheral circuit region, the memory cell region having a first active region and the peripheral circuit region having a second active region; forming a capacitor structure connected to the first active region in the memory cell region; forming a lower insulating film covering the substrate and the capacitor structure; forming a plurality of cell contacts penetrating the lower insulating film in the memory cell region and forming a peripheral circuit contact penetrating the lower insulating film in the peripheral circuit region; forming a first interlayer insulating film including a first lower interlayer insulating film and a first upper interlayer insulating film sequentially stacked on the lower insulating film; as well as forming a wiring line provided in the first interlayer insulating film and electrically connected to the capacitor structure, The first upper interlayer insulating film includes a first material including a benzene ring.

13. The method of claim 12, wherein the first material is represented by the following Chemical Formula 1: [Chemical formula 1] In Chemical Formula 1, R represents an alkyl group, and O—Si— represents Chemical Formula 1 repeatedly connected to Chemical Formula 1 through a SiO bond. 14 . The method of claim 12 , wherein forming the lower insulating film comprises forming the lower insulating film using a material having a dielectric constant greater than a dielectric constant of the first material.

15. The method of claim 12, wherein Forming the wiring line includes: forming a trench by etching the first interlayer insulating film; forming a preliminary wiring line covering the trench and the first interlayer insulating film; as well as A portion of the preliminary wiring line and a portion of the first upper interlayer insulating film are removed.

16. The method of claim 12, wherein Forming the first interlayer insulating film includes forming the first lower interlayer insulating film using a second material having a dielectric constant different from that of the first material. 17 . The method of claim 12 , wherein forming the first interlayer insulating film comprises forming the first lower interlayer insulating film using the same material as the first material.

18. The method of claim 12, further comprising: forming an interlayer capping layer including a lower capping layer covering the first interlayer insulating film and an upper capping layer covering the lower capping layer; forming a second interlayer insulating film covering the interlayer capping layer; as well as An upper contact penetrating the second interlayer insulating layer and the interlayer capping layer and electrically connected to the wiring line is formed.

19. The method of claim 12, wherein Forming the wiring line includes forming side walls of the wiring line to be coplanar in a region adjacent to a boundary where the first lower interlayer insulating film and the first upper interlayer insulating film are in contact with each other.

20. Semiconductor devices, including: a substrate including a memory cell region and a peripheral circuit region, the memory cell region having a first active region and the peripheral circuit region having a second active region; a capacitor structure including a lower electrode connected to the first active region in the memory cell region, an upper electrode surrounding the lower electrode in the memory cell region, and a capacitor dielectric film disposed between the lower electrode and the upper electrode; a lower insulating film provided on the substrate in the memory cell region and the peripheral circuit region and covering the capacitor structure in the memory cell region; a first interlayer insulating film disposed on the lower insulating film and including a first upper interlayer insulating film and a first lower interlayer insulating film, the first upper interlayer insulating film including a first material including a benzene ring, the first lower interlayer insulating film including a low-k dielectric material of the same type as the first material; as well as a wiring line provided in the first interlayer insulating film and electrically connected to the capacitor structure, and including coplanar side walls in a region adjacent to a boundary where the first lower interlayer insulating film and the first upper interlayer insulating film are in contact with each other, The first upper interlayer insulating film is represented by the following chemical formula 1: [Chemical formula 1] In Chemical Formula 1, R represents an alkyl group, and O—Si— represents Chemical Formula 1 repeatedly connected to Chemical Formula 1 through a SiO bond.

Images