Back-contact battery with a specific emitter, preparation method and application thereof

Abstract

The present invention belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery with a specific emitter, its preparation method and application. The first semiconductor layer includes a first passivation layer and a first doped silicon layer. The second semiconductor layer includes a first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer sequentially arranged on the back. The doped silicon dielectric layer and the second doped amorphous silicon layer have the same doping type, and the doping type is n-type or p-type. The doped silicon dielectric layer is silicon carbide, silicon oxide, or silicon carbon oxide of the corresponding doping type. The thickness of the doped silicon dielectric layer is 1-3 nm, and the thickness ratio of the doped silicon dielectric layer to the first intrinsic silicon layer and the second doped amorphous silicon layer is 1:(2-5):(3-7). The present invention is beneficial to promoting the rapid separation of photo-generated carriers, reducing recombination, increasing the open-circuit voltage of the battery, thereby improving the battery efficiency and its stability, and effectively reducing the battery efficiency attenuation under harsh environments such as high humidity and high temperature.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery with a specific emitter, a preparation method thereof, and an application thereof. Background Art

[0002] The existing back-contact battery includes an n-type monocrystalline silicon wafer, an intrinsic amorphous silicon layer, and an antireflection layer sequentially arranged on the front surface of the silicon wafer, an intrinsic amorphous silicon layer, a p-type amorphous silicon layer, a transparent conductive film layer, and a metal grid line layer sequentially arranged on the surface of the p-region on the back of the silicon wafer, and an intrinsic amorphous silicon layer, an n-type amorphous silicon layer, a transparent conductive film layer, and a metal grid line layer sequentially arranged on the surface of the n-region on the back of the silicon wafer.

[0003] However, in the above battery structure, due to the weak built-in electric field, there is a disadvantage of poor ability to effectively collect carriers, resulting in a decrease in battery performance such as short-circuit current and open-circuit voltage, poor battery stability, and serious efficiency decay.

[0004] It should be noted that this part of the content of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or well-known technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects that the battery efficiency and battery stability of the existing back-contact battery need to be further improved, and to provide a back-contact battery with a specific emitter, a preparation method thereof, and an application thereof, which is beneficial to promoting the rapid separation of photo-generated carriers, reducing recombination, increasing the open-circuit voltage of the battery, thereby improving the battery efficiency and its stability, and effectively reducing the battery efficiency decay in harsh environments such as high humidity and high temperature.

[0006] To achieve the above purpose, in a first aspect, the present invention provides a back-contact battery with a specific emitter, including a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back of the silicon wafer, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer sequentially arranged on the back, the doping type of the doped silicon dielectric layer is the same as that of the second doped amorphous silicon layer and the doping type is n-type or p-type, the doped silicon dielectric layer is silicon carbide, silicon oxide or silicon carbon oxide of the corresponding doping type; the thickness of the doped silicon dielectric layer is 1-3 nm, and the thickness ratio of the doped silicon dielectric layer, the first intrinsic silicon layer, and the second doped amorphous silicon layer is 1: (2-5): (3-7).

[0007] Preferably, in the present invention, the corresponding doping element of the doped silicon dielectric layer is boron or phosphorus and its corresponding doping element shows an increasing distribution in the direction away from the back of the silicon wafer; and / or, the corresponding doping element in the second doped amorphous silicon layer is boron or phosphorus and its doping concentration of the corresponding doping element shows an increasing distribution in the direction away from the back of the silicon wafer.

[0008] In some preferred embodiments of the present invention, the atomic content ratio of hydrogen element to silicon element in the second doped amorphous silicon layer is (0.05 - 0.33):1, and / or, the hydrogen element content in the second doped amorphous silicon layer by atomic content is 5% - 25%.

[0009] In some preferred embodiments of the present invention, the hydrogen element content in the second doped amorphous silicon layer shows a decreasing distribution in the direction away from the back surface of the silicon wafer.

[0010] In some preferred embodiments of the present invention, the second doped amorphous silicon layer comprises a stack of an initial film layer, an intermediate film layer, and an outermost film layer arranged in sequence or is an initial film layer and an outermost film layer arranged in sequence. The hydrogen element content in the initial film layer by atomic content is 15% - 25%, the hydrogen element content in the intermediate film layer by atomic content is 10% - 15%, and the hydrogen element content in the outermost film layer by atomic content is 5% - 12%.

[0011] In some preferred embodiments of the present invention, the second doped amorphous silicon layer comprises a stack of an initial film layer, an intermediate film layer, and an outermost film layer arranged in sequence. The film thickness ratio of the initial film layer, the intermediate film layer, and the outermost film layer is 1:(1 - 2):(1 - 3).

[0012] Preferably in the present invention, the second doped amorphous silicon layer is an initial film layer and an outermost film layer arranged in sequence, and the film thickness ratio of the initial film layer to the outermost film layer is 1:(1 - 4).

[0013] In some preferred embodiments of the present invention, the corresponding doping element of the doped silicon dielectric layer is boron or phosphorus; wherein, the doping concentration of the corresponding doping element of the doped silicon dielectric layer is 1e18 cm -3 -5e19 cm -3 , and / or, the doping concentration ratio of the corresponding doping element of the doped silicon dielectric layer to the corresponding doping element of the second doped amorphous silicon layer is (0.01 - 0.5):1.

[0014] In some preferred embodiments of the present invention, one of the first doped silicon layer and the second doped amorphous silicon layer is n-type and the other is p-type. The phosphorus doping concentration of the corresponding doping layer of the n-type is 5e19 cm -3 -5e21 cm -3 , and the boron doping concentration of the corresponding doping layer of the p-type is 2e18 cm -3 -8e20 cm -3 .

[0015] In some preferred embodiments of the present invention, the first intrinsic silicon layer is a first intrinsic amorphous silicon layer or a first intrinsic microcrystalline silicon layer. The thickness of the first intrinsic silicon layer is 5 - 12 nm, and the thickness of the second doped amorphous silicon layer is 6 - 15 nm.

[0016] In some preferred embodiments of the present invention, the first passivation layer is a tunneling oxide layer, the first doped silicon layer is a doped polysilicon layer, and the thickness ratio of the tunneling oxide layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(3 - 6):(1 - 2).

[0017] In some preferred embodiments of the present invention, the first passivation layer is an intrinsic silicon layer, the first doped silicon layer is doped amorphous silicon or doped microcrystalline silicon, and the thickness ratio of the intrinsic silicon layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(1 - 1.5):(0.8 - 2.5).

[0018] In some preferred embodiments of the present invention, the back contact battery further includes at least one of the following structures:

[0019] Structure 1: The back contact battery further includes a front passivation layer and an antireflection layer sequentially disposed on the front surface of the silicon wafer. The front passivation layer is a stack of a second intrinsic amorphous silicon layer and a microcrystalline silicon oxide layer sequentially disposed on the front surface or is a second intrinsic amorphous silicon layer. When the front passivation layer is a stack, the thickness ratio of the second intrinsic amorphous silicon layer contained therein to the microcrystalline silicon oxide layer and the first intrinsic silicon layer is 1:(1.5 - 4):(1.1 - 2.5);

[0020] Structure 2: Both ends of the second semiconductor layer extend outward to cover a part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is formed on the back surface of the first semiconductor layer. A second semiconductor opening region is formed between adjacent first semiconductor layers. The second semiconductor opening region and the first semiconductor opening region are arranged at intervals, and the region between them is an interval region; in the interval region, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer;

[0021] Structure 3: The back contact battery further includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and isolation grooves are formed on the conductive film layer.

[0022] In a second aspect, the present invention provides a method for manufacturing a back contact battery with a specific emitter, which is used to manufacture the back contact battery with a specific emitter described in the first aspect. The manufacturing method includes the following steps:

[0023] S1. Provide a double-sided polished silicon wafer;

[0024] S2. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer;

[0025] S3. Perform a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0026] S4. Texturing and cleaning, and then, according to needs, select whether to perform the step of removing the mask layer outside the second semiconductor opening area on the back of the silicon wafer through cleaning;

[0027] S6. Deposit a first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer on the back in sequence to form a second semiconductor layer.

[0028] In some preferred embodiments of the present invention, the doping types of the doped silicon dielectric layer and the second doped amorphous silicon layer are both p-type doping; wherein the preset PECVD film-forming temperatures in the corresponding preparation processes of the doped silicon dielectric layer and the second doped amorphous silicon layer are independently 140 - 250 °C; the deposition conditions for preparing the doped silicon dielectric layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to be 100 - 1000 Pa, the average flow rate of silane to be 10 - 2000 sccm, and the average flow rate of hydrogen to be 20000 - 200000 sccm; the deposition conditions for preparing the second doped amorphous silicon layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to be 40 - 500 Pa, the average flow rate of silane to be 100 - 2000 sccm, and the average flow rate of hydrogen to be 5000 - 100000 sccm.

[0029] In some preferred embodiments of the present invention, the preparation method further includes the following steps:

[0030] S5. After S4, form a front passivation layer on the front of the silicon wafer in sequence, and then perform S6;

[0031] S6. Further include forming a protective sacrificial layer on the outer surface of the second doped amorphous silicon layer, the protective sacrificial layer is a silicon oxide layer and / or a silicon nitride layer, and the thickness of the protective sacrificial layer is 5 - 50 nm; then perform S7;

[0032] S7. Form an antireflection layer on the front passivation layer on the front of the silicon wafer;

[0033] S8. Perform a second etching opening on a part of the second semiconductor layer on the back of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area; then perform cleaning, and remove the protective sacrificial layer during the cleaning process;

[0034] S9. Deposit a conductive film layer on the back obtained in S8;

[0035] S10. Perform a third etching opening on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form an isolation groove;

[0036] S11. Form metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located respectively.

[0037] In a third aspect, the present invention provides a battery assembly, which includes the back-contact battery with a specific emitter described in the first aspect, or includes a back-contact battery prepared by the preparation method of the back-contact battery with a specific emitter described in the second aspect.

[0038] Beneficial effects:

[0039] Through the above technical solutions, the present invention particularly uses a specific emitter formed by including a specific first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer as the second semiconductor layer. The doped silicon dielectric layer is silicon carbide, silicon oxide, or silicon oxycarbide of a corresponding doping type. Since the doped silicon dielectric layer with a specific composition has a larger optical bandgap than the second doped amorphous silicon layer, it is beneficial to form a larger energy band bending at the pn junction interface to enhance the built-in electric field, and further beneficial to promoting the rapid separation of photo-generated carriers, reducing recombination, increasing the open-circuit voltage of the battery, thereby improving the battery efficiency and its stability, and effectively reducing the attenuation of the battery efficiency in harsh environments such as high humidity and heat. Among them, controlling the thickness ratio of the doped silicon dielectric layer to the first intrinsic silicon layer and the second doped amorphous silicon layer within an appropriate range, and cooperating with controlling an appropriately thin doped silicon dielectric layer, can provide good interface passivation and is more conducive to effectively separating photo-generated carriers.

[0040] In a preferred embodiment of the present invention, the specific second semiconductor layer cooperates with controlling the hydrogen element content of the second doped amorphous silicon layer to be distributed in a decreasing manner along the direction away from the back surface of the silicon wafer, which can reduce the density of defect states while improving the compactness of the thin film, and is more conducive to improving the reliability and stability of the back-contact battery. Description of the drawings

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 It is a schematic structural diagram of a specific embodiment of the back-contact battery of the present invention.

[0043] Description of the reference numerals

[0044] 101 - silicon wafer; 201 - tunneling oxide layer; 202 - n-type polysilicon layer; 401 - first intrinsic amorphous silicon layer; 501 - second intrinsic amorphous silicon layer; 601 - p-type doped silicon carbide; 602 - p-type amorphous silicon layer; 701 - antireflection layer; 801 - transparent conductive film layer; 901 - metal electrode. Specific embodiments

[0045] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0046] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0047] The endpoints and any values of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values should be understood to include values close to these ranges. For numerical ranges, the endpoint values of each range, the endpoint values of each range and the individual point values, and the individual point values can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0048] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0049] The hydrogen content in the film layer of the present invention is obtained by Fourier infrared spectroscopy.

[0050] In a first aspect, the present invention provides a back-contact battery with a specific emitter, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, the first semiconductor layer comprising a first passivation layer and a first doped silicon layer, the second semiconductor layer comprising a first intrinsic silicon layer, a doped silicon dielectric layer and a second doped amorphous silicon layer sequentially arranged on the back side, the doped silicon dielectric layer and the second doped amorphous silicon layer having the same doping type and being n-type or p-type, the doped silicon dielectric layer being silicon carbide, silicon oxide or silicon oxycarbide of the corresponding doping type; the thickness of the doped silicon dielectric layer is 1-3 nm, and the ratio of the thickness of the doped silicon dielectric layer to the first intrinsic silicon layer and the second doped amorphous silicon layer is 1:(2-5):(3-7).

[0051] The doping type of the doped silicon dielectric layer is the same as that of the second doped amorphous silicon layer and is n-type or p-type, which means that when the second doped amorphous silicon layer is n-type, the doped silicon dielectric layer is also n-type, and when the second doped amorphous silicon layer is p-type, the doped silicon dielectric layer is also p-type. The doped silicon dielectric layer being silicon carbide, silicon oxide or silicon oxycarbide of the corresponding doping type means that if the doped silicon dielectric layer is n-type, the doped silicon dielectric layer is n-type doped silicon carbide, n-type doped silicon oxide or n-type doped silicon oxycarbide; if the doped silicon dielectric layer is p-type, the doped silicon dielectric layer is p-type doped silicon carbide, p-type doped silicon oxide or p-type doped silicon oxycarbide.

[0052] In the present invention, one of the first doped silicon layer and the second doped amorphous silicon layer is n-type and the other is p-type. In some preferred embodiments of the present invention, among the first doped silicon layer and the second doped amorphous silicon layer, the phosphorus doping concentration of the corresponding doped layer of the n-type is 5e19 cm -3 -5e21 cm -3 , and the boron doping concentration of the corresponding doped layer of the p-type is 2e18 cm -3 -8e20 cm -3 . It can be understood that if the first doped silicon layer is n-type, the corresponding doped layer of the n-type is the first doped silicon layer.

[0053] In some preferred embodiments of the present invention, the atomic content ratio of hydrogen element to silicon element in the second doped amorphous silicon layer is (0.05 - 0.33):1, preferably (0.05 - 0.15):1. Using the second doped amorphous silicon layer with an appropriate silicon-hydrogen content ratio is more conducive to balancing the passivation effect and conductivity of the film layer and improving the stability of the film layer.

[0054] Preferably in the present invention, the hydrogen element content in the second doped amorphous silicon layer is 5% - 25% by atomic content, more preferably 5% - 20%, and further preferably 8% - 17%. Using the second doped amorphous silicon layer with an appropriate hydrogen element content, hydrogen can passivate the dangling bonds in the second doped amorphous silicon layer, reduce the density of defect states, shift the Fermi level towards the valence band top, and thereby improve the hole mobility and conductivity of the second doped amorphous silicon layer; moreover, when the hydrogen element content is within an appropriate range, it can effectively avoid structural defects such as microvoids in the amorphous silicon thin film, the second doped amorphous silicon layer has good film compactness, so the film has good acid and alkali resistance and is not easily damaged during the corresponding preparation process (such as being cleaned with chemical solutions in subsequent patterning processes), thus being conducive to maintaining a high battery efficiency.

[0055] In some preferred embodiments of the present invention, the hydrogen element content of the second doped amorphous silicon layer shows a decreasing distribution in the direction away from the back surface of the silicon wafer, which can reduce the density of defect states while improving the compactness of the thin film, and is more conducive to enhancing the reliability and stability of the back contact battery.

[0056] In some more preferred embodiments of the present invention, the second doped amorphous silicon layer comprises a stack of an initial film layer, an intermediate film layer, and an outermost film layer arranged in sequence or is an initial film layer and an outermost film layer arranged in sequence. The hydrogen element content of the initial film layer in terms of atomic content is 15% - 25%, preferably 15% - 24%; the hydrogen element content of the intermediate film layer in terms of atomic content is 10% - 15%, preferably 10% - 14%; the hydrogen element content of the outermost film layer in terms of atomic content is 5% - 12%, preferably 5% - 9%. In a preferred embodiment of the present invention, the initial film layer having a suitably high hydrogen element content is conducive to forming a more stable interface and helps to reduce the interface state density; the outermost film layer having a suitably low hydrogen element content is conducive to increasing the effective doping concentration and the film denseness. Since patterning needs to be performed on the film during the preparation of the back contact battery, the improvement of the film denseness can reduce the influence of the chemical solution during the patterning process of the back contact battery, which is conducive to maintaining the quality of the film and further conducive to improving the stability and reliability of the battery.

[0057] In some preferred embodiments of the present invention, the second doped amorphous silicon layer comprises a stack of an initial film layer, an intermediate film layer, and an outermost film layer arranged in sequence. The film thickness ratio of the initial film layer, the intermediate film layer, and the outermost film layer is 1: (1 - 2): (1 - 3), preferably 1: (1 - 2): (1.5 - 3). Adopting this preferred embodiment is more conducive to reducing the interface and bulk defect state density and reducing the microvoids in the film layer, thereby enhancing the stability of the film layer.

[0058] In some preferred embodiments of the present invention, the second doped amorphous silicon layer is an initial film layer and an outermost film layer arranged in sequence. The film thickness ratio of the initial film layer and the outermost film layer is 1: (1 - 4), preferably 1: (1.5 - 4).

[0059] Preferably in the present invention, the corresponding doping element in the second doped amorphous silicon layer is boron or phosphorus and the doping concentration of its corresponding doping element shows an increasing distribution in the direction away from the back surface of the silicon wafer, which is more conducive to improving the effective transport of carriers, thereby enhancing the battery efficiency and its stability.

[0060] Preferably in the present invention, the corresponding doping element of the doped silicon dielectric layer is boron or phosphorus and its corresponding doping element shows an increasing distribution in the direction away from the back surface of the silicon wafer, which is more conducive to promoting the separation and transport of carriers.

[0061] Among them, the corresponding doping element of the doped silicon dielectric layer is boron or phosphorus, which respectively corresponds to p-type or n-type.

[0062] In some preferred embodiments of the present invention, the doping concentration of the corresponding doping element of the doped silicon dielectric layer is 1e18 cm -3 - 5e19 cm -3 、preferably 1e18 cm -3 - 3e19 cm-3 , which is more conducive to forming a gradient energy band structure, promoting the transfer of holes to the electrode, and at the same time blocking the reverse diffusion of electrons.

[0063] Preferably, in the present invention, the doping concentration ratio of the corresponding doping element of the doped silicon dielectric layer to the corresponding doping element of the second doped amorphous silicon layer is (0.01 - 0.5):1, preferably (0.02 - 0.5):1. Adopting this preferred scheme is more conducive to reducing lattice distortion, reducing the contact barrier with the transparent conductive film layer, and reducing carrier transport loss. It should be noted that the doping concentration ratio of the corresponding doping element of the doped silicon dielectric layer to the corresponding doping element of the second doped amorphous silicon layer in the present invention refers to that the ratio of the maximum doping concentration of the corresponding doping element of the doped silicon dielectric layer to the maximum doping concentration of the corresponding doping element of the second doped amorphous silicon layer is within the above range, and the ratio of the minimum doping concentration of the corresponding doping element of the doped silicon dielectric layer to the minimum doping concentration of the corresponding doping element of the second doped amorphous silicon layer is within the above range.

[0064] In some preferred embodiments of the present invention, the first intrinsic silicon layer is a first intrinsic amorphous silicon layer or a first intrinsic microcrystalline silicon layer, and the former is more preferred.

[0065] Further preferably, the thickness of the first intrinsic silicon layer is 5 - 12 nm.

[0066] Preferably, the thickness of the second doped amorphous silicon layer is 6 - 15 nm.

[0067] In some preferred embodiments of the present invention, the first passivation layer is a tunneling oxide layer, and the first doped silicon layer is a doped polysilicon layer. Adopting the combined passivation structure and the specific emitter of the present application as the second semiconductor layer is more conducive to improving the passivation ability and stability of the back contact battery.

[0068] Further preferably, the thickness ratio of the tunneling oxide layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(3 - 6):(1 - 2), preferably 1:(4 - 6):(1.1 - 2), which is more conducive to the effective separation of electrons and holes, thereby improving the battery efficiency and its stability.

[0069] The thickness and doping concentration of the doped polysilicon layer in the present invention can refer to the prior art respectively. For example, the thickness of the doped polysilicon layer can be 30 - 250 nm, and the doping concentration is greater than 5e18 cm -3 .

[0070] In some preferred embodiments of the present invention, the first passivation layer is an intrinsic silicon layer, and the first doped silicon layer is doped amorphous silicon or doped microcrystalline silicon. The intrinsic silicon layer is intrinsic amorphous silicon or intrinsic microcrystalline silicon.

[0071] Further preferably, the thickness ratio of the intrinsic silicon layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(1 - 1.5):(0.8 - 2.5), which is more conducive to balancing surface passivation and conductivity, and improving the final conversion efficiency of the battery.

[0072] In some preferred embodiments of the present invention, the back contact battery further includes a front passivation layer and an antireflection layer sequentially disposed on the front surface of the silicon wafer.

[0073] Further preferably, the front passivation layer is a stack of a second intrinsic amorphous silicon layer and a microcrystalline silicon oxide layer sequentially disposed on the front surface or is a second intrinsic amorphous silicon layer. Adopting this specific front passivation layer and cooperating with the specific back passivation structure of the present invention is more conducive to improving the effective utilization rate of photo-generated carriers.

[0074] Further preferably, when the front passivation layer is a stack, the thickness ratio of the second intrinsic amorphous silicon layer, the microcrystalline silicon oxide layer, and the first intrinsic silicon layer contained therein is 1:(1.5 - 4):(1.1 - 2.5), which is more conducive to improving surface passivation and carrier transport ability.

[0075] In some preferred embodiments of the present invention, both ends of the second semiconductor layer extend outward to cover a part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is formed on the back surface of the first semiconductor layer. A second semiconductor opening area is formed between adjacent first semiconductor layers. The second semiconductor opening area and the first semiconductor opening area are arranged at intervals, and the area between them is an interval area.

[0076] In the present invention, in the interval area, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer.

[0077] In some preferred embodiments of the present invention, the back contact battery further includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer. An isolation groove is formed on the conductive film layer to prevent short circuit between the first semiconductor layer and the second semiconductor layer. The isolation groove is located in the area where the interval area is located. It can be understood that the metal electrode is disposed on the outer surface of the conductive film layer corresponding to the second semiconductor opening area and the first semiconductor opening area respectively. The settings of the conductive film layer, the metal electrode, and the isolation groove can refer to the prior art and can all be used in the present invention, and will not be elaborated here.

[0078] In a second aspect, the present invention provides a method for manufacturing a back contact battery with a specific emitter, which is used to manufacture the back contact battery with a specific emitter described in the first aspect. The manufacturing method includes the following steps:

[0079] S1. Provide a double-sided polished silicon wafer;

[0080] S2. Form a first semiconductor layer and a mask layer on the back side of the silicon wafer in sequence.

[0081] S3. Conduct a first etching opening on the back side obtained in S2 to form a second semiconductor opening region.

[0082] S4. Perform texturing cleaning, and then select whether to perform the step of removing the mask layer outside the second semiconductor opening region on the back side of the silicon wafer according to needs.

[0083] S6. Deposit a first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer on the back side in sequence to form a second semiconductor layer.

[0084] In some preferred embodiments of the present invention, the doping types of both the doped silicon dielectric layer and the second doped amorphous silicon layer are p-type doping.

[0085] Preferably, the preset PECVD film-forming temperature in the corresponding preparation processes of the doped silicon dielectric layer and the second doped amorphous silicon layer is independently 140 - 250 °C. The suitable film-forming temperature is more conducive to forming a doped and uniform corresponding doped silicon layer with a more stable Si - Si network structure, which is beneficial to improving the battery stability.

[0086] Preferably in the present invention, the deposition conditions for preparing the doped silicon dielectric layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to be 100 - 1000 Pa, the average flow rate of silane to be 10 - 2000 sccm, and the average flow rate of hydrogen to be 20000 - 200000 sccm. The required doping gas source is determined according to the doping type and type of the doped silicon dielectric layer, as long as a doped film layer with the target doping concentration can be obtained; for example, when the doping type of the doped silicon dielectric layer is p-type and the type of the doped silicon dielectric layer is silicon carbide, the required doping gas source can be diborane and methane, the average flow rate of diborane is 1 - 50 sccm, and the average flow rate of methane is 5 - 200 sccm.

[0087] Preferably in the present invention, the deposition conditions for preparing the second doped amorphous silicon layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to be 40 - 500 Pa, the average flow rate of silane to be 100 - 2000 sccm, and the average flow rate of hydrogen to be 5000 - 100000 sccm. The required doping gas source is determined according to the doping type and type of the doped silicon dielectric layer, as long as a doped film layer with the target doping concentration can be obtained; for example, when the doping type of the second doped amorphous silicon layer is p-type, the required doping gas source can include diborane, and the average flow rate of diborane is 10 - 200 sccm. Among them, the average flow rate of the doping gas source and / or the average flow rate of hydrogen can be adjusted to adjust the trend of change in the content of the doping element and / or hydrogen.

[0088] In step S4 of the present invention, the texturing cleaning can remove the residual mask layer and the first semiconductor layer in the second semiconductor opening area, and at the same time form a textured surface on the front side of the silicon wafer and in the second semiconductor opening area.

[0089] In some preferred embodiments of the present invention, the preparation method further includes the following steps: S5, after S4, a front passivation layer is sequentially formed on the front side of the silicon wafer, and then S6 is carried out.

[0090] In some preferred embodiments of the present invention, the preparation method further includes the following steps: S6 further includes forming a protective sacrificial layer on the outer surface of the second doped amorphous silicon layer, and removing the protective sacrificial layer during the cleaning process of S7. Further preferably, the protective sacrificial layer is a silicon oxide layer and / or a silicon nitride layer. Further preferably, the thickness of the protective sacrificial layer is 5 - 50 nm. The present invention provides the protective sacrificial layer, which can reduce the influence of the second doped amorphous silicon layer during the subsequent chemical solution cleaning in the battery preparation and prevent it from being damaged, thereby being more conducive to maintaining the battery efficiency.

[0091] In some preferred embodiments of the present invention, the preparation method further includes the following steps:

[0092] S7, forming an antireflection layer on the front side of the silicon wafer;

[0093] S8, performing a second etching opening on a part of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area; then performing cleaning, and removing the protective sacrificial layer during the cleaning process;

[0094] S9, depositing a conductive film layer on the back obtained in S8;

[0095] S10, performing a third etching opening on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form an isolation groove;

[0096] S11, respectively forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located.

[0097] In a third aspect, the present invention provides a battery assembly, which includes the back contact battery having a specific emitter described in the first aspect, or includes a back contact battery prepared by the preparation method of the back contact battery having a specific emitter described in the second aspect.

[0098] The following details the embodiments of the present invention, which are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention.

[0099] Example 1

[0100] A back contact battery, the structure is as Figure 1As shown, it includes an n-type silicon wafer 101, a first semiconductor layer and a second semiconductor layer alternately arranged on the back surface of the silicon wafer 101. The second semiconductor layer includes a first intrinsic silicon layer (i.e., the first intrinsic amorphous silicon layer 401), a doped silicon dielectric layer, and a second doped amorphous silicon layer (p-type amorphous silicon layer 602) sequentially arranged on the back surface. The doped silicon dielectric layer is p-type doped silicon carbide 601. It is specifically prepared by the following method:

[0101] S1. Provide a double-sided polished silicon wafer 101;

[0102] S2. Form a first semiconductor layer and a mask layer on the back surface of the silicon wafer 101 in sequence; the first semiconductor layer includes a tunneling oxide layer 201 with a thickness of 1.5 nm and a first doped silicon layer (n-type polysilicon layer 202 with a thickness of 120 nm and a phosphorus doping concentration of 5e20 cm -3 );

[0103] S3. Perform a first etching opening on the back surface obtained in S2 to form a second semiconductor opening area;

[0104] S4. Texturing and cleaning, remove the residual mask layer and the first semiconductor layer in the second semiconductor opening area, and at the same time form a textured surface on the front surface of the silicon wafer 101 and the second semiconductor opening area, and then remove the mask layer;

[0105] S5. Form a front passivation layer on the front surface of the silicon wafer 101; the front passivation layer is a second intrinsic amorphous silicon layer 501 with a thickness of 6 nm.

[0106] S6. Deposit a first intrinsic silicon layer (i.e., intrinsic amorphous silicon layer) with a thickness of 7.5 nm, a doped silicon dielectric layer, and a second doped amorphous silicon layer (p-type amorphous silicon layer 602) with a thickness of 10 nm on the back surface in sequence to form a second semiconductor layer. After calculation, the thickness ratio of the second intrinsic amorphous silicon layer 501 to the first intrinsic silicon layer is 1:1.25. The doped silicon dielectric layer is p-type doped silicon carbide 601 with a thickness of 2 nm. The specific method for depositing p-type doped silicon carbide 601 is as follows: first preset the PECVD film-forming temperature to 200 °C, then introduce a mixed gas of silane, diborane, hydrogen, and methane, the reaction gas pressure is 600 Pa, the average flow rate of silane is 70 sccm, the average flow rate of diborane is 1.4 sccm; the average flow rate of methane is 20 sccm, and the average flow rate of hydrogen is 50000 sccm. The boron doping concentration of p-type doped silicon carbide 601 is 2e18 cm -3 -2e19 cm -3 and shows an increasing distribution in the direction away from the back surface of the silicon wafer 101. The boron doping concentration is controlled to change in an increasing manner by controlling the flow rate change of diborane. After conversion, the thickness ratio of the tunneling oxide layer 201 to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:5:1.3.

[0107] The specific method for depositing the p-type amorphous silicon layer 602 is as follows: First, preset the PECVD film-forming temperature at 210 °C, then introduce a mixed gas of silane, diborane, and hydrogen. The reaction gas pressure is 300 Pa, the average flow rate of silane is 400 sccm, the average flow rate of diborane is 20 sccm, and the average flow rate of hydrogen is 20,000 sccm. It is divided into an initial film layer, an intermediate film layer, and an outermost film layer arranged in sequence. Control the hydrogen content of the initial film layer at 20%, the hydrogen content of the intermediate layer at 13%, and the hydrogen content of the outermost layer at 8%, where the hydrogen content is calculated by atomic content. The total film thickness is 10 nm, and the film thickness ratio of the initial film layer, the intermediate film layer, and the outermost film layer is 1:1:2. The boron doping concentration of the p-type amorphous silicon layer 602 is 4e18 cm -3 -8e20 cm -3 and shows an increasing distribution in the direction away from the back surface of the silicon wafer 101. After conversion, the ratio of the boron doping concentration of the doped silicon dielectric layer to the second doped amorphous silicon layer is (0.025 - 0.5):1. Through Fourier transform infrared spectroscopy (FT-IR) testing, in the direction away from the back surface of the silicon wafer, the atomic content ratio of hydrogen and silicon elements in the p-type amorphous silicon layer 602 is (0.10 - 0.14):1.

[0108] S7. Form an antireflection layer 701 on the front surface of the silicon wafer obtained in S6;

[0109] S8. Perform a second etching opening on a part of the second semiconductor layer on the back surface of the silicon wafer 101 to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area; then perform cleaning;

[0110] S9. Deposit a transparent conductive film layer 801 on the back surface obtained in S8;

[0111] S10. Perform a third etching opening on a part of the transparent conductive film layer 801 located between the first semiconductor opening area and the second semiconductor opening area to form an isolation groove;

[0112] S11. Form metal electrodes 901 on the outer surfaces of the corresponding transparent conductive film layer 801 in the areas where the first semiconductor opening area and the second semiconductor opening area are located.

[0113] Example 2

[0114] It is carried out with reference to Example 1, the difference being that the doped silicon dielectric layer is p-type doped silicon oxide with the same thickness and boron doping concentration. The specific method for depositing p-type doped silicon oxide: First, preset the PECVD film-forming temperature at 210 °C, then introduce a mixed gas of silane, diborane, hydrogen, and carbon dioxide. The reaction gas pressure is 500 Pa, the average flow rate of silane is 85 sccm, the average flow rate of diborane is 3 sccm, the average flow rate of carbon dioxide is 50 sccm, and the average flow rate of hydrogen is 50,000 sccm, and deposit to the target thickness and target doping concentration.

[0115] Example 3

[0116] It is carried out with reference to Example 1, except that the doped silicon dielectric layer is a p-type doped silicon carbon oxide, and the thickness and boron doping concentration remain unchanged. The specific method for depositing the p-type doped silicon carbon oxide: first preset the PECVD film-forming temperature at 200 °C, then introduce a mixed gas of silane, diborane, hydrogen, methane and carbon dioxide, the reaction gas pressure is 600 Pa, the average flow rate of silane is 90 sccm, the average flow rate of diborane is 2.5 sccm; the average flow rate of methane is 20 sccm, the average flow rate of carbon dioxide is 60 sccm, and the average flow rate of hydrogen is 50000 sccm, and deposit to the target thickness and target doping concentration.

[0117] Example 4

[0118] It is carried out with reference to Example 1, except that the hydrogen element content in the second doped amorphous silicon layer is adjusted: the hydrogen element content in the initial film layer is 25% in terms of atomic content, the hydrogen element content in the intermediate film layer is 15% in terms of atomic content, and the hydrogen element content in the outermost film layer is 10% in terms of atomic content; however, the decreasing distribution trend of the hydrogen element content remains unchanged, and the film thickness ratio of the initial film layer, the intermediate film layer and the outermost film layer remains unchanged; the specific modified process parameters corresponding to the preparation process are: the reaction gas pressure is 200 Pa, and the average flow rate of silane is 500 sccm. After the same test, in the direction away from the back surface of the silicon wafer, the atomic content ratio of hydrogen element and silicon element in the second doped amorphous silicon layer is (0.12 - 0.16):1.

[0119] Example 5

[0120] It is carried out with reference to Example 1, except that the intermediate film layer is not formed in the second doped amorphous silicon layer, so it is composed of the initial film layer and the outermost film layer.

[0121] Example 6

[0122] It is carried out with reference to Example 1, except that the doping concentration of the corresponding doping element in the doped silicon dielectric layer is adjusted to 5e18 cm -3 -4e19 cm -3 , and after conversion, the ratio of the boron doping concentration of the doped silicon dielectric layer to the second doped amorphous silicon layer is (0.04 - 0.5):1.

[0123] Example 7

[0124] It is carried out with reference to Example 1, except that in S6, a protective sacrificial layer is further formed on the outer surface of the second doped amorphous silicon layer. The protective sacrificial layer is a silicon oxide layer, the thickness of the protective sacrificial layer is 10 nm, and the protective sacrificial layer is removed during the cleaning process in S7.

[0125] Comparative Example 1

[0126] It was carried out with reference to Example 1, except that the doped silicon dielectric layer was not provided.

[0127] Comparative Example 2

[0128] It was carried out with reference to Example 1, except that the thickness of the doped silicon dielectric layer was 4 nm. After conversion, the thickness ratio of the doped silicon dielectric layer to the first intrinsic amorphous silicon layer and the second doped amorphous silicon layer was 1:1.875:2.5.

[0129] Test Example

[0130] The back-contact batteries obtained from the above examples and comparative examples were subjected to the same performance tests, and the results are shown in Table 1. Among them, the efficiency decay ratio after damp heat test refers to testing the back-contact battery in a damp heat environment at a humidity of 85% and a temperature of 85 °C for 48 h to obtain the battery efficiency after the damp heat test, and then calculating the efficiency decay ratio before and after the damp heat test: (battery efficiency before damp heat test - battery efficiency after damp heat test) / battery efficiency before damp heat test. The battery efficiency in Table 1 refers to the battery efficiency before damp heat test. And among them, each performance index of each example and comparative example was respectively converted with reference to Comparative Example 1. The data of Comparative Example 1 was the normalization reference of 1.000, and other examples were converted based on Comparative Example 1. For example, the efficiency decay ratio before and after damp heat test of Example 1 / the efficiency decay ratio before and after damp heat test of Comparative Example 1 was 0.619.

[0131] Table 1

[0132]

[0133] From the above results, it can be seen that compared with the comparative examples, adopting the embodiment scheme of the present invention is beneficial to promoting the rapid separation of photo-generated carriers, reducing recombination, increasing the open-circuit voltage of the battery, thereby increasing the battery efficiency, reducing the efficiency decay before and after damp heat test, and improving the reliability and stability of the back-contact battery.

[0134] Furthermore, according to Example 1 and Examples 2-7, it can be seen that adopting the preferred scheme of the present invention is more beneficial to improving the battery efficiency, reducing the efficiency decay before and after damp heat test, and further improving the reliability and stability.

[0135] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited thereto. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, including any other suitable combination of each technical feature. These simple modifications and combinations should also be regarded as the content disclosed by the present invention and fall within the protection scope of the present invention.

Claims

1. A back-contact battery with a specific emitter, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back surface of the silicon wafer, the first semiconductor layer comprising a first passivation layer and a first doped silicon layer, characterized in that, The second semiconductor layer includes a first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer that are sequentially disposed on the back surface. The doped silicon dielectric layer and the second doped amorphous silicon layer have the same doping type, and the doping type is n-type or p-type. The doped silicon dielectric layer is silicon carbide, silicon oxide, or silicon oxycarbide of the corresponding doping type. The thickness of the doped silicon dielectric layer is 1 - 3 nm, and the thickness ratio of the doped silicon dielectric layer to the first intrinsic silicon layer and the second doped amorphous silicon layer is 1:(2 - 5):(3 - 7). The corresponding doping element of the doped silicon dielectric layer is boron or phosphorus, and the doping concentration of the corresponding doping element is distributed in an increasing manner in the direction away from the back surface of the silicon wafer. The hydrogen element content in the second doped amorphous silicon layer is distributed in a decreasing manner in the direction away from the back surface of the silicon wafer.

2. The back contact battery with a specific emitter according to claim 1, characterized in that, The corresponding doping element in the second doped amorphous silicon layer is boron or phosphorus, and the doping concentration of the corresponding doping element is distributed in an increasing manner in the direction away from the back surface of the silicon wafer.

3. The back-contact battery with a specific emitter according to claim 1 or 2, characterized in that The atomic content ratio of hydrogen element and silicon element in the second doped amorphous silicon layer is (0.05 - 0.33):1, and the hydrogen element content by atomic content in the second doped amorphous silicon layer is 5% - 25%.

4. The back-contact cell having a specific emitter according to claim 3, characterized in that, The second doped amorphous silicon layer includes a stack of an initial film layer, an intermediate film layer, and an outermost film layer that are sequentially disposed, or is an initial film layer and an outermost film layer that are sequentially disposed. The hydrogen element content by atomic content in the initial film layer is 15% - 25%, the hydrogen element content by atomic content in the intermediate film layer is 10% - 15%, and the hydrogen element content by atomic content in the outermost film layer is 5% - 12%.

5. The back contact battery having a specific emitter according to claim 4, characterized in that, The second doped amorphous silicon layer includes a stack of an initial film layer, an intermediate film layer, and an outermost film layer that are sequentially disposed. The film thickness ratio of the initial film layer, the intermediate film layer, and the outermost film layer is 1:(1 - 2):(1 - 3); Or, The second doped amorphous silicon layer is an initial film layer and an outermost film layer that are sequentially disposed. The film thickness ratio of the initial film layer and the outermost film layer is 1:(1 - 4).

6. The back contact battery with a specific emitter according to claim 1, characterized in that, The corresponding doping element of the doped silicon dielectric layer is boron or phosphorus; wherein, The doping concentration of the corresponding doping element in the doped silicon dielectric layer is 1e18 cm -3 -5e19 cm -3 , and / or, the ratio of the doping concentration of the corresponding doping element in the doped silicon dielectric layer to the doping concentration of the corresponding doping element in the second doped amorphous silicon layer is (0.01 - 0.5):

1.

7. The back contact cell with a specific emitter according to claim 1 or 6, characterized in that, One of the first doped silicon layer and the second doped amorphous silicon layer is n-type and the other is p-type. The phosphorus doping concentration of the corresponding doped layer of the n-type is 5e19 cm -3 -5e21 cm -3 , and the boron doping concentration of the corresponding doped layer of the p-type is 2e18 cm -3 -8e20 cm -3 ; And / or, The first intrinsic silicon layer is a first intrinsic amorphous silicon layer or a first intrinsic microcrystalline silicon layer. The thickness of the first intrinsic silicon layer is 5 - 12 nm, and the thickness of the second doped amorphous silicon layer is 6 - 15 nm.

8. The back-contact battery with a specific emitter according to claim 1, characterized in that, The first passivation layer is a tunneling oxide layer, and the first doped silicon layer is a doped polysilicon layer. The thickness ratio of the tunneling oxide layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(3 - 6):(1 - 2).

9. The back-contact battery with a specific emitter according to claim 1, characterized in that, The first passivation layer is an intrinsic silicon layer, and the first doped silicon layer is doped amorphous silicon or doped microcrystalline silicon. The thickness ratio of the intrinsic silicon layer to the first intrinsic silicon layer and the doped silicon dielectric layer is 1:(1 - 1.5):(0.8 - 2.5).

10. The back contact battery with a specific emitter according to claim 1, characterized in that, The back contact cell further includes at least one of the following structures: Structure 1: The back contact cell further includes a front passivation layer and an antireflection layer that are sequentially disposed on the front surface of the silicon wafer. The front passivation layer is a stack of a second intrinsic amorphous silicon layer and a microcrystalline silicon oxide layer that are sequentially disposed on the front surface, or is a second intrinsic amorphous silicon layer. When the front passivation layer is a stack, the thickness ratio of the second intrinsic amorphous silicon layer contained therein to the microcrystalline silicon oxide layer and the first intrinsic silicon layer is 1:(1.5 - 4):(1.1 - 2.5); Structure 2: Both ends of the second semiconductor layer extend outward to cover part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening area that does not cover the second semiconductor layer is formed on the back surface of the first semiconductor layer. A second semiconductor opening area is formed between adjacent first semiconductor layers. The second semiconductor opening area and the first semiconductor opening area are arranged at intervals, and the area between them is the interval area; in the interval area, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer; Structure 3: The back contact battery further includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and isolation grooves are formed on the conductive film layer.

11. A method for preparing a back-contact battery with a specific emitter, characterized in that, It is used to prepare the back contact battery with a specific emitter as described in any one of claims 1-10, and the preparation method includes the following steps: S1. Provide a double-sided polished silicon wafer; S2. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer; S3. Perform the first etching opening on the back surface obtained in S2 to form a second semiconductor opening area; S4. Texturing and cleaning, and then select whether to perform the step of removing the mask layer outside the second semiconductor opening area on the back surface of the silicon wafer according to needs; S6. Sequentially deposit a first intrinsic silicon layer, a doped silicon dielectric layer, and a second doped amorphous silicon layer on the back surface to form a second semiconductor layer.

12. The preparation method of the back-contact battery with a specific emitter according to claim 11, characterized in that, Both the doped silicon dielectric layer and the second doped amorphous silicon layer are doped with p-type doping; wherein the preset PECVD film formation temperature in the corresponding preparation processes of the doped silicon dielectric layer and the second doped amorphous silicon layer is independently 140-250 °C; The deposition conditions for preparing the doped silicon dielectric layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to be 100-1000 Pa, the average flow rate of silane to be 10-2000 sccm, and the average flow rate of hydrogen to be 20000-200000 sccm; the deposition conditions for preparing the second doped amorphous silicon layer include: introducing silane, the required doping gas source, and hydrogen, controlling the reaction gas pressure to be 40-500 Pa, the average flow rate of silane to be 100-2000 sccm, and the average flow rate of hydrogen to be 5000-100000 sccm; And / or, the preparation method further includes the following steps: S5. After S4, sequentially form a front passivation layer on the front surface of the silicon wafer, and then perform S6; S6. Further include forming a protective sacrificial layer on the outer surface of the second doped amorphous silicon layer. The protective sacrificial layer is a silicon oxide layer and / or a silicon nitride layer, and the thickness of the protective sacrificial layer is 5-50 nm; then perform S7; S7. Form an antireflection layer on the front passivation layer on the front surface of the silicon wafer; S8. Perform a second etching opening on a part of the second semiconductor layer on the back surface of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area; then perform cleaning, and remove the protective sacrificial layer during the cleaning process; S9. Deposit a conductive film layer on the back surface obtained in S8; S10. Perform a third etching opening on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form isolation grooves; S11. Metal electrodes are respectively formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located.

13. A battery assembly, characterized in that, It includes a back contact cell having a specific emitter as described in any one of claims 1-10, or a back contact cell obtained by the preparation method of a back contact cell having a specific emitter as described in claim 11 or 12.

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