A double-sided TOPCon cell based on front-side selective doping and its manufacturing method

Abstract

The present invention relates to the technical field of solar cell, and in particular to a double-sided TOPCon cell based on front-side selective doping and a preparation method thereof. The cell includes an N-type silicon wafer, and the silicon wafer includes a relative front side and a back side; the front side is divided into a contact area and a non-contact area. The contact area sequentially includes a front-side tunneling oxide layer, a boron-doped polysilicon layer, a first passivation layer, and a front-side electrode from inside to outside; the non-contact area sequentially includes a boron diffusion layer and a second passivation layer from inside to outside; the first passivation layer includes an alumina layer and a silicon nitride layer sequentially arranged from inside to outside, and the second passivation layer includes a silicon oxide layer, an alumina layer, and a silicon nitride layer sequentially arranged from inside to outside; the back side of the silicon wafer sequentially includes a back-side tunneling oxide layer, a phosphorus-doped polysilicon layer, a back-side passivation layer, and a back-side electrode. In the present invention, the non-contact area adopts a "laser-oxidized silicon + alumina + silicon nitride" composite passivation structure, and the weighted reflectivity is controlled within 5%, realizing the synergistic improvement of optical and electrical properties.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and particularly relates to a double-sided TOPCon cell based on front-side selective doping and a preparation method thereof. Background Art

[0002] With the continuous progress of photovoltaic technology, the improvement of the efficiency of solar cells has become a key research goal. Traditional single-sided cells usually have the problem of low efficiency. Especially when the light illumination conditions are insufficient or the angles are not ideal, the unutilized light cannot be fully converted into electrical energy. The double-sided TOPCon (Tunnel Oxide Passivated Contact) cell optimizes the front and back structures, enabling it to not only receive light from the front but also utilize the reflected light, thereby improving the overall photoelectric conversion efficiency. In order to further enhance the performance of double-sided TOPCon cells, selective doping technologies (such as selective emitter SE) play an important role in the cell preparation process.

[0003] In selective doping technologies, common treatment methods include laser method, reverse etching method, and printing boron source single-step diffusion method, etc. The laser method is to use laser energy to secondarily push the doping source in boron silicate glass (BSG) to form a heavily doped region, and the non-laser region forms a lightly doped region. The reverse etching method is to print an organic material mask on the wafer after heavy diffusion, which is the same as the front grid line pattern, as an etching barrier layer, and then use an etching solution to etch the heavy-diffused region outside the mask to form a shallow junction. The printing boron source single-step diffusion method is to screen-print the boron source and perform diffusion through high-temperature heating to form heavy doping at the positions in contact with the grid lines and light doping at other positions.

[0004] These methods optimize the charge collection performance of the front and back of the cell by adjusting the doping concentration in different regions, thereby effectively improving the photoelectric conversion efficiency. However, the difficulty lies in the coordination of front and back doping. The preparation of double-sided TOPCon cells requires precise doping treatment for both the front and back. Due to the differences in the cell structures and material properties of the front and back, how to ensure the coordination of doping concentration and doping method while maintaining the high efficiency of both sides of the cell is an important technical challenge. And compared with traditional single-sided cells, double-sided TOPCon cells require more complex process steps in the preparation process. For example, when forming a tunneling oxide layer (TOx) and a phosphorus-doped polysilicon layer on the back, it must not affect the front structure and ensure the compatibility of the cell structures on both sides, which requires precise control of the doping process. Especially in the selective doping process, how to combine the special requirements of double-sided cells to minimize the impact of each process step while improving the overall efficiency of the cell.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the overall background of the present invention and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0006] The main object of the present invention is to provide a double-sided TOPCon cell based on front-side selective doping and its preparation method, aiming to combine the double-sided TOPCon cell with front-side selective doping to achieve the synergistic optimization of passivation and optics in the front non-contact region, the gradient doping optimization in the front contact region, and systematically solve the bottlenecks of traditional TOPCon cells in passivation efficiency, optical loss, and process complexity.

[0007] To achieve the above object, the technical solution adopted by the present invention is:

[0008] A double-sided TOPCon cell based on front-side selective doping includes an N-type silicon wafer, and the silicon wafer includes opposite front and back sides;

[0009] The front side is divided into a contact region and a non-contact region. The contact region, from inside to outside, is successively a front tunneling oxide layer, a boron-doped polysilicon layer, a first passivation layer, and a front electrode; the non-contact region, from inside to outside, is successively a boron diffusion layer and a second passivation layer;

[0010] The first passivation layer includes an alumina layer and a silicon nitride layer arranged successively from inside to outside, and the second passivation layer includes a silicon oxide layer, an alumina layer, and a silicon nitride layer arranged successively from inside to outside;

[0011] The back side, from inside to outside, is successively a back tunneling oxide layer, a phosphorus-doped polysilicon layer, a back passivation layer, and a back electrode.

[0012] The present invention introduces ultrathin silicon oxide as a passivation layer on the surface of the boron-doped layer in the front non-contact region, which is compounded with the alumina layer and the silicon nitride layer for passivation, and laser-oxidized silicon as an interface passivation layer; alumina provides fixed negative charges to inhibit surface recombination; silicon nitride realizes antireflection and protection, and realizes high-efficiency passivation and optical optimization in the non-contact region through lamination.

[0013] Furthermore, the surface of the non-contact region has a nano-textured surface to enhance light trapping, and the surface of the contact region is a polished surface, which increases the contact area between the metal electrode and the silicon substrate, reduces the contact resistance, and the atomically flat surface reduces the scattering of carriers at the interface, improving the fill factor (FF). The present invention realizes the combined setting of "superconductivity in the contact region + super light absorption in the non-contact region" by precisely controlling the microtopography of different functional regions, improving the balance of optoelectronic performance.

[0014] Further preferably, the surface roughness (Ra) of the polished silicon surface in the contact region is ≤1 nm, and the reflectivity of the textured surface in the non-contact region is ≤10%.

[0015] Furthermore, the boron concentration in the boron-doped polysilicon layer increases exponentially from the inside to the outside. The boron concentration on the side of the boron-doped polysilicon layer close to the front tunneling oxide layer is 1×10 19 ~5×10 19 atoms / cm 3 , and the boron concentration on the side close to the first silicon nitride passivation layer is 5×10 20 ~1×10 21 atoms / cm 3 . The low-concentration region near the interface can reduce the band offset at the interface of the tunneling oxide layer and lower the interface recombination rate. The high-concentration region on the surface forms an excellent ohmic contact, and the surface Fermi level is closer to the valence band, improving the hole collection efficiency.

[0016] Furthermore, the thickness of the boron-doped polysilicon layer in the contact region is 50~300 nm. The grain size of the boron-doped polysilicon layer on the side close to the front tunneling oxide layer is 5~20 nm, and the grain size on the side close to the first silicon nitride passivation layer is 30~80 nm. The small-grain region (5~20 nm) increases the grain boundary density and promotes hydrogen passivation sites. The large-grain region (30~80 nm) reduces grain boundary scattering and improves the electron mobility. The present invention realizes precise control through dynamic LPCVD doping and is perfectly compatible with the laser-oxidized silicon passivation layer.

[0017] Furthermore, the silicon oxide layer in the second passivation layer includes a laser mask layer or a composite layer of a laser mask layer and a tunneling oxide layer, and the thickness of the silicon oxide layer is 1~5 nm. The laser mask layer is formed by laser-induced oxidation or laser-assisted deposition. It can not only be used as a protective layer to prevent p-poly doping during annealing but also be retained as a functional passivation layer. This non-contact processing avoids the pollution and damage caused by traditional mask processes. Combined with the alkali cleaning process, the remaining thickness can be precisely controlled, ensuring excellent chemical passivation effects and not hindering carrier tunneling.

[0018] Furthermore, the refractive index difference between the laser mask layer and the front tunneling oxide layer is ≤0.005. Through the precise coordinated control of laser process parameters (energy density 0.3~0.5 J / cm 2 , O2 partial pressure 10~50 Pa) and the ALD deposition temperature (300±5 °C), it is ensured that the two silicon oxide layers have the same stoichiometry (O / Si≈2.0) and density (>2.2 g / cm 3 ). The weighted reflectivity of the second passivation layer is ≤5% (wavelength 300~1200 nm), and the interface state density Dit≤5×10 10 eV -1 cm -2 . The extremely low interface defects not only significantly reduce the surface recombination rate but also make the fixed negative charge distribution in the alumina layer more uniform.

[0019] Specifically, to ensure that the deposition of the poly structure on the front side does not affect the non-contact area and enables it to be removed in subsequent steps, it is usually necessary to retain BSG here. The difficulty of the present invention is to add silicon oxide only in the front non-contact area without affecting the contact area. Specifically, there is no BSG in the front non-contact area when depositing poly on the front side, and the laser mask and the tunneling oxide layer together serve as the barrier layer for the non-contact area during the deposition of poly in the front contact area, which can be used as a protective layer to prevent p-poly doping during annealing and be retained as a functional passivation layer in subsequent steps.

[0020] Furthermore, aluminum oxide and silicon nitride in the second passivation layer are formed synchronously with the first passivation layer. The thickness of the aluminum oxide is 1 - 3 nm, the thickness of the silicon nitride is 70 - 100 nm, and the refractive index of the silicon nitride is 1.9 - 2.0. Through the synergistic process of atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD), aluminum oxide and silicon nitride can be continuously deposited in the same equipment cavity, eliminating the risk of interface contamination in the traditional step-by-step process. The precise control of the ultra-thin aluminum oxide layer ensures the acquisition of a high density of fixed negative charges. At the same time, the silicon nitride layer with a refractive index of 1.9 - 2.0 achieves the balance of the optimal anti-reflection effect and the hydrogen passivation function by precisely regulating the SiH4 / NH3 flow ratio (1:3 - 1:5), ensuring that the weighted reflectivity of the second passivation layer ≤ 5%.

[0021] Furthermore, the thickness of the phosphorus-doped polysilicon layer is 40 - 100 nm. In the phosphorus-doped polysilicon layer, the phosphorus concentration increases linearly from the inside out. The phosphorus concentration near the back tunneling oxide layer is 5×10 19 ~1×10 20 atoms / cm 3 , and the outer phosphorus concentration is 8×10 20 ~1×10 21 atoms / cm 3 . An electron transport channel is constructed on the back through the linearly increasing phosphorus concentration distribution: the lower doping concentration near the tunneling oxide layer effectively reduces the interface barrier, and at the same time significantly reduces the damage of phosphorus diffusion to the tunneling oxide layer, while the high-concentration doping on the surface layer forms a perfect ohmic contact, reducing the contact resistance. The gradient doping suppresses the lattice distortion caused by high-concentration phosphorus, reduces the stress of the polysilicon layer, and improves the film adhesion.

[0022] Furthermore, the back passivation layer is aluminum oxide and silicon nitride, and the thickness of the back passivation layer is 70 - 100 nm, and the refractive index is 1.9 - 2.0.

[0023] Furthermore, the gate line width of the front electrode is 15 - 30 μm, and the gate line width of the back electrode is 20 - 40 μm.

[0024] The second object of the present invention is to provide a preparation method of a double-sided TOPCon cell based on front-side selective doping, which has the same technical effects.

[0025] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0026] A preparation method of a double-sided TOPCon cell based on front-side selective doping, comprising the following steps:

[0027] S1: Surface treatment of the N-type silicon wafer and double-sided texturing;

[0028] S2: Boron diffusion is carried out on the front side of the silicon wafer after the texturing surface is prepared; at this time, the front side is textured silicon + boron diffusion layer + BSG, the back side is textured silicon, and it also includes the lateral diffusion generated during the front-side boron diffusion;

[0029] S3: Laser patterning is carried out on the front side to define the contact area and the non-contact area; specifically, BSG modification is carried out to loosen or remove the BSG in the contact area. At this time, the front side is divided into the contact area and the non-contact area, where the non-contact area includes textured silicon + boron diffusion layer + BSG, and the contact area includes textured silicon + boron diffusion layer (or + residual BSG), and the back side remains unchanged;

[0030] S4: Pickling is used to remove the lateral diffusion on the back side and around, as well as the BSG in the front-side contact area; at this time, the lateral diffusion generated during the boron diffusion in step S2 on the back side is removed by pickling, the back side is textured silicon, the BSG remaining in the front-side contact area is removed by pickling, the contact area includes textured silicon + boron diffusion layer, and the BSG in the front-side non-contact area is retained for protection, and the non-contact area remains unchanged;

[0031] S5: Polishing is carried out on the back side and the front-side contact area, and the front-side contact area is polished to the silicon wafer; at this time, the back side is a polished surface, the front-side contact area is bare silicon, and the front-side non-contact area remains unchanged;

[0032] S6: Laser or pickling is used to remove the BSG in the front-side non-contact area, and a laser mask is prepared on the non-contact area; at this time, both the back side and the front-side contact area remain unchanged, and the front-side non-contact area includes textured silicon + boron diffusion layer + laser mask;

[0033] S7: SiOx, p-poly, and mask oxide layer are sequentially deposited on the front side; at this time, the front-side contact area is SiOx + p-poly + mask oxide layer, the front-side non-contact area is textured silicon + boron diffusion layer + laser mask + SiOx + p-poly + mask oxide layer, the back side is a polished surface, and it also includes the overplating generated during the front-side deposition;

[0034] S8: Pickling is used to remove the BSG on the back and around the edges, and caustic washing is used to remove the SiOx / p-poly overplating on the back and around the edges; at this time, the mask oxide layer, p-poly, and SiOx on the back and around the edges are removed in sequence, presenting a polished bare silicon surface, and the front side remains unchanged;

[0035] S9: SiOx, n-poly, and mask oxide layer are deposited on the back in sequence; at this time, the back is SiOx + n-poly + mask oxide layer, the front contact area is SiOx + p-poly + mask oxide layer, the front non-contact area is textured silicon + boron diffusion layer + laser mask + SiOx + p-poly + mask oxide layer, and it also includes the overplating generated during the back deposition;

[0036] S10: Pickling is used to remove the phosphosilicate glass (PSG) on the front and around the edges, and caustic washing is used to remove the SiOx / n-poly overplating on the front and around the edges; at this time, the overplating (SiOx + n-poly + mask oxide layer) generated on the front during the back deposition is removed, the front contact area is SiOx + p-poly + mask oxide layer, the front non-contact area is textured silicon + boron diffusion layer + laser mask + SiOx + p-poly + mask oxide layer, and the back remains unchanged;

[0037] S11: Laser is used to remove the BSG in the front non-contact area, caustic washing is used to remove the p-poly deposition in the front non-contact area, pickling is used to remove the BSG and PSG on the front and back, and silica with a thickness of ≥1 nm in the front non-contact area is retained; at this time, the back is SiOx + n-poly, the front contact area is SiOx + p-poly, the front non-contact area is textured silicon + boron diffusion layer + laser mask + SiOx or textured silicon + boron diffusion layer + laser mask, where both the laser mask and SiOx are silica, and the silica layer with a thickness of ≥1 nm retained in this step serves as the silica layer of the second passivation layer, that is, a textured silicon + boron diffusion layer + silica structure is formed in the front non-contact area in this step;

[0038] S12: Aluminum oxide and silicon nitride are deposited on both sides in sequence, and hydrogen plasma treatment is carried out; at this time, the back is SiOx + n-poly + aluminum oxide + silicon nitride, the front contact area is SiOx + p-poly + aluminum oxide + silicon nitride, and the front non-contact area is textured silicon + boron diffusion layer + silica + aluminum oxide + silicon nitride;

[0039] S13: Screen printing, sintering, and testing and sorting are carried out. At this time, the back is SiOx + n-poly + silicon nitride + back electrode, the front contact area is SiOx + p-poly + aluminum oxide + silicon nitride + front electrode, and the front non-contact area is textured silicon + boron diffusion layer + silica + aluminum oxide + silicon nitride.

[0040] Preferably, in step S1, an N-type silicon wafer with a resistivity of 0.5-2Ω.cm and a minority carrier lifetime of >10ms is used, and after the damage is removed, a texturing is performed to form a pyramid structure with surface light trapping. The texturing liquid is prepared by mixing KOH and an additive in a volume ratio of 4-10:1, and the additive contains isopropanol and a surfactant. Specifically, the N-type silicon wafer is anisotropically etched on both sides at 75-85°C for about 4-6 minutes, and the thinning amount of the silicon wafer is controlled to be 0.1-0.3g. The surface metal contamination is removed by ultrasonic-assisted cleaning, and finally a uniform pyramid velvet structure is formed. The pyramid height is 0.5-2 μm, and the coverage is ≥95%.

[0041] Preferably, in step S2, a tubular diffusion furnace is used, BBr3 is used as a boron source, and doping and oxidation are performed at 850-1100°C, with an oxygen flow rate of 1.5 L / min and a time of 30 min. The BSG thickness is controlled at 90-150 nm, the doping square resistance is controlled at 200-400 ohm / sq, the junction depth is 0.2-0.5 μm, and the peak concentration of boron atoms is 1×10 18 ~1×10 19 atoms / cm 3 .

[0042] Preferably, in step S3, green skin / green nano / purple skin / purple nano laser is used to modify BSG, and the BSG in the contact area is loosened or removed. The laser area is the grid line printing area, and 80-200 μm of this area is removed by laser, and the non-laser area is retained.

[0043] Preferably, in step S4, a chain cleaning machine with an HF concentration volume ratio of 30% to 50% is used to remove the BSG layer on the back and sides, and a tank HF dip (2% to 15%) is used to remove the BSG remaining in the front contact area.

[0044] Preferably, in step S5, the etching solution used for back polishing is KOH and additives mixed in a volume ratio of 6 to 10:1, the polishing temperature is maintained at 75 to 85°C, the time is about 3 to 8 minutes, the thinning amount is controlled at 0.1 to 0.3 g, and the Ra roughness is reduced to 0.3 to 0.5 nm. The front contact area is spot-etched with HF / HNO3 (1:3) mixed acid for 30 seconds to remove BSG and the boron diffusion layer in this area, and the bare silicon surface Ra is less than 1 nm.

[0045] In this step, the contact surface is directly polished to the silicon wafer. The cleaning window is wider and the controllability is higher, which can make the silicon wafer surface present a more pure and flat state, conducive to forming a good metal-semiconductor contact, reducing the contact resistance, thereby improving the fill factor and conversion efficiency of the battery, and avoiding the increase in contact resistance caused by the possible boron diffusion layer in the contact area during subsequent metallization and other processes. And it can effectively reduce the recombination of carriers, improve the collection efficiency of carriers, and then enhance the photovoltaic conversion performance of the battery.

[0046] Preferably, in step S6, the BSG in the non-contact area is selectively removed to expose the underlying p+-doped silicon surface. Then a silicon dioxide (SiO2) laser mask is prepared to protect the non-contact area from overplating during subsequent deposition processes and serve as part of the passivation layer.

[0047] Specifically, pulsed nanosecond laser is used to selectively remove the BSG in the non-contact area while minimizing the heat-affected zone to prevent lattice damage on the silicon surface. After removing the BSG in the non-contact area, the underlying high-concentration boron diffusion layer is exposed, providing a low-recombination interface for the subsequent passivation layer. The silicon surface after laser treatment is quickly rinsed with dilute HF (1% - 2%) to remove laser oxidation residues and ensure the interface cleanliness for subsequent SiO2 deposition. Or the same pickling solution as in step S4 is used to pickle and remove the BSG in the non-contact area after polishing to better protect the textured surface of the non-contact area.

[0048] Then, ultraviolet laser with a wavelength of 266 nm is used in situ to induce silicon surface oxidation in an O2 atmosphere of 10 - 50 Pa to grow a 1 - 4 nm ultra-thin SiO2 layer. The energy density is 0.3 - 0.5 J / cm 2 , the scanning speed is 10 - 50 mm / s, and the thickness fluctuation is ±0.2 nm. Through precise control of the laser parameters, the stoichiometry of SiO2 (O / Si ≈ 2.0) and thickness uniformity are ensured.

[0049] Preferably, in step S7, when depositing SiOx on the front side, SiOx grows in the entire area of the contact area and the non-contact area. The silicon dioxide in the contact area serves as the front tunneling oxide layer, and the silicon dioxide in the non-contact area is superimposed with the laser mask in step S6 to form a silicon dioxide passivation layer to prevent the p-poly doping from affecting the boron diffusion layer in the non-contact area.

[0050] Preferably, in step S7, the gradient deposition of the boron-doped polysilicon layer is achieved by dynamically adjusting the boron source flow rate in the LPCVD reaction chamber. Specifically, the flow rate of BBr3 (10 - 100 sccm) is dynamically adjusted in the LPCVD reaction chamber, and a p-poly layer with a thickness of 50 - 300 nm is deposited at 600 °C. Subsequently, annealing is carried out at 850 - 950 °C, and the grain size increases from 5 nm (near the silicon dioxide) to 80 nm (on the surface), and the boron concentration gradient is 1×10 19~8×10 20 atoms / cm 3 , the deposition thickness of SiOx is 1 - 2 nm, the deposition thickness of p-poly is 50 - 300 nm, and the outer layer mask oxide is BSG with a thickness of 10 - 100 nm.

[0051] Preferably, in step S8, a chain cleaner with an HF concentration volume ratio of 30% - 50% is used to remove the BSG layer on the back and sides. An alkaline solution (KOH: additive = 6 - 10:1) is used for etching and polishing to remove the SiOx / p-poly overplating on the back and around.

[0052] Preferably, in step S9, SiOx, n-poly, and mask oxide are sequentially deposited on the back; the back structure is prepared by LPCVD + phosphorus diffusion or PECVD + annealing. The back structure is a conventional single-layer SiOx / n-poly structure. Among them, the thickness of SiOx is 1 - 2 nm, the thickness of n-poly is 40 - 100 nm, and the peak concentration of effective phosphorus atoms is 1 - 8×10 20 atoms / cm 3 , and the inflection point concentration is 5 - 9×10 18 atoms / cm 3 .

[0053] Preferably, in step S10, a chain cleaner with an HF concentration volume ratio of 5% - 30% is used to remove the PSG layer on the front and sides, and alkali washing is used to remove the n-poly overplating on the non-contact area of the front and sides.

[0054] Preferably, in step S11, the BSG in the non-contact area of the front is removed by laser, and the p-poly deposition in the non-contact area of the front is removed by alkali washing. The alkali washing solution is a 5% - 10% potassium hydroxide (KOH) solution, and the cleaning time is 30 - 60 s. Acid washing is used to remove the BSG and PSG on the front and back, and silica with a thickness of ≥1 nm in the non-contact area of the front is retained; the thickness of the SiOx retained in step S11 is 1 - 4 nm.

[0055] Preferably, in step S12, the deposition thickness of alumina is 1 - 3 nm, the deposition thickness of front-side silicon nitride is 70 - 100 nm, the deposition thickness of back-side silicon nitride is 70 - 100 nm, the refractive index is 1.9 - 2.0, and the hydrogen plasma treatment mainly treats the front, with a temperature of 350 - 450 °C and a treatment time of 5 - 15 min.

[0056] Preferably, in step S13, the peak sintering temperature of the silver paste for screen printing the electrode is 800 - 850 °C.

[0057] Advantages of the present invention:

[0058] (1) The non-contact area of the battery prepared by the present invention adopts a "laser-oxidized silicon + ALD Al2O3 + SiNx" composite passivation structure, achieving a synergistic improvement in optical and electrical properties. The laser-oxidized silicon serves as the bottom passivation interface, and its denseness and the fixed negative charges of alumina jointly suppress surface recombination. After adding the upper-layer SiNx, the weighted reflectivity is controlled within 5%. Compared with traditional single passivation, the present invention realizes an efficiency gain of ≥1.0% (absolute value) through refractive index matching and ultra-thin layer control, while being compatible with the requirements of double-sided power generation.

[0059] (2) The front non-contact area of the present invention retains the textured structure, and combined with the low-reflection characteristics of the composite passivation layer, it realizes the efficient absorption of incident light; while the polished surface of the contact area is conducive to forming a good metal-semiconductor contact, reducing the contact resistance, thereby improving the fill factor and conversion efficiency of the battery, and avoiding the increase in contact resistance caused by the possible boron diffusion layer in the contact area during subsequent processes such as metallization. And it can effectively reduce the recombination of carriers, improve the collection efficiency of carriers, and thus enhance the optoelectronic conversion performance of the battery.

[0060] (3) Through the synergistic application of laser-induced oxidation and atomic layer deposition technologies, the present method realizes the precise control of the passivation layers in the non-contact area and the contact area. The coordinated design of the thickness of the ultra-thin oxidized silicon layer (laser mask) generated in step S6 and the tunneling oxide layer ensures the p-poly doping in the front non-contact area during annealing, and it is also retained as part of the passivation layer through the alkali washing in step S11. The present application effectively reduces the interface light reflection by strictly controlling the refractive index difference between the tunneling oxide layer and the laser-oxidized silicon to be ≤0.005. In addition, the laser thermal damage is repaired through hydrogen plasma treatment, reducing the interface state density, and significantly improving the passivation quality and mass production compatibility. Description of the Drawings

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0062] Figure 1 It is a schematic diagram of the battery structure in Embodiment 1 of the present invention;

[0063] Figure 2 It is Figure 1 The partial enlarged view of part A in

[0064] Figure 3 It is the preparation flow chart of the battery structure in Embodiment 1 of the present invention;

[0065] Reference numerals: 01, N-type silicon wafer; 10, front side; 11, contact area; 12, non-contact area; 13, front tunneling oxide layer; 14, boron-doped polysilicon layer; 15, silicon oxide layer; 16, front aluminum oxide layer; 17, front silicon nitride layer; 18, front electrode; 19, boron diffusion layer; 20, back side; 21, back tunneling oxide layer; 22, phosphorus-doped polysilicon layer; 23, back aluminum oxide layer; 24, back silicon nitride layer; 25, back electrode. Detailed implementation manners

[0066] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, a double-sided TOPCon cell based on front-side selective doping and its preparation method according to the present invention will be described in detail below in terms of its specific implementation manners, features and effects.

[0067] In the embodiments of the present invention, the sources of commercially available materials are as follows:

[0068] ;

[0069] Example 1:

[0070] As Figure 1 and Figure 2 shown, a double-sided TOPCon cell based on front-side selective doping includes an N-type silicon wafer 01, and the N-type silicon wafer 01 includes a relative front side 10 and a back side 20;

[0071] The front side 10 is divided into a contact area 11 and a non-contact area 12. The contact area 11, from the inside to the outside, successively includes a front tunneling oxide layer 13, a boron-doped polysilicon layer 14, a first passivation layer, and a front electrode 18; the non-contact area 12, from the inside to the outside, successively includes a boron diffusion layer 19 and a second passivation layer;

[0072] The first passivation layer includes a front aluminum oxide layer 16 and a front silicon nitride layer 17 which are successively arranged from the inside to the outside, and the second passivation layer includes a silicon oxide layer 15, a front aluminum oxide layer 16 and a front silicon nitride layer 17 which are successively arranged from the inside to the outside;

[0073] The back side 20 successively includes a back tunneling oxide layer 21, a phosphorus-doped polysilicon layer 22, a back aluminum oxide layer 23, a back silicon nitride layer 24, and a back electrode 25.

[0074] The surface of the non-contact area 12 has a nano-textured surface structure with a reflectivity of the textured surface structure ≤ 10%, and the surface of the contact area 11 is a polished surface with Ra ≤ 1 nm.

[0075] The silicon oxide layer in the second passivation layer is a composite layer including a laser mask layer and a tunnel oxide layer, and the thickness of the silicon oxide layer is 3 nm. The laser mask layer is formed by laser induced oxidation or laser assisted deposition. The refractive index difference between the laser mask layer and the front tunnel oxide layer is ≤0.005. The weighted reflectivity of the second passivation layer is ≤5% (wavelength 300~1200 nm), and the interface state density Dit is ≤5×10 10 eV -1 cm -2 .

[0076] like Figure 3 , a method for preparing a double-sided TOPCon cell based on front selective doping, comprising the following steps:

[0077] S1. Use N-type silicon wafers with a resistivity of 0.5~2Ω.cm and a minority carrier lifetime of >10ms. After removing the damage, texturing is performed to form a pyramid structure with surface light trapping. The texturing liquid is a mixture of KOH and additives in a volume ratio of 6:1. The additives contain isopropyl alcohol and surfactants. Specifically, the N-type silicon wafer is anisotropically etched on both sides at 80°C for 5 minutes, and the thinning amount of the silicon wafer is controlled at 0.2g. Ultrasonic-assisted cleaning is used to remove surface metal contamination, and finally a uniform pyramid velvet structure is formed. The pyramid height is 0.1μm, and the coverage is ≥95%.

[0078] S2. Using a tubular diffusion furnace, BBr3 was used as the boron source, and doping and oxidation were performed at 1050°C, with an oxygen flow rate of 1.5 L / min and a time of 30 min. The BSG thickness was controlled at 120 nm, the doping square resistance was controlled at 350 ohm / sq, the junction depth was 0.3 μm, and the peak concentration of boron atoms was 3×10 18 atoms / cm 3 .

[0079] S3, use green laser to modify BSG, loosen or remove the BSG in the contact area. The laser area is the grid line printing area, and this area is removed by laser by 100μm, and the non-laser area is retained.

[0080] S4. Use a chain cleaning machine with an HF concentration volume ratio of 40% to remove the BSG layer on the back and sides, and use a slot-type HFdip (4%) to clean and remove the residual BSG in the front contact area.

[0081] S5. The etching solution used for back polishing is KOH and additives mixed in a volume ratio of 7:1. The polishing temperature is maintained at 80°C for 5 minutes, the thinning amount is controlled at 0.15g, and the Ra roughness is reduced to 0.5 nm. The front contact area is spot-etched with HF / HNO3 (1:3) mixed acid for 30 seconds to remove BSG and the boron diffusion layer in this area.

[0082] S6. Remove the BSG in the non-contact area by pickling to expose the underlying p+-doped silicon surface. Then, prepare a silicon oxide (SiO2) laser mask to protect the non-contact area from overplating during subsequent deposition processes and serve as part of the passivation layer.

[0083] S7. When depositing SiOx on the front side, SiOx grows over the entire contact area and non-contact area. The silicon oxide in the contact area serves as the front tunneling oxide layer, and the silicon oxide in the non-contact area is stacked with the laser mask in step S6 to form the silicon oxide passivation layer. The gradient deposition of the boron-doped polysilicon layer is achieved by dynamically adjusting the boron source flow rate in the LPCVD reaction chamber. Specifically, dynamically adjust the BBr3 flow rate (10 - 100 sccm) in the LPCVD reaction chamber and deposit a 150-nm-thick p-poly at 600 °C. Subsequently, anneal at 910 °C, and the grain size increases from 5 nm (near the silicon oxide) to 80 nm (surface), and the peak concentration of effective boron atoms is 5×10 20 atoms / cm 3 , the deposition thickness of SiOx is 1.5 nm, the deposition thickness of p-poly is 150 nm, and the outer mask oxide layer is BSG with a thickness of 80 nm.

[0084] S8. Use a chain cleaner with a 40% HF concentration by volume to remove the BSG layer on the back and sides. Use an alkaline solution (KOH: additive = 8:1) to etch and polish to remove the overplating of SiOx / p-poly on the back and around.

[0085] S9. Deposit SiOx, n-poly, and mask oxide layer on the back in sequence; use the LPCVD + phosphorus diffusion method to prepare the back structure. The back structure is a conventional single-layer SiOx / n-poly structure. Among them, the thickness of SiOx is 1.5 nm, the thickness of n-poly is 60 nm, and the peak concentration of effective phosphorus atoms is 3×10 20 atoms / cm 3 , and the inflection point concentration is 8×10 18 atoms / cm 3 .

[0086] S10. Use a chain cleaner with a 15% HF concentration by volume to remove the PSG layer on the front and sides, and use alkali cleaning to remove the overplating of n-poly on the front non-contact area and sides.

[0087] S11. Use a green laser on the front side for BSG modification to remove the BSG in the non-contact area, and then perform an alkali wash to remove the p-poly deposition in the non-contact area on the front side. The alkali wash solution is a 5% KOH solution, and the washing time is 30 - 60 s. Soak and pickle with 10% concentration of HF to remove the BSG and PSG on the front and back sides, and retain the silicon oxide with a thickness of ≥1 nm in the non-contact area on the front side; the thickness of the SiOx retained in step S11 is 3 nm.

[0088] S12. Use the ALD method to deposit alumina passivation on both sides. The thickness of the alumina is 3 nm, the deposition thickness of the silicon nitride is 80 nm, the temperature of the hydrogen plasma treatment is 400 °C, and the treatment time is 10 min.

[0089] S13. Screen-print the main / auxiliary grid lines on the front / back sides, sinter to form an ohmic contact, use light injection to improve passivation and light decay, and use LECO laser to enhance the passivation contact performance.

[0090] Comparative Example 1

[0091] A double-sided TOPCon cell based on front-side selective doping, including an N-type silicon wafer, and the silicon wafer includes opposite front and back sides;

[0092] The front side is divided into a contact area and a non-contact area. In the contact area, from the inside to the outside, there are a front-side tunneling oxide layer, a boron-doped polysilicon layer, an alumina layer, a silicon nitride layer, and a front-side electrode in sequence; in the non-contact area, from the inside to the outside, there are a boron diffusion layer, a front-side alumina layer, and a front-side silicon nitride layer in sequence;

[0093] On the back side of the silicon wafer, there are a back-side tunneling oxide layer, a phosphorus-doped polysilicon layer, a back-side alumina layer, a back-side silicon nitride layer, and a back-side electrode in sequence. The surface of the non-contact area has a nano-textured surface structure, and the reflectivity of the textured surface structure is ≤10%. The surface of the contact area is a polished surface, and the Ra of the polished surface is ≤1 nm.

[0094] A preparation method for a double-sided TOPCon cell based on front-side selective doping, including the following steps:

[0095] S1. Use an N-type silicon wafer with a resistivity of 0.5 - 2 Ω·cm and a minority carrier lifetime > 10 ms. After removing the damage, perform texturing to form a pyramid structure for surface light trapping. The texturing solution is prepared by mixing KOH and an additive in a volume ratio of 6:1. The additive contains isopropyl alcohol and a surfactant. Specifically, perform anisotropic etching on both sides of the N-type silicon wafer at 80 °C for 5 min, and control the silicon wafer thinning amount at 0.2 g. Remove the surface metal contamination through ultrasonic-assisted cleaning, and finally form a uniform pyramid textured surface structure. The pyramid height is 0.1 μm, and the coverage rate is ≥95%.

[0096] S2. Using a tubular diffusion furnace, BBr3 was used as the boron source, and doping and oxidation were performed at 1050°C, with an oxygen flow rate of 1.5 L / min and a time of 30 min. The BSG thickness was controlled at 120 nm, the doping square resistance was controlled at 350 ohm / sq, the junction depth was 0.3 μm, and the peak concentration of boron atoms was 3×10 18 atoms / cm 3 .

[0097] S3, use green laser to modify BSG, loosen or remove the BSG in the contact area. The laser area is the grid line printing area, and this area is removed by laser by 100μm, and the non-laser area is retained.

[0098] S4. Use a chain cleaning machine with an HF concentration volume ratio of 40% to remove the BSG layer on the back and sides, and use a slot-type HFdip (4%) to clean and remove the residual BSG in the front contact area.

[0099] S5. The etching solution used for back polishing is KOH and additives mixed in a volume ratio of 7:1. The polishing temperature is maintained at 80°C for 5 minutes, the thinning amount is controlled at 0.15g, and the Ra roughness is reduced to 0.5 nm. The front contact area is spot-etched with HF / HNO3 (1:3) mixed acid for 30 seconds to remove BSG and the boron diffusion layer in this area.

[0100] S6. Gradient deposition of boron-doped polysilicon layer is achieved by dynamically adjusting the boron source flow rate in the LPCVD reaction chamber. Specifically, the BBr3 flow rate (10-100 sccm) is dynamically adjusted in the LPCVD reaction chamber, and a 150nm thick p-poly is deposited at 600℃. Subsequently, annealing is performed at 910℃, and the grain size increases from 5 nm to 80 nm. The peak concentration of effective boron atoms is 5×10 20 atoms / cm 3 , the deposition thickness of SiOx is 1.5nm, the deposition thickness of p-poly is 150nm, and the outer mask oxide layer is BSG with a thickness of 80nm.

[0101] S7, use a chain cleaning machine with a HF concentration of 40% by volume to remove the BSG layer on the back and sides. Use an alkaline solution (KOH: additive = 8:1) to etch and polish to remove the SiOx / p-poly plating on the back and surrounding areas.

[0102] S8, SiOx, n-poly, and mask oxide layers are deposited on the back in sequence; the back structure is prepared by LPCVD+phosphorus diffusion. The back structure is a conventional single-layer SiOx / n-poly structure. The thickness of SiOx is 1.5nm, the thickness of n-poly is 60nm, and the peak concentration of effective phosphorus atoms is 3×1020 atoms / cm 3 and the inflection point concentration is 8×10 18 atoms / cm 3 .

[0103] S9. Use a chain cleaner with a HF concentration volume ratio of 15% to remove the PSG layer on the front and sides, and use alkali cleaning to remove the n-poly overplating on the non-contact area of the front and sides.

[0104] S10. Use a green laser on the front for BSG modification to remove the BSG in the non-contact area, and use alkali cleaning to remove the p-poly deposition in the non-contact area of the front. The alkali cleaning solution is a 5% potassium hydroxide (KOH) solution, and the cleaning time is 30 - 60 s. Soak and pickle with 0% concentration of HF to remove the BSG and PSG on the front and back.

[0105] S11. Use the ALD method to prepare alumina passivation on both sides. The thickness of the alumina is 3 nm, the deposition thickness of the silicon nitride is 80 nm, and the refractive index is 1.95.

[0106] S12. Screen-print the main / auxiliary grid lines on the front / back, sinter to form ohmic contacts, use light injection to improve passivation and light-induced degradation, and use LECO laser to enhance the passivation contact performance.

[0107] Battery performance test results

[0108] Characterize the blue film structure of the examples, that is, test before preparing the electrodes. The performance test results are shown in Table 1: This data is the blue film data of the battery structure, and this data can reflect that this solution is feasible.

[0109] Table 1

[0110] Example Voc [mV] FF [%] Eta [%] Conventional TOPCon cell structure - - - Example 1 10 1.2 0.65 Comparative Example 1 3 0.16 0.18

[0111] From the above data, it can be seen that the difference between Example 1 of this application and Comparative Example 1 is that this application sets a silicon oxide layer in the non-contact area, while Comparative Example 1 does not. That is, the passivation of the non-contact area of this application includes a silicon oxide layer, an alumina layer, and a silicon nitride layer, while Comparative Example 1 only has an alumina layer and a silicon nitride layer. Laser-oxidized silicon serves as the bottom passivation interface. Its compactness and the fixed negative charges of alumina jointly inhibit surface recombination. The retained textured structure in the non-contact area, combined with the low reflection characteristics of the composite passivation layer, realizes the efficient absorption of incident light. And the polished surface in the contact area is conducive to forming a good metal-semiconductor contact, reducing the contact resistance, thereby improving the fill factor and conversion efficiency of the battery, and avoiding the situation where the possible boron diffusion layer in the contact area causes an increase in contact resistance in subsequent metallization and other processes. And it can effectively reduce the recombination of carriers, improve the collection efficiency of carriers, and thus improve the photoelectric conversion performance of the battery.

[0112] Therefore, the experimental results of this application are better than those of Comparative Example 1. However, it is obvious that the data of Comparative Example 1 are better than those of conventional TOPCon, which also reflects that bifacial cells are superior to single-sided cells.

[0113] Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and the descriptions in the specification only illustrate the principle of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of the present invention claimed is defined by the appended claims and their equivalents.

Claims

1. A preparation method of a double-sided TOPCon battery based on front-side selective doping, characterized in that, It includes the following steps: S1: Surface treatment and double-sided texturing of the N-type silicon wafer; S2: Boron diffusion on the front side of the silicon wafer after the texturing surface is completed; S3: Laser patterning on the front side to define the contact area and non-contact area; S4: Pickling to remove the backside and the surrounding diffusion, as well as the BSG in the front contact area; S5: Polishing the backside and the front contact area, where the front contact area is polished to the silicon wafer; S6: Removing the BSG in the non-contact area on the front side and preparing a laser mask on the non-contact area; S7: Sequentially depositing SiOx, p-poly, and mask oxide layer on the front side; S8: Pickling to remove the BSG on the backside and the surrounding areas, and alkali washing to remove the SiOx / p-poly plating around the backside; S9: Sequentially depositing SiOx, n-poly, and mask oxide layer on the backside; S10: Pickling to remove the PSG on the front side and the surrounding areas, and alkali washing to remove the SiOx / n-poly plating around the front side; S11: Laser removing the BSG in the non-contact area on the front side, alkali washing to remove the p-poly deposition in the non-contact area on the front side, pickling to remove the BSG and PSG on the front side and the backside, and retaining the silicon oxide with a thickness of ≥1 nm in the non-contact area on the front side; S12: Sequentially depositing aluminum oxide and silicon nitride on both sides and performing hydrogen plasma treatment; S13: Performing screen printing, sintering, and testing and sorting; The obtained double-sided TOPCon cell includes an N-type silicon wafer, and the silicon wafer includes opposite front and back sides; The front side is divided into a contact area and a non-contact area, and the contact area from the inside to the outside is successively a front tunneling oxide layer, a boron-doped polycrystalline silicon layer, a first passivation layer, and a front electrode; The non-contact area from the inside to the outside is successively a boron diffusion layer and a second passivation layer; The first passivation layer includes an aluminum oxide layer and a silicon nitride layer successively arranged from the inside to the outside, and the second passivation layer includes a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer successively arranged from the inside to the outside; The backside of the silicon wafer is successively a back tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, a back passivation layer, and a back electrode.

2. The preparation method of a double-sided TOPCon cell based on positive selective doping according to claim 1, wherein, The surface of the non-contact area has a nano-textured surface structure, and the surface of the contact area is a polished surface.

3. The preparation method of a double-sided TOPCon battery based on positive selective doping according to claim 2, wherein, The silicon oxide layer in the second passivation layer includes a laser mask layer or a composite layer of a laser mask layer and a tunneling oxide layer, and the thickness of the silicon oxide layer is 1 - 4 nm.

4. The preparation method of a double-sided TOPCon cell based on front-side selective doping according to claim 3, wherein, The refractive index difference between the laser mask layer and the front tunneling oxide layer ≤0.

005.

5. The preparation method of a double-sided TOPCon cell based on front-side selective doping according to claim 4, characterized in that, The weighted reflectivity of the second passivation layer ≤5%.

6. The preparation method of a double-sided TOPCon battery based on front-side selective doping according to claim 2, wherein, The boron concentration of the boron-doped polysilicon layer increases exponentially from the inside to the outside, and the boron concentration of the boron-doped polysilicon layer near the front tunneling oxide layer is 1×10 19 ~5×10 19 atoms / cm 3 , and the boron concentration of the boron-doped polysilicon layer near the first passivation layer is 5×10 20 ~1×10 21 atoms / cm 3 .

7. The manufacturing method of a double-sided TOPCon cell based on front-side selective doping according to claim 6, characterized in that, The grain size of the boron-doped polycrystalline silicon layer on the side close to the front tunneling oxide layer is 5 - 20 nm, and the grain size on the side close to the first passivation layer is 30 - 80 nm.

8. The preparation method of a double-sided TOPCon battery based on front selective doping according to claim 1, characterized in that, In the phosphorus-doped polysilicon layer, the phosphorus concentration increases linearly from the inside to the outside, and the phosphorus concentration near the back tunneling oxide layer is 5×10 19 ~1×10 20 atoms / cm 3 , and the outer phosphorus concentration is 8×10 20 ~1×10 21 atoms / cm 3 .

9. The preparation method of a double-sided TOPCon battery based on positive selective doping according to claim 1, characterized in that, In step S7, when depositing SiOx on the front side, SiOx grows in the entire area of the contact area and the non-contact area. The silicon oxide in the contact area serves as the front tunneling oxide layer, and the silicon oxide in the non-contact area is superimposed with the laser mask in step S6 as the silicon oxide passivation layer.

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