Smart FFT measurement for reconfigurable sensors using broadband digital receivers

Abstract

A method and apparatus for finding a signal in a frequency range includes converting an analog input signal to a digital domain using an analog-to-digital converter to create a digital input signal. A first fast Fourier transform (FFT) converts a digital input signal into a frequency input signal that is binned based on frequency and thresholds to create a binary filter. A digital input signal (from an analog-to-digital converter) is classified into a container (e.g., using the Chinese remainder theorem), and then converted to a frequency intermediate signal by a second FFT. The frequency intermediate signal is classified into bins and multiplied using a binary filter to create an output frequency signal.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Ser. No. 63 / 399,055, filed Aug. 18, 2022, entitled “SMART FFT MEASUREMENT FOR RECONFIGURABLE SENSOR USING A WIDEBAND DIGITAL RECEIVER”, the disclosure of which is hereby incorporated by reference in its entirety. Background of the Invention

[0003] Various aspects of the present invention generally relate to fast Fourier transforms and, in particular, to intelligent fast Fourier transforms for use in wideband receivers.

[0004] Ultra - wideband (UWB) is a radio technology that can use very low energy levels for short - range, high - bandwidth communication over much of the radio spectrum. UWB has traditional applications in non - cooperative radar imaging. More recent applications are targeted at sensor data collection, precise positioning, and tracking.

[0005] A significant difference between conventional radio transmission and UWB is that conventional systems transmit information by varying the power level, frequency, and / or phase of a sine wave. UWB transmission transmits information by generating radio energy at specific time intervals and occupying a large bandwidth, thus enabling pulse - position or time modulation. Information can also be modulated on the UWB signal (pulse) by encoding the polarity of the pulse, its amplitude, and / or by using orthogonal pulses. UWB pulses can be sent sporadically at a relatively low pulse rate to support time or position modulation, but can also be sent at a rate up to the reciprocal of the UWB pulse bandwidth. Summary of the Invention

[0006] According to aspects of the present disclosure, a process for finding signals within a frequency range includes converting an analog input signal to the digital domain using an analog - to - digital converter to create a digital input signal. A first fast Fourier transform (FFT) converts the digital input signal to a frequency input signal that is binned based on frequency and a threshold to create a binary filter. The digital input signal (from the analog - to - digital converter) is sorted into bins (e.g., using the Chinese Remainder Theorem), and then the digital input signal is converted to a frequency intermediate signal by a second FFT. The frequency intermediate signal is sorted into bins and multiplied by the binary filter to create an output frequency signal.

[0007] According to another aspect of the present disclosure, an apparatus (e.g., a receiver) for finding signals within a frequency range includes converting an analog input signal to the digital domain using an analog-to-digital converter to create a digital input signal. A first Fast Fourier Transform (FFT) converts the digital input signal into a frequency input signal, which is binned based on frequency and a threshold to create a binary filter. The digital input signal (from the analog-to-digital converter) is classified into bins (e.g., using the Chinese Remainder Theorem), and then the digital input signal is converted into a frequency intermediate signal by a second FFT. The frequency intermediate signal is classified into bins and multiplied using the binary filter to create an output frequency signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an ultra-wideband receiver according to an aspect of the present disclosure;

[0009] Figure 2 is a flowchart of a process for detecting signals in an ultra-wideband signal according to an aspect of the present disclosure;

[0010] Figure 3 is a visual representation of a binning process using the Chinese Remainder Theorem according to an aspect of the present disclosure;

[0011] Figure 4 is a block diagram of an ultra-wideband receiver according to an aspect of the present disclosure;

[0012] Figure 5A is a frequency plot of an intelligent Fast Fourier Transform (SFFT) according to an aspect of the present disclosure.

[0013] Figure 5B is a frequency plot of a Fast Fourier Transform according to an aspect of the present disclosure.

[0014] Figure 5C is a spectrum of an SFFT binary filter according to an aspect of the present disclosure.

[0015] Figure 6A is a frequency plot showing the Fast Fourier Transform (FFT) of three signals according to an aspect of the present disclosure.

[0016] Figure 6B is a frequency plot after binning according to an aspect of the present disclosure.

[0017] Figure 7 is a block diagram of a computing system according to an aspect of the present disclosure that can be used in aspects of the processes and apparatuses disclosed herein. DETAILED DESCRIPTION

[0018] In accordance with aspects of the present disclosure, an intelligent fast Fourier transform (SFFT) is described which, among other things, allows a UWB receiver to quickly detect multiple signals within the UWB band. Thus, UWB provides low power consumption execution with fine time targeting and high throughput. To achieve this, UWB sends short data bursts at short intervals without interfering with other existing telecommunication frameworks.

[0019] In addition, embodiments of the SFFT discussed herein can be used in other applications such as transmitter and receiver mobile networks (such as 5G (fifth generation mobile network)), other network protocols, DNA (deoxyribonucleic acid) sequencing, molecular amplification, astronomical detection of various radio objects using satellite and ground antennas, arithmetic logic units for processors, neuromorphic networks, neural networks, etc. Basically, any application that requires other cross-correlation calculations that change from the original domain to the frequency domain and / or vice versa can utilize embodiments of the SFFT process described herein.

[0020] Figure 1 FIG. 7 illustrates a UWB receiver 100 in accordance with aspects of the present disclosure. The UWB receiver 100 includes an analog-to-digital converter (ADC) 102 for converting an analog input signal (e.g., a UWB signal) to the digital domain to create a digital input signal. The sampling rate of the ADC 102 should be at least twice the highest relevant frequency in the received signal. For example, if an analog signal including relevant frequencies of 40 - 1240 MHz in the time domain is received, a 2.56 GHz 12-bit ADC can be used to convert the analog input signal to a digital input signal.

[0021] The ADC 102 feeds both the window function 104 and the first FFT 106. The first FFT 106 converts the digital input signal to a frequency input signal and bins the frequency input signal using a threshold to create a binary filter 108.

[0022] The window function 104 distributes the digital input signal over time into a number of registers (e.g., eight twelve-bit registers, where the output of one of the eight twelve-bit registers feeds the subsequent twelve-bit register). For example, a 32768-point window function can store eight samples of 4096 bits of data (e.g., the output of the 12-bit ADC described above) over time and shift that data through the eight samples (e.g., 4096 bits of data from register_3 are shifted to register_4, register_4 is shifted to register_5, and so on).

[0023] The window function 104 feeds into the first classifier 110, which classifies the digital input signal from the window function 104 into bins. For example, the Chinese Remainder Theorem can be used in this classification process (binning process). For example, twelve consecutive digitized information foci are stored in bins with four information foci each.

[0024] The second FFT 112 (having the same number of points as the number of points of the first FFT 106) converts the classified digital input signal into an intermediate frequency signal. For example, if the first FFT 106 is a 4096-point FFT, then the second FFT 112 is a 4096-point FFT. The first FFT 106 and the second FFT 112 can be implemented in hardware (e.g., field programmable gate arrays, application specific integrated circuits, etc.), software running on a processor (e.g., graphics processing unit, other processors), or both.

[0025] The output of the second FFT 112 feeds into the second classifier 114, which classifies the intermediate frequency signal (i.e., the output of the second FFT) into designated bins.

[0026] (Via the multiplier 116) The binned intermediate frequency signal is multiplied by a binary filter to find the output signals, and error correction is performed on these output signals in the error correction 116. Then, the output signals pass through the ultra-wideband frequency detector 120 to detect the signal of interest in the received ultra-wideband signal.

[0027] Figure 2 The flowchart of the process 200 for detecting a signal in an ultra-wideband signal is illustrated. At 202, the received analog input signal is converted to the digital domain using an analog-to-digital converter (thus creating a digital input signal). At 204, the first FFT converts the digital input signal into a frequency input signal. In several embodiments, as discussed above, the digital input signal is also windowed using a window function. The FFT can be implemented in hardware (e.g., field programmable gate arrays, application specific integrated circuits, etc.), software running on a processor (e.g., graphics processing unit, other processors), or both.

[0028] At 206, the frequency input signal is binned based on frequency and a threshold to create a binary filter.

[0029] At 208, the digital input signal from step 202 (which, as discussed above, can be windowed) is classified into bins. For example, the Chinese Remainder Theorem can be used to assign the digital input signal to bins. At 210, a number of points equal to the number of points of the first FFT are collected from the bins, and at 212, the collected points are passed through a second FFT to convert the digital input signal into an intermediate frequency signal. For example, if the FFT is 4096 points, 4096 blocks of data are used. At 214, the intermediate frequency signal is classified into bins, and at 216 it is multiplied using the binary filter from step 206, which creates an output signal that can be further error corrected.

[0030] Accordingly, process 200 produces a signal that indicates the signals and frequencies carried by those frequencies in the ultra-wideband signal. This process 200 can be used Figure 1 in a receiver for military applications and the like. In some embodiments, the first FFT and the second FFT are part of an FFT system that includes two FFTs. In various embodiments, the first FFT and the second FFT are part of an FFT system that includes one FFT, such that the first FFT and the second FFT are the same FFT.

[0031] In an ultra-wideband (UWB) signal, using computationally intensive FFT activities to prepare for processing millions of points of data poses challenges. Applying Meager FFT requires a different emphasis of the SFFT algorithm, while Smart FFT requires a loop.

[0032] An important ability of advanced wideband beneficiaries is the identification of ultra-weak different signals with high frequency accuracy and high uniqueness. In any case, it should be possible to extend the FFT length from 256 foci to 4096. Many receivers use a 256-point FFT length for signal location. In the ongoing history, several algorithms for signal detection have been proposed. It is proposed in nuclear degradation receptors. Again, configurable receivers identify various signals before having different data arrangements. However, existing algorithms or systems are not sufficiently suitable for precisely distinguishing numerous signals. In addition, they offer lower processing and transmission speeds, thus making them extremely inefficient for precise signal detection. Currently, the development of GPUs, which are recommended as speed-up devices in many applications such as DNA sequencing, digital receivers, image processing algorithms, astrophysics, communication systems, and more, has prompted consideration of using GPUs to perform this work. In this article, a Smart and Ingenious FFT (SFFT) method that only uses an information library is proposed. Consider using a Tesla K40a GPU for execution. The FFT in the GPU is done by NVIDIA using the CuFFT library.

[0033] Ultra-wideband (UWB) is not a conventional narrowband radio. It is a long-range advanced communication framework that uses short bursts. Given the large transmission of signal data, UWB ensures low-power execution with high throughput and fine time targeting at short intervals without interfering with other existing long-range communication frameworks.

[0034] Beneficiaries include broadband low-noise amplifiers (LNAs), wide-tuning systems, range bandpass filters (BPFs), and dual-balanced channels. It also includes a Gilbert mixer for down-converting RF signals to quadrature zero IF.

[0035] At the heart of the SFFT algorithm is the implementation of FFT electronic data. FFT is a key part of the signal processing method. A formal description of the fast Fourier transform can be found in many articles and books

[18] . To group the f(x) electronic data, the Fourier transform produces I(X). The length of the FFT characterizes the size of the transform (N). The relationship is presented as follows:

[0036]

[0037] where k ranges from 0 to N - 1, f(x) = (x0, x1,... xN-1) is the digitized spatio-temporal information, and I(X) = (X0, X1,... XN-1) shows the transformed frequency-domain data. Each block of the SFFT is described below as Figure 4 shown.

[0038] A. FFT Binary Filter: Test information from the front end of the computer collector is extracted from the 2.56 GHz ADC sampler for 12.8 μs. The paired channels consist of 1 and 0.

[0039] B. Bucketing: The Chinese Remainder Theorem is included in the bucketing process. For example, 12 consecutive digitized information focuses are stored in a bucket, and the bucket has 4 information focuses. In this way, the set consists of {1, 6, 11, and 4}, which is labeled in Figure 3 as.

[0040] C. SFFT Binary Filter: The undersampled set is processed with a 4,096-point fast Fourier transform. For starters, any frequency receiver on the edge is an identified signal. Next, nearby spiky receiver buckets are removed from the SFFT channel.

[0041] Single-signal detection

[0042] Due to binning, the signal frequencies are correlated. A layout technique for re - establishing the area value of a 4,096 FFT is included later. Compared with the main FFT, the modified range shows a sufficient estimate of the recurrence of the canisters. The difference in richness (60 - 50 = 15 dB) between the FFT and the SFFT continues into the subsequent recurrence error correction phase.

[0043] Experimental results (UWB)

[0044] To reduce the power usage of a simple analog - to - digital conversion framework, an analog pre - processing stage is proposed before the asynchronous converter to discover the information values that generally need to be changed for a given application. Due to the situation where the information esteem was not known before, the simple pre - processing triggers the asynchronous converter for sampling, and the timing of the auto - converter measures the time period between samples. By changing only the required information values, the framework can save a significant amount of power both at the change stage and down the signal. The detection of an accurate signal requires a high separation between noise and signal quality. Although, based on the fact of Fourier - transform limitations, frequencies that are not on the digital receiver can be accurately distinguished. Frequency error assessment is of great significance. A replay was completed where the input frequency, which grows to 1 MHz, ranges from 40 MHz to 1240 MHz. The change in adequacy discrimination with frequency growth is also additionally shown in the side view. When the information frequency is on an integer container, the adequacy of discrimination is 0. For frequency errors of ±0.125 MHz and ±0.25 MHz respectively, the relative adequacy contrast is approximately 12.5 dB and 15 dB. The FFT cannot separate two signals that are close to each other. A collector based on SFFT can accurately distinguish two signals that have a small frequency partition (1 frequency bin) and no power, with a signal quality 19 dB below the commotion floor.

[0045] Consider two adjacent information signals, one is a reliable signal and the other is a weak signal. The reliable signal has an 11 dB SNR at 187.653125 MHz (bin 300.234); the weak signal has a 19 dB SNR at 188.903125 MHz (bin 302.234).

[0046] Figure 5Aindicates that it is difficult to identify the input signal from the FFT. As indicated by the first part of the SFFT pseudonym, in any case, there are 9 separate bins for an undersampling rate of 9. It was observed that after the dynamic loop, the detected signals were 187.222255 MHz (bin 299.5556) and 188.611125 MHz (bin 301.7778), and the frequency errors were 0.424 MHz and 0.28512 MHz respectively. The wide discrimination 10 dB signal error for 188.611125 MHz was reduced from 0.125 MHz to 0.16012 MHz. This model shows a 30 dB dual-signal information range, 2 receiver partitions, and an undersampling rate of 9 ({32,768 / 4096}+1). Additionally, as Figure 5C shown, parallel channels were created in the appropriate area. Figure 5B is the FFT spectrum.

[0047] The proposed SFFT-based receiver was verified by using 5 synchronous information signals, where almost 1 frequency bin was separated. It was found that the reported frequency error was less than 0.625 MHz (1 frequency receiver), where the 5-signal information range was 30 dB. The SFFT frequency receiver for discriminating SNR, the identified frequencies, and the identified frequency errors were reported. In this case, the most reliable (grounded) signal had an SNR of 11 dB, while the most vulnerable signal had an SNR of -19 dB, and the other three signals had an SNR of -15 dB. As Figure 6A shown, three signals were observed using the standard FFT. The sufficiency of the subsequent frequencies was much smaller, and the power of the FFT was within the main lobe of the strong signal. In this way, the FFT could not distinguish between two low-quality frequencies close to the reliable signal. However, as Figure 6B shown, after binning, all five frequencies were clearly separated by their amplitudes.

[0048] It is worth remembering that the dynamic loop problem is much smaller than that of any receiver's algorithm. The measured runtime by the hardware staff was 0.175 ms. The computational constraint was 0.11 ms for 4096 FFT activities in the Tesla K40c GPU.

[0049] As discussed above, embodiments of the SFFT can be used in any application that requires a transformation from one domain to another (e.g., frequency) domain or other cross-correlation calculations. For example, in DNA sequencing, a conventional FFT or discrete Fourier transform (DFT) can be used to perform correlation processing on DNA sequencing in log-linear complexity (O(n log n)) time. Thus, a Fourier transform (e.g., an embodiment of the SFFT disclosed herein) can be used for DNA sequencing.

[0050] ReferenceFigure 7 , depicts a block diagram of a data processing system (i.e., a computer system) in accordance with the present invention. The data processing system 700 may include a symmetric multiprocessor (SMP) system or other configurations including a plurality of processors 710 connected to a system bus 730. Alternatively, a single processor 710 may be employed. Local memory 720 is also connected to the system bus 730. An I / O bus bridge 740 is connected to the system bus 730 and provides an interface to an I / O bus 750. The I / O bus may be used to support one or more buses and corresponding devices 770, such as memory 760, removable media memory 770, input / output devices (I / O devices) 780, network adapters 790, and the like. The network adapter may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices via an intervening private or public network.

[0051] Devices such as a graphics adapter, memory, and computer-usable storage media having computer-usable program code embodied thereon may also be connected to the I / O bus. The computer-usable program code may be executed to implement any aspect of the present invention, e.g., to implement any aspect of any method and / or system component described herein.

[0052] As will be understood by those skilled in the art, aspects of the present disclosure may be implemented as a system, method, or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.) or an embodiment combining software and hardware aspects, which are generally referred to herein as “circuitry,” “module,” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product including computer readable program code embodied in one or more computer readable storage media.

[0053] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A computer storage medium does not include a propagated signal.

[0054] A computer-readable signal medium may include a propagated data signal having computer-readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including but not limited to electromagnetic, optical, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium that is not a computer-readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0055] The program code embodied on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0056] The computer program code for performing the operations of aspects of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, Smalltalk, C++, etc., and conventional procedural programming languages such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network connection, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the use of a network service provider's network).

[0057] Aspects of the present disclosure are described with reference to the flowchart illustrations and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of other programmable data processing apparatuses or a general-purpose computer, a special-purpose computer to produce a machine, such that the instructions executed via the processor of other programmable data processing apparatuses or a computer create a means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0058] These computer program instructions can also be stored in a computer-readable medium that can direct a computer, other programmable data processing apparatuses, or other devices to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture including instructions for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0059] The computer program instructions can also be loaded onto a computer, other programmable data processing apparatuses, or other devices to perform a series of operational steps on the computer, other programmable apparatuses, or other devices to produce a computer-implemented process, such that the instructions executed on the computer or other programmable apparatuses provide a process for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0060] The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of code that includes one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, depending on the functionality involved, two blocks shown in succession may actually be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by a dedicated system based on hardware for performing the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0061] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to limit the invention. Unless the context clearly dictates otherwise, the singular forms "a" and "the" as used herein are also intended to include the plural forms. It will also be understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0062] The corresponding structures, materials, acts, and equivalents of all means or step-plus-function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The aspects of the present disclosure were chosen and described in order to best explain the principles of the invention and its practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A method for finding a signal within a frequency range, the method comprising: converting a digital input signal into a frequency input signal using a first fast Fourier transform (FFT) having a plurality of points; binning the frequency input signal into bins based on frequency and a threshold to create a binary filter; classifying the digital input signal into containers; collecting from the containers a number of points equal to the number of points of the first FFT; converting the digital input signal into a frequency intermediate signal using a second FFT having a number of points equal to the number of points of the first FFT; classifying the frequency intermediate signal into bins; using the binary filter to select bins of interest from the bins to create an output frequency signal from the bins of interest.

2. The method according to claim 1, wherein, classifying the digital input signal into containers is performed using the Chinese Remainder Theorem.

3. The method according to claim 1, wherein, using the binary filter to select bins of interest from the bins to create an output frequency signal further includes an error correction algorithm.

4. The method according to claim 1, wherein the first FFT and the second FFT are implemented by a graphics processing unit.

5. The method according to claim 1, wherein the first FFT and the second FFT are implemented in hardware.

6. The method according to claim 5, wherein the second FFT is the first FFT.

7. The method according to claim 1, further comprising: converting an analog input signal into the digital domain using an analog-to-digital converter to create the digital input signal.

8. The method according to claim 1, further comprising: retrieving DNA sequencing data as the digital input signal.

9. The method according to claim 1, further comprising: receiving a digital input from a neural network.

10. The method according to claim 1, further comprising: receiving an analog signal from a communication network; and converting the analog input signal into the digital domain using an analog-to-digital converter to create the digital input signal.

11. An ultra-wideband receiver, comprising: an analog-to-digital converter that converts an analog input signal into a digital input signal; and a processor coupled to the analog-to-digital converter, wherein the processor performs: converting the digital input signal into a frequency input signal using a first fast Fourier transform (FFT) having a plurality of points, binning the frequency input signal into bins based on frequency and a threshold to create a binary filter, classifying the digital input signal into containers, collecting from the containers a number of points equal to the number of points of the first FFT, converting the digital input signal into a frequency intermediate signal using a second FFT having a number of points equal to the number of points of the first FFT, classifying the frequency intermediate signal into bins, using the binary filter to select bins of interest from the bins to create an output frequency signal from the bins of interest.

12. The ultra-wideband receiver according to claim 11, wherein, Classifying the digital input signal into bins is performed using the Chinese Remainder Theorem.

13. The ultra-wideband receiver according to claim 11, wherein using the binary filter to select the bins of interest in the bins to create an output frequency signal from the bins of interest further includes an error correction algorithm.

14. The ultra-wideband receiver according to claim 11, wherein the processor is a graphics processing unit.

15. An ultra-wideband receiver comprising: an analog-to-digital converter that converts an analog input signal into a digital input signal; a processor coupled to the analog-to-digital converter; a fast Fourier transform (FFT) system implemented in hardware; wherein: the FFT includes a plurality of points, and the FFT converts the digital input signal into a frequency input signal; the processor: bins the frequency input signal into bins based on frequency and a threshold to create a binary filter, classifies the digital input signal into bins, collects a number of points equal to the number of points of a first FFT from the bins; the FFT converts the digital input signal into a frequency intermediate signal; and the processor further: bins the frequency intermediate signal into bins, uses the binary filter to select the bins of interest in the bins to create an output frequency signal from the bins of interest.

16. The ultra-wideband receiver according to claim 15, wherein, classifying the digital input signal into bins is performed using the Chinese Remainder Theorem.

17. The ultra-wideband receiver according to claim 15, wherein using the binary filter to select the bins of interest in the bins to create an output frequency signal from the bins of interest further includes an error correction algorithm.

18. The ultra-wideband receiver according to claim 15, wherein the processor is a graphics processing unit.

19. The ultra-wideband receiver according to claim 15, wherein the FFT system includes one FFT.

20. The ultra-wideband receiver according to claim 15, wherein the FFT system includes two FFTs.

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