Display substrate, display panel and display device
Patent Information
- Application Number
- CN202380010924.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-26
- Publication Date
- 2025-06-13
AI Technical Summary
It is difficult for existing display technology to achieve a narrow-frame display screen, and the frame size is getting bigger and bigger, which affects the overall appearance and user experience of the display screen.
By setting a plurality of fan-out units on the display substrate, the first fan-out line and the second fan-out line are set on the different layer, and by adjusting the number and arrangement period of the fan-out line, the fan-out width of the fan-out area is reduced, thereby reducing the frame size.
It realizes the reduction of the border size of the display screen, improving the overall appearance and user experience of the display screen, and simplifying the design process.
Smart Images
Figure CN120153776A_ABST
Abstract
Description
Display substrate, display panel, and display device Technical Field
[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art
[0002] With the continuous development of display technology, the market has higher and higher requirements for display screens, for example, requiring the border size of display screens to be smaller and smaller.
[0003] Overview
[0004] The present disclosure provides a display substrate, comprising a base substrate, and a display area and a non-display area provided on one side of the base substrate, wherein the non-display area is located on at least one side of the display area;
[0005] The display area includes: a plurality of scan lines extending along a first direction, and a plurality of data lines extending along a second direction;
[0006] The non-display area includes a fan-out area, the fan-out area includes a plurality of fan-out units periodically arranged along a third direction, the fan-out units include a first fan-out line and a second fan-out line arranged in different layers, the plurality of first fan-out lines and the plurality of second fan-out lines are all arranged along the third direction, and the third direction intersects the first direction and the second direction respectively;
[0007] In the same fan-out unit, the number of the first fan-out lines is greater than the number of the second fan-out lines.
[0008] In some embodiments, in the same fan-out unit, the number of the second fan-out lines is 1, and the ratio of the number of the first fan-out lines to the number of the second fan-out lines is an integer greater than or equal to 2; or
[0009] In the same fan-out unit, the number of the second fan-out lines is greater than or equal to 2, and the ratio of the number of the first fan-out lines to the number of the second fan-out lines is a non-integer greater than 1.
[0010] In some embodiments, in the same fan-out unit, the sum of the number of the first fan-out lines and the number of the second fan-out lines is greater than or equal to 3 and less than or equal to 15.
[0011] In some embodiments, in the same fan-out unit, a difference between the number of the first fan-out lines and the number of the second fan-out lines is greater than or equal to 1 and less than or equal to 10.
[0012] In some embodiments, the first fan-out line includes a first sub-fan-out line, the second fan-out line includes a second sub-fan-out line, and in an orthographic projection on the substrate, the first sub-fan-out line is located within the range of the second sub-fan-out line; and
[0013] In an orthographic projection on the substrate, the first sub-fan-out line is centrally arranged in the third direction within the range of the second sub-fan-out line; or
[0014] In an orthographic projection on the substrate, boundaries of the first sub-fan-out line and the second sub-fan-out line located on the same side are substantially flush.
[0015] In some embodiments, the first fan-out line further includes a third sub-fan-out line, and in an orthographic projection on the substrate, the third sub-fan-out line does not overlap with the second fan-out line; and
[0016] At least one of the third sub-fan-out lines and the first sub-fan-out lines are arranged alternately along the third direction.
[0017] In some embodiments, the second fan-out line further includes a fourth sub-fan-out line, and in an orthographic projection on the substrate, the fourth sub-fan-out line partially overlaps with one of the first fan-out lines; and
[0018] A plurality of the fourth sub-fan-out lines and the second sub-fan-out lines are alternately arranged along the third direction.
[0019] In some embodiments, the first fan-out line further includes a third sub-fan-out line, and in an orthographic projection on the substrate, the third sub-fan-out line does not overlap with the second fan-out line; and
[0020] A first number of the third sub-fan-out lines are arranged between two adjacent fourth sub-fan-out lines, a second number of the third sub-fan-out lines are arranged between the second sub-fan-out line and the fourth sub-fan-out line, and the sum of the first number and the second number is an odd number.
[0021] In some embodiments, the second fan-out line further includes a fifth sub-fan-out line. In the orthographic projection on the substrate, the fifth sub-fan-out line is centered between two adjacent first fan-out lines, and the fifth sub-fan-out line has no overlap or partial overlap with the two adjacent first fan-out lines.
[0022] In some embodiments, in an orthographic projection on the substrate, the fifth sub-fan-out line is centrally disposed between two adjacent second sub-fan-out lines.
[0023] In some embodiments, the first fan-out line further includes a third sub-fan-out line, and in an orthographic projection on the substrate, the third sub-fan-out line does not overlap with the second fan-out line; and
[0024] In an orthographic projection on the substrate, the same number of third sub-fan-out lines are arranged between the second sub-fan-out lines and the fifth sub-fan-out lines.
[0025] In some embodiments, the second fan-out line further includes:
[0026] a fourth sub-fan-out line, wherein in an orthographic projection on the substrate, the fourth sub-fan-out line partially overlaps with one of the first fan-out lines;
[0027] The second sub-fan-out line, the fifth sub-fan-out line and the fourth sub-fan-out line are alternately arranged in sequence.
[0028] In some embodiments, the first fan-out line and the second fan-out line both extend along a fourth direction, and an angle between the fourth direction and the first direction is greater than or equal to 3° and less than or equal to 20°.
[0029] In some embodiments, the first fan-out line is located between the base substrate and the second fan-out line;
[0030] The non-display area also includes: a plurality of transparent traces arranged along the third direction and separated from each other, located on the side of the second fan-out line away from the base substrate, and the orthographic projection of the transparent traces on the base substrate completely covers the orthographic projection of the second fan-out line on the base substrate.
[0031] In some embodiments, the non-display area further includes:
[0032] a binding area, located on a side of the fan-out area away from the display area, comprising a plurality of pins arranged along the first direction, wherein the first fan-out line and the second fan-out line are connected to different pins;
[0033] The plurality of pins include at least one of the following:
[0034] A first pin is provided on the same layer as the first fan-out line and is connected to the first fan-out line;
[0035] A second pin is provided on the same layer as the second fan-out line and is connected to the second fan-out line;
[0036] A third pin is provided on the same layer as the first fan-out line and is connected to the second fan-out line;
[0037] a fourth pin, provided at the same layer as the second fan-out line and connected to the first fan-out line; and
[0038] The fifth pin includes a first pattern and a second pattern that are stacked and connected to each other, the first pattern is arranged on the same layer as the first fan-out line, the second pattern is arranged on the same layer as the second fan-out line, and the fifth pin is connected to the first fan-out line or the second fan-out line.
[0039] In some embodiments, the line width of the second fan-out line is greater than or equal to the line width of the first fan-out line, and the distance between two adjacent second fan-out lines is greater than or equal to the distance between two adjacent first fan-out lines.
[0040] In some embodiments, the first fan-out line and the second fan-out line are connected to different data lines respectively; or
[0041] The display area further includes a plurality of touch lines extending along the second direction, the first fan-out lines are connected to the data lines or the touch lines, and the second fan-out lines are connected to the data lines or the touch lines.
[0042] In some embodiments, the scan line is located between the base substrate and the data line, the first fan-out line and the scan line are arranged on the same layer, and the second fan-out line and the data line are arranged on the same layer.
[0043] The present disclosure provides a display panel, comprising: a cell substrate, a liquid crystal layer, and a display substrate as described in any embodiment, wherein the liquid crystal layer is located between the cell substrate and the display substrate, and the display area and the non-display area are arranged close to the liquid crystal layer.
[0044] The present disclosure provides a display device, comprising:
[0045] The display panel according to any one of the embodiments; and
[0046] A driving chip is bound and connected to the non-display area of the display substrate, and is used to drive the display panel to display.
[0047] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.
[0048] BRIEF DESCRIPTION OF THE DRAWINGS
[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.
[0050] FIG1 exemplarily shows a schematic planar structural diagram of a display substrate provided by the present disclosure;
[0051] 2 to 13a exemplarily show circuit layout diagrams and cross-sectional structural diagrams of the first to twelfth fan-out areas;
[0052] FIG13 b exemplarily shows a circuit layout diagram and a cross-sectional structure diagram of a thirteenth fan-out region;
[0053] FIG14 exemplarily shows the routing data of the first to twelfth fan-out areas;
[0054] 15 to 17 exemplarily show schematic diagrams of three pin connection methods.
[0055] 18 and 19 exemplarily show cross-sectional structural diagrams of two fan-out regions in the related art;
[0056] 20 , a schematic diagram of a preparation process of a display substrate is exemplarily shown.
[0057] Detailed description
[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.
[0059] 1 , a schematic diagram of a planar structure of a display substrate is exemplarily shown. As shown in FIG1 , the display substrate includes a base substrate 11 (not shown in FIG1 ), and a display area AA and a non-display area BZ arranged on one side of the base substrate 11. The non-display area BZ is located on at least one side of the display area AA.
[0060] The non-display area BZ is located on one side, two sides, three sides, or four sides of the display area AA. For example, in FIG1 , the non-display area BZ is located on the lower side of the display area AA.
[0061] As shown in FIG. 1 , the display area AA includes a plurality of scan lines SC extending along a first direction f1 and a plurality of data lines DT extending along a second direction f2 .
[0062] As shown in Figure 1, the non-display area BZ includes a fan-out area FA. The fan-out width x of the fan-out area FA along the second direction f2 has a significant impact on the bezel size. The fan-out width x can be calculated according to the following formula: x = n*P3*tanα, where n represents the number of fan-out lines in the fan-out area FA, α represents the angle between the fan-out lines in the fan-out area FA and the first direction f1, and P3 represents the average arrangement period of a single fan-out line in the fan-out area FA. The average arrangement period P3 = w / n, and w is the size of the fan-out area FA along the direction in which the multiple fan-out lines are arranged (the direction f3 shown in Figure 1).
[0063] According to the above formula, it can be found that reducing the average arrangement period P3 of a single fan-out line in the fan-out area FA can reduce the fan-out width x, thereby reducing the border.
[0064] 2 to 13 a , twelve structural diagrams of fan-out areas FA are exemplarily shown. As shown in any one of FIG. 2 to 13 a , the fan-out area FA includes a plurality of fan-out units UT periodically arranged along a third direction f3. The fan-out unit UT includes a first fan-out line 22 and a second fan-out line 23 arranged in different layers. The plurality of first fan-out lines 22 and the plurality of second fan-out lines 23 are all arranged along the third direction f3, and the third direction f3 intersects the first direction f1 and the second direction f2, respectively.
[0065] In the same fan-out unit UT, the number S2 of the first fan-out lines 22 is greater than the number S1 of the second fan-out lines 23 .
[0066] That is, in the same fan-out unit UT, the number of first fan-out lines 22 and second fan-out lines 23 is not one-to-one corresponding, but multiple first fan-out lines 22 correspond to one or more second fan-out lines 23 .
[0067] Exemplarily, in the same fan-out unit UT, the number S1 of the second fan-out lines 23 is greater than or equal to 1, and the number S2 of the first fan-out lines 22 is greater than or equal to 2.
[0068] In the present disclosure, the arrangement period of the fan-out unit UT = the number S1 of the second fan-out lines 23 * the arrangement period of the second fan-out lines 23 = the number S2 of the first fan-out lines 22 * the arrangement period of the first fan-out lines 22. Since the number S2 of the first fan-out lines 22 is greater than the number S1 of the second fan-out lines 23 in the same fan-out unit UT, the arrangement period of the first fan-out lines 22 is smaller than the arrangement period of the second fan-out lines 23.
[0069] Since the first fan-out lines 22 and the second fan-out lines 23 are arranged in different layers, they can be prepared using different masks. By properly designing the masks, the arrangement period of the first fan-out lines 22 can be made smaller than that of the second fan-out lines 23.
[0070] The present disclosure differentially arranges the arrangement periods of the first fan-out lines 22 and the second fan-out lines 23 , thereby reducing the average arrangement period P3 of each fan-out line in the fan-out unit UT, thereby reducing the fan-out width x of the fan-out area FA, reducing the frame size, and facilitating a narrow frame.
[0071] The display substrate provided by the present disclosure facilitates design simplification by providing a plurality of fan-out units UT arranged periodically along the third direction f3.
[0072] It should be noted that, in FIG. 2 to FIG. 13 a , the upper figure is a circuit layout diagram of the fan-out area, and the lower figure is a schematic diagram of the cross-sectional structure along the dotted arrow position in the fan-out area.
[0073] For example, as shown in Figures 2 to 13a, in the orthographic projection on the base substrate 11, the second fan-out line 23 can completely cover the first fan-out line 22, the first fan-out line 22 and the second fan-out line 23 can partially overlap, or the first fan-out line 22 and the second fan-out line 23 can also not overlap, which is not limited in the present disclosure.
[0074] Exemplarily, the first fan-out lines 22 may be prepared using a phase-shift mask, which is advantageous for preparing the first fan-out lines 22 with a smaller arrangement period.
[0075] Exemplarily, the arrangement period of the first fan-out lines 22 may be greater than or equal to 4 micrometers and less than or equal to 6 micrometers, such as 4.5 micrometers.
[0076] Exemplarily, the second fan-out line 23 may be prepared by using a half-tone mask.
[0077] Exemplarily, the arrangement period of the second fan-out lines 23 may be greater than or equal to 6 micrometers and less than or equal to 25 micrometers.
[0078] Exemplarily, the plurality of first fan-out lines 22 are arranged at equal intervals along the third direction f3.
[0079] Exemplarily, the plurality of second fan-out lines 23 are arranged at equal intervals along the third direction f3.
[0080] Exemplarily, in the same fan-out unit UT, the number S2 of the first fan-out lines 22 and the number S1 of the second fan-out lines 23 are both positive integers.
[0081] In some embodiments, in the same fan-out unit UT, the number S1 of the second fan-out lines 23 is 1, and the ratio of the number S2 of the first fan-out lines 22 to the number S1 of the second fan-out lines 23 is an integer greater than or equal to 2.
[0082] Exemplarily, the number S2 of the first fan-out lines 22 is 2, 3, 4, 5, 6, 7, 8, 9 or 10, etc.
[0083] In some embodiments, in the same fan-out unit UT, the number S1 of the second fan-out lines 23 is greater than or equal to 2, and the ratio of the number S2 of the first fan-out lines 22 to the number S1 of the second fan-out lines 23 is a non-integer greater than 1.
[0084] That is, in the same fan-out unit UT, the number S1 of the second fan-out lines 23 is greater than or equal to 2, and the number S2 of the first fan-out lines 22 cannot be divided evenly by the number S1 of the second fan-out lines 23 .
[0085] For example, as shown in FIG. 14 a , in the same fan-out unit UT, the number S1 of the second fan-out lines 23 is 2, and the number S2 of the first fan-out lines 22 is an odd number such as 3, 5, 7 or 9.
[0086] For example, as shown in FIG. 14 a , in the same fan-out unit UT, the number S1 of the second fan-out lines 23 is 3, and the number S2 of the first fan-out lines 22 is 4, 5, 7, 8 or 10, etc.
[0087] For example, as shown in FIG. 14 a , in the same fan-out unit UT, the number S1 of the second fan-out lines 23 is 4, and the number S2 of the first fan-out lines 22 is 5, 6, 7, 9 or 10, etc.
[0088] In some implementations, in the same fan-out unit UT, the sum of the number S2 of the first fan-out lines 22 and the number S1 of the second fan-out lines 23 is greater than or equal to 3 and less than or equal to 15.
[0089] 14 a, in the same fan-out unit UT, the sum of the number S2 of the first fan-out lines 22 and the number S1 of the second fan-out lines 23 is 3, 4, 5, 7, 8, 9, 10, 11 or 13, etc.
[0090] In some embodiments, in the same fan-out unit UT, a difference between the number S2 of the first fan-out lines 22 and the number S1 of the second fan-out lines 23 is greater than or equal to 1 and less than or equal to 10.
[0091] For example, as shown in FIG. 14 a , in the same fan-out unit UT, the difference between the number S2 of the first fan-out lines 22 and the number S1 of the second fan-out lines 23 is 1, 2, 3, 4, 5 or 7, etc.
[0092] In some embodiments, the line width of the second fan-out line 23 is greater than or equal to the line width of the first fan-out line 22 , and the distance between two adjacent second fan-out lines 23 is greater than or equal to the distance between two adjacent first fan-out lines 22 .
[0093] The distance between two adjacent first fan-out lines 22 = the arrangement period of the first fan-out lines 22 - the line width of the first fan-out lines 22 . The distance between two adjacent second fan-out lines 23 = the arrangement period of the second fan-out lines 23 - the line width of the second fan-out lines 23 .
[0094] Exemplarily, the line width of the first fan-out line 22 is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers. For example, the line width of the first fan-out line 22 is 0.8 micrometers, 1.3 micrometers, 2.3 micrometers, or 2.5 micrometers.
[0095] Exemplarily, the line width of the second fan-out line 23 is greater than or equal to 0.8 micrometers and less than or equal to 10 micrometers. For example, the line width of the second fan-out line 23 is 1.3 micrometers, 5 micrometers, or 9 micrometers.
[0096] In some embodiments, the scan lines SC are located between the base substrate 11 and the data lines DT. The first fan-out lines 22 are provided on the same layer as the scan lines SC, and the second fan-out lines 23 are provided on the same layer as the data lines DT. Thus, the first fan-out lines 22 are located on the side of the second fan-out lines 23 closer to the base substrate 11, which facilitates the preparation of a smaller arrangement period of the first fan-out lines 22.
[0097] Exemplarily, the display substrate includes a base substrate 11, and a first metal layer gate, a gate insulating layer GI, an active layer ACT, a second metal layer SD, a first transparent electrode layer 1ITO, a passivation layer PVX, and a second transparent electrode layer 2ITO, which are sequentially stacked on one side of the base substrate 11. The first metal layer gate is disposed adjacent to the base substrate 11. FIG20 shows a schematic diagram of the manufacturing process of the display substrate. The gate insulating layer GI and the passivation layer PVX share a PVX mask.
[0098] Illustratively, the first metal layer gate and the second metal layer SD are made of aluminum or molybdenum. The gate insulating layer GI and the passivation layer PVX are made of silicon nitride. The active layer ACT is made of a-Si. The first transparent electrode layer 1ITO and the second transparent electrode layer 2ITO are made of indium tin oxide.
[0099] Exemplarily, the scan line SC and the first fan-out line 22 are located in the first metal layer gate, and the data line DT and the second fan-out line 23 are located in the second metal layer SD.
[0100] For example, the active layer ACT and the second metal layer SD can be manufactured using the same half-tone mask. The arrangement period of the second fan-out lines 23 manufactured using the half-tone mask is generally greater than or equal to 10 micrometers.
[0101] In some embodiments, as shown in FIG. 2 to FIG. 13 a , the first fan-out lines 22 and the second fan-out lines 23 both extend along a fourth direction f4 , and the fourth direction f4 intersects with the first direction f1 and the second direction f2 .
[0102] By providing the first fan-out lines 22 and the second fan-out lines 23 parallel to each other, the aperture ratio of the fan-out area FA can be increased, thereby increasing the transmittance of incident light, which is beneficial for light curing of the frame sealant.
[0103] Exemplarily, the angle between the fourth direction f4 and the first direction f1 is greater than or equal to 3° and less than or equal to 20°.
[0104] In some embodiments, the first fan-out line 22 is located between the base substrate 11 and the second fan-out line 23 .
[0105] In some embodiments, as shown in FIG13b , the non-display area BZ further includes: a plurality of transparent traces 12 arranged along the third direction f3 and spaced apart from each other, located on the side of the second fan-out line 23 facing away from the base substrate 11, with the orthographic projections of the transparent traces 12 on the base substrate 11 completely covering the orthographic projections of the second fan-out line 23 on the base substrate 11. The transparent traces 12 can protect the second fan-out line 23.
[0106] By providing a plurality of transparent traces 12 separated from each other, short circuits can be avoided.
[0107] It should be noted that the plurality of transparent wirings 12 may also be interconnected to form a transparent electrode layer covering the entire surface, which is not limited in the present disclosure.
[0108] Exemplarily, the transparent trace 12 is located on the second transparent electrode layer 2ITO.
[0109] In some embodiments, as shown in any one of Figures 2 to 13a, the first fan-out line 22 includes a first sub-fan-out line 221, and the second fan-out line 23 includes a second sub-fan-out line 231. In the orthographic projection on the base substrate 11, the first sub-fan-out line 221 is located within the range of the second sub-fan-out line 231.
[0110] For ease of design, in some examples, as shown in any one of FIG. 2 to FIG. 13 a , in an orthographic projection on the base substrate 11 , the first sub-fan-out line 221 is substantially centered within the range of the second sub-fan-out line 231 in the third direction f3 .
[0111] That is, in the orthographic projection on the base substrate 11 , the symmetry axis of the first sub-fan-out line 221 along the fourth direction f4 substantially coincides with the symmetry axis of the second sub-fan-out line 231 along the fourth direction f4.
[0112] For ease of design, in other examples, as shown in FIG13 b , in the orthographic projection on the substrate 11 , the boundaries of the first sub-fan-out line 221 and the second sub-fan-out line 231 on the same side (the left side as shown in FIG13 b ) are substantially flush.
[0113] In some embodiments, as shown in FIG4 , FIG8 , or FIG11 , the first fan-out line 22 further includes a third sub-fan-out line 222 . In an orthographic projection on the substrate 11 , the third sub-fan-out line 222 does not overlap with the second fan-out line 23 . Furthermore, at least one third sub-fan-out line 222 is arranged alternately with the first sub-fan-out line 221 along the third direction f3 .
[0114] Exemplarily, as shown in FIG. 4 , a third sub-fan-out line 222 and a first sub-fan-out line 221 are alternately arranged along the third direction f3 .
[0115] Exemplarily, as shown in FIG8 , two third sub-fan-out lines 222 and the first sub-fan-out line 221 are alternately arranged along the third direction f3 .
[0116] Exemplarily, as shown in FIG11 , three third sub-fan-out lines 222 and the first sub-fan-out lines 221 are alternately arranged along the third direction f3.
[0117] In some embodiments, as shown in FIG2 , FIG3 , FIG5 , or FIG9 , the second fan-out line 23 further includes a fourth sub-fan-out line 232. In an orthographic projection on the base substrate 11, the fourth sub-fan-out line 232 partially overlaps with one of the first fan-out lines 22. Furthermore, a plurality of fourth sub-fan-out lines 232 and the second sub-fan-out lines 231 are alternately arranged along the third direction f3.
[0118] Exemplarily, as shown in FIG. 2 , FIG. 3 , FIG. 5 or FIG. 9 , two fourth sub-fan-out lines 232 and the second sub-fan-out lines 231 are alternately arranged along the third direction f3 .
[0119] In some embodiments, as shown in FIG2 , FIG3 , FIG5 , or FIG9 , the first fan-out line 22 further includes a third sub-fan-out line 222 . In an orthographic projection on the base substrate 11 , the third sub-fan-out line 222 does not overlap with the second fan-out line 23 . Furthermore, in an orthographic projection on the base substrate 11 , a first number of third sub-fan-out lines 222 are provided between two adjacent fourth sub-fan-out lines 232 , and a second number of third sub-fan-out lines 222 are provided between the second sub-fan-out line 231 and the fourth sub-fan-out line 232 , where the sum of the first number and the second number is an odd number.
[0120] 2 , one third sub-fan-out line 222 is provided between two adjacent fourth sub-fan-out lines 232, and zero third sub-fan-out lines 222 are provided between the second sub-fan-out line 231 and the fourth sub-fan-out line 232. That is, the first number is 1, the second number is 0, and the sum of the first and second numbers is 1.
[0121] 3 , there is no third sub-fan-out line 222 between two adjacent fourth sub-fan-out lines 232, and there is one third sub-fan-out line 222 between the second sub-fan-out line 231 and the fourth sub-fan-out line 232. That is, the first number is 0, the second number is 1, and the sum of the first and second numbers is 1.
[0122] 5 , one third sub-fan-out line 222 is provided between two adjacent fourth sub-fan-out lines 232, and two third sub-fan-out lines 222 are provided between the second sub-fan-out line 231 and the fourth sub-fan-out line 232. That is, the first number is 1, the second number is 2, and the sum of the first and second numbers is 3.
[0123] 9 , two third sub-fan-out lines 222 are provided between two adjacent fourth sub-fan-out lines 232, and three third sub-fan-out lines 222 are provided between the second sub-fan-out line 231 and the fourth sub-fan-out line 232. That is, the first number is 2, the second number is 3, and the sum of the first and second numbers is 5.
[0124] In some embodiments, as shown in Figures 6, 7, 10, 12 or 13a, the second fan-out line 23 also includes a fifth sub-fan-out line 233. In the orthographic projection on the base substrate 11, the fifth sub-fan-out line 233 is centered between the two adjacent first fan-out lines 22, and the fifth sub-fan-out line 233 has no overlap or partially overlaps with the two adjacent first fan-out lines 22.
[0125] 6 , in the orthographic projection on the base substrate 11 , two adjacent first fan-out lines 22 are symmetrically arranged on the left and right sides of the fifth sub-fan-out line 233 , and the two adjacent first fan-out lines 22 partially overlap with the fifth sub-fan-out line 233 .
[0126] Exemplarily, as shown in Figures 7, 10, 12 and 13a, in the orthographic projection on the base substrate 11, the two adjacent first fan-out lines 22 are symmetrically arranged on the left and right sides of the fifth sub-fan-out line 233, and the two adjacent first fan-out lines 22 have no overlap with the fifth sub-fan-out line 233.
[0127] In some embodiments, as shown in FIG. 6 , FIG. 10 , FIG. 12 , or FIG. 13 a , in an orthographic projection on the base substrate 11 , the fifth sub-fan-out line 233 is centrally disposed between two adjacent second sub-fan-out lines 231 .
[0128] As shown in Figures 6, 10, 12 or 13a, in the orthographic projection on the base substrate 11, the two adjacent second sub-fan-out lines 231 are symmetrically arranged on the left and right sides of the fifth sub-fan-out line 233, and the symmetry axis of the two adjacent second sub-fan-out lines 231 is approximately located at the position of the fifth sub-fan-out line 233.
[0129] In some embodiments, as shown in FIG6 , FIG10 , FIG12 , or FIG13 a , the first fan-out line 22 further includes a third sub-fan-out line 222 . In an orthographic projection on the base substrate 11 , the third sub-fan-out line 222 does not overlap with the second fan-out line 23 . Furthermore, in an orthographic projection on the base substrate 11 , the same number of third sub-fan-out lines 222 are spaced between the second sub-fan-out line 231 and the fifth sub-fan-out line 233 .
[0130] Exemplarily, as shown in FIG. 6 or FIG. 13 a , in an orthographic projection on the base substrate 11 , a third sub-fan-out line 222 is provided between adjacent second sub-fan-out lines 231 and fifth sub-fan-out lines 233 .
[0131] Exemplarily, as shown in FIG10 , in an orthographic projection on the base substrate 11 , three third sub-fan-out lines 222 are spaced apart between adjacent second sub-fan-out lines 231 and fifth sub-fan-out lines 233 .
[0132] Exemplarily, as shown in FIG12 , in an orthographic projection on the base substrate 11 , four third sub-fan-out lines 222 are spaced apart between adjacent second sub-fan-out lines 231 and fifth sub-fan-out lines 233 .
[0133] In some embodiments, as shown in FIG. 7 , the second fan-out line 23 includes a second sub-fan-out line 231 , a fourth sub-fan-out line 232 , and a fifth sub-fan-out line 233 , and the second sub-fan-out line 231 , the fifth sub-fan-out line 233 , and the fourth sub-fan-out line 232 are alternately arranged.
[0134] Exemplarily, as shown in Figures 2, 3, 5, 6, 7, 10, 12 and 13a, the first fan-out line 22 also includes a sixth sub-fan-out line 223, and in the orthographic projection on the base substrate 11, the second fan-out line 23 covers a portion of the sixth sub-fan-out line 223.
[0135] In some embodiments, as shown in FIG1 , the non-display area BZ further includes: a binding area BD, located on a side of the fan-out area FA away from the display area AA, including a plurality of pins PIN arranged along a first direction f1, and the first fan-out line 22 and the second fan-out line 23 are connected to different pins PIN.
[0136] Exemplarily, as shown in FIG. 15 or FIG. 16 , the plurality of pins PIN include: a first pin PIN1 , which is provided at the same layer as the first fan-out line 22 and is directly connected to the first fan-out line 22 .
[0137] Exemplarily, as shown in FIG. 15 or FIG. 16 , the plurality of pins PIN include: a second pin PIN2 , which is provided at the same layer as the second fan-out line 23 and is directly connected to the second fan-out line 23 .
[0138] Exemplarily, as shown in FIG16 , the plurality of pins PIN include: a third pin PIN3 , which is provided on the same layer as the first fan-out line 22 and is connected to the second fan-out line 23 via a via.
[0139] Exemplarily, as shown in FIG. 16 , the plurality of pins PIN include: a fourth pin PIN4 , which is provided on the same layer as the second fan-out line 23 and is connected to the first fan-out line 22 through a via.
[0140] Exemplarily, as shown in Figure 17, multiple pins PIN include: a fifth pin PIN5, including a first pattern 151 and a second pattern 152 that are stacked and interconnected, the first pattern 151 and the first fan-out line 22 are arranged on the same layer, the second pattern 152 and the second fan-out line 23 are arranged on the same layer, and the fifth pin PIN5 is directly connected to the first fan-out line 22 or the second fan-out line 23.
[0141] For example, the first pattern 151 and the second pattern 152 can be connected through vias on the insulating layer between the first pattern 151 and the second pattern 152 , or can be connected to the transparent trace 12 through vias to achieve connection between the first pattern 151 and the second pattern 152 .
[0142] In some embodiments, as shown in any one of FIG. 15 to FIG. 17 , the first fan-out line 22 and the second fan-out line 23 are connected to different data lines DT.
[0143] For example, as shown in any one of Figures 15 to 17 , the first fan-out line 22 has one end near the display area AA connected to the data line DT, and one end away from the display area AA connected to the pin PIN. The second fan-out line 23 has one end near the display area AA connected to the data line DT, and one end away from the display area AA connected to the pin PIN.
[0144] In some embodiments, the display area AA further includes a plurality of touch lines TC extending along the second direction f2 , the first fan-out lines 22 are connected to the data lines DT or the touch lines TC, and the second fan-out lines 23 are connected to the data lines DT or the touch lines TC.
[0145] Exemplarily, the touch lines TC and the data lines DT are disposed in the same layer.
[0146] For example, the first fan-out line 22 has an end near the display area AA connected to the data line DT or the touch line TC, and an end away from the display area AA connected to the pin PIN. The second fan-out line 23 has an end near the display area AA connected to the data line DT or the touch line TC, and an end away from the display area AA connected to the pin PIN.
[0147] The display substrate provided by the present disclosure is exemplarily described below with reference to FIG. 2 to FIG. 13 a and FIG. 14 .
[0148] For example, as shown in FIG2 , a fan-out unit UT includes four first fan-out lines 22 and three second fan-out lines 23. The four first fan-out lines 22 include a first sub-fan-out line 221, a sixth sub-fan-out line 223, a third sub-fan-out line 222, and a sixth sub-fan-out line 223, arranged sequentially along the third direction f3. The three second fan-out lines 23 include a second sub-fan-out line 231 and two fourth sub-fan-out lines 232, arranged sequentially along the third direction f3.
[0149] For example, as shown in FIG3 , a fan-out unit UT includes five first fan-out lines 22 and three second fan-out lines 23. The five first fan-out lines 22 include a first sub-fan-out line 221, a third sub-fan-out line 222, two sixth sub-fan-out lines 223, and a third sub-fan-out line 222, arranged sequentially along the third direction f3. The three second fan-out lines 23 include a second sub-fan-out line 231 and two fourth sub-fan-out lines 232, arranged sequentially along the third direction f3.
[0150] For example, as shown in FIG4 , a fan-out unit UT includes two first fan-out lines 22 and one second fan-out line 23. The two first fan-out lines 22 include a first sub-fan-out line 221 and a third sub-fan-out line 222 arranged sequentially along a third direction f3. The second fan-out line 23 includes a second sub-fan-out line 231.
[0151] For example, as shown in FIG5 , a fan-out unit UT includes seven first fan-out lines 22 and three second fan-out lines 23. The seven first fan-out lines 22 include: a first sub-fan-out line 221, a third sub-fan-out line 222, a sixth sub-fan-out line 223, two third sub-fan-out lines 222, a sixth sub-fan-out line 223, and a third sub-fan-out line 222, arranged sequentially along the third direction f3. The three second fan-out lines 23 include: a second sub-fan-out line 231 and two fourth sub-fan-out lines 232, arranged sequentially along the third direction f3.
[0152] For example, as shown in FIG6 , a fan-out unit UT includes five first fan-out lines 22 and two second fan-out lines 23. The five first fan-out lines 22 include a first sub-fan-out line 221, a third sub-fan-out line 222, two sixth sub-fan-out lines 223, and a third sub-fan-out line 222, arranged sequentially along the third direction f3. The two second fan-out lines 23 include a second sub-fan-out line 231 and a fifth sub-fan-out line 233, arranged sequentially along the third direction f3.
[0153] For example, as shown in FIG7 , a fan-out unit UT includes eight first fan-out lines 22 and three second fan-out lines 23. The eight first fan-out lines 22 include a first sub-fan-out line 221, four third sub-fan-out lines 222, a sixth sub-fan-out line 223, and two third sub-fan-out lines 222, arranged sequentially along the third direction f3. The three second fan-out lines 23 include a second sub-fan-out line 231, a fifth sub-fan-out line 233, and a fourth sub-fan-out line 232, arranged sequentially along the third direction f3.
[0154] For example, as shown in FIG8 , a fan-out unit UT includes three first fan-out lines 22 and one second fan-out line 23. The three first fan-out lines 22 include a first sub-fan-out line 221 and two third sub-fan-out lines 222 arranged sequentially along a third direction f3. The second fan-out line 23 includes a second sub-fan-out line 231.
[0155] For example, as shown in FIG9 , a fan-out unit UT includes ten first fan-out lines 22 and three second fan-out lines 23. The ten first fan-out lines 22 include: a first sub-fan-out line 221, two third sub-fan-out lines 222, a sixth sub-fan-out line 223, three third sub-fan-out lines 222, a sixth sub-fan-out line 223, and two third sub-fan-out lines 222, arranged sequentially along the third direction f3. The three second fan-out lines 23 include: a second sub-fan-out line 231 and two fourth sub-fan-out lines 232, arranged sequentially along the third direction f3.
[0156] For example, as shown in FIG10 , a fan-out unit UT includes seven first fan-out lines 22 and two second fan-out lines 23. The seven first fan-out lines 22 include one first sub-fan-out line 221 and six third sub-fan-out lines 222, which are arranged sequentially along the third direction f3. The two second fan-out lines 23 include one second sub-fan-out line 231 and one fifth sub-fan-out line 233, which are arranged sequentially along the third direction f3.
[0157] For example, as shown in FIG11 , a fan-out unit UT includes four first fan-out lines 22 and one second fan-out line 23. The four first fan-out lines 22 include a first sub-fan-out line 221 and three third sub-fan-out lines 222 arranged sequentially along a third direction f3. The second fan-out line 23 includes a second sub-fan-out line 231.
[0158] For example, as shown in FIG12 , a fan-out unit UT includes nine first fan-out lines 22 and two second fan-out lines 23. The nine first fan-out lines 22 include one first sub-fan-out line 221 and eight third sub-fan-out lines 222, which are arranged sequentially along the third direction f3. The two second fan-out lines 23 include one second sub-fan-out line 231 and one fifth sub-fan-out line 233, which are arranged sequentially along the third direction f3.
[0159] For example, as shown in FIG13a , a fan-out unit UT includes three first fan-out lines 22 and two second fan-out lines 23. The three first fan-out lines 22 include a first sub-fan-out line 221 and two third sub-fan-out lines 222, which are sequentially arranged along a third direction f3. The two second fan-out lines 23 include a second sub-fan-out line 231 and a fifth sub-fan-out line 233, which are sequentially arranged along the third direction f3.
[0160] 14 shows the number S1 of second fan-out lines 23, the number S2 of first fan-out lines 22, the arrangement period P1 of the first fan-out lines 22, the arrangement period P2 of the second fan-out lines 23, the total number S3 of the second fan-out lines 23 and the first fan-out lines 22, and the average arrangement period P3 of the fan-out lines included in a fan-out unit UT in the first to twelfth fan-out areas FA.
[0161] As shown in FIG14 , in the fan-out area FA shown in FIG2 , FIG13 a , and FIG3 to FIG12 , the average arrangement period P3 of the fan-out lines increases successively.
[0162] When the arrangement period P1 of the first fan-out lines 22 is 4.5 microns, as shown in Figures a or b of Figure 14, the average arrangement period P3 of the fan-out lines in the fan-out area FA shown in Figure 2 is 2.57 microns, and the average arrangement period P3 of the fan-out lines in the fan-out area FA shown in Figure 12 is 3.68 microns. In Figure 14, Figure a shows the arrangement in order of increasing number S1 of the second fan-out lines 23 and number S2 of the first fan-out lines 22, while Figure b shows the arrangement in order of increasing average arrangement period P3 of the fan-out lines.
[0163] When the arrangement period P1 of the first fan-out line 22 is 4.8 microns, as shown in Figure c in Figure 14, the average arrangement period P3 of the fan-out lines in the fan-out area FA shown in Figure 2 is 2.74 microns, and the average arrangement period P3 of the fan-out lines in the fan-out area FA shown in Figure 12 is 3.93 microns.
[0164] When the arrangement period P1 of the first fan-out lines 22 is 5 microns, as shown in Figure 14 d, the average arrangement period P3 of the fan-out lines in the fan-out area FA shown in Figure 2 is 2.86 microns, and the average arrangement period P3 of the fan-out lines in the fan-out area FA shown in Figure 12 is 4.09 microns.
[0165] When the arrangement period P1 of the first fan-out line 22 is 5.3 microns, as shown in Figure e in Figure 14, the average arrangement period P3 of the fan-out lines in the fan-out area FA shown in Figure 2 is 3.03 microns, and the average arrangement period P3 of the fan-out lines in the fan-out area FA shown in Figure 12 is 4.34 microns.
[0166] For comparison, Figure 14 shows data for two comparative examples, namely, Comparative Example 1 and Comparative Example 2. Figure 18 shows a cross-sectional structural diagram of the fan-out area FA in Comparative Example 1, and Figure 19 shows a cross-sectional structural diagram of the fan-out area FA in Comparative Example 2. As shown in Figures 18 and 19, in the same fan-out unit UT, the number S2 of first fan-out lines 22 is equal to the number S1 of second fan-out lines 23.
[0167] In FIG18 , the orthographic projections of the first fan-out line 22 and the second fan-out line 23 on the substrate 11 overlap. The fan-out unit UT includes one first fan-out line 22 and one second fan-out line 23. When the arrangement period of the first fan-out line 22 and the second fan-out line 23 are both 4.5 microns, the average arrangement period P3 of the fan-out lines in the fan-out area FA shown in FIG18 is: arrangement period P3 of the first fan-out line 22 / 2 = arrangement period P3 of the second fan-out line 23 / 2 = 2.25 microns.
[0168] In FIG19 , the first fan-out lines 22 and the second fan-out lines 23 are alternately arranged in their orthographic projections on the substrate 11. A fan-out unit UT includes one first fan-out line 22 and one second fan-out line 23. When the arrangement period of the first fan-out lines 22 and the second fan-out lines 23 is both 7.2 microns, the average arrangement period P3 of the fan-out lines in the fan-out area FA shown in FIG19 is: arrangement period P3 of the first fan-out lines 22 / 2 = arrangement period P3 of the second fan-out lines 23 / 2 = 3.6 microns.
[0169] A half-tone mask is used to form the second fan-out lines 23, with an arrangement period of, for example, 10 microns. Based on the fan-out area FA arrangement shown in FIG18 or FIG19 , the average arrangement period P3 of the fan-out lines is calculated to be 5 microns, which is greater than the average arrangement period P3 of the fan-out lines in the fan-out area FA shown in FIG2 to FIG13a . Thus, the display substrate provided by the present disclosure can reduce the average arrangement period of the fan-out lines, thereby facilitating a reduction in the size of the frame.
[0170] The present disclosure provides a display panel, including: a cell substrate, a liquid crystal layer, and a display substrate as provided in any embodiment, wherein the liquid crystal layer is located between the cell substrate and the display substrate, and the display area AA and the non-display area BZ are arranged close to the liquid crystal layer.
[0171] Those skilled in the art will appreciate that the display panel provided by the present disclosure has the advantages of the above-mentioned display substrate.
[0172] The present disclosure provides a display device, comprising: a display substrate as provided in any embodiment; and a driving chip bound and connected to a non-display area BZ of the display substrate, for driving a display panel for display.
[0173] Those skilled in the art will appreciate that the display device provided by the present disclosure has the advantages of the above-mentioned display substrate.
[0174] The display device provided by the present disclosure can be: a display module, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a car display device, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function.
[0175] In the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.
[0176] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present disclosure.
[0177] As used herein, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.
[0178] References herein to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "an example," "an example," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.
[0179] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.
[0180] When describing some embodiments, the expressions "coupled" and "connected" may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.
[0181] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.
[0182] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.
[0183] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.
[0184] The use of "for" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.
[0185] The use of "based on" or "according to" in this document is intended to be open and inclusive. A process, step, calculation, or other action based on one or more stated conditions or values may, in practice, be based on other conditions or values beyond the stated values. A process, step, calculation, or other action based on one or more stated conditions or values may, in practice, be based on other conditions or values beyond the stated values.
[0186] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).
[0187] As used herein, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two being equal is less than or equal to 5% of either one. "Flush" includes absolute equality and approximate flushness, wherein the acceptable deviation range of approximate flushness can be, for example, the distance between the two being flush is less than or equal to 5% of either one's size.
[0188] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.
[0189] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.
[0190] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.
Claims
1. A display substrate, comprising a base substrate, and a display area and a non-display area arranged on one side of the base substrate, wherein the non-display area is located on at least one side of the display area; The display area includes: A plurality of scan lines extending along a first direction, and a plurality of data lines extending along a second direction; The non-display area includes a fan-out area, the fan-out area includes a plurality of fan-out units periodically arranged along a third direction, the fan-out units include a first fan-out line and a second fan-out line arranged in different layers, a plurality of the first fan-out lines and a plurality of the second fan-out lines are arranged along the third direction, and the third direction intersects the first direction and the second direction respectively; In the same fan-out unit, the number of the first fan-out lines is greater than the number of the second fan-out lines.
2. The display substrate according to claim 1, wherein: In the same fan-out unit, the number of the second fan-out lines is 1, and the ratio of the number of the first fan-out lines to the number of the second fan-out lines is an integer greater than or equal to 2; or In the same fan-out unit, the number of the second fan-out lines is greater than or equal to 2, and the ratio of the number of the first fan-out lines to the number of the second fan-out lines is a non-integer greater than 1.
3. The display substrate according to claim 1 or 2, wherein: In the same fan-out unit, a sum of the number of the first fan-out lines and the number of the second fan-out lines is greater than or equal to 3 and less than or equal to 15.
4. The display substrate according to any one of claims 1 to 3, wherein: In the same fan-out unit, a difference between the number of the first fan-out lines and the number of the second fan-out lines is greater than or equal to 1 and less than or equal to 10.
5. The display substrate according to any one of claims 1 to 4, wherein: The first fan-out line includes a first sub-fan-out line, the second fan-out line includes a second sub-fan-out line, and in an orthographic projection on the substrate, the first sub-fan-out line is located within the range of the second sub-fan-out line; and In the orthographic projection on the substrate, the first sub-fan-out line is centrally arranged in the third direction within the range of the second sub-fan-out line; or In an orthographic projection on the substrate, boundaries of the first sub-fan-out line and the second sub-fan-out line located on the same side are substantially flush.
6. The display substrate according to claim 5, wherein: The first fan-out line further includes a third sub-fan-out line, and in an orthographic projection on the substrate, the third sub-fan-out line has no overlap with the second fan-out line; and At least one of the third sub-fan-out lines is arranged alternately with the first sub-fan-out line along the third direction.
7. The display substrate according to claim 5, wherein: The second fan-out line further includes a fourth sub-fan-out line, and in an orthographic projection on the substrate, the fourth sub-fan-out line partially overlaps with one of the first fan-out lines; and The plurality of fourth sub-fan-out lines and the second sub-fan-out lines are arranged alternately along the third direction.
8. The display substrate according to claim 7, wherein: The first fan-out line further includes a third sub-fan-out line, and in an orthographic projection on the substrate, the third sub-fan-out line has no overlap with the second fan-out line; and A first number of the third sub-fan-out lines are arranged between two adjacent fourth sub-fan-out lines, a second number of the third sub-fan-out lines are arranged between the second sub-fan-out line and the fourth sub-fan-out line, and the sum of the first number and the second number is an odd number.
9. The display substrate according to claim 5, wherein: The second fan-out line further includes a fifth sub-fan-out line. In the orthographic projection on the substrate, the fifth sub-fan-out line is centrally arranged between two adjacent first fan-out lines, and the fifth sub-fan-out line has no overlap or partially overlaps with the two adjacent first fan-out lines.
10. The display substrate according to claim 9, wherein: In the orthographic projection on the substrate, the fifth sub-fan-out line is centrally arranged between two adjacent second sub-fan-out lines.
11. The display substrate according to claim 9, wherein: The first fan-out line further includes a third sub-fan-out line, and in an orthographic projection on the substrate, the third sub-fan-out line has no overlap with the second fan-out line; and In the orthographic projection on the substrate, the same number of third sub-fan-out lines are arranged between the second sub-fan-out line and the fifth sub-fan-out line.
12. The display substrate according to claim 9, wherein: The second fan-out line also includes: a fourth sub-fan-out line, wherein in an orthographic projection on the substrate, the fourth sub-fan-out line partially overlaps with one of the first fan-out lines; The second sub-fan-out line, the fifth sub-fan-out line and the fourth sub-fan-out line are alternately arranged in sequence.
13. The display substrate according to any one of claims 1 to 12, wherein: The first fan-out line and the second fan-out line both extend along a fourth direction, and an angle between the fourth direction and the first direction is greater than or equal to 3° and less than or equal to 20°.
14. The display substrate according to any one of claims 1 to 13, wherein: The first fan-out line is located between the substrate base and the second fan-out line; The non-display area also includes: a plurality of transparent routing lines arranged along the third direction and separated from each other, located on the side of the second fan-out line away from the base substrate, and the orthographic projection of the transparent routing line on the base substrate completely covers the orthographic projection of the second fan-out line on the base substrate.
15. The display substrate according to any one of claims 1 to 14, wherein: The non-display area also includes: a binding area, located at a side of the fan-out area away from the display area, comprising a plurality of pins arranged along the first direction, wherein the first fan-out line and the second fan-out line are connected to different pins; The plurality of pins include at least one of the following: A first pin is arranged at the same layer as the first fan-out line and connected to the first fan-out line; A second pin is arranged at the same layer as the second fan-out line and connected to the second fan-out line; A third pin is arranged at the same layer as the first fan-out line and connected to the second fan-out line; a fourth pin, which is arranged at the same layer as the second fan-out line and is connected to the first fan-out line; and The fifth pin includes a first pattern and a second pattern that are stacked and connected to each other, the first pattern is arranged in the same layer as the first fan-out line, the second pattern is arranged in the same layer as the second fan-out line, and the fifth pin is connected to the first fan-out line or the second fan-out line.
16. The display substrate according to any one of claims 1 to 15, wherein: The line width of the second fan-out line is greater than or equal to the line width of the first fan-out line, and the distance between two adjacent second fan-out lines is greater than or equal to the distance between two adjacent first fan-out lines.
17. The display substrate according to any one of claims 1 to 16, wherein: The first fan-out line and the second fan-out line are respectively connected to different data lines; or The display area further includes a plurality of touch lines extending along the second direction, the first fan-out lines are connected to the data lines or the touch lines, and the second fan-out lines are connected to the data lines or the touch lines.
18. The display substrate according to any one of claims 1 to 17, wherein: The scan line is located between the base substrate and the data line, the first fan-out line and the scan line are arranged in the same layer, and the second fan-out line and the data line are arranged in the same layer.
19. A display panel, comprising: A pairing substrate, a liquid crystal layer, and a display substrate as claimed in any one of claims 1 to 18, wherein the liquid crystal layer is located between the pairing substrate and the display substrate, and the display area and the non-display area are arranged close to the liquid crystal layer.
20. A display device, comprising: The display panel as claimed in claim 19; as well as A driving chip is bound and connected to the non-display area of the display substrate, and is used to drive the display panel to display.