A data transmission system for LVDS interface

Abstract

The present invention discloses a data transmission system for an LVDS interface. The system comprises a transmitting end and a receiving end. The transmitting end includes a first splicing module, a first FIFO memory, a mapping module, and a first conversion module. The first splicing module is used to receive video data, splice each row of pixel data, and then write the spliced ​​video data into the first FIFO memory. The mapping module is used to read the spliced ​​video data, receive externally transmitted packet data and the number of data lines, and then sequentially map the spliced ​​video data and packet data to the corresponding data lines according to the number of data lines and mapping principles. The first conversion module is used to convert each group of data with a bit width of 1 byte mapped to the data line into serial bit stream data with a bit width of 1 bit, and then transmit the data to the receiving end. The present invention avoids the problem of rigid number of lanes in XN mode and maximizes the bandwidth utilization of the LVDS interface.

Description

Technical Field

[0001] The present invention relates to the technical field of video data transmission, and in particular to a data transmission system for an LVDS interface. Background Art

[0002] The current mainstream LVDS transmission system has a low transmission rate and cannot flexibly adjust the number of data lanes while meeting bandwidth requirements. The general video signal interface includes Pixel_clk (pixel clock), Vsync (field sync), Hsync (horizontal sync), DataEnable (data valid), and Data (video data). Calculating the bandwidth required for video transmission: (in Mbps) Bandwidth = Pixel_Clk bpp. Pixel_Clk refers to the pixel clock frequency, and bpp (bits per pixel) refers to the number of effective bits occupied by a pixel.

[0003] Common parallel transmission interfaces include TTL and LVDS. TTL generally transmits at the original Pixel Clock frequency, meaning the data rate is Pixel Clock x1. Common LVDS transmission methods include VESA (OpenLDI) / JEIDA (SPWG), where the data rate is Pixel Clock x7. These two modes are collectively referred to as "XN mode." This fixed XN mode has many application limitations. X1 (TTL) mode requires too many PINs and has a maximum speed of 300 Mbps. The number of data lines (Lane_num) required in XN mode is calculated by dividing the bit-per-second (bpp) by N. Therefore, the bpp and N determine the lane_num, which is also fixed. Regardless of the pixel clock of the video being transmitted, the corresponding lanes must be fully utilized. The maximum input clock frequency, Pixel Clock, can be calculated based on the maximum bandwidth per lane and N.

[0004] Disadvantages of the prior art:

[0005] 1. The adjustment of the number of data lanes and bandwidth utilization is not flexible enough, and it is impossible to utilize the maximum lane bandwidth to achieve the minimum lane number;

[0006] 2. Under the premise of sufficient bandwidth, due to the limited number of lanes, no XN mode supports all timings of 4K60 and below. In other words, different video formats require switching modes, which is inconvenient to use;

[0007] 3. The VESA format dual pixel mode cannot send 4K60 timing with a pixel clock of 594MHz. If the quad pixel mode is used, too many PINs will be occupied. Summary of the Invention

[0008] The object of the present invention is to provide a data transmission system for an LVDS interface in view of the deficiencies in the prior art.

[0009] To achieve the above object, the present invention provides a data transmission system for an LVDS interface, comprising a transmitting end and a receiving end, wherein the transmitting end comprises:

[0010] A first splicing module is used to receive video data, splice pixel data of each row in the video data, and then write the spliced ​​video data into a first FIFO memory;

[0011] A first FIFO memory, for temporarily storing the spliced ​​video data written by the first splicing module;

[0012] a mapping module, configured to read the spliced ​​video data from the first FIFO memory and receive the number of data lines sent externally, then sequentially map the spliced ​​video data to the corresponding data lines according to the number of data lines and a mapping principle, and generate a row data valid signal during the mapping period, mapping one byte at a time as a group;

[0013] A first conversion module is used to convert each group of data with a bit width of 1 byte mapped to the data line into serial bit stream data with a bit width of 1 bit, and send the converted serial bit stream data with a bit width of 1 bit and a row data valid signal to the receiving end;

[0014] The receiving end includes:

[0015] a second conversion module, configured to receive data sent by the first conversion module from the data line, obtain the boundary of the serial bit stream according to the row data valid signal, perform boundary alignment, and then convert the serial bit stream data with a bit width of 1 bit into data with a bit width of 1 byte per group;

[0016] An unpacking module is used to perform validity judgment on each group of data with a bit width of 1 byte after the second conversion module is converted, and generate a CRC stability signal after the validity judgment is passed;

[0017] a second splicing module, configured to splice each group of data with a bit width of 1 byte converted by the second conversion module, and write the spliced ​​video data into a second FIFO memory;

[0018] a second FIFO memory for receiving the video data spliced ​​by the second splicing module and temporarily storing the received spliced ​​video data in sequence when a CRC stability signal is received;

[0019] The video timing generation module is used to read the spliced ​​video data from the second FIFO memory and restore it to standard data that complies with the video transmission protocol.

[0020] Furthermore, the first splicing module splices the valid data of each pixel in the video data according to the number of valid bits occupied by one pixel.

[0021] Furthermore, when the mapping module maps the spliced ​​video data to the corresponding data lines in sequence, the video data read from the first FIFO memory for the first time is mapped starting from the first data line Lane 1, and is mapped sequentially from bottom to top according to the data line number. If there is still video data remaining after all data lines in the current cycle are mapped, the mapping will continue in a loop starting from the first data line Lane 1 until all the video data read this time are mapped. In subsequent FIFO read operations, the mapping starting position will inherit the data line position of the last mapping. Furthermore, after the last line of video data in each frame, a configuration information packet is sent on the first data line Lane 1. The configuration information packet contains the information required for the receiving end to receive and process the data on the data line.

[0022] Furthermore, the information includes the effective time of the data valid signal and the effective data volume occupied by the last cycle of the data valid signal, which is specifically calculated as follows:

[0023] The effective time of the data valid signal is calculated as the number N of cycles of reading the first FIFO memory:

[0024] N=(Hactive bpp) / (Lane_num 8)

[0025] Among them, Hactive is the number of effective pixels, bpp is the number of effective bits occupied by one pixel, and Lane_num is the number of data lines;

[0026] Calculate the number of bits occupied by the data line in the last cycle according to the number of valid pixels, and then determine the data

[0027] The amount of valid data occupied by the last cycle of the valid signal.

[0028] Furthermore, the transmitting end further includes a packet arbitration module, which is configured to receive other types of data packets, such as audio packets. During a brief blank period after the transmission of valid pixel data is completed, the mapping module is further configured to sequentially map the data in the other types of data packets to the corresponding data lines, and convert the data in the other types of data packets mapped to the data lines into serial bit stream data through the first conversion module, and then transmit the data to the receiving end.

[0029] The depacketizing module is further configured to parse and process data in other types of data packets converted by the second conversion module.

[0030] Furthermore, the first conversion module supports sending data at a fixed rate, so that the receiving end can perform a clock calibration once to adapt to and stably receive video data of multiple different resolutions.

[0031] Beneficial effects: 1. Avoid the problem of rigid number of lanes in XN mode and maximize the bandwidth utilization of LVDS interface;

[0032] 2. Whether it is Progressive Video, Interlaced Video, VRR Video, or FreeSync Video, the pixel clock can be accurately restored based on the Vsync position and effective timing parameters, thereby achieving unlimited cascading;

[0033] 3. Avoids sending Video Hsync / Vsync signals, saving Lane overhead;

[0034] 4. Flexible transmission of other types of data packet modes. Except for the header and the following packet length, the rest of each type of data packet can be customized;

[0035] 5. The sending end can transmit the configuration information to the receiving end, and the downstream can automatically configure the relevant mode;

[0036] 6. Supports fixed Data Rate mode, greatly simplifying the calibration process of the receiver. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a principle block diagram of a transmitting end according to an embodiment of the present invention;

[0038] Figure 2 is a principle block diagram of a receiving end according to an embodiment of the present invention;

[0039] Figure 3 It is a schematic diagram for mapping data onto data lines;

[0040] Figure 4It is a schematic diagram for mapping the data in the configuration information packet onto the data line;

[0041] Figure 5 It is a schematic diagram for mapping data in other types of data packets onto data lines. DETAILED DESCRIPTION

[0042] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. These embodiments are implemented based on the technical solutions of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0043] like Figure 1 and Figure 2 As shown, an embodiment of the present invention provides a data transmission system for an LVDS interface, including a transmitting end and a receiving end, wherein the transmitting end includes a first splicing module 11, a first FIFO memory 12, a mapping module 13 and a first conversion module 14.

[0044] The first splicing module 11 is used to receive video data, splice each row of pixel data in the video data, and then write the spliced ​​video data into the first FIFO memory 12. Figure 1 In addition to the aforementioned video data, the first splicing module 11 generally receives signals such as pixel clock (Pixel_clk), field synchronization (Vsync), horizontal synchronization (Hsync), and data enable (DataEnable). These signals are known in the art and their use will not be described in detail. The aforementioned splicing method specifically splices the valid data of each pixel in the video data based on the effective bit count (bpp) of each pixel.

[0045] The first FIFO memory 12 is used to temporarily store the spliced ​​video data written by the first splicing module 11 .

[0046] The mapping module 13 is used to read the spliced ​​video data from the first FIFO memory 12, and receive the number of data lines lane_num sent from the outside, and then map the spliced ​​video data to the corresponding data lines in sequence according to the number of data lines lane_num and the mapping principle, and generate the row data valid signal DataDE during the mapping period, mapping 1 byte each time as a group. When the mapping module 13 maps the spliced ​​video data to the corresponding data lines in sequence, the video data read from the first FIFO memory for the first time is mapped starting from the first data line Lane1, and mapped in sequence from bottom to top according to the data line number. If there is still data remaining after all the data lines in the current cycle are mapped, the mapping will continue to be cyclically started from the first data line Lane1 until all the video data read this time are mapped. After the mapping of the video data read this time is completed, continue to read data from the first FIFO memory 12, and the mapping starting position will inherit the data line position of the last mapping completed. The above-mentioned maximum number of supported data lines lane_num can be calculated in the following way:

[0047] Lane_num= ⌈Total Data Rate / Per Lane Max Data Rate⌉

[0048] Total Data Rate represents the total bandwidth required for video data transmission, Per Lane Max Data Rate represents the maximum bandwidth for each lane, and ⌈.⌉ represents the rounding symbol. The Lane_num value can be calculated based on actual requirements and can be selected between 1 and 50.

[0049] The first conversion module 14 is used to convert each group of data with a bit width of 1 byte mapped to the data line into serial bit stream data with a bit width of 1 bit, thereby forming a bit stream, and send the converted serial bit stream data with a bit width of 1 bit and the row data valid signal to the receiving end.

[0050] The receiving end of the embodiment of the present invention includes a second conversion module 21 , a depacketization module 22 , a second splicing module 23 , a second FIFO memory 24 and a video timing generation module 25 .

[0051] The second conversion module 21 is used to receive the data sent by the first conversion module from the data line, obtain the serial bit stream boundary according to the row data valid signal, perform boundary alignment, and then convert the serial bit stream data with a bit width of 1 bit into data with a bit width of 1 byte per group.

[0052] The unpacking module 22 is used to perform validity judgment on each group of 1-byte data converted by the second conversion module 21, including frame header recognition, Lane length analysis, valid data extraction, CRC check and judgment, etc., and generates a CRC stability signal after the validity judgment passes.

[0053] The second splicing module 23 is used for splicing the video data with a bit width of 1 byte each converted by the second conversion module 21 , and writing the spliced ​​video data into the second FIFO memory 24 .

[0054] The second FIFO memory 24 is used to receive the video data spliced ​​by the second splicing module 23 and temporarily store the received spliced ​​video data in sequence when receiving the CRC stability signal.

[0055] The video timing generation module 25 is used to read the spliced ​​video data from the second FIFO memory 24 and restore it to standard data that conforms to the video transmission protocol. Specifically, when the second FIFO memory 24 is written to a certain depth, the video timing generation module 25 is activated and generates signals such as data valid, HSync, and VSync. The video data in the second FIFO memory 24 is then sequentially retrieved and the data valid signal is used to restore the video data read from the second FIFO memory 24 to standard data that conforms to the video transmission protocol.

[0056] After the last line of video data in each frame, a configuration packet is sent on the lane 1 data line. This packet contains the information required by the receiver to process the data on the data line, including bpp, lane_num, and video timing parameters. It also includes the valid time of the data valid signal and the amount of valid data occupied by the last cycle of the data valid signal. The specific calculation method is as follows:

[0057] The effective time of the data valid signal is calculated as the number N of cycles of reading the first FIFO memory:

[0058] N=(Hactive bpp) / (Lane_num 8)

[0059] Among them, Hactive is the number of effective pixels, bpp is the number of effective bits occupied by one pixel, and Lane_num is the number of data lines;

[0060] The number of bits occupied on the data line in the last cycle is calculated according to the number of valid pixels, thereby determining the amount of valid data occupied in the last cycle of the data valid signal.

[0061] The transmitting end also includes a packet arbitration module 15, which is used to receive other types of data packets, such as audio or other custom packets. During the short blank period (Video Blank) after the transmission of valid pixel data is completed, the mapping module 13 is also used to sequentially map the data in the other types of data packets to the corresponding data lines, and convert the data in the other types of data packets mapped to the data lines into serial bit stream data through the first conversion module 14, and then send it to the receiving end. The unpacking module 22 is also used to parse and process the data in the other types of data packets converted by the second conversion module 21, and then send the parsed data packet content to the corresponding subsequent processing module, such as the audio processing module. When these other types of data packets are sent to the packet arbitration module 15, they also send a request message pkt_req. The packet arbitration module 15 arbitrates these requests and only sends one data packet at a time.

[0062] To facilitate reception at the receiving end, the first conversion module 14 in this embodiment of the present invention supports sending data at a fixed rate (Lane pixel clock). This allows the receiving end to adapt to and stably receive video data of various resolutions after a single clock calibration. In this case, the data is intermittent, and the transmitting end needs to provide a Data Valid signal to indicate when the valid data is within the valid period of the row.

[0063] The following combination Figures 3 to 5 Specific instructions:

[0064] See also Figure 3 For video transmission based on the LVDS standard of up to 1.5Gbps per lane, take Htotal = 120, Hactive = 100, bpp = 30, Lane_num = 4, and Pixel_clk = 150Mhz as an example. With Hactive = 100, there are 100 valid pixel data bits. The valid pixel bits are concatenated based on the bpp and then divided into byte groups, with each 8-bit group allocated to each lane. Lane PHY clock = DataRate = Pixel_clk bpp / Lane_num=150 30 / 4 = 1125 Gbps. If the maximum bandwidth per lane does not exceed 1.5 Gbps, the DataRate cannot exceed 1.5 Gbps. The DataRate can be used to calculate the maximum supported input Pixel_clk while maintaining the maximum bandwidth. Each byte is sent to the analog end as a group for the analog interface, with Phy_Clk = DataRate / 8. Data valid signals, such as DE_Lane, are required during data mapping to ensure valid 8-bit data boundaries.

[0065] See also Figure 4 , supporting the transmission scheme proposed by the current LVDS interface data transceiver module. This transmission scheme sends a configuration packet on the first data line, lane 1, after the last line of video data in each frame. This packet includes information such as lane_num and bit-per-number (bpp) required for the receiving module to receive data on that lane. A complete data packet includes: frame header, packet length, bit-per-number (bpp), lane_num, valid timing parameters such as H / V Total / Active / Front / Sync / Back / Polarity / Interlaced / Progressive, and a CRC checksum. For example, the frame header is 0xAA. The receiver uniquely identifies the configuration packet based on the De_Lane and 0xAA values, obtaining valid information.

[0066] See also Figure 5 During the video blank period, data packets such as audio can be sent. Different packet headers represent different types. For each type, except for the header and the immediately following packet length, everything else is customizable. If consecutive packet requests are received, the header of the second packet can be placed immediately after the end of the first, thereby utilizing the available bandwidth. In addition, a Vsync packet is sent to indicate the arrival of Vsync. The Vsync packet includes a frame header (0xAB) and the number of cycles from Vsync to the Vsync packet header. Because Vsync may arrive while receiving data packets such as audio, the Vsync packet header may be delayed by several cycles relative to Vsync. Therefore, when sending a Vsync packet to identify the Vsync position, the number of cycles from Vsync to the Vsync packet header must be included. This allows the receiving module to accurately determine the Vsync position, facilitating clock recovery and accurately restoring pixel timing.

[0067] The above description is merely a preferred embodiment of the present invention. It should be noted that any other aspects not specifically described are considered prior art or common knowledge to those skilled in the art. Improvements and modifications may be made without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention.

Claims

1. A data transmission system for an LVDS interface, comprising a transmitting end and a receiving end, characterized in that: The transmitting end includes: A first splicing module is used to receive video data, splice pixel data of each row in the video data, and then write the spliced ​​video data into a first FIFO memory; A first FIFO memory, for temporarily storing the spliced ​​video data written by the first splicing module; a mapping module, configured to read the spliced ​​video data from the first FIFO memory and receive the number of data lines sent externally, then sequentially map the spliced ​​video data to the corresponding data lines according to the number of data lines and a mapping principle, and generate a row data valid signal during the mapping period, mapping one byte at a time as a group; A first conversion module is used to convert each group of data with a bit width of 1 byte mapped to the data line into serial bit stream data with a bit width of 1 bit, and send the converted serial bit stream data with a bit width of 1 bit and a row data valid signal to the receiving end; The receiving end includes: a second conversion module, configured to receive data sent by the first conversion module from the data line, obtain the boundary of the serial bit stream according to the row data valid signal, perform boundary alignment, and then convert the serial bit stream data with a bit width of 1 bit into data with a bit width of 1 byte per group; An unpacking module is used to perform validity judgment on each group of data with a bit width of 1 byte after the second conversion module is converted, and generate a CRC stability signal after the validity judgment is passed; a second splicing module, configured to splice each set of video data with a bit width of 1 byte converted by the second conversion module, and write the spliced ​​video data into a second FIFO memory; a second FIFO memory for receiving the video data spliced ​​by the second splicing module and temporarily storing the received spliced ​​video data in sequence when a CRC stability signal is received; The video timing generation module is used to read the spliced ​​video data from the second FIFO memory and restore it to standard data that complies with the video transmission protocol.

2. A data transmission system for LVDS interface according to claim 1, characterized in that: The first splicing module splices valid data of each pixel in the video data according to the number of valid bits occupied by one pixel.

3. A data transmission system for LVDS interface according to claim 1, characterized in that: When the mapping module maps the spliced ​​video data to the corresponding data lines in sequence, the video data read from the first FIFO memory for the first time is mapped starting from the first data line Lane 1, and is mapped sequentially from bottom to top according to the data line number. If there is still remaining video data after all video data lines in the current cycle are mapped, the mapping will continue in a loop starting from the first data line Lane 1 until all the video data read this time are mapped. In subsequent FIFO reading operations, the mapping starting position will inherit the data line position where the last mapping was completed.

4. A data transmission system for LVDS interface according to claim 1, characterized in that: After the last line of video data in each frame, a configuration information packet is sent on the first data line lane 1. The configuration information packet contains information required by the receiving end to receive and process the data on the data line.

5. A data transmission system for LVDS interface according to claim 4, characterized in that: The information includes the effective time of the data valid signal and the effective data volume occupied by the last cycle of the data valid signal, and the specific calculation method is as follows: The effective time of the data valid signal is calculated as the number N of cycles of reading the first FIFO memory: N=(Hactive bpp) / (Lane_num 8); Among them, Hactive is the number of effective pixels, bpp is the number of effective bits occupied by one pixel, and Lane_num is the number of data lines; The number of bits occupied on the data line in the last cycle is calculated according to the number of valid pixels, thereby determining the amount of valid data occupied in the last cycle of the data valid signal.

6. A data transmission system for LVDS interface according to claim 1, characterized in that: The transmitting end further includes a packet arbitration module, the packet arbitration module is used to receive other types of data packets, and during a blank period after the effective pixel data is transmitted, the mapping module is further used to sequentially map the data in the other types of data packets to the corresponding data lines, and convert the data in the other types of data packets mapped to the data lines into serial bit stream data through the first conversion module, and then transmit the data to the receiving end; The depacketizing module is further configured to parse and process data in other types of data packets converted by the second conversion module.

7. A data transmission system for LVDS interface according to claim 1, characterized in that: The first conversion module supports sending data at a fixed rate, so that the receiving end can adapt to and stably receive video data of multiple different resolutions by performing a clock calibration once.

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