Waveform Propagation Method, Electronic Device, and Storage Medium

Abstract

This application belongs to the field of electronic design automation technology, and proposes a waveform propagation method, an electronic device, and a storage medium. The method includes: obtaining a circuit design and a waveform file; determining initial waveform information in the waveform file that matches the target design level of the circuit design; establishing a binary decision diagram for each instance at the target design level, and encapsulating the established binary decision diagrams into a unified interface to call the binary decision diagrams of each instance through the unified interface; based on the initial waveform information, starting from the first instance in each instance, using the unified interface for waveform propagation until the complete waveform information of the target design level is obtained. This application can quickly establish the waveforms of all devices in the entire design in the early stage of integrated circuit design, solving the pain point that designers are difficult to obtain post-layout simulation waveforms to accurately calculate circuit power consumption in the early stage.

Description

Technical Field

[0001] This application relates to the field of electronic design automation technology, and in particular, to a waveform propagation method, an electronic device, and a storage medium. Background Art

[0002] With the progress of manufacturing technology and design technology, the design method of electronic systems has undergone profound changes. From computer-aided design (CAD), computer-aided engineering (CAE) to electronic design automation (EDA), the degree of design automation is getting higher and higher, and the design complexity is also getting stronger.

[0003] Integrated circuit (IC) EDA refers to a design method that uses electronic design automation software to complete the functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule checking, etc.) of very large-scale integrated circuit chips. At present, EDA technology has become a powerful tool for modern electronic design. Without the support of EDA technology, it is unthinkable to complete the design and manufacturing of very large-scale integrated circuits. IC designers need to use EDA tools to develop complex integrated circuits with hundreds of thousands to tens of billions of transistors to reduce design deviations, improve the success rate of tape-out, and save tape-out costs.

[0004] In the entire IC design process, generally, the earlier the power consumption problem is considered using EDA tools, the better the power consumption optimization effect, the more power consumption can be saved, and discovering and solving the power consumption problem in the early stage of the IC design process is also an important guarantee for successful tape-out. The accurate estimation of power consumption depends on the waveform data of the circuit. However, in the early stages of IC design such as the RTL (register transfer level) stage or the netlist stage, the complete waveform data of the circuit is generally not easily obtained. Therefore, the earlier in the IC design process, the greater the difficulty of power consumption analysis and the lower the accuracy of power consumption estimation.

[0005] Related technologies usually use the simulation process to establish a complete waveform. This circuit simulation process is computationally intensive, very slow, and requires strict environmental settings, resulting in IC designers having to switch between the simulation environment and the analysis environment when analyzing power consumption. In addition, the complete waveform files in various formats such as FSDB, USDB, and VCD generated by the traditional simulation process are very large in size, resulting in slow waveform file reading speed and large memory consumption. Summary of the Invention

[0006] The present application provides a waveform propagation method, an electronic device, and a storage medium, so as to at least solve the problems of low efficiency and long time consumption in establishing waveforms for each device in a circuit in the related art. The technical solution of the present application is as follows:

[0007] According to a first aspect of the present application, there is provided a waveform propagation method applied to electronic design automation software. The method includes: obtaining a circuit design and a waveform file, where the circuit design has multiple design levels; determining initial waveform information matching a target design level of the circuit design in the waveform file; respectively establishing a binary decision diagram for each instance of the target design level, and encapsulating the established binary decision diagram into a unified interface to call the binary decision diagram of each instance through the unified interface; based on the initial waveform information, starting from a first instance among each instance, performing waveform propagation using the unified interface until complete waveform information of the target design level is obtained, where all input pins of the first instance have corresponding waveform data in the initial waveform information.

[0008] According to a second aspect of the present application, there is provided an electronic device, including: a processor; a memory for storing processor-executable instructions, where when the processor-executable instructions are run by the processor, the processor is caused to execute the waveform propagation method according to the present application.

[0009] According to a third aspect of the present application, there is provided a computer-readable storage medium, which when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the waveform propagation method according to the present application.

[0010] The technical solution provided by the present application at least brings the following beneficial effects:

[0011] When the present application obtains a circuit design and a waveform file with multiple design levels, it can hierarchically determine the initial waveform information of each design level, and quickly propagate the waveforms of each device in the level by calling the unified interface of the binary decision diagram to obtain the complete waveform information of each design level. Furthermore, the present application can read in the waveforms of each design stage for propagation while maintaining the analysis environment. Especially for early RTL waveforms or netlist-level waveform data, it can quickly establish the waveforms of all devices in the entire design through a unique waveform propagation technology, providing a more comprehensive power consumption view for IC designers without multiple circuit simulations, thereby quickly and efficiently calculating the design power consumption, and solving the pain point of being difficult to obtain post-layout simulation waveforms in the early stage to accurately calculate the circuit power consumption.

[0012] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Description of the Drawings

[0013] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application, and do not constitute an improper limitation of the present application.

[0014] Figure 1 is a flowchart showing a waveform propagation method according to an exemplary embodiment of the present application.

[0015] Figure 2 is a logic diagram showing a circuit design according to an exemplary embodiment of the present application.

[0016] Figure 3 is a schematic diagram showing a glitch signal according to an exemplary embodiment of the present application.

[0017] Figure 4 is a block diagram showing an electronic device according to an exemplary embodiment of the present application. Detailed Embodiments

[0018] In order to enable those skilled in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0019] It should be noted that the steps in the specification and drawings of the present application are not limited to the specific order or sequence described. It should be understood that these steps can be interchanged when appropriate so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0020] At the beginning of the formulation of the digital electronic chip design standard, power consumption was considered simple and easy to implement. However, with the increasing number of devices using mobile power sources such as mobile phones, laptops, and electric vehicles, the continuous progress of electronic circuit manufacturing processes, and the increase in the functional size of designs, power consumption as a design constraint has become increasingly important, and power analysis has also become increasingly complex.

[0021] The power consumption of a chip can be divided into dynamic power and static power. Among them, dynamic power is further divided into switching power and short-circuit power, and static power refers to leakage power. More specifically, switching power, also known as switching power consumption, is the power consumption caused by charging and discharging the capacitors in the circuit due to signal flipping; short-circuit power, also known as internal power, is the power consumption generated by the formation of a short-term short-circuit current inside the device during the signal flipping at the output end of the device; leakage power, also known as leakage power consumption, is the power consumption caused by device leakage.

[0022] The development trend of modern electronics is that the geometric size of semiconductors is getting smaller and smaller, the supply voltage is getting lower and lower, the threshold voltage of the unit is getting smaller and smaller, the circuit scale is getting larger and larger, the power consumption density is getting higher and higher, and the leakage current is getting larger and larger. In the process of 90nm or below, the static power consumption accounts for more than 20% of the total design power consumption. In addition, the greater the chip power consumption, the higher the temperature of its active area, resulting in a higher chip failure rate and a lower lifespan; when the power consumption exceeds 100W, the energy consumption density is too large and the heat dissipation cost is too high, resulting in the chip temperature exceeding the tolerance limit and the clock frequency unable to be increased any further. Therefore, more consideration needs to be given to power consumption optimization in IC design, so that low-power design has gradually become an integral part of the basic capabilities of IC design.

[0023] In the entire IC design process, generally, the earlier the power consumption issue is considered, the better the power consumption optimization effect, and the more power consumption can be saved. Also, discovering and solving power consumption problems in the early stage of the IC design process is an important guarantee for successful chip tape-out. However, in the early stage of the IC design process, due to the lack of logic gate information, physical information, etc., it is difficult to improve the accuracy of power consumption analysis. Moreover, the earlier the stage, the greater the difficulty of power consumption analysis, the lower the accuracy of power consumption estimation. In addition, the impact of the later design stage on power consumption needs to be weighed, resulting in the early power consumption estimation and planning becoming a major challenge in low-power design. Therefore, designers increasingly need to use advanced low-power design methodologies to solve the problem of accurate power consumption calculation and evaluate the pain points of power consumption in the design earlier.

[0024] In EDA tools, generally, the greatest benefit of power consumption optimization is achieved during the RTL stage of IC design, followed by the netlist stage. Moreover, accurate estimation of power consumption depends on the waveform data of the circuit. However, during the early stage of IC design, complete waveform data of the circuit is generally not easily obtainable. For example, during the RTL stage, usually only the original waveform data containing only stimuli generated by IC designers initially according to their own requirements is available, and at this time, the waveform data of most device input / output signals is missing. Therefore, waveforms need to be established one by one. In addition, although the actual netlist and the RTL design description have the same function, when converting the RTL design into a netlist during the synthesis process, the actual netlist often has some additional devices compared to the RTL design, such as buffers, inverters, gated units, etc. To calculate power consumption more accurately, waveforms for these additional devices also need to be established separately.

[0025] As mentioned above, in the related art, a complete waveform is usually established through a simulation process, and then the relevant waveform is shifted by combining the timing data obtained from static timing analysis (STA). For example, the Chinese patent application with the application number 202180005990.6 discloses a glitch power analysis method using RTL vectors. This method uses an advanced simulation process to generate vector waveforms, then generates STA timing data for each node of the circuit design based on the vector waveforms, and then uses the STA timing data to shift the zero-delay vector waveforms to generate shifted waveforms. On the one hand, this circuit simulation process is usually computationally intensive, very slow, and requires strict environment settings, making the simulation environment and the analysis environment completely separate and operate independently of each other, resulting in the need to switch back and forth between the analysis environment and the simulation environment in the related art. On the other hand, the complete waveform files in various formats such as FSDB, USDB, and VCD generated through the traditional simulation process are all very large in size, resulting in problems such as slow waveform file reading speed and high memory consumption in the related art. Therefore, the related art is often inefficient and time-consuming, and it has become increasingly difficult to meet the current low-power IC design requirements.

[0026] In view of the above problems, the exemplary embodiments of the present application propose a waveform propagation method, an electronic device, and a computer-readable storage medium, which can solve or at least alleviate the above problems.

[0027] In the first aspect of the exemplary embodiments of the present application, a waveform propagation method is provided, which will be described in detail below with reference to Figures 1 to 4 for detailed description.

[0028] According to an exemplary embodiment of the present application, the waveform propagation method can be applied to electronic design automation (EDA) software. A user terminal can load the EDA software, enabling the user terminal to obtain a circuit design and a waveform file; determine initial waveform information in the waveform file that matches the target design level of the circuit design; establish a Binary Decision Diagram (BDD) for each instance at the target design level, and encapsulate the established binary decision diagrams into a unified interface to call the binary decision diagrams of each instance through the unified interface; based on the initial waveform information, starting from the first instance in each instance, use the unified interface for waveform propagation until the complete waveform information of the target design level is obtained.

[0029] This method can, when obtaining a circuit design and a waveform file with multiple design levels, hierarchically determine the initial waveform information of each design level, and quickly propagate the waveforms of each device in the level by calling the unified interface of the binary decision diagram to obtain the complete waveform information of each design level. Furthermore, it can, while maintaining the analysis environment, read in the waveforms of each design stage for propagation. Especially for early RTL waveforms or netlist-level waveform data, it can quickly establish the waveforms of all devices in the entire design through a unique waveform propagation technology, providing a more comprehensive power consumption view for IC designers without multiple circuit simulations, thereby quickly and efficiently calculating the design power consumption and solving the pain point of being difficult to obtain post-layout simulation waveforms to accurately calculate the circuit power consumption in the early stage.

[0030] The above user terminal can be, for example, a tablet computer, a laptop computer, a digital assistant, a wearable device, etc. However, the implementation scenario of the waveform propagation method described above is only an example scenario. The waveform propagation method according to the exemplary embodiment of the present application can also be applied to other application scenarios. For example, it can also be that a user requests to access relevant data from a server through a network on a user terminal (such as a mobile phone, a desktop computer, a tablet computer, etc.). The server can access the data by executing the waveform propagation method according to the exemplary embodiment of the present application and return the result to the user terminal. Here, the server can be an independent server, a server cluster, a cloud computing platform, or a virtualization center, etc.

[0031] Next, reference will be made to Figure 1 Describe the specific steps of the waveform propagation method according to the exemplary embodiment of the present application. As Figure 1 shown, the waveform propagation method can include the following steps:

[0032] In step S110, a circuit design and a waveform file can be obtained.

[0033] In the design of integrated circuit chips, the functions and behaviors of electronic circuits are described by a Hardware Description Language (HDL). By using HDL to describe the structure and behavior of digital system hardware in text form, logical circuit diagrams, logical expressions, and the logical functions performed by digital logic systems can be represented, enabling modeling at multiple abstract design levels such as the algorithm level, register transfer level, gate level, and switch level. IC designers typically use hardware description languages such as Verilog HDL (simply referred to as Verilog), VHDL (Very High Speed Integrated Circuit HDL), and System Verilog HDL for design, so circuit design can include HDL files such as Verilog files. In addition, circuit design can also include source files related to the circuit such as library files and synopsys design constraint (SDC) files.

[0034] According to an exemplary embodiment of the present application, the circuit design can have multiple design levels to achieve a hierarchical design structure. A module is the basic component of hierarchical design, and its practical meaning is to represent a logical entity on the hardware circuit. In hierarchical design, modules are hierarchical, and high-level modules achieve complex functions by calling and connecting instances of low-level modules. To complete the entire system, each module or instance connection requires a design top layer (i.e., the top module). The top input port (primary input port) and top output port (primary output port) of the design are defined in the design top layer. In addition, the concept of the design top layer can also be relative. For example, for any instance at a certain level in the design, this instance can also be regarded as the current design top layer of its lower-level instances.

[0035] According to an exemplary embodiment of the present application, corresponding to a multi-level circuit design, the waveform data in the waveform file can also have corresponding multiple levels, so that the waveform signal and the circuit design are reasonably adapted in terms of design flow, data structure, etc., facilitating subsequent processing. At the same time, in order to provide the original input of the circuit signal, the waveform file can at least include the waveform data corresponding to the signal excitation ports of the circuit design, and the signal excitation ports are connected to the input pins of at least one instance in the circuit design through a net, so that signals can be transmitted to the connected instances through the net. Here, the signal excitation ports can include at least one of a top-level input port, a register output port, a macro output port, and a blackbox output port.

[0036] Next, in step S120, initial waveform information matching the target design level of the circuit design can be determined in the waveform file.

[0037] Here, the target design level of the circuit design can be the current design top level or any specified design level. Further, the target design level can be used as the starting level, and each level can be processed layer by layer from top to bottom, or only a specified number of design levels starting from the starting level can be processed, such as, but not limited to, the first three levels. It should be understood that in another implementation, in order to obtain targeted results and save computing resources at the same time, only the target design level can also be processed, and the present application does not limit this.

[0038] According to an exemplary embodiment of the present application, a first module name corresponding to the target design level can be determined in the circuit design and searched in the module names recorded in the waveform file; in response to finding a second module name that matches the first module name, the waveform data of the associated level corresponding to the second module name in the waveform file is used as the initial waveform information. Here, the way to determine the match can be name matching or mapping matching, etc. For example, module name matching can be that the names of the modules are the same, or the names are different but there is a mapping relationship in the relevant mapping file, and the present application does not limit this. When determining the initial waveform information, by performing module name matching, the relevant waveform data in the waveform file can be quickly located, which has higher processing efficiency, faster speed, and lower resource occupancy rate compared with traversing all data.

[0039] Further, the first ports of the target design level can be matched with the second ports of the associated level to determine the proportion of the ports in the second ports that match the first ports; when the port proportion exceeds the first preset ratio, the waveform data of the associated level is used as the initial waveform information. Here, the target design level can have multiple first ports, and the associated level can have multiple second ports. If there are more than the first preset ratio of ports matching between the associated level and the target design level, the waveform data of the associated level in the waveform file can be used as the initial waveform information of the target design level in the circuit design. Further, the first preset ratio can be but is not limited to 80%, to provide some redundant space during matching and retain reasonable accuracy. However, this application does not limit this, and those skilled in the art can determine the specific value of the first preset ratio according to the actual situation. For example, the first preset ratio can also be determined to be 0%. In this implementation, as long as any port matches, the waveform data of the associated level is used as the initial waveform information. After matching the target design level and the associated level by module name, then matching their ports can achieve secondary confirmation, further improving the matching accuracy. And when matching ports, the setting of the first preset ratio also improves the redundancy and flexibility of related processing.

[0040] It should be understood that in the above matching process, if no second module name matching the first module name is found, that is, neither the module name recorded in the waveform file nor the target design level of the circuit design can be matched, or although the module name matching is successful, but there are more than a certain proportion of ports that cannot be matched between the associated level and the target design level, an error reporting process can be performed to indicate that the waveform information acquisition fails. In another implementation, it is also possible not to perform the error reporting process, but directly exit all processing flows, or enforce the subsequent processes. This application does not limit this.

[0041] Next, in step S130, a binary decision diagram can be established for each instance of the target design level, and the established binary decision diagram can be encapsulated into a unified interface to call the binary decision diagram of each instance through the unified interface.

[0042] Each instance in circuit design can be regarded as a cell for implementing a specific logic function. Different cells often have different characteristics, such as delay, power consumption, area, etc. Here, the logic function can be expressed by a Boolean function in the code, and the binary decision diagram is a data structure for representing Boolean functions. It is based on Shannon decomposition and simplifies and represents Boolean functions through a directed acyclic graph (DAG). Further, those skilled in the art can build a binary decision diagram based on the above principles by themselves, or can use the open-source tool named BuDDy to build a binary decision diagram. This application does not limit this.

[0043] In high-level languages for object-oriented programming such as C++, a class is its core feature, which is used to specify the form of an object. It is a user-defined data type and a combination that encapsulates data and functions. The data in a class is called a member variable, and the function is called a member function. A class can be regarded as a template, which can be used to create multiple objects with the same attributes and behaviors. Therefore, defining a class is essentially defining a blueprint for a data type, which defines what the objects of the class include and what operations can be performed on this object. Declaring an object of a class is like declaring a variable of a basic type.

[0044] According to an exemplary embodiment of the present application, for the current instance in each instance, the unit type of the current instance can be determined; in the case where there is no management class for this unit type, a management class is established for this unit type, and based on the logical function of the current instance, a binary decision diagram of the current instance is defined in the management class of this unit type, and then the management class of this unit type is encapsulated into a unified interface; in the case where there is a management class for this unit type, the current instance is associated with the management class of this unit type so that the current instance can reuse the binary decision diagram defined in the management class of this unit type. Here, each instance in the circuit design can generally belong to various unit types such as registers, latches, random access memories (RAMs), combinational gates, etc. Instances of the same unit type often have the same logical function, and the same logical function can be established as a binary decision diagram with the same structure. Therefore, a management class for the binary decision diagram can be established for each unit type respectively. For instances of the same unit type, they are associated with the management class of the corresponding unit type, and directly reuse the binary decision diagram defined in the established management class. For example, in the attribute data of the current instance, declare the management class of its unit type, and when in use, the binary decision diagram of the current instance can be obtained by instantiating the management class of its unit type, thereby reducing repeated calculations and resource consumption.

[0045] According to an exemplary embodiment of the present application, in an implementation of defining a binary decision diagram of a current instance in the management class of its unit type based on the logical function of the current instance, a unique index can be determined for each input pin of the current instance respectively, and each unique index of the current instance is mapped to the corresponding level of the binary decision diagram of the current instance in a preset order. Here, the unique indexes mapped to each level of the binary decision diagram of the current instance are different. Specifically, the unique index can be determined after obtaining the circuit design. The unique indexes of each instance can be used as the unique identifiers of the corresponding input pins to effectively distinguish each input pin of the instance. Further, when determining the unique index, each instance can be regarded as independent, that is, the index is unique within the instance, but there is no association between the indexes of different instances. Furthermore, when mapping the unique index to the binary decision diagram, the preset order of the unique index can be determined by those skilled in the art according to the actual situation, and the present application does not limit this.

[0046] Next, in step S140, based on the initial waveform information, starting from the first instance in each instance, waveform propagation can be performed using the unified interface until the complete waveform information of the target design level is obtained. Here, all input pins of the first instance have corresponding waveform data in the initial waveform information.

[0047] According to an exemplary embodiment of the present application, in the process of wave propagation using a unified interface starting from the first instance in each instance based on initial waveform information, an integer array can be established for the first instance, and the input signal value of the first instance at each moment can be determined from the initial waveform information; the input signal value at each moment is passed into the unified interface using the integer array for logical calculation to obtain the output signal value of the first instance at each moment, thereby obtaining the waveform data corresponding to the output pin of the first instance. Here, each parameter position in the integer array can correspond one-to-one with each unique index of the first instance in a preset order. Therefore, in the process of passing the input signal value at each moment into the unified interface using the integer array for logical calculation to obtain the output signal value of the first instance at each moment, the input signal value of each input pin of the first instance at the current moment can be assigned to the corresponding parameter position in the integer array in the preset order, and the assigned integer array is passed into the unified interface for logical calculation to obtain the output signal value of the output pin of the first instance at the current moment.

[0048] For ease of understanding, a function pseudocode example of the unified interface described above is as follows:

[0049] DdNode * / / Return value of the function, such as 0 or 1

[0050] Cudd_Eval ( / / Function name

[0051] DdManager *dd / / Input parameter dd to indicate the corresponding management class

[0052] DdNode *f / / Input parameter f to indicate the corresponding instance node

[0053] int *inputs / / Input parameter inputs to indicate the corresponding integer array )

[0055] By assigning the input signal value of the instance at each moment to the pre-set integer array in the preset order and then passing the integer array into the unified interface, it is possible to ensure the timing consistency of the data received by the unified interface at the same moment, reduce the probability of errors during calculation, and improve the wave propagation efficiency.

[0056] According to the waveform propagation method of an exemplary embodiment of the present application, before starting waveform propagation using a unified interface from the first instance in each instance, a numerical identifier can also be established for each instance respectively based on the number of target input pins of each instance. Here, the target input pins do not have corresponding waveform data in the initial waveform information. Further, the number of target input pins can be directly used as the numerical identifier, or the number of target input pins can be used as the numerical identifier after a certain operation / mapping, such as but not limited to increasing or decreasing a fixed value according to actual needs, and the present application does not limit this.

[0057] Further, in the process of starting from the first instance in each instance based on the initial waveform information and using a unified interface to perform waveform propagation until the complete waveform information of the target design level is obtained, in each instance, at least one instance with a numerical identifier as the target value can be used as the first instance; the output pins of each first instance can be added to the starting point set as starting points; the waveform data corresponding to each starting point in the starting point set can be calculated by at least one thread. Here, the target value indicates that the number of target input pins of the first instance is 0, in other words, all input pins of the first instance have corresponding waveform data in the initial waveform information. In addition, in addition to adding the output pins of each first instance to the starting point set as starting points, the nets connected to the output pins of each first instance can also be added to the starting point set as starting points, so that the starting point set is a set of nets rather than a set of pins, and the present application does not limit this. By using the numerical identifier to determine the first instance with complete input signals and putting the output pins of all first instances into the starting point set, the starting point set has the feasibility of parallel processing, which can facilitate multi-threaded waveform propagation to accelerate the waveform propagation process and reduce the time consumption.

[0058] According to an exemplary embodiment of the present application, in the process of calculating the waveform data corresponding to each starting point in the starting point set by at least one thread, for the current thread, the current starting point can be taken out from the starting point set for calculation; in response to calculating the waveform data corresponding to the current starting point, the next starting point can be taken out from the starting point set for calculation until the starting point set is empty. Here, any thread can take out any starting point from the starting point set for calculation, and the present application does not limit the processing order of taking out the starting points, so as to improve the operation efficiency of multi-threads.

[0059] Further, before the current thread fetches the next starting point from the set of starting points for calculation, it is also possible to determine whether there is at least one second instance in the target design hierarchy that is connected to the current starting point through a net; if there is at least one second instance, the numerical identifier of each second instance is decremented by 1 respectively, and then the output pin of the second instance with the numerical identifier being the target numerical value is added as a new starting point to the set of starting points. It should be understood that if there is no at least one second instance, or after the numerical identifier of each second instance is decremented by 1 respectively, the number of second instances with the numerical identifier being the target numerical value is 0, the current thread can directly fetch the next starting point from the set of starting points for calculation. In addition, if the number of second instances with the numerical identifier being the target numerical value is 1, the current thread can directly use this second instance as the next starting point for calculation to reduce redundant calculations. By continuously adding new starting points to the set of starting points, the number of starting points in the set of starting points is dynamic, which may decrease or increase. Until all threads have finished processing, the set of starting points is finally empty, improving the overall operating efficiency of multi-threaded waveform propagation.

[0060] Although the example steps before the current thread fetches the next starting point from the set of starting points for calculation are described above, the exemplary embodiments of the present application are not limited thereto. As another example, after the numerical identifier of each second instance is decremented by 1 respectively, it is also possible not to add the output pin of the second instance with the numerical identifier being the target numerical value as a new starting point to the set of starting points first, but to first use each thread to process the starting points in the current set of starting points, that is, after the set of starting points is empty, then uniformly add the output pins of the second instances with the numerical identifier being the target numerical value as starting points to the set of starting points, so as to reduce the probability of multi-threaded operation errors.

[0061] For ease of understanding, the following will refer to Figure 2 to describe at least some implementation manners. Figure 2 is a logic diagram showing a circuit design according to an exemplary embodiment of the present application.

[0062] As Figure 2 shown, the circuit includes input ports A, B, C, output port OUT, instances I1, I2, I3, nets n1, n2. The input pins of instance I1 are connected to ports A and B, the input pins of instance I2 are connected to port C, the output pins of instance I3 are connected to port OUT, net n2 is connected to the output pin of instance I1 and one input pin of instance I3, net n1 is connected to the output pin of instance I2 and the other input pin of instance I3, and n2 = A & B and n1 =!C.

[0063] Assume that the initial waveform information only contains the waveform data of ports A, B, and C. Then the implementation steps of waveform propagation are as follows:

[0064] Step (1): Based on the unique indexes of the input pins of instances I1, I2, and I3 respectively, establish the binary decision diagrams output by each instance and encapsulate them into a unified interface.

[0065] Step (2): Establish respective numerical identifiers <ref num> for instances I1, I2, and I3. This numerical identifier corresponds to the number of input pins of each instance that do not have waveform data. Here, since ports A, B, and C all have waveform data, while n1 and n2 do not have waveform data, the <ref num> of I1 and I2 is 0, and the <ref num> of I3 is 2.

[0066] Step (3): Start waveform propagation from the output terminals of the instances with <ref num> equal to 0. The propagation process can be multi-threaded, and each thread independently processes one starting point. Here, n1 and n2 are used as the starting points.

[0067] Step (4): Start calculating the waveforms of each starting point. Here, assume that the unique index of the input pin of instance I1 connected to port A is <id1>, and the unique index of the input pin connecting to port B is <id2>, the signal value of port A at time t0 is 0, and the signal value of port B is 1. Will <id1> 、 <id2>The corresponding signal values are placed in an integer array, and the parameter positions in this integer array are the same as <id1> 、 <id2>Correspondingly. Pass this integer array through a unified interface, and the signal value output by I1 at time t0 is obtained as 0. And so on, calculate the signal values output by I1 at all subsequent times to obtain the complete waveform corresponding to n2. Similarly, calculate the signal values output by I2 at all times to obtain the complete waveform corresponding to n1.

[0068] Step (5): Collect and set the starting point of the next level. Here, when the complete waveform of n1 is obtained, subtract 1 from the <ref num> of I3. Similarly, when the complete waveform of n2 is obtained, also subtract 1 from the <ref num> of I3. At this time, the <ref num> of I3 is 0, and it will be set as the starting point of the next level.

[0069] Step (6): Repeat steps (3), (4), and (5) until there is no starting point in the next level.

[0070] It should be noted that although specific circuit designs are used as examples to describe some implementation methods in the exemplary embodiments of the present application, the exemplary embodiments of the present application are not limited to the examples described above, and the partial implementation methods described by taking specific circuit designs as examples above can also be similarly applied to other circuit designs.

[0071] Glitches are caused by different delays in different paths of the circuit, resulting in a short-term signal flip at the output of the logic gate. As Figure 3 shown, glitch signals are divided into transport glitches and inertial glitches. Transport glitches are caused by different delay signals on different pins, resulting in a short-term signal flip at the output. Inertial glitches are caused by a short 101 (or 010) signal, resulting in a partial flip at the output.

[0072] Glitch signals are useless signals, and the power consumption generated therefrom is also useless power consumption. Specifically, transport glitches will generate internal power consumption and switching power consumption, and inertial glitches will generate internal power consumption. These power consumptions are all power waste caused by logic gate delays. Therefore, the smaller the proportion of glitch power consumption in the total power consumption value of IC design, the better.

[0073] Due to process limitations, in IC devices designed and manufactured by traditional means, the proportion of glitch power consumption in the total power consumption is very small. Therefore, traditional power analysis tools often directly ignore glitch power consumption or only provide a rough estimate of glitch power consumption, and cannot accurately capture glitch power consumption. However, with the continuous evolution of IC manufacturing technology, glitch power consumption is becoming increasingly impossible to ignore. In some cases, glitch power consumption may even account for 20% to 40% of the total power consumption of circuit design. Therefore, the demand for accurate estimation of glitch power consumption in circuit design is increasing day by day.

[0074] According to the waveform propagation method of an exemplary embodiment of the present application, during the waveform propagation process or after the waveform propagation is completed, it is also possible to perform glitch recognition on each pulse on the net at the target design level based on the complete waveform information. Here, for the current pulse on the target net, if the signal width of the current pulse is less than the first glitch width, the current pulse can be recognized as a conductive glitch; if the signal width of the current pulse is less than the second glitch width, the current pulse can be recognized as an inertial glitch. Further, the first glitch width is the product of the minimum period of the clock on the target net and the second preset ratio, and the second glitch width is the product of twice the signal transition time on the target net and the third preset ratio. Furthermore, the second preset ratio and the third preset ratio can be set by those skilled in the art according to the actual situation, such as 0.6, etc., to determine whether to recognize some pulse signals as glitches, thereby improving the flexibility of glitch recognition. Through the above glitch recognition, the glitch signals can be analyzed quickly and accurately, and the glitch power consumption of the chip can be calculated, helping IC designers to discover the problems caused by the glitch power consumption at an early stage.

[0075] According to the waveform propagation method of an exemplary embodiment of the present application, when obtaining a circuit design and a waveform file with multiple design levels, the initial waveform information of each design level can be determined hierarchically. By calling the unified interface of the binary decision diagram, the waveforms of each device in the hierarchy can be propagated quickly, and the complete waveform information of each design level can be obtained. Furthermore, the present application can read in the waveforms of each design stage for propagation while maintaining the analysis environment. Especially for the early RTL waveforms or netlist-level waveform data, the unique waveform propagation technology can quickly establish the waveforms of all devices in the entire design, providing a more comprehensive power consumption view for IC designers without multiple circuit simulations, thereby calculating the design power consumption quickly and efficiently, and solving the pain point of being difficult to obtain post-layout simulation waveforms to accurately calculate the circuit power consumption in the early stage.

[0076] In the second aspect of the exemplary embodiment of the present application, an electronic device is provided. The electronic device includes: a processor; a memory for storing processor-executable instructions, wherein when the processor-executable instructions are run by the processor, the processor is caused to execute the waveform propagation method according to the exemplary embodiment of the present application.

[0077] Figure 4 is a block diagram of an electronic device according to an exemplary embodiment of the present application. As Figure 4 shown, the electronic device 10 includes a processor 101 and a memory 102 for storing processor-executable instructions. Here, when the processor-executable instructions are run by the processor, the processor is caused to execute the waveform propagation method according to the exemplary embodiment of the present application.

[0078] As an example, the electronic device 10 does not have to be a single device, but can also be any collection of devices or circuits that can execute the above instructions (or instruction sets) individually or jointly. The electronic device 10 can also be part of an integrated control system or system manager, or can be configured to interface with a server locally or remotely (e.g., via wireless transmission).

[0079] In the electronic device 10, the processor 101 can include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example and not limitation, the processor 101 can also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0080] The processor 101 can run instructions or code stored in the memory 102, where the memory 102 can also store data. The instructions and data can also be sent and received over a network via a network interface device, where the network interface device can employ any known transmission protocol.

[0081] The memory 102 can be integrated with the processor 101, for example, by arranging RAM or flash memory within an integrated circuit microprocessor, etc. In addition, the memory 102 can include a separate device, such as an external disk drive, a storage array, or other storage devices that can be used by any database system. The memory 102 and the processor 101 can be operatively coupled or can communicate with each other, for example, via an I / O port, a network connection, etc., such that the processor 101 can read files stored in the memory 102.

[0082] In addition, the electronic device 10 can also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, a mouse, a touch input device, etc.). All components of the electronic device 10 can be connected to each other via a bus and / or a network.

[0083] In an exemplary embodiment, a computer-readable storage medium may also be provided. When instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the waveform propagation method as described in the above exemplary embodiment. The computer-readable storage medium may be, for example, a memory including instructions. Optionally, the computer-readable storage medium may be: read-only memory (ROM), random access memory (RAM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc memory, hard disk drive (HDD), solid state drive (SSD), cartridge memory (such as, multimedia card, secure digital (SD) card or extreme digital (XD) card), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk, and any other device configured to store a computer program and any associated data, data files, and data structures in a non-transitory manner and to provide the computer program and any associated data, data files, and data structures to a processor or computer such that the processor or computer can execute the computer program. The computer program in the above computer-readable storage medium may run in an environment deployed in computer devices such as clients, hosts, proxy devices, servers, etc. In addition, in one example, the computer program and any associated data, data files, and data structures are distributed on a networked computer system such that the computer program and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner by one or more processors or computers.

[0084] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only to be considered exemplary, and the true scope and spirit of the present application are pointed out by the claims.

[0085] In addition, it should be noted that although several examples of the steps are described above with reference to specific drawings, it should be understood that the embodiments of the present application are not limited to the combinations given in the examples, and the steps appearing in different drawings can be combined, and no exhaustive listing is made here.

[0086] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the claims. < / id1> < / id1>

Claims

1. A waveform propagation method, applied to electronic design automation software, characterized in that, The method includes: Obtaining a circuit design and a waveform file, where the circuit design has multiple design levels; Determining initial waveform information in the waveform file that matches a target design level of the circuit design; Establishing a binary decision diagram for each instance of the target design level respectively, and encapsulating the established binary decision diagram into a unified interface to call the binary decision diagram of each instance through the unified interface; Based on the initial waveform information, starting from the first instance among each instance, performing waveform propagation using the unified interface until complete waveform information of the target design level is obtained, where all input pins of the first instance have corresponding waveform data in the initial waveform information; Wherein, establishing a binary decision diagram for each instance of the target design level respectively, and encapsulating the established binary decision diagram into a unified interface, includes: For a current instance among each instance, determining the cell type of the current instance; In the case where there is no management class for the cell type, establishing a management class for the cell type, defining the binary decision diagram of the current instance in the management class of the cell type based on the logic function of the current instance, and then encapsulating the management class of the cell type into the unified interface; In the case where there is a management class for the cell type, associating the current instance with the management class of the cell type so that the current instance can reuse the binary decision diagram defined in the management class of the cell type.

2. The waveform propagation method according to claim 1, characterized in that Determining initial waveform information in the waveform file that matches a target design level of the circuit design, includes: Determining a first module name corresponding to the target design level in the circuit design, and then searching in the module names recorded in the waveform file; In response to finding a second module name that matches the first module name, using the waveform data of the associated level corresponding to the second module name in the waveform file as the initial waveform information.

3. The waveform propagation method according to claim 2, wherein Using the waveform data of the associated level corresponding to the second module name in the waveform file as the initial waveform information, includes: Matching a first port of the target design level with a second port of the associated level to determine the port ratio of the port in the second port that matches the first port; In the case where the port ratio exceeds a first preset ratio, using the waveform data of the associated level as the initial waveform information.

4. The waveform propagation method according to claim 1, characterized in that, Defining the binary decision diagram of the current instance in the management class of the cell type based on the logic function of the current instance, includes: Determining a unique index for each input pin of the current instance respectively, and mapping each unique index of the current instance to the corresponding level of the binary decision diagram of the current instance in a preset order, where the unique indexes mapped to each level of the binary decision diagram of the current instance are different.

5. The waveform propagation method according to claim 4, characterized in that, Based on the initial waveform information, starting from the first instance among each instance, performing waveform propagation using the unified interface, includes: Create an integer array for the first instance, and determine the input signal values of the first instance at each moment in the initial waveform information; Use the integer array to pass the input signal values at each moment into the unified interface for logical calculation, obtain the output signal values of the first instance at each moment, and thus obtain the waveform data corresponding to the output pins of the first instance.

6. The waveform propagation method according to claim 5, wherein Each parameter position in the integer array corresponds one-to-one with each unique index of the first instance according to the preset order, wherein, using the integer array to pass the input signal values at each moment into the unified interface for logical calculation, and obtaining the output signal values of the first instance at each moment, includes: Assign the input signal values of each input pin of the first instance at the current moment to the corresponding parameter positions in the integer array according to the preset order, and pass the integer array after assignment into the unified interface for logical calculation to obtain the output signal value of the output pin of the first instance at the current moment.

7. The waveform propagation method according to claim 1, wherein It also includes: Based on the number of target input pins of each instance, establish a numerical identifier for each instance respectively, wherein the target input pins do not have corresponding waveform data in the initial waveform information; wherein, based on the initial waveform information, starting from the first instance in each instance, use the unified interface for waveform propagation until the complete waveform information of the target design hierarchy is obtained, including: In each instance, use at least one instance with the numerical identifier being the target numerical value as the first instance, wherein the target numerical value indicates that the number of target input pins of the first instance is 0; Add the output pins of each first instance as starting points to the starting point set; Calculate the waveform data corresponding to each starting point in the starting point set through at least one thread.

8. The waveform propagation method according to claim 7, wherein Calculating the waveform data corresponding to each starting point in the starting point set through at least one thread includes: For the current thread, take out the current starting point from the starting point set for calculation; In response to calculating the waveform data corresponding to the current starting point, take out the next starting point from the starting point set for calculation until the starting point set is empty.

9. The waveform propagation method according to claim 8, characterized in that, Before the current thread takes out the next starting point from the starting point set for calculation, calculating the waveform data corresponding to each starting point in the starting point set through at least one thread further includes: Determine whether there is at least one second instance in the target design hierarchy connected to the current starting point through a wire net; If there is the at least one second instance, subtract 1 from the numerical identifier of each second instance respectively, and then add the output pins of the second instances with the numerical identifier being the target numerical value as new starting points to the starting point set.

10. The waveform propagation method according to any one of claims 1 to 9, characterized in that, It also includes: Based on the complete waveform information, perform glitch recognition on each pulse on the wire net of the target design hierarchy. For the current pulse on the target wire net, In the case where the signal width of the current pulse is less than the first glitch width, the current pulse is identified as a conductive glitch, where the first glitch width is the product of the minimum period of the clock on the target net and a second preset ratio. In the case where the signal width of the current pulse is less than the second glitch width, the current pulse is identified as an inertial glitch, where the second glitch width is the product of twice the signal transition time on the target net and a third preset ratio.

11. An electronic device, characterized in that, Comprising: A processor; A memory for storing processor-executable instructions, wherein, when the processor-executable instructions are run by the processor, the processor is caused to execute the waveform propagation method according to any one of claims 1 to 10.

12. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the waveform propagation method according to any one of claims 1 to 10.

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