Signal providing method, signal providing module and display device

By setting the DC voltage in the hold time period and increasing the clock signal frequency in the refresh time period, the problem of failure to reduce IC power consumption in related technologies is solved, and the power consumption reduction and display effect are guaranteed during low-frequency display.

CN120164404APending Publication Date: 2025-06-17BOE TECHNOLOGY GROUP CO LTD +2
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Patent Information

Application Number
CN202510570190.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-04-30
Publication Date
2025-06-17

AI Technical Summary

Technical Problem

In related art, the clock signal is not down-frequency during the holding period, resulting in some power consumption gains not being realized.

Method used

In the hold time period, the starting voltage is set to the DC voltage, and the frequency of the clock signal is set to be higher than the frequency of the hold time period during the refresh time period to reduce IC power consumption without affecting signal transmission.

Benefits of technology

By this method, it is possible to reduce IC power consumption during low frequency display, while ensuring the display effect of the display panel.

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Abstract

The invention provides a signal providing method, a signal providing module and a display device. The signal providing method is applied to the display device, the display device comprises a driving module, and the driving module is used for generating a driving signal according to an initial voltage provided by an initial voltage end and a clock signal provided by a clock signal end; the display period comprises a holding time period and a refreshing time period which are arranged at intervals; the signal providing method comprises the following steps: in the holding time period, setting the initial voltage as direct current voltage; and setting the frequency of the clock signal in the refreshing time period to be higher than the frequency of the clock signal in the holding time period. According to the invention, the power consumption of an IC (integrated circuit) can be reduced under the condition that signal transmission is not influenced.
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Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a signal providing method, a signal providing module, and a display device. Background Art

[0002] In the related art, as Figure 1 shown, taking the falling edge of the synchronization signal TE as the demarcation line, that is, the start time of the refresh period TS can be the first falling edge of TE, and the end time of the refresh period TS can be the second falling edge of TE; taking the first falling edge of TE as the start time of the refresh period TS and the second falling edge of TE as the end time of the refresh period TS; before the refresh period TS, a first holding period TB1 is set, and after the refresh period TS, a second holding period TB2 is set;

[0003] During the refresh period TS, the frequencies of the first clock signal CK and the second clock signal CB are relatively high; during the first holding period TB1 and the second holding period TB2, the frequencies of the first clock signal CK and the second clock signal CB are reduced;

[0004] As Figure 1 shown, during the first holding period TB1, there is a pulse provided by the start voltage terminal STV, which will cause the driving signal OT generated by the driving module to lose the pulse, and this situation will affect the display effect of the display panel; therefore, in the related art, during the holding period, the clock signal is not downscaled, resulting in a loss of some power consumption benefits. Summary of the Invention

[0005] The main purpose of the present invention is to provide a signal providing method, a signal providing module, and a display device, which solve the problem that in the related art, during the holding period, the clock signal is not downscaled, resulting in a loss of some power consumption benefits.

[0006] In one aspect, an embodiment of the present invention provides a signal providing method, which is applied to a display device. The display device includes a driving module, and the driving module is configured to generate a driving signal according to a start voltage provided by a start voltage terminal and a clock signal provided by a clock signal terminal; a display period includes a holding period and a refresh period that are arranged at intervals; the signal providing method includes:

[0007] During the holding period, set the start voltage to a direct current voltage;

[0008] Set the frequency of the clock signal during the refresh period to be higher than the frequency of the clock signal during the holding period.

[0009] The signal providing method according to at least one embodiment of the present invention further includes:

[0010] During the refresh period, setting the start voltage to include N pulses; N is an integer greater than 1.

[0011] The signal providing method according to at least one embodiment of the present invention further includes:

[0012] During the refresh period, setting the start time of the first pulse of the clock signal before the start time of the first pulse of the start voltage.

[0013] The signal providing method according to at least one embodiment of the present invention further includes:

[0014] During the refresh period, the driving module generates a driving signal according to the start voltage and the clock signal, so that the driving signal has N pulses.

[0015] The signal providing method according to at least one embodiment of the present invention includes:

[0016] Subtracting the first time x from the a-th falling edge time of the synchronization signal and setting it as the start time of the b-th refresh period, and setting the (a + 1)-th falling edge time of the synchronization signal as the end time of the b-th refresh period;

[0017] Both a and b are positive integers; x is a positive or negative number.

[0018] In a second aspect, an embodiment of the present invention provides a signal providing module, which is applied to a display device. The display device includes a driving module, and the driving module is used to generate a driving signal according to the start voltage provided by the start voltage terminal and the clock signal provided by the clock signal terminal; the display period includes a holding period and a refresh period that are arranged at intervals; the signal providing module includes:

[0019] A start voltage providing circuit, configured to set the start voltage as a DC voltage during the holding period; and

[0020] A clock signal providing circuit, configured to set the frequency of the clock signal during the refresh period to be higher than the frequency of the clock signal during the holding period.

[0021] Optionally, the start voltage providing circuit is further configured to set the start voltage to include N pulses during the refresh period; N is an integer greater than 1.

[0022] Optionally, the clock signal providing circuit is further configured to set the start time of the first pulse of the clock signal before the start time of the first pulse of the start voltage during the refresh period.

[0023] In a third aspect, an embodiment of the present invention provides a display device, including the above-mentioned signal providing module.

[0024] The display device according to at least one embodiment of the present invention further includes a driving module;

[0025] The starting voltage providing circuit in the signal providing module is used to set the starting voltage to include N pulses during a refresh period; N is an integer greater than 1;

[0026] The driving module is used to generate a driving signal according to the starting voltage and a clock signal during the refresh period, so that the driving signal has N pulses.

[0027] When the signal providing method, the signal providing module, and the display device according to the embodiments of the present invention are working, during low-frequency display, the display period may include a holding period and a refresh period that are set at intervals; during the holding period, the starting voltage is set to a DC voltage, and the frequency of the clock signal is set to be low during the holding period, so as to reduce the power consumption of the IC (integrated circuit) without affecting signal transmission. Description of the Drawings

[0028] Figure 1 is the working timing diagram of the related display panel;

[0029] Figure 2A is a schematic diagram of the boundary time between the holding frame and the refresh frame in the related art;

[0030] Figure 2B is a schematic diagram of the boundary time between the holding frame and the refresh frame in at least one embodiment of the present invention;

[0031] Figure 2C is a schematic diagram of the duration of the refresh period TS in at least one embodiment of the present invention;

[0032] Figure 3 is the waveform diagram of the synchronization signal, the first clock signal, the second clock signal, and the starting voltage in at least one embodiment of the present invention;

[0033] Figure 4 is the structural diagram of the signal providing module according to at least one embodiment of the present invention. Detailed Embodiments

[0034] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0035] The transistors used in all embodiments of the present invention can be thin-film transistors or field-effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two poles of the transistor other than the gate, one pole is called the first pole and the other pole is called the second pole.

[0036] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first pole can be the drain and the second pole can be the source; or, the first pole can be the source and the second pole can be the drain.

[0037] The embodiments of the present invention provide a signal providing method, which is applied to a display device. The display device includes a driving module, and the driving module is used to generate a driving signal according to the starting voltage provided by the starting voltage terminal and the clock signal provided by the clock signal terminal; the display period includes a holding time period and a refreshing time period arranged at intervals; the signal providing method includes:

[0038] In the holding time period, set the starting voltage as a direct current voltage;

[0039] Set the frequency of the clock signal in the refreshing time period to be higher than the frequency of the clock signal in the holding time period.

[0040] In the embodiments of the present invention, during low-frequency display, the display period can include a holding time period and a refreshing time period arranged at intervals; in the holding time period, set the starting voltage as a direct current voltage, and set the frequency of the clock signal in the holding time period to be lower to reduce the power consumption of the IC (integrated circuit) without affecting signal transmission.

[0041] The signal providing method described in at least one embodiment of the present invention further includes:

[0042] In the refreshing time period, set the starting voltage to include N pulses; N is an integer greater than 1.

[0043] In specific implementation, in the refreshing time period, the starting voltage can be set to include at least two pulses;

[0044] Optionally, the pulse can be a downward pulse, or the pulse can be an upward pulse.

[0045] The signal providing method according to at least one embodiment of the present invention further includes:

[0046] During the refresh period, set the start time of the first pulse of the clock signal before the start time of the first pulse of the starting voltage.

[0047] In at least one embodiment of the present invention, during the refresh period, set the start time of the first pulse of the clock signal before the start time of the first pulse of the starting voltage, so that the driving signal generated by the driving module does not lose output pulses.

[0048] In the signal providing method according to at least one embodiment of the present invention, during the refresh period, set the start time of the first pulse of the clock signal before the start time of the first pulse of the starting voltage, so that the driving signal generated by the driving module does not lose pulses, and on the premise of reducing power consumption, the display effect of the display panel can be ensured.

[0049] The signal providing method according to at least one embodiment of the present invention further includes:

[0050] During the refresh period, the driving module generates a driving signal according to the starting voltage and the clock signal, so that the driving signal has N pulses.

[0051] In specific implementation, the driving module generates a driving signal according to the starting voltage and the clock signal, so that the driving signal has N pulses, so that the number of pulses of the starting voltage is the same as the number of pulses of the driving signal, so that the driving signal generated by the driving module does not lose pulses, and on the premise of reducing power consumption, the display effect of the display panel can be ensured.

[0052] The signal providing method according to at least one embodiment of the present invention includes:

[0053] Subtract the first time x from the a-th falling edge time of the synchronization signal and set it as the start time of the b-th refresh period, and set the (a + 1)-th falling edge time of the synchronization signal as the end time of the b-th refresh period;

[0054] Both a and b are positive integers, and x is a positive or negative number.

[0055] In specific implementation, subtract the first time x from the a-th falling edge time of the synchronization signal and set it as the start time of the b-th refresh period, and set the (a + 1)-th falling edge time of the synchronization signal as the end time of the b-th refresh period. The duration of the b-th refresh period is shorter than the full frame time, which can further increase the clock signal down-frequency time.

[0056] In specific implementation, the first time x is set in the form of a register and is set according to the waveform of the starting voltage, so that during the refresh period, the driving signal generated by the driving module will not lose pulses.

[0057] In specific implementation, when x is a positive number, the time of the a-th falling edge of the synchronization signal minus the first time x is set as the start time of the b-th refresh period, that is, the start time of the b-th refresh period is advanced.

[0058] When x is a negative number, the time of the a-th falling edge of the synchronization signal minus the first time x is set as the start time of the b-th refresh period, that is, the start time of the b-th refresh period is postponed.

[0059] In at least one embodiment of the present invention, when the start time of the first pulse included in the starting voltage is set after the a-th falling edge of the synchronization signal, x can be set as a negative number to postpone the start time of the b-th refresh period.

[0060] As Figure 2A shown, in the related art, the boundary time between the holding frame and the refresh frame is RS_sync;

[0061] As Figure 2B shown, in at least one embodiment of the present invention, according to the pulse of the starting voltage provided by STV, the boundary time between the holding frame and the refresh frame is advanced by the first time x, so that the boundary time between the holding frame and the refresh frame is RS_clk_sync;

[0062] In at least one embodiment of the present invention, as Figure 2C shown, the duration of the refresh period TS can be the time between the rising edge of the first pulse of the starting voltage provided by STV and the falling edge of the second pulse of the synchronization signal TE. Generally, this time is shorter than the time of a whole frame, and the time of the clock signal frequency reduction can be further increased.

[0063] As Figure 3 shown, the one labeled TS is the refresh period; the one labeled TB1 is the first holding period, and the one labeled TB2 is the second holding period;

[0064] The start time of the refresh period TS can be advanced by the first time x compared to the falling edge of the first pulse of the synchronization signal TE, and the end time of the refresh period TS is the falling edge of the second pulse of the synchronization signal TE;

[0065] During the refresh period TS, the frequency of the first clock signal CK is greater than the frequency of the first clock signal CK during the first holding period TB1;

[0066] During the refresh period TS, the frequency of the first clock signal CK is greater than the frequency of the first clock signal CK during the second hold period TB2;

[0067] During the refresh period TS, the frequency of the second clock signal CB is greater than the frequency of the second clock signal CB during the first hold period TB1;

[0068] During the refresh period TS, the frequency of the second clock signal CB is greater than the frequency of the second clock signal CB during the second hold period TB2;

[0069] During the refresh period TS, the starting voltage provided by the starting voltage terminal STV has two downward pulses, and the driving signal OT generated by the driving module has two downward pulses;

[0070] The duration of the refresh period TS is greater than or equal to the sum of the first time t1 and the second time t2;

[0071] The first time t1 is the time between the falling edge of the first pulse of the starting voltage provided by STV and the falling edge of the second pulse of the starting voltage provided by STV;

[0072] The second time t2 is the time between the falling edge of the second pulse of the starting voltage provided by STV and the falling edge of the second pulse of TE.

[0073] In at least one embodiment of the present invention, x and t1 are relatively close. In theory, x can be equal to t1, but fine-tuning is required according to the actual effect of the driving signal (the purpose is to ensure the normal output of all driving signals).

[0074] In specific implementation, many driving signals require more than two pulses to play different roles in two stages. For example, when the driving signal is a reset control signal, its role in the first stage can be reset, and its role in the second stage can be on bais (bias control).

[0075] In at least one embodiment of the present invention, the boundary between adjacent refresh periods and hold periods is designed to be movable. When reducing the frequency of the clock signal in the hold period, the clock signal in the high-frequency part can retain the pulse provided by the starting voltage terminal, without affecting the generation of the driving signal and reducing the IC power consumption.

[0076] An embodiment of the present invention provides a signal providing module, which is applied to a display device. The display device includes a driving module, and the driving module is used to generate a driving signal according to the starting voltage provided by the starting voltage terminal and the clock signal provided by the clock signal terminal; the display period includes alternately arranged hold periods and refresh periods; the signal providing module includes:

[0077] An initial voltage providing circuit for setting the initial voltage as a DC voltage during the holding period; and,

[0078] A clock signal providing circuit for setting the frequency of the clock signal during the refresh period to be higher than the frequency of the clock signal during the holding period.

[0079] In a specific implementation, the signal providing module may include an initial voltage providing circuit and a clock signal providing circuit. During the holding period, the initial voltage providing circuit sets the initial voltage as a DC voltage; during the refresh period, the clock signal providing circuit sets the frequency of the clock signal to be higher than the frequency of the clock signal during the holding period. When the signal body using module according to the embodiment of the present invention is working, during low-frequency display, the display period may include a holding period and a refresh period that are arranged at intervals; during the holding period, the initial voltage providing circuit sets the initial voltage as a DC voltage, and the clock signal providing circuit sets the frequency of the clock signal during the refresh period to be higher than the frequency of the clock signal during the holding period, so as to reduce the power consumption of the IC (integrated circuit) without affecting signal transmission.

[0080] An embodiment of the present invention provides a signal providing module, which is applied to a display device, such as Figure 4 As shown, the display device includes a driving module 40, and the driving module 40 is electrically connected to an initial voltage terminal STV, a first clock signal terminal CLK, and a second clock signal terminal CKB, and is used to generate a driving signal OT according to the initial voltage provided by the initial voltage terminal STV, the first clock signal provided by the first clock signal terminal CLK, and the second clock signal provided by the second clock signal terminal CKB; the display period includes a holding period and a refresh period that are arranged at intervals; the signal providing module includes:

[0081] An initial voltage providing circuit 41, which is electrically connected to the initial voltage terminal STV and is used to set the initial voltage as a DC voltage during the holding period; and,

[0082] A clock signal providing circuit 42, which is respectively electrically connected to the first clock signal terminal CLK and the second clock signal terminal CKB, and is used to set the frequency of the first clock signal during the refresh period to be higher than the frequency of the first clock signal during the holding period, and set the frequency of the second clock signal during the refresh period to be higher than the frequency of the second clock signal during the holding period.

[0083] In at least one embodiment of the present invention, the initial voltage providing circuit is further used to set the initial voltage to include N pulses during the refresh period; N is an integer greater than 1.

[0084] In specific implementation, during the refresh period, the starting voltage providing circuit can set the starting voltage to include at least two pulses;

[0085] Optionally, the pulse can be a downward pulse, or the pulse can be an upward pulse.

[0086] In at least one embodiment of the present invention, the clock signal providing circuit is further configured to, during the refresh period, set the start time of the first pulse of the clock signal before the start time of the first pulse of the starting voltage.

[0087] In specific implementation, during the refresh period, the clock signal providing circuit sets the start time of the first pulse of the clock signal before the start time of the first pulse of the starting voltage, so that the driving signal generated by the driving module does not lose output pulses.

[0088] An embodiment of the present invention further provides a display device, including the above-mentioned signal providing module.

[0089] The display device according to at least one embodiment of the present invention further includes a driving module;

[0090] The starting voltage providing circuit in the signal providing module is configured to, during the refresh period, set the starting voltage to include N pulses; N is an integer greater than 1;

[0091] The driving module is configured to, during the refresh period, generate a driving signal according to the starting voltage and the clock signal, so that the driving signal has N pulses.

[0092] In specific implementation, the display device according to at least one embodiment of the present invention may include a driving module and a signal providing module. In the signal providing module, the starting voltage providing circuit sets the starting voltage to include N pulses during the refresh period. The driving module generates a driving signal according to the starting voltage and the clock signal during the refresh period, so that the driving signal has N pulses, so that the driving signal generated by the driving module does not lose output pulses.

[0093] The above is the preferred implementation manner of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A signal providing method, applied to a display device, wherein the display device comprises a driving module, wherein the driving module is used to generate a driving signal according to a starting voltage provided by a starting voltage terminal and a clock signal provided by a clock signal terminal; characterized in that: The display cycle includes a holding period and a refresh period set at intervals; the signal providing method includes: During the holding period, the starting voltage is set to a DC voltage; The frequency of the clock signal in the refresh period is set to be higher than the frequency of the clock signal in the retaining period.

2. The signal providing method according to claim 1, characterized in that: Also includes: During the refresh time period, the start voltage is set to include N pulses; N is an integer greater than 1.

3. The signal providing method according to claim 2, characterized in that: Also includes: In the refresh time period, the start time of the first pulse of the clock signal is set before the start time of the first pulse of the start voltage.

4. The signal providing method according to claim 2 or 3, characterized in that: Also includes: In the refresh time period, the driving module generates a driving signal according to the starting voltage and the clock signal, so that the driving signal has N pulses.

5. The signal providing method according to any one of claims 1 to 3, characterized in that: include: Subtract the first time x from the ath falling edge time of the synchronization signal to set the result as the start time of the bth refresh time period, and set the a+1th falling edge time of the synchronization signal as the end time of the bth refresh time period; a and b are both positive integers; x is positive or negative.

6. A signal providing module, applied to a display device, the display device comprising a driving module, the driving module is used to generate a driving signal according to a starting voltage provided by a starting voltage terminal and a clock signal provided by a clock signal terminal; characterized in that: The display cycle includes a holding period and a refresh period set at intervals; the signal providing module includes: a starting voltage providing circuit, used for setting the starting voltage to a DC voltage during the holding time period; and The clock signal providing circuit is used to set the frequency of the clock signal in the refresh period to be higher than the frequency of the clock signal in the retaining period.

7. The signal providing module according to claim 6, wherein: The starting voltage providing circuit is further used to set the starting voltage to include N pulses during the refresh time period; N is an integer greater than 1.

8. The signal providing module according to claim 7, characterized in that: The clock signal providing circuit is further used to set the start time of the first pulse of the clock signal before the start time of the first pulse of the start voltage during the refresh time period.

9. A display device, characterized in that: The method comprises a signal providing module as claimed in any one of claims 6 to 8.

10. The display device according to claim 9, characterized in that Also includes driver modules; The starting voltage providing circuit in the signal providing module is used to set the starting voltage to include N pulses during the refresh period; N is an integer greater than 1; The driving module is used to generate a driving signal according to a starting voltage and a clock signal during the refresh time period, so that the driving signal has N pulses.