Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a display area and a non-display area, in the display area, the display panel comprises pixel driving circuits arranged in an array and a plurality of data signal lines, and at least part of the pixel driving circuits located in the same column are electrically connected with the same data signal line; in the non-display area, the display panel comprises an isolation compensation module; the isolation compensation module is electrically connected with each data signal line, and the isolation compensation module receives the first control signal and the data signal of each data signal line; the isolation compensation module is used for controlling a signal transmission path of each data signal to each corresponding data signal line according to the first control signal; one data refresh cycle of the display panel comprises a data writing frame and a holding frame; in the holding frame, the first control signal comprises a non-enabling level, so that the transmission path of each data signal to each corresponding data signal line is in a turn-off state, the leakage current of the pixel driving circuit is effectively reduced, and the display uniformity is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Currently, popular applications such as short videos and games are widely loved. To meet the high-quality requirements for the display screens of short videos, games, etc., a high-frequency driving method is adopted to make the refresh rate of the display device relatively high. As a result, the power consumption of the display device becomes larger and larger, and the battery life becomes worse and worse.

[0003] To ensure the battery life of the display device, a low-frequency driving method is adopted in certain specific application scenarios to reduce the refresh rate of the display device. For example, when the display panel displays a static picture, a lower refresh rate can be used to reduce power consumption.

[0004] During low-frequency driving, the writing of a data voltage needs to be maintained for a long time. Due to the leakage current problem of the display panel, the data voltage will change significantly, resulting in a large difference between the actual light-emitting brightness of the pixel and the preset light-emitting brightness. Obvious screen shaking or flickering will occur during the screen refresh, affecting the display effect and user experience of the display device. Summary of the Invention

[0005] The present invention provides a display panel and a display device to improve the low-frequency flicker problem of the display panel and enhance the display effect of the display panel.

[0006] According to one aspect of the present invention, a display panel is provided, including: a display area and a non-display area;

[0007] In the display area, the display panel includes: pixel driving circuits arranged in an array and a plurality of data signal lines, and at least some of the pixel driving circuits in the same column are electrically connected to the same data signal line;

[0008] In the non-display area, the display panel includes: an isolation compensation module; the isolation compensation module is electrically connected to each of the data signal lines, and the isolation compensation module receives a first control signal and the data signals of each data signal line; the isolation compensation module is used to control the signal transmission path of each data signal to the corresponding data signal line according to the first control signal;

[0009] One data refresh cycle of the display panel includes a data writing frame and a holding frame; in the holding frame, the first control signal includes a non-enabling level, so that the signal transmission path of each data signal to the corresponding data signal line is in an off state.

[0010] According to another aspect of the present invention, a display device is provided, including: the above-mentioned display panel.

[0011] The display panel provided by the present invention electrically connects at least some of the pixel driving circuits in the same column in the display area to the same data signal line, so that each data signal line can provide data signals to at least some of the pixel driving circuits in the same column. By arranging an isolation compensation module in the non-display area, the isolation compensation module is electrically connected to each data signal line and receives a first control signal and the data signals of each data signal line, and can control the signal transmission paths of the respective data signals to the corresponding respective data signal lines according to the first control signal through the isolation compensation module. During the hold frame of each data refresh cycle, the first control signal is controlled to include a non-enabling level, so that the signal transmission paths of the respective data signals to the corresponding respective data signal lines are in an off state, and the data signal lines can be maintained at the preset data voltage written in the data write frame during the hold frame, effectively reducing the leakage current of the pixel driving circuit, making the voltage of the data signal output by the pixel driving circuit relatively stable, effectively improving the display uniformity, and being beneficial to enhancing the use experience of the display panel.

[0012] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0014] Figure 1 is a schematic structural diagram of a display panel of the prior art;

[0015] Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0016] Figure 3 is a driving timing diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0017] Figure 4 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0018] Figure 5 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0019] Figure 6It is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 7 It is a schematic structural diagram of yet another display panel provided by an embodiment of the present invention;

[0021] Figure 8 It is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present invention;

[0022] Figure 9 It is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present invention;

[0023] Figure 10 It is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present invention;

[0024] Figure 11 It is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present invention;

[0025] Figure 12 It is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present invention;

[0026] Figure 13 It is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present invention;

[0027] Figure 14 It is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present invention;

[0028] Figure 15 It is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present invention;

[0029] Figure 16 It is a driving timing diagram of yet another pixel driving circuit provided by an embodiment of the present invention;

[0030] Figure 17 It is a schematic structural diagram of yet another display panel provided by an embodiment of the present invention;

[0031] Figure 18 It is a schematic structural diagram of yet another display panel provided by an embodiment of the present invention;

[0032] Figure 19 It is a schematic structural diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0033] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0035] Figure 1 is a schematic structural diagram of a display panel in the prior art, as Figure 1 shown, in the display panel, the pixel driving circuit 10' is electrically connected to the data signal line DL', and the data voltage Vdata' is provided to the pixel driving circuit 10' through the data signal line DL'. In the data writing stage, the pixel driving circuit 10' is turned on so that the data voltage Vdata' is written into and stored in the pixel driving circuit 10', and can drive the corresponding pixel to emit light. In the holding stage, the pixel driving circuit 10' is turned off and the data voltage Vdata' transmitted on the data signal line DL' is set to zero, and the pixel driving circuit 10' continues to control the pixel to emit light through the stored data voltage Vdata'. At this time, the voltage difference between the end of the pixel driving circuit 10' electrically connected to the pixel and the end electrically connected to the data signal line DL' is relatively large, causing the pixel driving circuit 10' to continuously leak current. And because the time of the holding stage is relatively long during low-frequency driving, the duration of the leakage current of the pixel circuit 10' is relatively long, resulting in a relatively large voltage change of the data voltage Vdata', so that the difference between the actual light emission brightness of the pixel and the preset light emission brightness is relatively large, resulting in obvious screen shaking or flickering phenomena during the screen refresh, affecting the display effect of the display device during low-frequency driving, and thus affecting the user experience.

[0036] To solve the above technical problems, an embodiment of the present invention provides a display panel, including: a display area and a non-display area; in the display area, the display panel includes: pixel driving circuits arranged in an array and a plurality of data signal lines, at least some of the pixel driving circuits located in the same column are electrically connected to the same data signal line; in the non-display area, the display panel includes: an isolation compensation module; the isolation compensation module is electrically connected to each data signal line, and the isolation compensation module receives a first control signal and the data signals of each data signal line; the isolation compensation module is configured to control the signal transmission paths of the respective data signals to the corresponding respective data signal lines according to the first control signal; one data refresh cycle of the display panel includes a data writing frame and a holding frame; in the holding frame, the first control signal includes a non-enabling level, so that the signal transmission paths of the respective data signals to the corresponding respective data signal lines are in an off state.

[0037] By adopting the above technical solution, by arranging at least some of the pixel driving circuits located in the same column in the display area to be electrically connected to the same data signal line, each data signal line can provide data signals to at least some of the pixel driving circuits located in the same column. By arranging an isolation compensation module in the non-display area, the isolation compensation module is electrically connected to each data signal line and receives the first control signal and the data signals of each data signal line, and can control the signal transmission paths of the respective data signals to the corresponding respective data signal lines according to the first control signal. In the holding frame of each data refresh cycle, the first control signal is controlled to include a non-enabling level, so that the signal transmission paths of the respective data signals to the corresponding respective data signal lines are in an off state, and the data signal lines can maintain the voltage corresponding to the data signals written in the data writing frame in the holding frame, which can effectively reduce the leakage current of the pixel driving circuits, make the voltage of the data signals output by the pixel driving circuits relatively stable, effectively improve the display uniformity, and is beneficial to improving the use experience of the display panel.

[0038] Figure 2 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention, as Figure 2 shown, the display panel 100 includes: a display area A1 and a non-display area A2; in the display area A1, the display panel 100 includes: pixel driving circuits 10 arranged in an array and a plurality of data signal lines DL, at least some of the pixel driving circuits 10 located in the same column are electrically connected to the same data signal line DL; in the non-display area A2, the display panel 100 includes: an isolation compensation module 20; the isolation compensation module 20 is electrically connected to each data signal line DL, and the isolation compensation module 20 receives a first control signal VCT and the data signals Vdata of each data signal line DL; the isolation compensation module 20 is configured to control the signal transmission paths of the respective data signals Vdata to the corresponding respective data signal lines DL according to the first control signal VCT.

[0039] Specifically, pixel driving circuits 10 arranged in an array are provided in the display area A1, so that the display area A1 can achieve a display function through the pixel driving circuits 10. In the display area A1, at least some of the pixel driving circuits 10 located in the same column can be electrically connected to the same data signal line DL, so that each data signal line DL can provide data signals to at least some of the pixel driving circuits 10 located in the same column. In a feasible embodiment, each of the pixel driving circuits 10 located in the same column can be electrically connected to the same data signal line DL. At this time, each data signal line DL can provide data signals to all of the pixel driving circuits 10 located in the same column.

[0040] In the non-display area A2, an isolation compensation module 20 can be provided. The isolation compensation module 20 can include a control terminal, input terminals provided in one-to-one correspondence with the respective data signal lines DL, and output terminals provided in one-to-one correspondence with the respective data signal lines DL. Among them, the control terminal of the isolation compensation module 20 is used to receive a first control signal VCT. Each input terminal of the isolation compensation module 20 is used to receive a data signal Vdata to be transmitted to each data signal line DL, and each output terminal of the isolation compensation module 20 is electrically connected to the corresponding data signal line DL. Then, the isolation compensation module 20 can be turned on or off under the control of the first control signal VCT, and when it is turned on, it can make the signal transmission paths of the respective data signals Vdata to the corresponding data signal lines DL conductive, so that the data signal Vdata can be transmitted to the corresponding data signal line DL, and when the isolation compensation module 20 is turned off, it makes the signal transmission paths of the respective data signals Vdata to the corresponding data signal lines DL open, so that the respective data signals Vdata cannot be transmitted to the corresponding data signal lines DL.

[0041] Exemplarily, assuming that the display panel includes N data signal lines DL, then along the arrangement direction of the respective data signals, the data signals Vdata received by the respective data signal lines DL can be a first data signal Vdata1, a second data signal Vdata2, a third data signal Vdata3,..., an (N - 1)th data signal VdataN - 1, and an Nth data signal VdataN respectively. The data signals Vdata provided to the respective data signal lines DL can be set according to display requirements, and can be the same or different. The embodiments of the present invention do not make specific limitations thereto.

[0042] Figure 3 is a driving timing diagram of a pixel driving circuit provided by an embodiment of the present invention. With reference to Figure 2 and Figure 3, a data refresh period T of the display panel 100 includes a data writing frame T1 and a holding frame T2; in the holding frame T2, the first control signal VCT includes a non-enabling level, so that the signal transmission paths of the respective data signals Vdata to the corresponding respective data signal lines DL are in an off state.

[0043] Specifically, the data writing frame T1 may be a stage in which the pixel driving circuit 10 remains conductive, so that the data signal Vdata on the data signal line DL can be written into the pixel driving circuit 10 and stored. In the data writing frame T1, the first control signal VCT may be at an enabling level for at least part of the time, so that the isolation compensation module 20 is turned on, so that the respective data signals Vdata can be written into the corresponding data signal lines DL when the isolation compensation module 20 is turned on, so that the respective data signal lines DL can transmit the data signal Vdata to the electrically connected pixel driving circuit 10. At this stage, the pixel driving circuit 10 can be controlled to be turned on at the same time, so that the pixel driving circuit 10 can drive the pixel to emit light according to the data signal Vdata and store the data signal Vdata.

[0044] After entering the holding frame T2, the respective data signals Vdata received by the isolation compensation module 20 can be set to zero to reduce the charging time to the data signal line DL. At the same time, the pixel driving circuit 10 can be controlled to be turned off. At this time, the pixel driving circuit 10 drives the pixel to continue to emit light according to the stored data signal Vdata, which can reduce power consumption on the basis of ensuring the display of the picture.

[0045] It can be understood that for a non-self-luminous liquid crystal display panel, the pixel driving circuit 10 can drive the liquid crystal molecules to deflect according to the data signal Vdata, and different data signals Vdata result in different deflection angles of the liquid crystal molecules in the corresponding pixels, so that the light emission brightness of the pixels is different. Therefore, the pixels have different light emission brightnesses under the control of different data signals Vdata. For a self-luminous display panel including light-emitting elements, the pixel driving circuit can generate a driving current for driving the light-emitting elements to emit light according to the data signal Vdata, so that the light-emitting elements in the pixels emit light according to the driving current, and different data signals Vdata result in different driving currents generated by the pixel driving circuit, so that the light emission brightness of the light-emitting elements in the pixels can be different. The embodiments of the present invention do not specifically limit the type of the display panel. For the convenience of understanding, the embodiments of the present invention only exemplarily explain the technical solutions of the present invention with a non-self-luminous liquid crystal display panel.

[0046] Exemplarily, Figure 4 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention, specifically a schematic structural diagram of a pixel driving circuit in a liquid crystal display panel, as Figure 4As shown, the pixel driving circuit 10 includes a driving transistor T0 and a pixel capacitor C0; the gate of the driving transistor T0 receives a scanning signal Gout, the first pole of the driving transistor T0 is electrically connected to a data signal line DL, and the second pole of the driving transistor T0 is electrically connected to the pixel capacitor C0.

[0047] Specifically, the voltage value of the pixel capacitor C0 is the voltage value of the pixel. The driving transistor T0 can be turned on or off under the control of the scanning signal, and when turned on, transmits the data signal Vdata received by its first pole to the second pole, so that the data signal Vdata can be written into the pixel capacitor C0 for storage, enabling the pixel to emit light according to the data signal Vdata. After the data signal Vdata is written into the pixel capacitor C0, the driving transistor T0 can be controlled to disconnect, so that the pixel continues to emit light according to the data signal Vdata stored in the pixel capacitor C0, so that the current display screen continues to be displayed. At this time, if the data signal Vdata on the data signal line DL is set to zero, it will cause a large voltage difference between the first pole and the second pole of the driving transistor T0, resulting in leakage current in the driving transistor T0. For example, if the data signal Vdata written into the pixel capacitor C0 is 2.7V, then after the data signal Vdata on the data signal line DL is set to zero, the high voltage at the second pole of the driving transistor T0 will gradually leak current to the low potential at the first pole, causing the voltage of the pixel capacitor C0 to gradually decrease and the light emission brightness of the pixel to gradually decrease; or, if the data signal Vdata written into the pixel capacitor C0 is -2.7V, then after the data signal Vdata on the data signal line DL is set to zero, the high voltage at the first pole of the driving transistor T0 will gradually leak current to the low potential at the second pole, causing the voltage of the pixel capacitor C0 to gradually increase, and also causing the light emission brightness of the pixel to gradually decrease. In addition, a long holding frame T2 in the low-frequency driving mode will result in a long leakage current time, causing a large difference between the voltage at the second pole of the driving transistor T0 (i.e., the voltage of the pixel capacitor C0) and the voltage of the data signal Vdata written in the data writing frame T1, resulting in a large degree of reduction in the light emission brightness of the pixel. Then, the light emission brightness at the initial stage and the end stage of the pixel within the same data refresh cycle T is significantly reduced. When refreshing the data of the same display screen multiple times, it will also cause a sudden change in the light emission brightness of the pixel when the data signal Vdata is rewritten in the data writing frame T1, resulting in obvious screen shaking or flickering phenomena, affecting the use experience.

[0048] Based on the above problems, while maintaining frame T2, the first control signal VCT can include a non-enabling level to control the isolation compensation module 20 to turn off, so that the zero potential of each data signal Vdata will not be transmitted to each data signal line DL, enabling the data signal lines DL to maintain the data signal Vdata written in the data write frame T1. Assuming that the data signal Vdata provided to the data signal lines DL in the data write frame T1 is the preset data voltage Vd0, then at both the end where the pixel driving circuit 10 outputs the data signal Vdata and the end that receives the data signal Vdata in the hold frame T2, they are both maintained at the preset data voltage Vd0, that is, both the first pole and the second pole of the driving transistor T0 are at the preset data voltage Vd0, effectively reducing the voltage difference across the driving transistor T0 in the pixel driving circuit 10, thereby effectively reducing the leakage current situation of the driving transistor T0 in the pixel driving circuit 10, making the voltage of the pixel capacitor C0 in the pixel driving circuit 10 relatively stable, and thus being able to effectively reduce the difference in the light emission brightness of the pixel at the end of the hold frame T2 and the light emission brightness of the data write frame T1, thereby being able to effectively improve the screen shaking or flickering phenomenon during screen refreshing, effectively improving the display uniformity, especially being able to effectively improve the display uniformity during low-frequency driving of the display device, which is beneficial to enhancing the user experience.

[0049] Exemplarily, with reference to Figure 2 、 Figure 3 and Figure 4 , the moment when the first control signal VCT jumps from the enabling level to the non-enabling level is the first moment t1; the first moment t1 and the zeroing moment t2 of the data signal Vdata are the same moment. In this way, it can be ensured that when the data signal Vdata is zeroed, the isolation compensation module 20 is controlled to turn off simultaneously, and it can be avoided that the zero potential of the data signal Vdata is written into the data signal line DL, thereby avoiding excessive voltage difference across the pixel driving circuit 10 and leakage current, that is, avoiding excessive voltage difference between the first pole and the second pole of the driving transistor T0, and being able to avoid the screen shaking or flickering phenomenon during low-frequency driving, and improving the display uniformity during low-frequency driving.

[0050] Or, Figure 5 is another driving timing diagram of the pixel circuit provided by the embodiment of the present invention. With reference to Figure 2 、 Figure 3 and Figure 5 , the moment when the first control signal VCT jumps from the enabling level to the non-enabling level is the first moment t1, and the first moment t1 is before the zeroing moment t2 of the data signal Vdata. In this way, it can be ensured that the isolation compensation module 20 is controlled to turn off first before the data signal Vdata is zeroed, and it can also avoid the zero potential of the data signal Vdata being written into the data signal line DL, being able to avoid the screen shaking or flickering phenomenon during low-frequency driving, and improving the display uniformity during low-frequency driving.

[0051] Exemplarily, the first electrode of the driving transistor T0 can be set as the drain electrode, the second electrode as the source electrode, and the control electrode as the gate electrode. Moreover, the driving transistor T0 can be a P-type MOS transistor or an N-type MOS transistor, and the embodiments of the present invention do not make specific limitations in this regard. When the driving transistor T0 is a P-type MOS transistor, its enabling level is a low level and its non-enabling level is a high level, that is, when the scan signal Gout is at a low level, the driving transistor T0 is controlled to conduct, and when the scan signal Gout is at a high level, the driving transistor T0 is controlled to turn off; when the driving transistor T0 is an N-type MOS transistor, its enabling level is a high level and its non-enabling level is a low level, that is, when the scan signal Gout is at a high level, the driving transistor T0 is controlled to conduct, and when the scan signal Gout is at a low level, the driving transistor T0 is controlled to turn off. Without special instructions, the following embodiments will explain the technical solutions of the present invention with the driving transistor T0 being an N-type MOS transistor.

[0052] Exemplarily, referring to Figure 2 , in the display area A1, the display panel 100 further includes scan signal lines SCAN; at least some of the pixel driving circuits 10 in the same row are electrically connected to the same scan signal line SCAN. In this way, it is possible to achieve a progressive scan of each pixel driving circuit 10 in the display area A1, and each pixel driving circuit 10 can perform data refreshing row by row. In addition, a shift register circuit (not shown in the figure) can be provided in the non-display area A2, and a sequentially shifted scan signal Gout is output to each scan signal line SCAN through the shift register circuit to achieve a progressive scan of each pixel driving circuit 10.

[0053] For the display panel provided by the embodiments of the present invention, by setting at least some of the pixel driving circuits in the same column in the display area to be electrically connected to the same data signal line, each data signal line can provide data signals to at least some of the pixel driving circuits in the same column. By providing an isolation compensation module in the non-display area, the isolation compensation module is electrically connected to each data signal line and receives the first control signal and the data signals of each data signal line. It is possible to control the signal transmission path of each data signal to the corresponding data signal line through the isolation compensation module according to the first control signal. During the hold frame of each data refresh cycle, controlling the first control signal to include a non-enabling level so that the signal transmission path of each data signal to the corresponding data signal line is in an off state, it is possible to make the data signal line maintain the preset data voltage written in the data write frame during the hold frame, effectively reducing the leakage current of the pixel driving circuit, making the voltage of the data signal output by the pixel driving circuit relatively stable, effectively improving the display uniformity, and being beneficial to enhancing the user experience of the display panel.

[0054] Exemplarily, referring to Figure 3, during two adjacent data refresh cycles T, the polarities of the data signals Vdata provided to the data signal lines DL can be different. In this way, when a liquid crystal layer is included in the pixel, flexible control of the liquid crystal molecules in the liquid crystal layer can be ensured.

[0055] Optionally, Figure 6 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. As Figure 6 shown, the isolation compensation module 20 includes switch units 21 corresponding to each data signal line DL one by one; the control ends of the switch units 21 receive a first control signal VCT, the first ends of the switch units 21 receive the data signal Vdata, and the second ends of the switch units 21 are electrically connected to the corresponding data signal lines DL.

[0056] Specifically, one switch unit 21 can be correspondingly arranged for each data signal line DL, so that each data signal Vdata can be transmitted to the corresponding data signal line DL through a separate channel, and signal crosstalk can be avoided. Among them, the first control signal VCT can be transmitted by the control signal line L0, and the control ends of the switch units 21 are all electrically connected to the control signal line L0, so that the switch units 21 can be controlled to be turned on or off by the first control signal VCT transmitted by the control signal line L0.

[0057] Optionally, Figure 7 is a schematic structural diagram of yet another display panel provided by an embodiment of the present invention. As Figure 7 shown, the switch unit 21 includes a switching transistor T1; the first pole of the switching transistor T1 receives the data signal Vdata, the second end of the switching transistor T1 is electrically connected to the corresponding data signal line DL, and the gate of the switching transistor T1 receives the first control signal VCT.

[0058] Specifically, the gates of the switching transistors T1 in each switch unit 21 are all electrically connected to the control signal line L0, and can be turned on or off under the control of the first control signal VCT transmitted by the control signal line L0. Taking one of the switching transistors T1 as an example, when the first control signal VCT controls the switching transistor T1 to be turned on, the data signal Vdata received by its first pole can be transmitted to the data signal line DL electrically connected to its second pole. When the first control signal VCT controls the switching transistor T1 to be turned off, the data signal Vdata received by its first pole cannot be transmitted to the data signal line DL electrically connected to its second pole.

[0059] Optionally, referring to Figure 3 or Figure 5, during the stage when the first control signal VCT remains at a non - enabling level, each data signal Vdata includes a first voltage V1. Among them, the first voltage V1 is the initial voltage of the data signal Vdata. In a preferred embodiment, the first voltage can be 0V, that is, during the stage when the first control signal VCT remains at a non - enabling level, the data signal Vdata can be set to zero. In this way, the time for the data signal Vdata output by the driving IC to remain at a relatively high voltage can be reduced, thereby effectively reducing power consumption.

[0060] Optionally, Figure 8 is another driving timing diagram of the pixel driving circuit provided by the embodiment of the present invention. With reference to Figure 2 、 Figure 4 and Figure 8 , in the holding frame T2, the first control signal VCT includes an effective pulse EP; the first control signal VCT between two adjacent effective pulses EP is at a non - enabling level; during the stage when the first control signal VCT is an effective pulse, each data signal Vdata is a compensation voltage Vd1 corresponding to each data signal line DL.

[0061] Specifically, in the display panel 100, there may be parasitic capacitance between the data signal line DL and other signal lines or components, etc. Then, after the driving transistor T0 in the pixel driving circuit 10 is turned off and each switch unit 21 in the isolation compensation module 20 is turned off in the holding frame T2, the voltage stored on the data signal line DL may leak current through the parasitic capacitance, thereby causing the data signal Vdata on the data signal line DL to change. At this time, the voltage imbalance between the first pole and the second pole of the driving transistor T0 in the pixel driving circuit 10 will also occur, resulting in a leakage current phenomenon, which affects the accuracy of pixel light emission. Accordingly, the first control signal VCT can be controlled to output an effective pulse EP in the holding frame T2, and during the period when the first control signal VCT outputs the effective pulse EP, each data signal Vdata is controlled to output a compensation voltage Vd1, and the compensation voltage Vd1 is related to the data signal Vdata in the data writing stage, so that the voltage compensation for the data signal Vdata on each data signal line DL meets the display requirements of the corresponding pixels. In this way, the leakage current of the driving transistor T0 can be further reduced, thereby further improving the phenomena of screen shaking and flickering.

[0062] Optionally, Figure 9 is another driving timing diagram of the pixel driving circuit provided by the embodiment of the present invention. With reference to Figure 2 、 Figure 4 and Figure 9 , in the data writing frame T1, the data signal Vdata is a preset data voltage Vd0; the absolute value of the compensation voltage Vd1 is greater than the absolute value of the preset data voltage Vd0.

[0063] Specifically, the display screen has corresponding grayscale data, which is reflected as the data voltage of the data signal Vdata. In the data writing frame T1, a preset data voltage Vd0 is provided to each corresponding pixel according to the grayscale data of the current display screen, so that each pixel emits light according to the received preset data voltage Vd0, and the display screen can be accurately displayed. In the holding frame T2, since the driving transistor T0 is in the off state, in order to avoid the leakage current of the driving transistor T0 affecting the light emission accuracy, the pixel capacitor C0 can be voltage compensated. If voltage compensation is to be performed on the pixel capacitor C0 electrically connected to the second pole of the driving transistor T0 so that the pixel emits light accurately, the absolute value of the compensation voltage Vd1 provided to the first pole of the driving transistor T0 can be made greater than the absolute value of the preset data voltage Vd0 provided to the data signal line DL in the data writing frame T1, that is, |Vd1| > |Vd0|. In this way, it can be ensured that the voltage difference between the first pole and the second pole of the driving transistor T0 is too large to generate leakage current, so that the voltage of the first pole and the second pole of the driving transistor T0 gradually balances, thereby realizing the voltage compensation of the pixel capacitor C0 and ensuring that the pixel emits light accurately.

[0064] Optionally, Figure 10 is another driving timing diagram of the pixel driving circuit provided by the embodiment of the present invention. With reference to Figure 2 , Figure 4 and Figure 10 , the absolute value of the compensation voltage Vd1 is less than the absolute value VEP of the pulse voltage of the first control signal.

[0065] Specifically, in the holding frame T2, the pulse voltage VEP when the first control signal VCT outputs an effective pulse EP can be greater than the compensation voltage Vd1. In this way, the larger pulse voltage VEP can ensure that each switching transistor T1 in the isolation compensation module 20 is fully turned on at a faster speed, thereby improving the charging speed of the compensation voltage Vd1 to the data signal line DL, so that the voltage on the data signal line DL quickly reaches the voltage value corresponding to the compensation voltage Vd1, thereby enabling timely voltage compensation of the pixel capacitor C0 in the pixel driving circuit 10 and effectively ensuring accurate light emission of the pixel.

[0066] Optionally, Figure 11 is another driving timing diagram of the pixel driving circuit provided by the embodiment of the present invention. Referring to Figures 8 to 11 any one of the drawings, in the holding frame T2, the first control signal VCT includes N1 effective pulses EP, where N1 ≥ 1 and N1 is an integer.

[0067] Among them, Figures 8 to 10 shows N1 = 1, that is, in the holding frame T2, the first control signal VCT includes 1 effective pulse, which can perform voltage compensation on the pixel once in the holding frame T2 to improve the light emission accuracy of the pixel. Refer toFigure 11 Moreover, N1>1 can be set, that is, while maintaining that the first control signal VCT of the holding frame T2 includes multiple effective pulses. In this way, the holding frame T2 can provide the compensation voltage Vd1 to the data signal line DL multiple times, so that the pixel can be voltage-compensated multiple times, and the accuracy of pixel light emission can be further ensured when the duration of the holding frame T2 is relatively long.

[0068] It can be understood that Figure 11 Exemplarily, N1 = 3 is shown, that is, the first control signal VCT of the holding frame T2 includes 3 effective pulses. It can be understood that in other feasible embodiments of the present invention, N1 = 2 or N1>3 can also be set, so that the number of effective pulses EP of the first control signal VCT of the holding frame T2 is 2 or more than 3. The specific value of N1 can be determined according to the duration of the holding frame T2 and the pulse width of the first control signal VCT, and the embodiments of the present invention do not make specific limitations on this.

[0069] Optionally, Figure 12 is the driving timing diagram of another pixel driving circuit provided by the embodiment of the present invention. Refer to Figure 12 , refer to Figure 3 , Figure 5 and Figures 8 to 12 Any one of the drawings, in the data writing frame T1, the first control signal VCT includes N2 effective pulses, N2≥1 and N1 is an integer.

[0070] Specifically, Figure 3 , Figure 5 and Figures 8 to 11 show N2 = 1, that is, the first control signal VCT includes 1 effective pulse in the data writing frame T1. At this time, the pulse width of this effective pulse can be relatively large, so that the conduction time of each switching transistor T1 in the isolation compensation module 20 is relatively long, so as to ensure that each data signal Vdata is fully written into the corresponding data signal line DL during the conduction stage of the switching transistor T1.

[0071] Exemplarily, refer to Figure 3 and Figures 8 to 11 Any one of the drawings, N2 = 1; in the data writing frame T1, the pulse width of the first control signal VCT is equal to the time length of the data writing frame T1. In this way, it can be further ensured that each data signal Vdata is fully written into the corresponding data signal line DL during the conduction stage of the switching transistor T1, so as to further ensure the accuracy of pixel light emission.

[0072] Or, refer to Figure 12, it is also possible to set N2 > 1, that is, to make the first control signal VCT in the data writing frame T1 include multiple valid pulses. At this time, since the data signal Vdata remains at the preset data voltage Vd0 in the data writing frame T1, when the first control signal VCT includes multiple valid pulses in the data writing frame T1, each switching transistor T1 in the isolation compensation module 20 can be controlled to conduct multiple times. In this way, the data signal Vdata at the first pole can be transmitted to the corresponding data signal line DL each time it conducts, so that the voltage on the data signal line DL can reach the preset data voltage Vd0 through multiple conductions, and then the voltage of the pixel capacitor C0 can reach the preset data voltage Vd0 through multiple chargings, so as to be able to drive the pixel to emit light accurately.

[0073] Exemplarily, when the first control signal VCT includes multiple valid pulses in the data writing frame T1, since the driving transistor T0 is in the conducting state, the pulse voltage of the first control signal VCT in the data writing frame T1 can be made less than the pulse voltage in the holding frame T1. After the voltage of the data signal line DL reaches the preset data voltage Vd0 through multiple chargings, the preset data voltage Vd0 can be written into the pixel capacitor C0 through the driving transistor T0. Or, Figure 13 is the driving timing diagram of another pixel driving circuit provided by an embodiment of the present invention. Refer to Figure 13 , the pulse voltage of the first control signal VCT in the data writing frame T1 can be equal to the pulse voltage in the holding frame T1, so as to drive the switching transistor T1 to fully open at a faster speed and improve the charging speed of the data signal Vdata to the data signal line DL.

[0074] Optionally, Figure 14 is the driving timing diagram of another pixel driving circuit provided by an embodiment of the present invention. As Figure 14 shown, N1 ≥ 2 and N2 ≥ 2; the pulse width of the first control signal VCT in the holding frame T2 is greater than the pulse width in the data writing frame T1.

[0075] Specifically, compared with the case where the data signal Vdata continuously maintains the preset data voltage Vd0 in the data write frame T1 and the voltage of the data signal line DL can reach the preset data voltage Vd0 by controlling the switch transistor T1 to conduct multiple times, the data signal Vdata in the hold frame T2 can jump from the zero voltage to the compensation voltage Vd1 only when the switch transistor T1 conducts. At this time, the data signal Vdata has a charging process from the zero voltage to the compensation voltage Vd1. Therefore, setting the pulse width of the first control signal VCT in the hold frame T2 to be greater than the pulse width in the data write frame T1 can ensure that each switch transistor T1 in the isolation switch module 20 in the hold frame T2 fully writes the received compensation voltage Vd1 to the data signal line DL, and further ensure that the compensation voltage Vd1 received by the data signal line DL can effectively compensate the voltage of the pixel.

[0076] Exemplarily, referring to Figure 12 or Figure 13 , when N1 = 1 and N2 ≥ 2, it is also possible to make the pulse width of the first control signal VCT in the hold frame T2 greater than the pulse width in the data write frame T1, which can also ensure that each switch transistor T1 in the isolation switch module 20 in the hold frame T2 fully writes the received compensation voltage Vd1 to the data signal line DL, and can ensure the voltage compensation of the pixel.

[0077] Optionally, Figure 15 is another driving timing diagram of the pixel driving circuit provided by the embodiment of the present invention. As Figure 15 shown, N1 ≥ 2; in the same hold frame T2, when the first control signal VCT outputs each effective pulse EP, the compensation voltage Vd1 received by the same data signal line DL is different.

[0078] Specifically, due to the signal interference of other signal lines or components, the leakage current situation of the data signal line Vdata in different stages of the hold frame T2 is different, and the preset data voltages Vd0 written to each data signal line DL in the data write frame T1 may also be different. Therefore, when the first control signal VCT outputs multiple effective pulses EP, different compensation voltages Vd1 provided to the data signal line DL can be set so that the compensation voltage Vd1 received by the data signal line DL can compensate the voltage of the pixel capacitor C0 to the preset data voltage Vd0 to ensure the accuracy of pixel light emission. Each time the compensation voltage Vd1 provided to the data signal line DL can be calibrated according to the leakage current situation of the data signal line Vdata in different stages of the hold frame T2 and the preset data voltage Vd0 written in the data write frame T1. The embodiment of the present invention does not make specific limitations on this.

[0079] Optionally, Figure 16 is another driving timing diagram of the pixel driving circuit provided by the embodiment of the present invention. Referring to Figures 8 to 16In any one of the accompanying drawings, while maintaining frame T2, the data signal Vdata further includes N3 compensation voltages Vd1, where N3 ≥ 1 and N3 is an integer; the data signal Vdata between two adjacent compensation voltages Vd1 is a first voltage; when the data signal Vdata is the compensation voltage Vd1, the first control signal VCT includes N4 valid pulses, where N4 ≥ 1 and N4 is an integer; the first control signal VCT between two adjacent valid pulses is a non - enabling level.

[0080] Specifically, referring to Figures 8 to 15 In any one of the accompanying drawings, during the ta stage when the data signal Vdata maintains the compensation voltage Vd1 in frame T2, the first control signal VCT may include 1 valid pulse EP, that is, N4 = 1. Then, when the valid pulse EP of the first control signal VCT controls the switching transistor T1 in the isolation compensation module 20 to conduct, the compensation voltage Vd1 can be transmitted to the corresponding data signal line DL through the conducting switching transistor T1.

[0081] Or referring to Figure 16 , during the ta stage when the data signal Vdata maintains the compensation voltage Vd1 in frame T2, the first control signal VCT may include multiple valid pulses EP, that is, N4 > 1. By controlling the switching transistor T1 in the isolation compensation module 20 to conduct multiple times, the compensation voltage Vd1 can be provided to the data signal line DL multiple times, which can avoid large changes in the voltage on the data signal line DL due to leakage current, thereby avoiding leakage current of the driving transistor T0 in the pixel driving circuit 10 and ensuring the accuracy of pixel light emission. Moreover, during the ta stage when the data signal Vdata maintains the compensation voltage Vd1 in frame T2 and N4 > 1, the holding time of the compensation voltage Vd1 can be longer. In this way, the number of transitions of the data signal Vdata in frame T2 from the first voltage V1 to the compensation voltage Vd1 can be reduced, the charging times of the driving IC for the data signal Vdata can be reduced, and thus the power consumption can be further reduced.

[0082] Optionally, Figure 17 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. As Figure 17 shown, in the non - display area A2, the display panel further includes a bonding area A21; the bonding area A21 is electrically connected to the isolation compensation module 20 and is at least used to output the first control signal VCT to the isolation compensation module 20 and output the data signal Vdata of each data signal line DL to the isolation compensation module 20.

[0083] Specifically, bonding pads can be set in the bonding area A21. The bonding pads are electrically connected to the isolation compensation module 20, and the bonding pads can be set to be electrically connected to the driving IC. Then, each data signal Vdata and the first control signal VCT provided by the driving IC can be transmitted to the isolation transmission module 20 through the bonding pads.

[0084] Exemplarily, the driving IC can be set in the glass step area of the display panel, that is, the driving IC can be set in the COG (Chip on Glass) manner, or the driving IC can be set on the FPC (flexible printed circuit board), that is, the driving IC can be set in the COF (Chip on FPC) manner. The embodiments of the present invention do not make specific limitations on this.

[0085] Optionally, referring to Figure 17 , the non-display area A2 further includes a fan-out area A22; the fan-out area A22 includes fan-out traces L1 provided corresponding to each data signal line DL one by one; the bonding area A21 is located on the side of the fan-out area A22 away from the display area A1. By setting the fan-out traces L1, it is beneficial to reduce the area of the bonding area A21, that is, it is beneficial to reduce the occupied space of the bonding pads on the display panel 100, which is beneficial to realizing the narrow border design of the display panel 100, and can enable the accurate transmission of each data signal Vdata, the first control signal VCT, and other signals.

[0086] Exemplarily, the isolation compensation module 20 can be set at a position adjacent to the display area A1 in the non-display area A2. Optionally, continuing to refer to Figure 17 , the isolation compensation module 20 is located between the fan-out area A22 and the display area A1; the bonding area A21 is electrically connected to the isolation compensation module 20 through each fan-out trace L1. In this way, the bonding area A21 can be electrically connected to the corresponding switching transistors T1 in the isolation compensation module 20 through each fan-out trace L1. And when the isolation compensation module 20 is located between the fan-out area A22 and the display area A1, fan-out traces L1 corresponding to the control signal line L0 can also be set in the fan-out area A22, so that the control signal line L0 for transmitting the first control signal VCT in the isolation compensation module 20 is electrically connected to the bonding area A21 through the fan-out traces.

[0087] Optionally, Figure 18 is a schematic structural diagram of another display panel provided by the embodiment of the present invention. As shown in Figure 18 , the isolation driving module 20 is located between the bonding area A21 and the fan-out area A22; the isolation driving module 20 is electrically connected to each data signal line DL through each fan-out trace L1. In this way, the occupied space of the isolation compensation module 20 and the bonding area A21 can be relatively small, and the narrow border of the display panel 100 can be further realized.

[0088] Based on the same inventive concept, an embodiment of the present invention further provides a display device. The display device includes the display panel provided in any embodiment of the present invention. Therefore, the display device provided in the embodiment of the present invention includes the technical features of the display panel provided in any embodiment of the present invention, and can achieve the beneficial effects of the display panel provided in any embodiment of the present invention. For the same parts, reference may be made to the description of the display panel provided in the embodiment of the present invention above, and details are not described herein again.

[0089] Exemplarily, Figure 19 FIG. is a schematic structural diagram of a display device provided in an embodiment of the present invention. As Figure 19 shown, the display device 200 includes the display panel 100 provided in the embodiment of the present invention. The display device 200 provided in the embodiment of the present invention may be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control devices, touch interaction terminals, etc. The embodiment of the present invention does not make special limitations in this regard.

[0090] It should be understood that various forms of the processes shown above may be used, steps may be reordered, added or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. No limitation is made herein.

[0091] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: Display area and non-display area; In the display area, the display panel includes: a pixel driving circuit and a plurality of data signal lines arranged in an array, and at least part of the pixel driving circuits in the same column are electrically connected to the same data signal line; In the non-display area, the display panel includes: an isolation compensation module; the isolation compensation module is electrically connected to each of the data signal lines, and the isolation compensation module receives a first control signal and a data signal of each data signal line; the isolation compensation module is used to control a signal transmission path of each of the data signals to the corresponding data signal lines according to the first control signal; A data refresh cycle of the display panel includes a data writing frame and a holding frame; in the holding frame, the first control signal includes a non-enabling level so that the signal transmission path of each of the data signals to the corresponding data signal lines is in an off state.

2. The display panel according to claim 1, characterized in that: The isolation compensation module includes a switch unit corresponding to each of the data signal lines one by one; The control end of the switch unit receives the first control signal, the first end of the switch unit receives the data signal, and the second end of the switch unit is electrically connected to the corresponding data signal line.

3. The display panel according to claim 2, characterized in that: The switch unit includes a switch transistor; The first electrode of the switch transistor receives the data signal, the second end of the switch transistor is electrically connected to the corresponding data signal line, and the gate of the switch transistor receives the first control signal.

4. The display panel according to claim 1, characterized in that: The moment when the first control signal jumps from the enable level to the non-enable level is the first moment; The first time is the same as the time when the data signal is reset to zero, or the first time is before the time when the data signal is reset to zero.

5. The display panel according to claim 1, characterized in that: In the holding frame, during a stage in which the first control signal is held at a non-enable level, each of the data signals includes a first voltage.

6. The display panel according to claim 1, characterized in that: In the holding frame, the first control signal includes a valid pulse; the first control signal between two adjacent valid pulses is the non-enable level; In the stage where the first control signal is a valid pulse, each of the data signals is a compensation voltage corresponding to each of the data signal lines.

7. The display panel according to claim 6, characterized in that: In the data writing frame, the data signal is a preset data voltage; An absolute value of the compensation voltage is greater than an absolute value of the preset data voltage.

8. The display panel according to claim 6, characterized in that: An absolute value of the compensation voltage is smaller than an absolute value of the pulse voltage of the first control signal.

9. The display panel according to claim 1, characterized in that: In the holding frame, the first control signal includes N1 valid pulses, where N1≥1 and N1 is an integer.

10. The display panel according to claim 9, characterized in that: In the data writing frame, the first control signal includes N2 valid pulses, N2≥1 and N1 is an integer.

11. The display panel according to claim 10, characterized in that: N1≥2 and N2≥2; The pulse width of the first control signal in the hold frame is greater than the pulse width in the data write frame.

12. The display panel according to claim 10, characterized in that: N2＝1； In the data writing frame, the pulse width of the first control signal is equal to the time length of the data writing frame.

13. The display panel according to claim 9, characterized in that: N1≥2； In the same holding frame, when the first control signal outputs each valid pulse, the same data signal line receives different compensation voltages.

14. The display panel according to claim 5, characterized in that: In the holding frame, the data signal further includes N3 compensation voltages, N3≥1 and N3 is an integer; the data signal between two adjacent compensation voltages is a first voltage; When the data signal is the compensation voltage, the first control signal includes N4 valid pulses, N4≥1 and N4 is an integer; the first control signal between two adjacent valid pulses is the non-enable level.

15. The display panel according to claim 1, characterized in that: The pixel driving circuit includes a driving transistor and a pixel capacitor; The gate of the driving transistor receives a scanning signal, the first electrode of the driving transistor is electrically connected to the data signal line, and the second electrode of the driving transistor is electrically connected to the pixel capacitor.

16. The display panel according to claim 1, characterized in that: In the display area, the display panel further includes a scanning signal line; At least part of the pixel driving circuits in the same row are electrically connected to the same scanning signal line.

17. The display panel according to claim 1, characterized in that: In the non-display area, the display panel further includes a binding area; The binding area is electrically connected to the isolation compensation module, and is at least used to output a first control signal to the isolation compensation module, and output a data signal of each of the data signal lines to the isolation compensation module.

18. The display panel according to claim 17, characterized in that: The non-display area also includes a fan-out area; the fan-out area includes fan-out wirings arranged in one-to-one correspondence with each of the data signal lines; The binding area is located at a side of the fan-out area away from the display area.

19. The display panel according to claim 18, characterized in that: The isolation compensation module is located between the fan-out area and the display area; The binding area is electrically connected to the isolation driving module through the fan-out wirings.

20. The display panel according to claim 18, characterized in that: The isolation driving module is located between the binding area and the fan-out area; The isolation driving module is electrically connected to each of the data signal lines through each of the fan-out wirings.

21. A display device, characterized in that: A display panel comprising any one of claims 1 to 20.

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