Memory device, memory system and operating method thereof

Abstract

The embodiment of the invention discloses a memory device, a memory system and an operation method of the memory system. The memory system comprises the memory device and a memory controller coupled with the memory device. The memory device includes a plurality of memory cells; the memory controller is configured to: receive a read request that needs to perform a first read operation on a target memory cell; acquiring data retention time of the target storage unit; and based on the data retention time of the target storage unit, determining the magnitude of the voltage which needs to be applied to the word line adjacent to the word line coupled with the target storage unit when the first reading operation is carried out.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor technologies, including but not limited to a memory device, a memory system, and an operation method thereof. Background Art

[0002] With the rapid development of information technology, the technology of memory has also been continuously broken through and innovated. Memory is a crucial component in a computer system. It is responsible for storing and reading data, directly affecting the performance of the computer and the user experience. In the past few decades, memory has experienced many important technological breakthroughs and innovations. However, memory still faces many challenges. How to continuously improve the performance of memory has become an urgent problem to be solved. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory device and an operation method thereof, a memory system and an operation method thereof.

[0004] In a first aspect, embodiments of the present disclosure provide a memory system. The memory system includes a memory device and a memory controller coupled to the memory device. The memory device includes a plurality of memory cells. The memory controller is configured to:

[0005] Receive a read request for performing a first read operation on a target memory cell;

[0006] Obtain the data retention time of the target memory cell;

[0007] Based on the data retention time of the target memory cell, determine the magnitude of the voltage to be applied to a word line adjacent to the word line coupled to the target memory cell when performing the first read operation.

[0008] In a second aspect, embodiments of the present disclosure further provide a memory device. The memory device includes a peripheral circuit and a memory array coupled to the peripheral circuit. The memory array includes a plurality of memory cells. The peripheral circuit is configured to:

[0009] Apply a read voltage to the word line coupled to the target memory cell to perform a read operation on the target memory cell;

[0010] Apply a second conduction voltage to a word line adjacent to the word line coupled to the target memory cell during the read operation; and

[0011] Apply a third conduction voltage to word lines other than the word line coupled to the target memory cell and the word line adjacent to the word line coupled to the target memory cell during the read operation; wherein the magnitude of the second conduction voltage is different from the magnitude of the third conduction voltage.

[0012] In a third aspect, embodiments of the present disclosure further provide a memory system, the memory system including a memory device and a memory controller coupled to the memory device; the memory device includes a plurality of memory cells; the memory controller is configured to:

[0013] Receive a read request for performing a first read operation on a target memory cell to perform the first read operation on the target memory cell;

[0014] Determine a first conduction voltage to be applied to a word line adjacent to the word line to which the target memory cell is coupled;

[0015] Receive a first read result of the first read operation;

[0016] When the first read result indicates a read failure, determine a second conduction voltage to be applied to a word line adjacent to the word line to which the target memory cell is coupled to perform a second read operation on the target memory cell; the magnitude of the first conduction voltage is different from the magnitude of the second conduction voltage.

[0017] In a fourth aspect, embodiments of the present disclosure further provide a memory device, the memory device including a peripheral circuit and a memory array coupled to the peripheral circuit, the memory array including a plurality of memory cells, the peripheral circuit being configured to:

[0018] Receive a read request for applying a first conduction voltage to a word line adjacent to the word line to which a target memory cell is coupled to perform a first read operation on the target memory cell;

[0019] Send a first read result of the first read operation;

[0020] When the first read result indicates a read failure, receive a read request for applying a second conduction voltage to a word line adjacent to the word line to which the target memory cell is coupled to perform a second read operation on the target memory cell; the magnitude of the first conduction voltage is different from the magnitude of the second conduction voltage.

[0021] In a fifth aspect, embodiments of the present disclosure further provide an operation method of a memory system, including:

[0022] Receive a read request for performing a first read operation on a target memory cell;

[0023] Obtain the data retention time of the target memory cell;

[0024] Based on the data retention time of the target memory cell, determine the magnitude of the voltage to be applied to a word line adjacent to the word line to which the target memory cell is coupled when performing the first read operation.

[0025] In a sixth aspect, an embodiment of the present disclosure further provides an operation method for a memory system, including:

[0026] Receiving a read request for performing a first read operation on a target storage unit;

[0027] Determining a first conduction voltage to be applied to a word line adjacent to the word line coupled to the target storage unit to perform the first read operation on the target storage unit;

[0028] Receiving a first read result of the first read operation;

[0029] When the first read result indicates a read failure, determining a second conduction voltage to be applied to a word line adjacent to the word line coupled to the target storage unit to perform a second read operation on the target storage unit; the magnitude of the first conduction voltage is different from the magnitude of the second conduction voltage.

[0030] The memory controller in the embodiment of the present disclosure can determine the magnitude of the voltage to be applied to the word line adjacent to the word line coupled to the target storage unit during the first read operation based on the data retention time of the target storage unit, and then apply the determined voltage to the word line adjacent to the word line coupled to the target storage unit through a peripheral circuit coupled to the memory array.

[0031] By applying conduction voltages of different magnitudes to the word lines adjacent to the word line coupled to the target storage unit under different data retention times, the overall threshold voltage distribution of the storage unit becomes narrower, reducing the number of failed bits during the read operation, thereby improving the correct rate of data reading of the target storage unit and improving the data retention characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In the drawings, like reference numerals may describe like components in different views. Like reference numerals with different letter suffixes may represent different examples of like components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0033] Figure 1A A schematic structural diagram of a memory system provided by an embodiment of the present disclosure;

[0034] Figure 1B A schematic structural diagram of a memory card provided by an embodiment of the present disclosure;

[0035] Figure 1C A schematic structural diagram of a solid state drive (SSD) provided by an embodiment of the present disclosure;

[0036] Figure 1Dand Figure 1E Schematic structural diagram of a memory device including a storage array and a peripheral circuit provided by an embodiment of the present disclosure;

[0037] Figure 2A Schematic diagram of the number of stacked layers in a 3D flash memory;

[0038] Figure 2B Shows the correlation between the pitch of adjacent word lines in the channel direction and the degree of damage to data retention ability;

[0039] Figure 3 Schematic diagram of the phenomena of vertical charge loss and lateral charge loss of electrons in the channel;

[0040] Figure 4 Schematic diagram 1 of the offset of the threshold voltage of a memory cell in the PPP mode and the EPE mode;

[0041] Figure 5 Schematic diagram 2 of the offset of the threshold voltage of a memory cell in the PPP mode and the EPE mode;

[0042] Figure 6 Schematic diagram of the voltage values applied to each word line when the data retention time reaches a preset value and when the data retention time does not reach the preset value;

[0043] Figures 7 to 12 Schematic flowchart of a read operation provided by an embodiment of the present disclosure. Detailed implementation manners

[0044] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0046] Such as Figure 1AAs shown, an exemplary system 10 is shown in an embodiment of the present disclosure. The exemplary system 10 may include a host 20 and a memory system 30. Among them, the exemplary system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory 34 therein; the host 20 may be a processor of the electronic device (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP))).

[0047] In an embodiment of the present disclosure, the host 20 may be configured to send data to the memory system 30 or receive data from the memory system 30. Here, the memory system 30 may include a memory controller 32 and one or more memory devices 34. Among them, the memory device 34 may include, but is not limited to, a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a magnetoresistive random access memory (MRAM), a phase change random access memory (PCRAM), a resistive random access memory (RRAM), a nano random access memory (NRAM), etc.

[0048] In one embodiment of the present disclosure, a Memory Controller 32 may be coupled to a memory device 34 and a host 20 and be used to control the memory device 34. Exemplarily, the memory controller 32 may be designed to operate in a low-duty cycle environment, such as Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 32 may also be designed to operate in a high-duty cycle environment, such as SSDs or embedded Multi-Media Cards (eMMCs), and the SSDs or eMMCs may be used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0049] Further, the memory controller 32 may manage data in the memory device 34 and communicate with the host. The memory controller 32 may be configured to control operations such as reading, erasing, and programming of the memory device 34; may also be configured to manage various functions regarding data stored in or to be stored in the memory device 34, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; may also be configured to process Error Checking and Correction (ECC) for data read from or written to the memory device 34. In addition, the memory controller 32 may also perform any other suitable functions, such as formatting the memory device 34, or communicating with external devices according to a specific communication protocol (e.g., Figure 1Acommunicate with the external host 20). Exemplarily, the memory controller 32 may communicate with the external host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Peripheral Component Interconnect Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire protocol, etc.

[0050] In an embodiment of the present disclosure, the memory controller 32 and one or more memory devices 34 may be integrated into various types of storage devices. For example, they may be included in the same package (such as Universal Flash Storage (UFS) package or eMMC package). That is to say, the memory system 30 may be implemented and packaged into different types of terminal electronic products. As Figure 1B shown, the memory controller 32 and a single memory device 34 may be integrated together to form a memory card 40. The memory card 40 may include PC card (Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, Memory Stick, Multi-Media Card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMC micro), SD card (SD, miniSD, microSD, Secure Digital High Capacity (SDHC)), UFS, etc. The memory card 40 may also include a memory card connector 42 for coupling the memory card 40 to a host (such as, Figure 1A the host 20 in). In another embodiment as shown in Figure 1C shown, the memory controller 32 and multiple memory devices 34 may be integrated together to form an SSD 50. The SSD 50 may also include an interface for coupling the SSD 50 to a host (such as, Figure 1AThe SSD connector 52 coupled to the host 20 therein. In some embodiments, the storage capacity and / or operating speed of the SSD 50 are greater than the storage capacity and / or operating speed of the memory card 40.

[0051] It should be noted that the memory involved in an embodiment of the present disclosure may be a semiconductor memory, which is a solid-state electronic device for storing data information made by semiconductor integrated circuit processes. Exemplarily, Figure 1D This is a schematic diagram of an optional memory device 34 in an embodiment of the present disclosure. As Figure 1D shown, the memory device 34 may include a storage array 62 and a peripheral circuit 64 coupled to the storage array 62, etc. Here, the storage array may be a NAND flash storage array, where the storage cells are arranged in the form of an array of NAND memory strings 66, and each NAND memory string 66 extends vertically above the substrate. In some embodiments, each NAND memory string 66 may include a plurality of storage cells coupled in series and vertically stacked. Among them, each storage cell holds a continuous analog value, for example, voltage or charge, which depends on the number of electrons captured in the storage cell region. In addition, the storage cells in the above storage array 62 may be floating-gate type storage cells including floating-gate transistors, or charge-trapping type storage cells including charge-trapping transistors.

[0052] In an embodiment of the present disclosure, the above storage cell may be a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, the first storage state "0" may correspond to a first threshold voltage range, and the second storage state "1" may correspond to a second threshold voltage range. In other embodiments, each storage cell may be a multi-level cell (MLC) capable of storing more than a single bit of data. For example, an MLC can store two bits per cell. Each storage cell may also be a triple-level cell (TLC), or each storage cell may also be a quad-level cell (QLC). Each MLC can be programmed to a range of possible nominal storage values. Exemplarily, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values to the storage cell, such that the storage cell is programmed from an erased state to one of three possible programmed states. Among them, the fourth nominal storage value can be used to correspond to the erased state.

[0053] In an embodiment of the present disclosure, the above-mentioned peripheral circuit 64 can be coupled to the memory array through bit lines (BL), word lines (WL), source lines, source select gates (SSG), and drain select gates (DSG). Here, the peripheral circuit 64 can include any suitable analog, digital, and mixed-signal circuits for facilitating related operations of the memory array by applying voltage signals and / or current signals to each target memory cell and sensing voltage signals and / or current signals from each target memory cell via bit lines, word lines, source lines, SSGs, or DSGs, etc. In addition, the peripheral circuit 64 can also include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. Exemplarily, as Figure 1E shown. The peripheral circuit 64 can include a page buffer (PB) / sense amplifier 71, a column decoder / bit line driver 72, a row decoder / word line driver 73, a voltage generator 74, a control logic unit 75, a latch circuit 76, an interface 77, and a data bus 78. In some other embodiments, the peripheral circuit 64 can also include Figure 1E additional peripheral circuits not shown in

[0054] In the embodiment of the present disclosure, the memory device is exemplarily described as a three-dimensional flash memory. It should be understood that the present disclosure is not limited thereto.

[0055] In order to pursue higher storage density, the number of stacked layers in the three-dimensional flash memory is getting higher and higher, and the number of storage bits of the memory cells is getting more and more. There are TLCs that can achieve three-bit storage and QLCs that can achieve four-bit storage. For QLCs, a page needs to be divided into 16 states, resulting in poor reliability, especially data retention. An important indicator for measuring data retention is the data retention time. It can be understood that for any storage technology, the stored data cannot be saved forever, and there is a data retention time. When the data retention time expires, the data may go wrong, and the sign of data error is that the data read from the memory device cannot be successfully corrected by error checking and correcting (ECC) technology.

[0056] As Figure 2A and Figure 2B shown, as the number of stacked layers in the three-dimensional flash memory increases (from Figure 2Afrom (a) to (b) in (the number of stacked layers increases), in order to reduce the difficulty of channel etching, while the number of stacked layers increases, the increase in channel depth should be minimized as much as possible, which requires the ratio of Lg (the length of a single word line in the channel direction) / Ls (the pitch between adjacent word lines in the channel direction) to increase continuously (from Figure 2A From (b) to (c) in shows that, when the number of stacked layers remains unchanged, by increasing the ratio of Lg / Ls, the channel depth can be reduced), which will lead to a deterioration in the data retention characteristics of the memory cell. Figure 2B Shows the correlation between the pitch (Ls) between adjacent word lines in the channel direction and the degree of damage to the data retention ability, that is, the correlation between the ratio of Lg / Ls and the degree of damage to the data retention ability. It can be understood that, when Lg remains unchanged, as the value of Ls decreases, the ratio of Lg / Ls will increase, and the data retention ability of the memory cell will be worse.

[0057] The mechanism of flash memory storage is through the quantum tunneling effect, electrons transition to the floating gate layer and remain in the floating gate layer. As time passes, there is still a certain probability that electrons will leave the floating gate layer and return to the channel. When the number of electrons leaving the floating gate layer reaches a certain level, it may cause errors in reading data. As Figure 3 shown, there are vertical charge loss phenomenon and lateral charge loss phenomenon for electrons in the channel. The vertical direction can be understood as the direction perpendicular to the channel extension direction, and the lateral direction can be understood as the direction parallel to the channel extension direction. Vertical charge loss is the charge loss caused by the quantum tunneling effect, mainly caused by the potential difference between the word line WL n and the channel; while lateral charge loss is due to the threshold voltage of the memory cell coupled to the word line WL n and the threshold voltage difference between the memory cell coupled to the adjacent word line (WL n+1 and WL n-1 ). And the longer the data retention time, the more electrons will be lost in the channel.

[0058] There can be multiple modes between the target memory cell and the adjacent memory cell. For example, the PPP (Program-Program-Program) mode and the EPE (Erase-Program-Erase) mode. The so-called PPP mode means that the target memory cell (the memory cell coupled to the word line WL n ) and the adjacent memory cell (the memory cell coupled to the adjacent word lines (WL n+1 and WL n-1 )) are both in the high programming state. The so-called EPE mode means that the target memory cell (the memory cell coupled to the word line WL n ) is in the high programming state, while the adjacent memory cell (the adjacent word lines (WL n+1and WL n-1 ) The coupled memory cells are in a low programming state or an erased state. The threshold voltage of the memory cells in the high programming state is greater than that of the memory cells in the low programming state or the erased state. Taking the QLC memory cells as an example, in some embodiments, the high programming state may be P8 to P15 states, the low programming state may be P1 to P7 states, and the erased state is E0.

[0059] The threshold voltage offset of the memory cells coupled to WLn is strongly correlated with WL n+1 and WL n-1 coupled memory cells. In the PPP mode and the EPE mode, when the threshold voltage of the memory cells coupled to WLn and the voltage applied on WLn are fixed, the degree of charge loss of the memory cells coupled to WLn due to the quantum tunneling effect is fixed, and the threshold voltage offset caused by the charge loss due to the quantum tunneling effect is fixed. However, compared with the PPP mode, since the threshold voltage of the memory cells coupled to WL n+1 and WL n-1 coupled memory cells is smaller in the EPE mode, the voltage difference between the threshold voltage of the memory cells coupled to WL n+1 and WL n-1 coupled memory cells and the threshold voltage of the memory cells coupled to WLn is larger, resulting in more lateral charge loss. As Figure 4 shown, this makes the threshold voltage offset △V2 of the memory cells coupled to WLn in the EPE mode greater than the threshold voltage offset △V1 of the memory cells coupled to WLn in the EPE mode, resulting in a wider overall threshold voltage distribution, and further resulting in a significant increase in the number of failed bits during reading. In severe cases, reading failure will occur, resulting in data loss.

[0060] To solve the above one or more problems, an embodiment of the present disclosure provides a memory system 30, which includes a memory device 34 and a memory controller 32 coupled to the memory device 34; the memory device 34 includes a plurality of memory cells; the memory controller 32 is configured to:

[0061] Receive a read request for performing a first read operation on a target memory cell;

[0062] Obtain the data retention time of the target memory cell;

[0063] Based on the data retention time of the target memory cell, determine the magnitude of the voltage to be applied to the word line adjacent to the word line coupled to the target memory cell when performing the first read operation.

[0064] In an embodiment of the present disclosure, an external entity (e.g., host 20) issues a read request, and the memory controller 32 can receive the read request. The read request includes the logical address corresponding to the target storage unit. Moreover, a mapping table for logical address to physical address conversion can be maintained in the memory controller 32 or in the memory device 34. According to this mapping table, the physical address of the target storage unit in the memory device 34 can be obtained through the logical address in the read request.

[0065] The memory controller 32 can also obtain the data retention time of the target storage unit. A data retention time table for recording the data retention time of storage units can also be maintained in the memory controller 32 or in the memory device 34. The data retention time in the data retention time table can be recorded in units of storage pages, that is, one storage page corresponds to one data retention time; or it can be recorded in units of storage blocks, that is, one storage block corresponds to one data retention time. When rewriting a storage page, the data retention time is cleared and the data retention time is recorded again.

[0066] Therefore, when the memory controller 32 receives the logical address of the target storage unit and finds the physical address corresponding to the logical address, the data retention time of the target storage unit in the data retention time table can be found according to the storage page address or storage block address where the physical address is located.

[0067] Since the number of electrons lost by the storage unit at different data retention times is different, this will cause different degrees of offset of the threshold voltage of the storage unit. For a storage unit with a short data retention time, less electrons are lost, and in different modes (e.g., EPE mode or PPP mode), the difference in the number of electrons lost is small, even negligible, and it can be considered that the threshold voltage of the storage unit has not shifted and the threshold voltage distribution is narrow. When the data retention time of the storage unit is long, more electrons are lost, and in different modes (e.g., EPE mode or PPP mode), the difference in the number of electrons lost is large, and it can be considered that the threshold voltage of the storage unit has shifted and the threshold voltage distribution has become wider.

[0068] The memory controller in the embodiment of the present disclosure can determine the voltage magnitude to be applied to the word line adjacent to the word line coupled to the target storage unit during the first read operation based on the data retention time of the target storage unit, and then apply the determined voltage to the word line adjacent to the word line coupled to the target storage unit through the peripheral circuit coupled to the memory array.

[0069] In the embodiments of the present disclosure, by applying different conduction voltages of different magnitudes to the word lines adjacent to the word line to which the target storage cell is coupled at different data retention times, the threshold voltage distribution of the entire storage cell is narrowed, the number of failed bits during the read operation is reduced, so that the correct rate of data reading of the target storage cell can be improved, and the data retention characteristics are improved.

[0070] In some embodiments, the memory controller 32 is configured to:

[0071] When the data retention time of the target storage cell is less than or equal to a preset value, determine the first conduction voltage to be applied to the word line adjacent to the word line to which the target storage cell is coupled for a first read operation on the target storage cell;

[0072] When the data retention time of the target storage cell is greater than the preset value, determine the second conduction voltage to be applied to the word line adjacent to the word line to which the target storage cell is coupled for a first read operation on the target storage cell; the second conduction voltage is greater than the first conduction voltage.

[0073] In some embodiments, the preset value of the data retention time can be preset, and this preset value can be the upper limit of the data retention time of the memory obtained by testing or 80% of the upper limit of the data retention time.

[0074] When reading the data in the target storage cell, applying a larger conduction voltage to the word line adjacent to the word line to which the target storage cell is coupled will affect the threshold voltage of the target storage cell. The specific principle is as follows. By applying a higher conduction voltage to the word line adjacent to the word line to which the target storage cell is coupled, the number of inversion electrons in the WLn±1 channel increases, so that the channel current increases, which is equivalent to a decrease in the threshold voltage of the target storage cell. And in different modes, the degree of influence of applying a larger conduction voltage on the offset of the threshold voltage of the target storage cell is different. The following will be combined with Figure 5 Specifically described.

[0075] Such as Figure 5As shown, in the PPP mode, a relatively large conduction voltage is applied to the word line adjacent to the word line coupled to the target storage cell, and the increase in the inverted electrons in the channel is a little less. Therefore, the threshold voltage distribution of the target storage cell shifts to the left more, by ΔV3, that is, it shifts to the left by a total of ΔV1 + ΔV3 relative to the initial threshold voltage distribution. In the EPE mode, a relatively large conduction voltage is applied to the word line adjacent to the word line coupled to the target storage cell, and the increase in the inverted electrons in the channel is relatively large. Therefore, the threshold voltage of the target storage cell shifts to the left less, by ΔV4, that is, it shifts to the left by a total of ΔV2 + ΔV4 relative to the initial threshold voltage distribution. And ΔV3 is greater than ΔV4. At this time (referring to when the data retention time reaches the preset value and a second conduction voltage is applied to the adjacent word line), the difference between the offset amounts of the threshold voltages of the target storage cells in the PPP mode and the EPE mode is (ΔV2 + ΔV4) - (ΔV1 + ΔV3). Before the data retention time reaches the preset value and a first conduction voltage is applied to the adjacent word line, the difference between the offset amounts of the threshold voltages of the target storage cells in the PPP mode and the EPE mode is (ΔV2) - (ΔV1). Since ΔV1 is less than ΔV2 and ΔV3 is greater than ΔV4, ((ΔV2 + ΔV4) - (ΔV1 + ΔV3)) is less than (ΔV2) - (ΔV1). That is, for the target storage cell, when the data retention time is greater than the preset value, after a relatively larger conduction voltage is applied to the word line coupled to the target storage cell, its threshold voltage distribution becomes narrower relative to the overall threshold voltage distribution after a relatively smaller conduction voltage is applied, which is beneficial to improving the data retention characteristics.

[0076] In some embodiments, the range of the preset value is 5 years to 10 years.

[0077] When the data retention time of the storage cell is greater than the preset value, it can be considered that the overall threshold voltage offset is relatively large and the threshold voltage distribution is relatively wide. During a read operation, the memory controller 32 determines a relatively large conduction voltage (second conduction voltage) that needs to be applied to the word line adjacent to the word line coupled to the target storage cell to perform a first read operation on the target storage cell. The peripheral circuit can apply the determined conduction voltage to the word line adjacent to the word line coupled to the target storage cell, so that the threshold voltage distribution of the storage cell becomes narrower, making it easier to perform the read operation.

[0078] It should be noted that the preset value given in the above embodiments is only an exemplary demonstration and is not used to limit the range of the preset value in the embodiments of the present disclosure. In some specific examples, it can be set according to the influence of the data retention time on the threshold voltage offset and distribution.

[0079] When the data retention time of the storage unit is less than or equal to the preset value, it can be considered that the overall threshold voltage offset is small and the threshold voltage distribution is narrow. During a read operation, the memory controller 32 determines a relatively small conduction voltage (the first conduction voltage) to be applied to the word line adjacent to the word line coupled to the target storage unit for a first read operation of the target storage unit. The peripheral circuit can apply the determined conduction voltage to the word line adjacent to the word line coupled to the target storage unit, thereby performing the read operation.

[0080] In some embodiments, the range of the first conduction voltage is 6V to 7.5V, and the range of the second conduction voltage is 7.5V to 9V. For example, the first conduction voltage can be selected as 7V, and the second conduction voltage can be selected as 8V.

[0081] It should be noted that the above ranges of the first conduction voltage and the second conduction voltage given are only exemplary demonstrations and are not used to limit the ranges of the first conduction voltage and the second conduction voltage.

[0082] In some embodiments, the memory controller is further configured to:

[0083] Determine a first read voltage to be applied to the word line coupled to the target storage unit for a first read operation of the target storage unit.

[0084] During a read operation of the target storage unit, a read voltage (Vread) is applied to the word line coupled to the target storage unit, and a conduction voltage (Vpass) is applied to other storage units on the same memory string 66 as the target storage unit, and the conduction voltage is greater than the threshold voltage of the storage unit to turn on the channels corresponding to these storage units.

[0085] In some embodiments, the memory controller 32 is further configured to:

[0086] Determine a third conduction voltage to be applied to the word lines other than the word line coupled to the target storage unit and the word lines adjacent to the word line coupled to the target storage unit for a first read operation of the target storage unit; the third conduction voltage is equal to the first conduction voltage.

[0087] Specifically, referring to Figure 6 As shown, in the embodiments of the present disclosure, when the data retention time of the target storage unit is less than or equal to the preset value, when performing a read operation on the target storage unit at this time, a first read voltage (Vread1) can be applied to the word line coupled to the target storage unit, a first conduction voltage (Vpass1) is applied to the word lines adjacent to the word line coupled to the target storage unit (WLn±1), and a third conduction voltage (Vpass3) is applied to the word lines other than the word line coupled to the target storage unit and the word lines adjacent to the word line coupled to the target storage unit.

[0088] When the data retention time of the target storage unit is greater than a preset value, when performing a read operation on the target storage unit at this time, a first read voltage (Vread1) can be applied to the word line coupled to the target storage unit, a second conduction voltage (Vpass2) can be applied to the word line adjacent to the word line coupled to the target storage unit (WLn±1), and a third conduction voltage (Vpass3) can be applied to the word lines other than the word line coupled to the target storage unit and the word line adjacent to the word line coupled to the target storage unit.

[0089] In the embodiments of the present disclosure, when performing a read operation on the target storage unit, a third conduction voltage can be applied to the word lines that are far from the word line coupled to the target storage unit, and the third conduction voltage is less than the second conduction voltage.

[0090] In some embodiments, the third conduction voltage can be different from the first conduction voltage. In other embodiments, the third conduction voltage can be the same as the first conduction voltage.

[0091] The embodiments of the present disclosure further provide a memory device 34. The memory device 34 includes a peripheral circuit and a memory array coupled to the peripheral circuit. The memory array includes a plurality of storage units. The peripheral circuit is configured to:

[0092] Apply a read voltage to the word line coupled to the target storage unit to perform a read operation on the target storage unit;

[0093] Apply a second conduction voltage to the word line adjacent to the word line coupled to the target storage unit during the read operation; and

[0094] Apply a third conduction voltage to the word lines other than the word line coupled to the target storage unit and the word line adjacent to the word line coupled to the target storage unit during the read operation; wherein the magnitude of the second conduction voltage is different from the magnitude of the third conduction voltage.

[0095] In the embodiments of the present disclosure, after the memory controller 32 determines the second conduction voltage that needs to be applied to the word line adjacent to the word line coupled to the target storage unit, and determines the third conduction voltage that needs to be applied to the word lines other than the word line coupled to the target storage unit and the word line adjacent to the word line coupled to the target storage unit, the memory controller 32 sends a command for performing a read operation on the target storage unit with the second conduction voltage and the third conduction voltage to the peripheral circuit of the memory device 34.

[0096] The peripheral circuit of the memory device 34 receives the command for the read operation, generates the voltages required for the read operation through the voltage generator 74, including the second conduction voltage and the third conduction voltage, applies the second conduction voltage to the word line adjacent to the word line coupled to the target memory cell, and applies the third conduction voltage to the word lines other than the word line coupled to the target memory cell and the word line adjacent to the word line coupled to the target memory cell, so as to perform a read operation on the target memory cell.

[0097] In an embodiment of the present disclosure, during the read operation, the second conduction voltage is different from the third conduction voltage, and the second conduction voltage may be greater than the third conduction voltage.

[0098] In an embodiment of the present disclosure, after determining that the data retention time of the target memory cell is greater than a preset value, when performing a read operation on the target memory cell, the second conduction voltage may be applied to the word line adjacent to the word line coupled to the target memory cell, and the third conduction voltage may be applied to the word lines other than the word line coupled to the target memory cell and the word line adjacent to the word line coupled to the target memory cell, so that the threshold voltage distribution of the memory cell becomes narrower, thereby making it easier to perform the read operation.

[0099] An embodiment of the present disclosure further provides a memory system 30. The memory system 30 includes a memory device 34 and a memory controller 32 coupled to the memory device 34; the memory device 34 includes a plurality of memory cells; as Figure 7 shown, the memory controller 32 is configured to:

[0100] Receive a read request for performing a first read operation on a target memory cell to perform the first read operation on the target memory cell;

[0101] Determine a first conduction voltage to be applied to a word line adjacent to the word line coupled to the target memory cell;

[0102] Receive a first read result of the first read operation;

[0103] When the first read result indicates a read failure, determine a second conduction voltage to be applied to a word line adjacent to the word line coupled to the target memory cell to perform a second read operation on the target memory cell; the magnitude of the first conduction voltage is different from the magnitude of the second conduction voltage.

[0104] In an embodiment of the present disclosure, the read request may be executed by performing multiple read operations on the target memory cell. After each read operation is performed, the read result corresponding to each read operation also needs to be received.

[0105] After the read result of any read operation shows a successful read, the data in the target storage unit can be read successfully. After the read result of any read operation shows a failed read, the next read operation can be continued.

[0106] Hereinafter, two read operations on the target storage unit will be described.

[0107] When the memory controller 32 performs a first read operation on the target storage unit, it is necessary to determine to apply a first conduction voltage to the word line adjacent to the word line coupled to the target storage unit, and the peripheral circuit can apply the first conduction voltage to the word line adjacent to the word line coupled to the target storage unit. The memory controller 32 can also determine the fourth read voltage to be applied to the word line coupled to the target storage unit when the target storage unit performs the first read operation, and the peripheral circuit can apply the fourth read voltage to the word line coupled to the target storage unit.

[0108] In the embodiments of the present disclosure, a successful read can be understood as that all the data read out in the first read result of the first read operation is correct, that is, there is no error bit data; it can also be understood as that there is error bit data in the first read result of the first read operation, but the number of the error bit data is small, and the ECC error correction mechanism of the memory device can correct the small amount of error bit data so that all the read data is correct.

[0109] In the embodiments of the present disclosure, a failed read can be understood as that when the error bit count of the first read result of the first read operation is greater than the maximum value of the error detection and correction algorithm of the memory, the ECC error correction mechanism of the memory device cannot correct the large amount of error bit data, that is, it is determined that the read fails.

[0110] The memory controller 32 receives the first read result of the first read operation. In some embodiments, if the first read result shows a successful read, the read operation ends, and the read data is returned to the memory controller 32 and then returned to the host 20. In some embodiments, if the first read result shows a failed read, the second read operation is continued.

[0111] In some embodiments, the memory controller 32 is further configured to:

[0112] Determine the third conduction voltage to be applied to the word lines other than the word line coupled to the target storage unit and the word line adjacent to the word line coupled to the target storage unit for the first read operation on the target storage unit; the third conduction voltage is equal to the first conduction voltage.

[0113] In some embodiments, the memory controller 32 is further configured to:

[0114] Determine the first read voltage to be applied to the word line coupled to the target memory cell for performing a second read operation on the target memory cell.

[0115] In an embodiment of the present disclosure, the first read voltage is equal to the fourth read voltage. The read voltages applied in the first read operation and the second read operation are the same.

[0116] In some embodiments, the memory controller 32 is further configured to:

[0117] Determine the third conduction voltage to be applied to the word lines other than the word line coupled to the target memory cell and the word lines adjacent to the word line coupled to the target memory cell for performing a second read operation on the target memory cell; the third conduction voltage is equal to the first conduction voltage.

[0118] After the memory controller determines the first read voltage, the second conduction voltage, and the third conduction voltage to be applied during the second read operation, the peripheral circuit applies the corresponding voltages to the corresponding word lines.

[0119] Using the method of the embodiment of the present disclosure, when the first read operation fails, a second read operation is performed. Compared with the first read operation, the read voltage applied to the word line coupled to the target memory cell is not changed during the second read operation, and the conduction voltage applied to the word lines adjacent to the word line coupled to the target memory cell is changed to perform the second read operation. Through multiple different read operations, the probability of successful reading is increased, and the reliability of the memory is improved.

[0120] In some embodiments, the second conduction voltage is greater than the first conduction voltage.

[0121] During the second read operation, a second conduction voltage greater than the first conduction voltage is applied to the word lines adjacent to the word line coupled to the target memory cell. Then, the inversion electrons in the WLn±1 channel increase, so that the channel current increases, which is equivalent to a decrease in the threshold voltage of the target memory cell. In the PPP mode, the increase in inversion electrons in the channel is less, and in the EPE mode, the increase in inversion electrons in the channel is more. That is, for the target memory cell, after applying a relatively larger conduction voltage to the word line coupled to the target memory cell, the overall threshold voltage distribution becomes narrower compared with the threshold voltage distribution after applying a relatively smaller conduction voltage, which is beneficial to improving the data retention characteristics.

[0122] In some embodiments, the range of the first conduction voltage is 6V to 7.5V, and the range of the second conduction voltage is 7.5V to 9V.

[0123] In some embodiments, in the case where the second read operation fails, a third read operation can be further performed.

[0124] In some embodiments, with reference to Figure 8, the memory controller 32 is further configured to:

[0125] Receive a second read result of the second read operation;

[0126] When the second read result indicates a read failure, determine a second turn-on voltage that needs to be applied to a word line adjacent to the word line coupled to the target storage cell, and determine a second read voltage that needs to be applied to the word line coupled to the target storage cell to perform a third read operation on the target storage cell; the magnitude of the second read voltage is different from the magnitude of the first read voltage.

[0127] After performing the second read operation, the memory controller 32 receives the read result corresponding to the second read operation. In some embodiments, if the second read result indicates a successful read, the read operation ends, and the read data is returned to the memory controller 32 and then returned to the host 20. In some embodiments, if the second read result indicates a read failure, an instruction indicating a read failure is sent to the memory controller 32 and the instruction is returned to the host 20.

[0128] When the memory controller 32 performs a third read operation on the target storage cell, the memory controller 32 can also determine a third turn-on voltage to be applied to word lines other than the word line coupled to the target storage cell and word lines adjacent to the word line coupled to the target storage cell, and the peripheral circuit can apply the third turn-on voltage to word lines other than the word line coupled to the target storage cell and word lines adjacent to the word line coupled to the target storage cell.

[0129] That is, relative to the second read operation, what the third read operation changes is the read voltage applied to the word line coupled to the target storage cell, changing the read voltage from the first read voltage to the second read voltage, but not changing the turn-on voltage on the word line adjacent to the word line coupled to the target storage cell, which is all the second turn-on voltage.

[0130] The second read voltage Vread2 is different from the first read voltage Vread1. In some specific examples, the second read voltage Vread2 can be higher or lower than the first read voltage Vread1.

[0131] In the embodiments of the present disclosure, during the second read operation, if a read error that cannot be corrected by ECC occurs, the closest threshold voltage can be found by trying to deviate from the normal threshold voltage. When the threshold voltage distribution has shifted, if the normal or default read voltage is still used for reading during reading, errors will inevitably occur. Therefore, during the third read operation, the second read voltage Vread2 can be used to attempt to correctly read the data.

[0132] In some embodiments, referring to Figure 9 , the memory controller 32 is further configured to:

[0133] Before receiving a read request for a first read operation on a target storage unit, receive a read request for a fourth read operation on the target storage unit;

[0134] Determine a third read voltage to be applied to a word line coupled to the target storage unit and a first conduction voltage to be applied to a word line adjacent to the word line coupled to the target storage unit to perform a fourth read operation on the target storage unit;

[0135] Receive a third read result of the fourth read operation;

[0136] When the third read result indicates a read failure, determine a fourth read voltage to be applied to the word line coupled to the target storage unit to perform a first read operation on the target storage unit; the third read voltage is different from the fourth read voltage, and the fourth read voltage is equal to the first read voltage.

[0137] It should be noted that the first read operation in the embodiments of the present disclosure may not be the first read operation, and there may be one or more read operations before performing the first read operation on the target storage unit. When only one read operation is performed before the first read operation, the fourth read operation may be considered as the first read operation. When multiple read operations are performed before the first read operation, the fourth read operation may be considered as any one of the multiple read operations.

[0138] In some embodiments, in the fourth read operation, the memory controller 32 may further determine a third conduction voltage to be applied to word lines other than the word line coupled to the target storage unit and the word line adjacent to the word line coupled to the target storage unit, and the peripheral circuit may apply the third conduction voltage to word lines other than the word line coupled to the target storage unit and the word line adjacent to the word line coupled to the target storage unit.

[0139] In some embodiments, the third conduction voltage is equal to the first conduction voltage.

[0140] The embodiments of the present disclosure realize multiple different read operations by changing the conduction voltage applied to the word line adjacent to the word line coupled to the target storage unit and / or the read voltage applied to the word line coupled to the target storage unit in each read operation, increase the probability of successful reading, and improve the reliability of the memory.

[0141] In some embodiments, the memory controller 32 further includes: a register; a first voltage configuration table and a second voltage configuration table are stored in the register; wherein, the first voltage configuration table stores the correspondence between the number of read operations and the conduction voltage; the second voltage configuration table stores the correspondence between the number of read operations and the read voltage.

[0142] The memory controller 32 is further configured to determine the turn-on voltage required for performing a corresponding read operation by querying the first voltage configuration table according to the number of read times; and / or determine the read voltage required for performing a corresponding read operation by querying the second voltage configuration table according to the number of read times.

[0143] An embodiment of the present disclosure further provides a specific example, such as Figure 10 shown as: Figure 10 The default read operation in may be the fourth read operation in the above embodiment, that is, a third read voltage may be applied to the word line coupled to the target storage unit, and a first turn-on voltage may be applied to the word line adjacent to the word line coupled to the target storage unit. If the default read operation is successful or if the default read operation fails and is successfully corrected by the ECC error correction mechanism of the memory device, the current read process ends. If the default read operation fails and cannot be corrected by the ECC error correction mechanism of the memory device, the global read operation continues to be executed.

[0144] The global read operation may apply a fifth read voltage to the word line coupled to the target storage unit and a first turn-on voltage to the word line adjacent to the word line coupled to the target storage unit. The fifth read voltage may be obtained by performing a first voltage offset on the third read voltage. That is, the first voltage offset amount = the fifth read voltage minus the third read voltage. If the global read operation is successful or if the global read operation fails and is successfully corrected by the ECC error correction mechanism of the memory device, the current read process ends, and the read data is returned to the host. If the global read operation fails and cannot be corrected by the ECC error correction mechanism of the memory device, the optimal read operation continues to be executed.

[0145] The optimal read operation may apply a sixth read voltage to the word line coupled to the target storage unit and a first turn-on voltage to the word line adjacent to the word line coupled to the target storage unit. The sixth read voltage may be obtained by performing a second voltage offset on the third read voltage. That is, the second voltage offset amount = the sixth read voltage minus the third read voltage. Compared with the coarse adjustment operation of the global read operation, the optimal read operation is a fine adjustment operation. That is, the second voltage offset amount may be less than the first voltage offset amount. The second voltage configuration table may include multiple sub-voltage configuration tables. The first sub-voltage configuration table may include the correspondence between the global read operation and the first voltage offset amount, and the second sub-voltage configuration table may include the relationship between the optimal read operation and the second voltage offset amount.

[0146] In some embodiments, one or both of the global read operation and the optimal read operation can be selected. If the global read operation is the last read operation before the second read operation, the global read operation is equivalent to the first read operation in the above embodiments, and the fifth read voltage is equal to the fourth read voltage. If the optimal read operation is the last read operation before the second read operation, the optimal read operation is equivalent to the first read operation in the above embodiments, and the sixth read voltage is equal to the fourth read voltage. In the embodiments of the present disclosure, if the optimal read operation is successful or if the optimal read operation fails and is successfully corrected by the ECC error correction mechanism of the memory device, the current read process ends, and the read data is returned to the host.

[0147] In the embodiments of the present disclosure, between the first read operation and the second read operation, LDCP (Low-Density Parity-Check) decoding can also be added. If the LDPC decoding is the last read operation before the second read operation, the LDPC decoding is equivalent to the first read operation in the above embodiments.

[0148] If the optimal read operation fails and cannot be corrected by the ECC error correction mechanism of the memory device, the LDCP decoding is continued. The LDCP decoding includes LDPC soft decoding and LDPC hard decoding. If the LDCP decoding is successful, the current read process ends, and the decoded data is returned to the host. If the LDCP decoding fails, the second read operation is continued.

[0149] The second read operation changes the conduction voltage on the word line adjacent to the word line coupled to the target storage cell, making the threshold voltage distribution of the storage cell narrower, thereby making it easier to perform the read. If the second read operation is successful, the current read process ends, and the read data is returned to the host. In the case where the second read operation fails, a third read operation can also be performed.

[0150] In some embodiments, whether to perform the second read operation can be determined by the user. The memory controller can select to use or not use the function of the second read operation by means of Set Feature.

[0151] Relative to the second read operation, the third read operation changes the read voltage applied to the word line coupled to the target storage cell, changing the read voltage from the first read voltage to the second read voltage. That is, the third read operation further changes the offset of the read voltage on the basis of making the threshold voltage distribution of the storage cell narrower for reading. If the third read operation is successful, the current read process ends, and the read data is returned to the host. In the case where the third read operation fails, the current read process also ends, and an instruction indicating a read failure is returned to the host.

[0152] In some other embodiments, in the case where the third read operation fails, LDPC hard decoding and LDPC soft decoding can also be used again to obtain correct data.

[0153] The present disclosure also provides a memory device 34, which includes a peripheral circuit and a memory array coupled to the peripheral circuit. The memory array includes a plurality of memory cells, and the peripheral circuit is configured to:

[0154] Receive a read request for applying a first conduction voltage to a word line adjacent to the word line coupled to the target memory cell to perform a first read operation on the target memory cell;

[0155] Send a first read result of the first read operation;

[0156] When the first read result indicates a read failure, receive a read request for applying a second conduction voltage to a word line adjacent to the word line coupled to the target memory cell to perform a second read operation on the target memory cell; the magnitude of the first conduction voltage is different from the magnitude of the second conduction voltage.

[0157] In the embodiments of the present disclosure, in the first read operation, the memory controller 32 determines the first conduction voltage that needs to be applied to the word line adjacent to the word line coupled to the target memory cell. In the first read operation and the second read operation, a third conduction voltage applied to word lines other than the word line coupled to the target memory cell and the word line adjacent to the word line coupled to the target memory cell is determined, and the third conduction voltage is equal to the first conduction voltage.

[0158] The peripheral circuit of the memory device 34 receives the command of the first read operation. During the first read operation, the voltage generator 74 can be configured to generate the first conduction voltage and other voltages required for the first read operation. In addition, the row decoder / WL driver can be configured to apply the first conduction voltage and other voltages to the corresponding word lines to implement the first read operation on the target memory cell. After obtaining the first read result of the first read operation, the peripheral circuit sends the first read result of the first read operation to the memory controller 32.

[0159] When the first read result indicates a successful read, the peripheral circuit returns the read data to the memory controller 32 and then to the host 20. When the first read result indicates a read failure, after the memory controller 32 determines the second conduction voltage that needs to be applied to the word line adjacent to the word line coupled to the target memory cell and determines the third conduction voltage applied to word lines other than the word line coupled to the target memory cell and the word line adjacent to the word line coupled to the target memory cell, the memory controller 32 sends a command for performing a second read operation on the target memory cell with the determined voltage to the peripheral circuit of the memory device 34.

[0160] In some embodiments, if the second read result indicates a successful read, the read operation ends, and the read data is returned to the memory controller 32 and then to the host 20. In some embodiments, if the second read result indicates a failed read, an instruction of read failure is sent to the memory controller 32 and the instruction is returned to the host 20.

[0161] Using the method of the embodiments of the present disclosure, when the first read operation fails, a second read operation is performed. Compared with the first read operation, the second read operation changes the conduction voltage on the word line adjacent to the word line coupled to the target storage unit. By performing multiple different read operations, the probability of successful read is increased and the memory reliability is improved.

[0162] The embodiments of the present disclosure further provide an operation method for a memory system, as Figure 11 shown: including:

[0163] Step S10: Receive a read request for performing a first read operation on a target storage unit;

[0164] Step S20: Obtain the data retention time of the target storage unit;

[0165] Step S30: Based on the data retention time of the target storage unit, determine the magnitude of the voltage to be applied to the word line adjacent to the word line coupled to the target storage unit when performing the first read operation.

[0166] In some embodiments, based on the data retention time of the target storage unit, determining the magnitude of the voltage to be applied to the word line adjacent to the word line coupled to the target storage unit when performing the first read operation includes:

[0167] When the data retention time of the target storage unit is less than or equal to a preset value, determine a first conduction voltage to be applied to the word line adjacent to the word line coupled to the target storage unit to perform the first read operation on the target storage unit;

[0168] When the data retention time of the target storage unit is greater than the preset value, determine a second conduction voltage to be applied to the word line adjacent to the word line coupled to the target storage unit to perform the first read operation on the target storage unit; the second conduction voltage is greater than the first conduction voltage.

[0169] In some embodiments, the method further includes:

[0170] Determine a third conduction voltage to be applied to the word lines other than the word line coupled to the target storage unit and the word line adjacent to the word line coupled to the target storage unit to perform the first read operation on the target storage unit; the third conduction voltage is equal to the first conduction voltage.

[0171] An embodiment of the present disclosure also provides an operation method for a memory system, as Figure 12 shown below: including:

[0172] Step S11: Receive a read request for performing a first read operation on a target storage unit;

[0173] Step S21: Determine a first conduction voltage to be applied to a word line adjacent to the word line coupled to the target storage unit to perform a first read operation on the target storage unit;

[0174] Step S31: Receive a first read result of the first read operation;

[0175] Step S41: When the first read result indicates a read failure, determine a second conduction voltage to be applied to a word line adjacent to the word line coupled to the target storage unit to perform a second read operation on the target storage unit; the magnitude of the first conduction voltage is different from the magnitude of the second conduction voltage.

[0176] In some embodiments, the second conduction voltage is greater than the first conduction voltage.

[0177] In some embodiments, the method further includes:

[0178] Determine a third conduction voltage to be applied to word lines other than the word line coupled to the target storage unit and the word line adjacent to the word line coupled to the target storage unit to perform a first read operation on the target storage unit; the third conduction voltage is equal to the first conduction voltage.

[0179] In some embodiments, the method further includes:

[0180] Determine a first read voltage to be applied to the word line coupled to the target storage unit to perform a second read operation on the target storage unit.

[0181] In some embodiments, the method further includes:

[0182] Receive a second read result of the second read operation;

[0183] When the second read result indicates a read failure, determine a second conduction voltage to be applied to a word line adjacent to the word line coupled to the target storage unit, and determine a second read voltage to be applied to the word line coupled to the target storage unit to perform a third read operation on the target storage unit; the magnitude of the second read voltage is different from the magnitude of the first read voltage.

[0184] In some embodiments, the method further includes:

[0185] Before receiving the read request for performing a first read operation on the target storage unit, receive a read request for performing a fourth read operation on the target storage unit;

[0186] It is determined that a third read voltage needs to be applied to the word line coupled to the target memory cell, and a first conduction voltage is applied to the word line adjacent to the word line coupled to the target memory cell to perform a fourth read operation on the target memory cell;

[0187] Receive the third read result of the fourth read operation;

[0188] When the third read result indicates a read failure, it is determined that a fourth read voltage needs to be applied to the word line coupled to the target memory cell to perform a first read operation on the target memory cell; the third read voltage is different from the fourth read voltage, and the fourth read voltage is equal to the first read voltage.

[0189] Regarding the method in the above embodiments, its specific implementation method has been described in detail in the embodiments of the product corresponding to the method, and will not be elaborated here.

[0190] It should be understood that the term "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0191] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, the element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0192] As described above, only the implementation manners of the present disclosure are provided, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory system, characterized in that, The memory system includes a memory device and a memory controller coupled to the memory device; the memory device includes a plurality of memory cells; the memory controller is configured to: Receive a read request for performing a first read operation on a target memory cell; Obtain the data retention time of the target memory cell; Based on the data retention time of the target memory cell, determine the magnitude of the voltage to be applied to a word line adjacent to the word line coupled to the target memory cell when performing the first read operation.

2. The memory system according to claim 1, characterized in that, The memory controller is configured to: When the data retention time of the target memory cell is less than or equal to a preset value, determine a first conduction voltage to be applied to a word line adjacent to the word line coupled to the target memory cell to perform the first read operation on the target memory cell; When the data retention time of the target memory cell is greater than the preset value, determine a second conduction voltage to be applied to a word line adjacent to the word line coupled to the target memory cell to perform the first read operation on the target memory cell; The second conduction voltage is greater than the first conduction voltage.

3. The memory system according to claim 2, characterized in that, The range of the first conduction voltage is 6V to 7.5V, and the range of the second conduction voltage is 7.5V to 9V.

4. The memory system according to claim 2, characterized in that, The range of the preset value is 5 years to 10 years.

5. The memory system according to claim 2, characterized in that, The memory controller is further configured to: Determine a third conduction voltage to be applied to word lines other than the word line coupled to the target memory cell and the word line adjacent to the word line coupled to the target memory cell to perform the first read operation on the target memory cell; The third conduction voltage is equal to the first conduction voltage.

6. The memory system according to claim 1, characterized in that, The memory controller is further configured to: Determine a first read voltage to be applied to the word line coupled to the target memory cell to perform the first read operation on the target memory cell.

7. A memory device, characterized in that, The memory device includes a peripheral circuit and a memory array coupled to the peripheral circuit, the memory array includes a plurality of memory cells, and the peripheral circuit is configured to: Apply a read voltage to the word line coupled to the target memory cell to perform a read operation on the target memory cell; Apply a second conduction voltage to a word line adjacent to the word line coupled to the target memory cell during the read operation; And Apply a third conduction voltage to word lines other than the word line coupled to the target memory cell and the word line adjacent to the word line coupled to the target memory cell during the read operation; Wherein the magnitude of the second conduction voltage is different from the magnitude of the third conduction voltage.

8. A memory system, characterized in that, The memory system includes a memory device and a memory controller coupled to the memory device; the memory device includes a plurality of memory cells; the memory controller is configured to: Receive a read request for performing a first read operation on a target memory cell to perform the first read operation on the target memory cell; Determine a first conduction voltage to be applied to a word line adjacent to the word line coupled to the target memory cell; Receive a first read result of the first read operation; When the first read result indicates a read failure, determine a second conduction voltage to be applied to a word line adjacent to the word line coupled to the target storage unit for performing a second read operation on the target storage unit; the magnitude of the first conduction voltage is different from the magnitude of the second conduction voltage.

9. The memory system according to claim 8, characterized in that, The second conduction voltage is greater than the first conduction voltage.

10. The memory system according to claim 8, characterized in that, The range of the first conduction voltage is 6V to 7.5V, and the range of the second conduction voltage is 7.5V to 9V.

11. The memory system according to claim 8, characterized in that, The memory controller is further configured to: Determine a third conduction voltage to be applied to word lines other than the word line coupled to the target storage unit and the word line adjacent to the word line coupled to the target storage unit for performing a second read operation on the target storage unit; The third conduction voltage is equal to the first conduction voltage.

12. The memory system according to claim 8, wherein, The memory controller is further configured to: Determine a first read voltage to be applied to the word line coupled to the target storage unit for performing a second read operation on the target storage unit.

13. The memory system according to claim 12, wherein, The memory controller is further configured to: Receive a second read result of the second read operation; When the second read result indicates a read failure, determine the second conduction voltage to be applied to the word line adjacent to the word line coupled to the target storage unit, and determine a second read voltage to be applied to the word line coupled to the target storage unit for performing a third read operation on the target storage unit; the magnitude of the second read voltage is different from the magnitude of the first read voltage.

14. The memory system according to claim 12, wherein, The memory controller is further configured to: Before receiving a read request for performing a first read operation on a target storage unit, receive a read request for performing a fourth read operation on the target storage unit; Determine a third read voltage to be applied to the word line coupled to the target storage unit and the first conduction voltage to be applied to the word line adjacent to the word line coupled to the target storage unit for performing a fourth read operation on the target storage unit; Receive a third read result of the fourth read operation; When the third read result indicates a read failure, determine a fourth read voltage to be applied to the word line coupled to the target storage unit for performing the first read operation on the target storage unit; The third read voltage is different from the fourth read voltage, and the fourth read voltage is equal to the first read voltage.

15. A memory device, wherein, The memory device includes a peripheral circuit and a memory array coupled to the peripheral circuit. The memory array includes a plurality of storage units. The peripheral circuit is configured to: Receive a read request for applying a first conduction voltage to a word line adjacent to the word line coupled to the target storage unit for performing a first read operation on the target storage unit; Send a first read result of the first read operation; When the first read result indicates a read failure, receive a read request for applying a second conduction voltage to the word line adjacent to the word line coupled to the target storage unit for performing a second read operation on the target storage unit; The magnitude of the first conduction voltage is different from the magnitude of the second conduction voltage.

16. A method for operating a memory system, wherein, Include: Receive a read request for performing a first read operation on a target storage unit; Obtain the data retention time of the target storage unit; Based on the data retention time of the target storage unit, determine the voltage magnitude to be applied to the word line adjacent to the word line coupled to the target storage unit during the first read operation.

17. The method for operating according to claim 16, wherein, The determining, based on the data retention time of the target storage unit, the voltage magnitude to be applied to the word line adjacent to the word line coupled to the target storage unit during the first read operation includes: When the data retention time of the target storage unit is less than or equal to a preset value, determine the first conduction voltage to be applied to the word line adjacent to the word line coupled to the target storage unit for the first read operation of the target storage unit; When the data retention time of the target storage unit is greater than the preset value, determine the second conduction voltage to be applied to the word line adjacent to the word line coupled to the target storage unit for the first read operation of the target storage unit; the second conduction voltage is greater than the first conduction voltage.

18. The method for operating according to claim 17, wherein, The method further includes: Determine the third conduction voltage to be applied to the word lines other than the word line coupled to the target storage unit and the word line adjacent to the word line coupled to the target storage unit for the first read operation of the target storage unit; the third conduction voltage is equal to the first conduction voltage.

19. A method for operating a memory system, wherein, Includes: Receive a read request for a first read operation on a target storage unit; Determine the first conduction voltage to be applied to the word line adjacent to the word line coupled to the target storage unit for the first read operation of the target storage unit; Receive the first read result of the first read operation; When the first read result indicates a read failure, determine the second conduction voltage to be applied to the word line adjacent to the word line coupled to the target storage unit for a second read operation of the target storage unit; the magnitude of the first conduction voltage is different from the magnitude of the second conduction voltage.

20. The method for operating according to claim 19, wherein, The second conduction voltage is greater than the first conduction voltage.

21. The operating method according to claim 19, wherein, The method further includes: Determine the third conduction voltage to be applied to the word lines other than the word line coupled to the target storage unit and the word line adjacent to the word line coupled to the target storage unit for the first read operation of the target storage unit; the third conduction voltage is equal to the first conduction voltage.

22. The operating method according to claim 19, wherein, The method further includes: Determine the first read voltage to be applied to the word line coupled to the target storage unit for a second read operation of the target storage unit.

23. The operating method according to claim 22, wherein, The method further includes: Receive the second read result of the second read operation; When the second read result indicates a read failure, determine the second conduction voltage to be applied to the word line adjacent to the word line coupled to the target storage unit, and determine the second read voltage to be applied to the word line coupled to the target storage unit for a third read operation of the target storage unit; the magnitude of the second read voltage is different from the magnitude of the first read voltage.

24. The operating method according to claim 22, wherein, The method further includes: Before receiving the read request for the first read operation on the target storage unit, receive the read request for the fourth read operation on the target storage unit; Determine a third read voltage to be applied to the word line coupled to the target memory cell, and apply the first conduction voltage to the word line adjacent to the word line coupled to the target memory cell to perform a fourth read operation on the target memory cell; Receive a third read result of the fourth read operation; When the third read result indicates a read failure, determine a fourth read voltage to be applied to the word line coupled to the target memory cell to perform the first read operation on the target memory cell; the third read voltage is different from the fourth read voltage, and the fourth read voltage is equal to the first read voltage.

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