Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: providing a substrate, wherein a plurality of active regions extending along a first direction are arranged in the substrate; forming a plurality of patterned mask layers extending along a second direction on the substrate; etching the active region by using the patterned mask layer so as to form a plurality of active columns which are arranged in an array along the first direction and the second direction; forming a gate dielectric layer on the side wall of the active column; filling a conductive material between the adjacent active columns and covering the surface of the gate dielectric layer to form a conductive material layer; forming a side wall mask layer on the side wall of the patterned mask layer; wherein the patterned mask layer and the side wall mask layer jointly define the position of a word line structure; the first direction and the second direction are both parallel to the substrate, and the first direction and the second direction intersect with each other.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Generally, a Dynamic Random Access Memory (DRAM) uses a capacitor to implement data storage. The DRAM may have a structure of 1 transistor and 1 capacitor (1T1C). The first source / drain of the transistor is connected to the capacitor, the second source / drain of the transistor is connected to the bit line, and the gate of the transistor is connected to the word line.

[0003] However, with the development of the semiconductor field towards higher integration density and higher electrical performance, the development of DRAM also faces challenges brought by manufacturing processes. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof.

[0005] To achieve the above object, the technical solution of the present disclosure is realized as follows:

[0006] In a first aspect, embodiments of the present disclosure provide a manufacturing method of a semiconductor device, the method comprising:

[0007] Providing a substrate, wherein a plurality of active regions extending in a first direction are provided in the substrate;

[0008] Forming a plurality of patterned mask layers extending in a second direction on the substrate;

[0009] Etching the active regions by using the patterned mask layers to form a plurality of active pillars arranged in an array along the first direction and the second direction;

[0010] Forming a gate dielectric layer on sidewalls of the active pillars;

[0011] Filling a conductive material between adjacent active pillars and covering a surface of the gate dielectric layer to form a conductive material layer;

[0012] Forming a sidewall mask layer on sidewalls of the patterned mask layers; wherein the patterned mask layers and the sidewall mask layer jointly define positions of word line structures; both the first direction and the second direction are parallel to the substrate and the first direction intersects with the second direction.

[0013] In some embodiments, after forming the sidewall mask layer on the sidewalls of the patterned mask layers, the method further comprises:

[0014] Etch the conductive material layer by using the patterned mask layer and the sidewall mask layer to form the word line structures extending along the second direction and arranged at intervals along the first direction; wherein, the word line structures cover a plurality of the active pillars arranged along the second direction.

[0015] In some embodiments, providing the substrate, wherein a plurality of active regions extending along the first direction are provided in the substrate, includes:

[0016] Provide a substrate;

[0017] Etch the substrate to form a plurality of first isolation grooves extending along the first direction; the first isolation grooves divide the substrate into a plurality of active regions;

[0018] Fill the first isolation grooves with an isolation material to form an isolation layer between adjacent active regions.

[0019] In some embodiments, forming a plurality of patterned mask layers extending along the second direction on the substrate, includes:

[0020] Form an initial mask layer covering the active regions and the isolation layer;

[0021] Form a patterned photoresist layer on the initial mask layer;

[0022] Etch the initial mask layer by using the patterned photoresist layer to form a plurality of the patterned mask layers extending along the second direction.

[0023] In some embodiments, etching the active regions by using the patterned mask layer to form a plurality of active pillars arranged in an array along the first direction and the second direction, includes:

[0024] Etch the active regions and the isolation layer by using the patterned mask layer to form a plurality of second isolation grooves extending along the second direction; the first isolation grooves and the second isolation grooves jointly divide the substrate into a plurality of active pillars.

[0025] In some embodiments, before forming a gate dielectric layer on the sidewalls of the active pillars, the method further includes:

[0026] Through the second isolation grooves, remove a part of the isolation layer between adjacent active pillars to form a third isolation groove in the first isolation grooves and expose the sidewalls of the active pillars.

[0027] In some embodiments, filling a conductive material between adjacent active pillars and covering the surface of the gate dielectric layer to form a conductive material layer, includes:

[0028] Fill the second isolation groove and the third isolation groove with a conductive material to cover the surface of the gate dielectric layer, so as to form an initial conductive material layer; the initial conductive material layer also covers the surface of the patterned mask layer;

[0029] Remove the initial conductive material layer covering the top surface and the side walls of the patterned mask layer to form the conductive material layer.

[0030] In some embodiments, each of the active pillars has a first connection end, a second connection end, and a channel region located between the first connection end and the second connection end in a direction perpendicular to the substrate;

[0031] After etching the conductive material layer by using the patterned mask layer and the sidewall mask layer to form the word line structures extending in the second direction and arranged at intervals in the first direction, the method further includes:

[0032] Fill an insulating material between adjacent word line structures to form a word line isolation layer;

[0033] Etch the patterned mask layer to expose the second connection end.

[0034] In some embodiments, after exposing the second connection end, the method further includes:

[0035] Form a plurality of bit line structures extending in the first direction, and connect the bit line structures to the second connection ends arranged in the first direction;

[0036] Thin the substrate to expose the first connection end of the active pillar;

[0037] Form a plurality of storage node structures, and connect the storage node structures to the first connection end.

[0038] In some embodiments, after exposing the second connection end, the method further includes:

[0039] Form a plurality of storage node structures, and connect the storage node structures to the second connection end;

[0040] Thin the substrate to expose the first connection end of the active pillar;

[0041] Form a plurality of bit line structures extending in the first direction, and connect the bit line structures to the first connection ends arranged in the first direction.

[0042] In some embodiments, before forming a plurality of patterned mask layers extending in the second direction on the substrate, the method further includes:

[0043] Form a plurality of bit line structures extending in the first direction in the substrate, and connect the bit line structures to a portion of the active region close to the substrate;

[0044] After the second connection end is exposed, the method further includes:

[0045] Form a plurality of storage node structures, and connect the storage node structures to the second connection end.

[0046] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, which is manufactured by the manufacturing method of the semiconductor device described in the above technical solution.

[0047] In some embodiments, the semiconductor device includes a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), a phase change random access memory (PCRAM), and a dynamic random access memory (DRAM).

[0048] An embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof. In the embodiment of the present disclosure, a patterned mask layer is used to etch an active region to form a plurality of active pillars arranged in an array, and the patterned mask layer is retained; a gate dielectric layer covering the sidewalls of the active pillars is formed; a conductive material is filled between adjacent active pillars and covers the surface of the gate dielectric layer to form a conductive material layer; a sidewall mask layer is formed on the sidewalls of the patterned mask layer; the positions of the word line structures are jointly defined by the patterned mask layer and the sidewall mask layer retained in the foregoing process steps, so that the use of the mask layer can be reduced to reduce the process cost; and self-alignment during the formation of the word line structures can also be achieved to reduce the process difficulty. Description of the Drawings

[0049] Figure 1 A top view structural schematic diagram of a semiconductor device provided for some examples;

[0050] Figures 2A to 2E A cross-sectional structural schematic diagram of a semiconductor device provided for some examples;

[0051] Figure 3 A flowchart of the manufacturing method of the semiconductor device provided by the embodiment of the present disclosure;

[0052] Figures 4A to 4J A cross-sectional structural schematic diagram of the semiconductor device provided by the embodiment of the present disclosure during the manufacturing process. Detailed Embodiments

[0053] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0054] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other instances, in order to avoid confusion with the present disclosure, some well-known technical features are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0055] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals throughout the drawings denote the same elements.

[0056] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not mean that the present disclosure necessarily has a first element, component, region, layer, or part.

[0057] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figure with other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both the upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0058] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0059] To thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0060] Before introducing the embodiments of the present disclosure, three directions for describing semiconductor devices that may be used in the embodiments of the present disclosure are defined first. The three directions may include the X direction, the Y direction, and the Z direction. Both the X direction and the Y direction are parallel to the substrate and the X direction and the Y direction intersect. The Z direction is perpendicular to the substrate. In the embodiments of the present disclosure, the memory cells may be arranged in an array along the X direction and the Y direction. In the embodiments of the present disclosure, the memory cells may be arranged in an array along the X direction and the Y direction. The X direction may also be referred to as the row direction, and the Y direction may also be referred to as the column direction.

[0061] It should be noted that the first direction, the second direction, and the third direction may be defined. In the embodiments of the present disclosure, the first direction is defined as the Y direction, the second direction is defined as the X direction, and the third direction is defined as the Z direction.

[0062] Reference Figure 1 , Figure 1 A top view structural schematic diagram of a semiconductor device provided for some examples. AsFigure 1 As shown, the semiconductor device 100 includes a device region 104 (as shown by the dashed square in Figure 1 ), and a peripheral region 106. The peripheral region 106 can be disposed around the device region 104. Among them, a memory cell array is disposed in the device region 104, and the memory cell array includes a plurality of memory cells arranged in an array along the X direction and the Y direction. A peripheral circuit is disposed in the peripheral region 106, and the peripheral circuit can be used to control the memory cell array. A plurality of active pillars 108 arranged in an array along the X direction and the Y direction are disposed in the device region 104. The active pillar 108 includes a first connection end and a second connection end oppositely disposed along the Z direction and a channel region located between the first connection end and the second connection end. The drain of the transistor can be, for example, the first connection end of the active pillar, the source of the transistor can be, for example, the second connection end of the active pillar, and the gate of the transistor can surround the channel region of the active pillar. The first connection ends of the active pillars located in the same column (i.e., arranged along the Y direction) can be connected to the same bit line (BL), and the gates outside the channel regions of the active pillars located in the same row (i.e., arranged along the X direction) can be connected to the same word line (WL).

[0063] Reference Figures 2A to 2E , Figures 2A to 2E is a schematic cross-sectional structure diagram of a semiconductor device provided for some examples. Figures 2A to 2E Schematically shows the cross-sectional structure diagrams along the Figure 1 a-a direction and the b-b direction in

[0064] Figure 1 and Figures 2A to 2E schematically shows a vertical channel transistor (VGT), and the vertical channel transistor is a gate-all-around (GAA) structure.

[0065] As Figure 2A shown, the etching of the substrate 102 forms a plurality of active pillars 108 arranged in an array; a gate dielectric layer 110 covering the sidewalls of the active pillars 108 is formed; a conductive material is filled between adjacent active pillars 108 to form an initial conductive material layer 112.

[0066] As Figure 2B shown, the active pillar 108 includes a first connection end 130 and a second connection end 132 oppositely disposed along the Z direction and a channel region 134 located between the first connection end 130 and the second connection end 132; a part of the initial conductive material layer 112 is etched to form a conductive material layer 114 exposing the second connection end 132; a sacrificial material is filled between adjacent active pillars 108 to form a sacrificial layer 116 covering the second connection end 132; a mask layer 118 is formed on the sacrificial layer 116.

[0067] As shown in Figure 2C , the mask layer 118 is patterned to form a patterned mask layer; the sacrificial layer 116 is etched using the patterned mask layer to form sacrificial units 120 on the active pillars 108; wherein, after the etching is completed, the conductive material layer 114 is exposed, and the second connection end 132 of the active pillar 108 contacts the sacrificial unit 120.

[0068] As shown in Figure 2D , a spacer structure 122 covering the sidewalls of the sacrificial units 120 is formed.

[0069] As shown in Figure 2E , using the sacrificial units 120 and the spacer structure 122 as masks, the conductive material layer 114 is etched to form a word line trench 124 that divides the conductive material layer 114 between adjacent active pillars 108 into two parts, and the remaining conductive material layer 114 forms a gate conductive layer 126 covering the active pillars 108 in the same row; wherein, the gate dielectric layer 110 and the gate conductive layer 126 together form a word line structure 128.

[0070] Figure 1 And Figures 2A to 2E In the manufacturing process of the semiconductor device shown, filling the conductive material between adjacent active pillars and forming the word line structure need to be manufactured separately, that is, etching to form isolation trenches between active pillars in different rows and etching to form the gate conductive layer require different photomasks and hard masks (HM), which is not conducive to reducing the process cost.

[0071] In view of this, embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof.

[0072] Referring to Figure 3 , Figure 3 is a schematic flow chart of the manufacturing method of the semiconductor device provided by the embodiments of the present disclosure. As shown in Figure 3 , embodiments of the present disclosure provide a manufacturing method of a semiconductor device, the method comprising:

[0073] Step S301: Providing a substrate, wherein a plurality of active regions extending along a first direction are provided in the substrate;

[0074] Step S302: Forming a plurality of patterned mask layers extending along a second direction on the substrate;

[0075] Step S303: Etching the active regions using the patterned mask layer to form a plurality of active pillars arranged in an array along the first direction and the second direction;

[0076] Step S304: Forming a gate dielectric layer on the sidewalls of the active pillars;

[0077] Step S305: Fill a conductive material between adjacent active pillars and cover the surface of the gate dielectric layer to form a conductive material layer;

[0078] Step S306: Form a sidewall mask layer on the sidewalls of the patterned mask layer; wherein, the patterned mask layer and the sidewall mask layer jointly define the position of the word line structure; both the first direction and the second direction are parallel to the substrate and the first direction intersects with the second direction.

[0079] In the implementation of the present disclosure, the active region is etched using the patterned mask layer to form a plurality of active pillars arranged in an array, and the patterned mask layer is retained; a gate dielectric layer covering the sidewalls of the active pillars is formed; a conductive material is filled between adjacent active pillars and covers the surface of the gate dielectric layer to form a conductive material layer; a sidewall mask layer is formed on the sidewalls of the patterned mask layer; the positions of the word line structures are jointly defined by the patterned mask layer and the sidewall mask layer retained by the foregoing process steps, so that the use of the mask layer can be reduced to lower the process cost; and self-alignment during the formation of the word line structure can also be achieved to reduce the process difficulty.

[0080] Reference Figures 4A to 4J , Figures 4A to 4J is a schematic cross-sectional structure diagram of a semiconductor device during manufacturing provided by an embodiment of the present disclosure. The manufacturing process of the semiconductor device will be described in detail below in combination with Figure 3 and Figures 4A to 4J .

[0081] In an embodiment of the present disclosure, in step S301, a substrate 402 is provided, and a plurality of active regions 406 extending along a first direction (i.e., the Y direction) are provided in the substrate 402.

[0082] As Figure 4A shown, in some embodiments, step S301 includes: providing a substrate 402; etching the substrate 402 along the Z direction to form a plurality of first isolation grooves 404 extending along the Y direction; the first isolation grooves 404 divide the substrate 402 into a plurality of active regions 406 extending along the Y direction; filling an isolation material in the first isolation grooves 404 to form an isolation layer 408 between two adjacent active regions 406.

[0083] Here, the substrate 402 can be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (such as a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. It can also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, and a silicon-germanium substrate, etc.

[0084] Exemplarily, a mask layer can be formed on the substrate, and the substrate can be etched along the Z direction using the mask layer to form a plurality of active regions extending along the Y direction and a first isolation groove located between two adjacent active regions. Among them, the etching process does not penetrate the substrate, and the etching depth along the Z direction is less than the height of the substrate along the Z direction.

[0085] Here, the process of forming the first isolation groove 404 can include but is not limited to dry etching (Dry Etch), wet etching (Wet Etch), or a combination thereof.

[0086] Exemplarily, an isolation material is filled in the first isolation groove to form an isolation material layer that fills the first isolation groove and covers the active regions; the isolation material layer is planarized to form an isolation layer that fills the first isolation groove and exposes the active regions. Among them, the planarization process can include but is not limited to chemical mechanical polishing (Chemical Mechanical Polishing, CMP).

[0087] Here, the process of forming the isolation layer 408 can include but is not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), spin-on dielectric (Spin-On Dielectric, SOD), or any combination thereof.

[0088] Here, the material of the isolation layer 408 can include a low dielectric constant material. For example, tetraethyl orthosilicate (TEOS) is used for CVD growth of silicon oxide. Another example is spin-coating and curing to form silicon oxide.

[0089] In the embodiment of the present disclosure, in step S302, a plurality of patterned mask layers 414 extending along the second direction (i.e., the X direction) are formed on the substrate 402.

[0090] As Figure 4B shown, in some embodiments, step S302 includes: forming an initial mask layer 410 covering the active region 406 and the isolation layer 408. Among them, the initial mask layer 410 can be used as a hard mask layer.

[0091] Here, the process of forming the initial mask layer 410 may include but is not limited to CVD, PVD, ALD, or any combination thereof.

[0092] Here, the material of the initial mask layer 410 may include but is not limited to silicon nitride.

[0093] As Figure 4C shown, a photoresist layer (Photoresist, PR) is formed on the initial mask layer 410; the photoresist layer is patterned to form a patterned photoresist layer 412 on the initial mask layer 410.

[0094] Here, according to the chemical reaction mechanism and the development principle, photoresists can be divided into positive photoresists and negative photoresists. For positive photoresists (Positive Resist), the positive photoresist itself is insoluble and becomes more soluble after being exposed, so it is easier to be removed in the development step. For negative photoresists (Negative Resist), the negative photoresist forms insoluble substances after being exposed, so it will not be removed in the development step. The pattern generated by the positive photoresist is the same as the pattern of the hard mask layer, and the pattern generated by the negative photoresist is the reverse of the pattern of the hard mask layer. Figure 4C The illustrated patterned photoresist layer 412 is described by taking a positive photoresist as an example, which does not limit the protection scope of the present disclosure. The present disclosure has no special limitation on the type of photoresist.

[0095] As Figure 4D shown, the initial mask layer 410 is etched using the patterned photoresist layer 412 to form a plurality of patterned mask layers 414 extending in the X direction.

[0096] In the embodiment of the present disclosure, in step S303, the active region 406 is etched using the patterned mask layer 414 to form a plurality of active pillars 418 arranged in an array in the first direction (i.e., the Y direction) and the second direction (i.e., the X direction).

[0097] As Figure 4D shown, in some embodiments, step S303 includes: etching the active region 406 and the isolation layer 408 along the Z direction using the patterned mask layer 414 to form a plurality of second isolation grooves 416 extending in the X direction; the first isolation groove 404 and the second isolation groove 416 together divide the substrate 402 into a plurality of active pillars 418 (as Figure 4Das shown by the dashed circular frame in the figure). Among them, the etching process does not penetrate the substrate, and the etching depth in the Z direction is less than the height of the substrate in the Z direction. Moreover, after the active pillars 418 are formed, the patterned mask layer 414 for forming the second isolation groove 416 is retained.

[0098] Here, the process of forming the second isolation groove 416 may include, but is not limited to, dry etching, wet etching, or a combination thereof.

[0099] Here, the positive projection of the active pillar 418 on the XY plane may be a quadrilateral, and the active pillar includes four side walls, where two side walls are oppositely arranged in the X direction, and the other two side walls are oppositely arranged in the Y direction. Of course, the positive projection of the active pillar 418 on the XY plane may also be circular, elliptical, etc. The present disclosure does not have a special limitation on the shape of the positive projection of the active pillar on the XY plane.

[0100] In some embodiments, the depth of the first isolation groove 404 in the Z direction is greater than the depth of the second isolation groove 416 in the Z direction. In other words, the dimensions of the two oppositely arranged side walls of the active pillar 418 in the Z direction are greater than the dimensions of the two oppositely arranged side walls of the active pillar 418 in the Y direction in the Z direction.

[0101] Here, each active pillar 418 has a first connection end 420, a second connection end 422, and a channel region 424 located between the first connection end 420 and the second connection end 422 in the Z direction. Among them, the second connection end 422 is in contact with the patterned mask layer 414.

[0102] In some embodiments, when the first connection end is the source electrode of the transistor, the second connection end is the drain electrode of the transistor. In other embodiments, when the first connection end is the drain electrode of the transistor, the second connection end is the source electrode of the transistor.

[0103] In some embodiments, the substrate may be doped first, and then the substrate may be etched to form the active pillars. In this way, the etched active pillars have a doped region, and the doped region may form the first connection end, the second connection end, and the channel region. In other embodiments, the substrate may be etched to form the active pillars first, and then the active pillars may be doped. In this way, after doping the etched active pillars, the active pillars may also have a doped region, and the doped region may form the first connection end, the second connection end, and the channel region. The present disclosure does not have a special limitation on the order of doping the active pillars to form the first connection end, the second connection end, and the channel region.

[0104] Such as Figure 4EAs shown, in some embodiments, before step S304, the method further includes: through the second isolation groove 416, removing a part of the isolation layer 408 between adjacent active pillars 418 to form a third isolation groove 426 in the first isolation groove 404 and expose the sidewalls of the active pillars 418. Wherein, the depth of the third isolation groove 426 in the Z direction is less than the depth of the first isolation groove 404 in the Z direction.

[0105] Here, removing a part of the isolation layer 408 between adjacent active pillars 418 refers to removing a part of the isolation layer 408 between adjacent active pillars 418 along the X direction to expose two opposite sidewalls of the active pillars 418 along the X direction. As described above, etching to form the second isolation groove 416 exposes two opposite sidewalls of the active pillars 418 along the Y direction, and etching to form the third isolation groove 426 exposes two opposite sidewalls of the active pillars 418 along the X direction.

[0106] Here, the process of etching to form the third isolation groove 426 may include but is not limited to wet etching, vapor etching, dry etching or any combination thereof.

[0107] In the embodiments of the present disclosure, in step S304, a gate dielectric layer 428 is formed on the sidewalls of the active pillars 418.

[0108] As Figure 4F shown, a gate dielectric layer 428 covering the sidewalls of each active pillar 418 is formed.

[0109] Here, the process of forming the gate dielectric layer 428 may include but is not limited to in-situ steam generation (ISSG), rapid thermal oxidation (RTO), ALD or any combination thereof.

[0110] In some embodiments, the material of the gate dielectric layer 428 may include silicon oxide or other suitable dielectric materials.

[0111] In the embodiments of the present disclosure, in step S305, a conductive material is filled between adjacent active pillars 418 and covers the surface of the gate dielectric layer 428 to form a conductive material layer 432.

[0112] As Figure 4GAs shown, in some embodiments, step S305 includes: filling the second isolation groove 416 and the third isolation groove 426 with a conductive material and covering the surface of the gate dielectric layer 428 to form an initial conductive material layer 430; the initial conductive material layer 430 also covers the surface of the patterned mask layer 414. In some embodiments, the initial conductive material layer 430 not only covers the surface of the gate dielectric layer 428, but also fills the gaps between adjacent active pillars 418. In some embodiments, the initial conductive material layer 430 covers the top surface, sidewalls, and exposed bottom surface of the patterned mask layer 414.

[0113] Here, the process of forming the initial conductive material layer 430 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0114] Here, the material of the initial conductive material layer 430 may include, but is not limited to, titanium nitride, tungsten, tungsten, molybdenum, and polysilicon, etc.

[0115] As Figure 4H shown, in some embodiments, step S305 further includes: removing the initial conductive material layer 430 covering the top surface and sidewalls of the patterned mask layer 414 to form a conductive material layer 432.

[0116] Here, the process of removing part of the initial conductive material layer 430 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0117] In the embodiments of the present disclosure, in step S306, a sidewall mask layer 436 is formed on the sidewalls of the patterned mask layer 414; wherein, the patterned mask layer 414 and the sidewall mask layer 436 jointly define the position of the word line structure 438; the first direction (i.e., the Y direction) and the second direction (i.e., the X direction) are both parallel to the substrate 402 and the first direction and the second direction intersect.

[0118] As Figure 4I shown, an initial mask material layer 434 covering the top surface and sidewalls of the patterned mask layer 414 is formed.

[0119] Here, the process of forming the initial mask material layer 434 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0120] Here, the material of the initial mask material layer 434 may include, but is not limited to, silicon nitride, silicon oxynitride, or amorphous carbon.

[0121] As Figure 4JAs shown, the initial mask material layer 434 covering the top surface of the patterned mask layer 414 is removed, while the initial mask material layer 434 covering the sidewalls of the patterned mask layer 414 is retained. The remaining initial mask material layer 434 forms the sidewall mask layer 436. As described above, after the second isolation groove 416 is etched using the patterned mask layer 414, the subsequent positions of the word line structures 438 are jointly defined by the patterned mask layer 414 and the sidewall mask layer 436, thereby realizing the reuse of the patterned mask layer 414 to reduce the process cost.

[0122] As Figure 4J shown, in some embodiments, after step S306, the method further includes: etching the conductive material layer 432 using the patterned mask layer 414 and the sidewall mask layer 436 to cut off the conductive material layer 432 between the adjacent active pillars 418 along the Y direction, so as to form a word line isolation groove extending along the X direction and form word line structures 438 extending along the second direction (i.e., the X direction) and spaced apart along the first direction (i.e., the Y direction); wherein, each word line structure 438 covers a plurality of active pillars 418 corresponding to the same row (extending along the X direction). Using the patterned mask layer 414 and the sidewall mask layer 436 as masks to etch the conductive material layer 432 can achieve self-alignment during the formation of the discrete word line structures 438, thereby reducing the process difficulty.

[0123] In some embodiments, after using the patterned mask layer and the sidewall mask layer to etch the conductive material layer to form word line structures extending along the X direction and spaced apart along the Y direction, the method further includes: filling an insulating material between adjacent word line structures to form a word line isolation layer; etching the patterned mask layer to expose the second connection end.

[0124] Here, an insulating material is filled in the word line isolation groove to form a word line isolation layer extending along the X direction.

[0125] Here, the process of forming the word line isolation layer may include but is not limited to CVD, PVD, ALD, or any combination thereof.

[0126] Here, the material of the word line isolation layer may include but is not limited to silicon oxide and silicon nitride.

[0127] In some embodiments, all the patterned mask layers and / or sidewall mask layers are first removed by etching to expose the top surface of the word line structure and the second connection end, and then an insulating material is filled in the word line trench. The insulating material also covers the exposed top surface of the word line structure and the second connection end, and the second connection end is then exposed by other etching processes. In other embodiments, an insulating material is first filled in the word line trench, and then part of the patterned mask layer is removed by etching to expose only the second connection end. Exposing the second connection end can effectively protect the second connection end only before manufacturing the structure electrically connected to the second connection end. In some embodiments, after etching the patterned mask layer to expose the second connection end, the method further includes: forming a plurality of bit line structures extending in the Y direction, the bit line structures being connected to the second connection ends arranged in the Y direction; thinning the substrate to expose the first connection end of the active pillar; and forming a plurality of storage node structures, the storage node structures being connected to the first connection end.

[0128] Here, exposing the second connection end of the active pillar can form a plurality of bit line structures extending in the Y direction on the front surface of the substrate, and each bit line structure is connected to a plurality of second connection ends corresponding to the same column (i.e., extending in the Y direction); after thinning the back surface of the substrate to expose the first connection end of the active pillar, a storage node structure can also be formed on the back surface of the substrate, and the storage node structure is connected to the first connection end.

[0129] In some embodiments, the storage node structure can be a storage capacitor, and the semiconductor device is a DRAM; wherein, the storage capacitor includes a first electrode plate, a second electrode plate, and a dielectric layer located between the first electrode plate and the second electrode plate; wherein, the dielectric layer can be a high-k material. In other embodiments, the storage node structure can be a transistor, and the storage device is a capacitorless DRAM, such as a DRAM with 1T0C or 2T0C as the storage unit.

[0130] In some embodiments, the storage node structure can be a ferroelectric capacitor, a ferroelectric transistor, or a ferroelectric tunnel junction, and the semiconductor device is a ferroelectric memory; wherein, the ferroelectric capacitor includes a first electrode plate, a second electrode plate, and a ferroelectric crystal thin film located between the first electrode plate and the second electrode plate, the ferroelectric transistor includes a field effect transistor having a ferroelectric crystal material as the gate dielectric layer, and the ferroelectric tunnel junction includes two electrodes and a barrier layer of ferroelectric crystal material between the electrodes.

[0131] In some embodiments, after etching the patterned mask layer to expose the second connection end, the method further includes: forming a plurality of storage node structures, the storage node structures being connected to the second connection end; thinning the substrate to expose the first connection end of the active pillar; forming a plurality of bit line structures extending in the Y direction, the bit line structures being connected to the first connection ends arranged in the Y direction.

[0132] Here, after exposing the second connection end of the active pillar, storage node structures can be formed on the front surface of the substrate, the storage node structures being connected to the second connection end; thinning the back surface of the substrate to expose the first connection end of the active pillar; and a plurality of bit line structures extending in the Y direction can also be formed on the back surface of the substrate, each bit line structure being connected to a plurality of first connection ends in the same column (i.e., extending in the Y direction).

[0133] In some embodiments, before step S302, the method further includes: forming a plurality of bit line structures extending in the Y direction in the substrate, the bit line structures being connected to the portion of the active region close to the substrate; after etching the patterned mask layer to expose the second connection end, the method further includes: forming a plurality of storage node structures, the storage node structures being connected to the second connection end.

[0134] Here, after forming the active region and the first isolation groove, a plurality of bit line structures extending in the Y direction can be formed in the substrate, each bit line structure being connected to the portion of the active region close to the substrate, i.e., forming buried bit line structures; after forming the active pillar and the second isolation groove, the portion where the active pillar contacts the bit line structure is the first connection end; and storage node structures can also be formed on the front surface of the substrate, the storage node structures being connected to the second connection end.

[0135] Embodiments of the present disclosure provide a semiconductor device, which is manufactured by the manufacturing method of the semiconductor device in the above technical solution.

[0136] Here, the conductive material layer is etched through the patterned mask layer and the sidewall mask layer to form a gate conductive layer covering the active pillar; wherein, the gate dielectric layer covering the sidewalls of the active pillar and the gate conductive layer covering the active pillars in the same row (i.e., extending in the X direction) together form a word line structure. The positive projection of the gate conductive layer in the XY plane is located within the positive projections of the patterned mask layer and the sidewall mask layer in the XY plane.

[0137] In some embodiments, a conductive material is filled between the active pillars in the same row, and two adjacent active pillars in the X direction are connected through the gate conductive layer at different height positions in the Z direction. That is, in the positive projections of two adjacent active pillars in the X direction in the XY plane at different height positions in the Z direction, a conductive material is filled between the two adjacent active pillars in the X direction.

[0138] In some other embodiments, a conductive material is filled between active columns in the same row. At a height position far from the substrate, two adjacent active columns in the X direction are connected by a gate conductive layer; at a height position close to the substrate, there is a certain spacing between the gate conductive layers of two adjacent active columns in the X direction.

[0139] In some embodiments, the semiconductor device includes DRAM, FeRAM, Magnetoresistive Random Access Memory (MRAM), and Phase Change Random Access Memory (PCRAM). The present disclosure does not have any special limitation on the type of the semiconductor device.

[0140] Here, the storage unit of MRAM includes a transistor and a Magnetic Tunnel Junction (MTJ); wherein, the source of the transistor is connected to the source line, the gate of the transistor is connected to the word line, and the drain of the transistor is connected to the bit line through the magnetic tunnel junction. Specifically, the magnetic tunnel junction sequentially includes a Fixed Layer, a Tunneling Oxide, and a Free Layer; wherein, the drain of the transistor is connected to the fixed layer, and the free layer is connected to the bit line. Information is stored by using the magnetic moment directions of the free layer and the fixed layer; the resistance is low in the parallel state; the resistance is high in the non-parallel state. That is, the first connection end (or the second connection end) of the active column is connected to the source line, and the second connection end (or the first connection end) of the active column is connected to the bit line through the magnetic tunnel junction.

[0141] Here, generally, the storage unit of PCRAM includes 1 Transistor 1 Resistance (1T1R), and data is stored by using the conductivity difference exhibited when the phase change material mutually transforms between the crystalline state and the amorphous state. Among them, the source of the transistor is connected to the source line, the gate of the transistor is connected to the word line, and the drain of the transistor is connected to the bit line through the phase change storage unit. Specifically, the phase change storage unit may include, for example, a heater (i.e., the lower electrode), a phase change layer, and titanium nitride (i.e., the upper electrode), and the heater heats the phase change layer to enable it to realize the conversion between the crystalline state and the amorphous state. That is, the first connection end (or the second connection end) of the active column is connected to the source line, and the second connection end (or the first connection end) of the active column is connected to the bit line through the phase change storage unit.

[0142] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. In the embodiments of the present disclosure, an active region is etched using a patterned mask layer to form a plurality of active pillars arranged in an array, and the patterned mask layer is retained; a gate dielectric layer covering the sidewalls of the active pillars is formed; a conductive material is filled between adjacent active pillars and covers the surface of the gate dielectric layer to form a conductive material layer; a sidewall mask layer is formed on the sidewalls of the patterned mask layer; the positions of the word line structures are jointly defined by using the patterned mask layer and the sidewall mask layer retained in the foregoing process steps, so that the use of the mask layer can be reduced to lower the process cost; and self-alignment during the formation of the word line structures can also be achieved to reduce the process difficulty.

[0143] It should be understood that the term "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of the phrase "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the order numbers of the above processes do not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The order numbers of the embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0144] The above are only the preferred embodiments of the present disclosure, and do not limit the patent scope of the present disclosure. Any equivalent structural transformation made by using the content of the specification and drawings of the present disclosure under the inventive concept of the present disclosure, or any direct / indirect application in other related technical fields, is included in the patent protection scope of the present disclosure.

Claims

1. A manufacturing method of a semiconductor device, characterized in that, The method includes: providing a substrate, in which a plurality of active regions extending in a first direction are provided; forming a plurality of patterned mask layers extending in a second direction on the substrate; etching the active regions by using the patterned mask layers to form a plurality of active pillars arranged in an array along the first direction and the second direction; forming a gate dielectric layer on sidewalls of the active pillars; filling a conductive material between adjacent active pillars and covering a surface of the gate dielectric layer to form a conductive material layer; forming sidewall mask layers on sidewalls of the patterned mask layers; wherein, the patterned mask layers and the sidewall mask layers jointly define positions of word line structures; both the first direction and the second direction are parallel to the substrate and the first direction intersects with the second direction.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, After forming the sidewall mask layers on the sidewalls of the patterned mask layers, the method further includes: etching the conductive material layer by using the patterned mask layers and the sidewall mask layers to form the word line structures extending in the second direction and arranged at intervals along the first direction; wherein, the word line structures cover a plurality of the active pillars arranged in the second direction.

3. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The providing a substrate, in which a plurality of active regions extending in a first direction are provided, includes: providing a substrate; etching the substrate to form a plurality of first isolation grooves extending in the first direction; the first isolation grooves divide the substrate into a plurality of active regions; filling an isolation material in the first isolation grooves to form an isolation layer between adjacent active regions.

4. The manufacturing method of the semiconductor device according to claim 3, characterized in that, The forming a plurality of patterned mask layers extending in a second direction on the substrate includes: forming an initial mask layer covering the active regions and the isolation layer; forming a patterned photoresist layer on the initial mask layer; etching the initial mask layer by using the patterned photoresist layer to form a plurality of the patterned mask layers extending in the second direction.

5. The manufacturing method of the semiconductor device according to claim 3, characterized in that, The etching the active regions by using the patterned mask layers to form a plurality of active pillars arranged in an array along the first direction and the second direction includes: etching the active regions and the isolation layer by using the patterned mask layers to form a plurality of second isolation grooves extending in the second direction; the first isolation grooves and the second isolation grooves jointly divide the substrate into a plurality of active pillars.

6. The manufacturing method of the semiconductor device according to claim 5, characterized in that, Before forming the gate dielectric layer on the sidewalls of the active pillars, the method further includes: removing a part of the isolation layer between adjacent active pillars through the second isolation grooves to form third isolation grooves in the first isolation grooves and expose sidewalls of the active pillars.

7. The manufacturing method of the semiconductor device according to claim 6, characterized in that, The filling a conductive material between adjacent active pillars and covering a surface of the gate dielectric layer to form a conductive material layer includes: filling a conductive material in the second isolation grooves and the third isolation grooves and covering a surface of the gate dielectric layer to form an initial conductive material layer; the initial conductive material layer also covers a surface of the patterned mask layer; removing the initial conductive material layer covering a top surface and sidewalls of the patterned mask layer to form the conductive material layer.

8. The manufacturing method of the semiconductor device according to claim 2, characterized in that, Each of the active pillars has a first connection end, a second connection end, and a channel region located between the first connection end and the second connection end in a direction perpendicular to the substrate; After etching the conductive material layer using the patterned mask layer and the sidewall mask layer to form the word line structures extending in the second direction and spaced apart in the first direction, the method further includes: Filling an insulating material between adjacent word line structures to form a word line isolation layer; Etching the patterned mask layer to expose the second connection end.

9. The manufacturing method of the semiconductor device according to claim 8, characterized in that, After exposing the second connection end, the method further includes: Forming a plurality of bit line structures extending in the first direction, the bit line structures being connected to the second connection ends arranged in the first direction; Thinning the substrate to expose the first connection end of the active pillar; Forming a plurality of storage node structures, the storage node structures being connected to the first connection end.

10. The manufacturing method of the semiconductor device according to claim 8, wherein, After exposing the second connection end, the method further includes: Forming a plurality of storage node structures, the storage node structures being connected to the second connection ends; Thinning the substrate to expose the first connection end of the active pillar; Forming a plurality of bit line structures extending in the first direction, the bit line structures being connected to the first connection ends arranged in the first direction.

11. The manufacturing method of the semiconductor device according to claim 8, wherein, Before forming a plurality of patterned mask layers extending in the second direction on the substrate, the method further includes: Forming a plurality of bit line structures extending in the first direction in the substrate, the bit line structures being connected to a portion of the active region close to the substrate; After exposing the second connection end, the method further includes: Forming a plurality of storage node structures, the storage node structures being connected to the second connection ends.

12. A semiconductor device, wherein, The semiconductor device is manufactured by the manufacturing method of the semiconductor device according to any one of claims 1 to 11.

13. The semiconductor device according to claim 12, wherein, The semiconductor device includes a ferroelectric random access memory FeRAM, a magnetic random access memory MRAM, a phase change random access memory PCRAM, and a dynamic random access memory DRAM.

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