Semiconductor device and data storage system including same

Abstract

A semiconductor device and a data storage system including the same are provided. The semiconductor device includes a first structure including a first memory block and a second memory block. The first memory block has a first connection region, a first memory cell array region, and a second connection region. The second memory block has a third connection region, a second memory cell array region, and a fourth connection region. A first gate electrode of the first memory block includes a first word line having a first word line pad disposed in the second connection region and a first upper gate line having a first upper gate pad disposed in the first connection region and disposed on the first word line. A second gate electrode of the second memory block includes a second word line having a second word line pad disposed in the third connection region and a second upper gate line having a second upper gate pad disposed in the fourth connection region and disposed on the second word line.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0181989, filed with the Korean Intellectual Property Office on December 14, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the inventive concept relate to a semiconductor device and a data storage system including the semiconductor device. Background Art

[0003] Semiconductor devices capable of storing a large amount of data in a data storage system that requires data storage have been developed. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been developed. For example, as a method for increasing the data storage capacity of semiconductor devices, semiconductor devices including three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells have been developed. Summary of the Invention

[0004] According to an example embodiment of the inventive concept, a semiconductor device includes a first structure and a second structure. The first structure has a first side surface and a second side surface facing each other and includes a first memory block and a second memory block sequentially arranged in a first direction from the first side surface to the second side surface. The second structure includes a peripheral circuit and is stacked on the first structure. The first memory block has a first connection region, a first memory cell array region, and a second connection region sequentially arranged in the first direction. The second memory block has a third connection region, a second memory cell array region, and a fourth connection region sequentially arranged in the first direction. The first memory block includes first gate electrodes spaced apart from each other and extending from the first connection region to the second connection region. The second memory block includes second gate electrodes spaced apart from each other and extending from the third connection region to the fourth connection region. The first gate electrodes of the first memory block include a first word line and a first upper gate line. The first word line has a first word line pad disposed in the second connection region. The first upper gate line has a first upper gate pad disposed in the first connection region and is disposed on the first word line. The second gate electrodes of the second memory block include a second word line and a second upper gate line. The second word line has a second word line pad disposed in the third connection region. The second upper gate line has a second upper gate pad disposed in the fourth connection region and is disposed on the second word line. The first structure includes a first word line contact plug connected to the first word line pad, a first upper gate contact plug connected to the first upper gate pad, a second word line contact plug connected to the second word line pad, and a second upper gate contact plug connected to the second upper gate pad.

[0005] According to an exemplary embodiment of the inventive concept, a semiconductor device includes a first structure and a second structure. The first structure has a first side surface and a second side surface facing each other and includes a first connection region, a first memory cell array region, a second connection region, a third connection region, a second memory cell array region, and a fourth connection region sequentially arranged from the first side surface in a first direction toward the second side surface. The second structure includes a peripheral circuit and is stacked on the first structure. Herein, the first structure includes a first side conductive layer, a first vertical memory structure, a second side conductive layer, and a second vertical memory structure. The first side conductive layer is disposed in the first connection region, the first memory cell array region, and the second connection region. The first vertical memory structure penetrates the first side conductive layer in the first memory cell array region. The second side conductive layer is disposed in the third connection region, the second memory cell array region, and the fourth connection region. The second vertical memory structure penetrates the second side conductive layer in the second memory cell array region. Herein, the first side conductive layer includes a first lower conductive group and a first upper conductive group. The first lower conductive group has a first lower pad arranged in a stepped shape in the second connection region. The first upper conductive group is disposed at a height higher than the height of the first lower conductive group and has a first upper pad arranged in a stepped shape in the first connection region. Herein, the second side conductive layer includes a second lower conductive group and a second upper conductive group. The second lower conductive group is disposed at the same height as the height of the first lower conductive group and has a second lower pad arranged in a stepped shape in the third connection region. The second upper conductive group is disposed at the same height as the height of the first upper conductive group and has a second upper pad arranged in a stepped shape in the fourth connection region.

[0006] According to an exemplary embodiment of the inventive concept, a data storage system includes a semiconductor device and a controller. The semiconductor device includes input / output pads, and the controller is electrically connected to the semiconductor device through the input / output pads and controls the semiconductor device. The semiconductor device includes a first structure and a second structure. The first structure has a first side surface and a second side surface facing each other and includes a first memory block and a second memory block arranged in sequence in a first direction. The second structure includes a peripheral circuit and is stacked on the first structure. The first memory block has a first connection region, a first memory cell array region, and a second connection region arranged in sequence in the first direction. The second memory block has a third connection region, a second memory cell array region, and a fourth connection region arranged in sequence in the first direction. The first memory block includes first gate electrodes spaced apart from each other in a vertical direction and extending from the first connection region to the second connection region. The second memory block includes second gate electrodes spaced apart from each other in the vertical direction and extending from the third connection region to the fourth connection region. The first gate electrodes of the first memory block include a first word line and a first upper gate line. The first word line has a first word line pad disposed in the second connection region. The first upper gate line has a first upper gate pad disposed in the first connection region and is disposed on the first word line. The second gate electrodes of the second memory block include a second word line and a second upper gate line. The second word line has a second word line pad disposed in the third connection region. The second upper gate line has a second upper gate pad disposed in the fourth connection region and is disposed on the second word line. The first structure includes a first word line contact plug connected to the first word line pad, a first upper gate contact plug connected to the first upper gate pad, a second word line contact plug connected to the second word line pad, and a second upper gate contact plug connected to the second upper gate pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects of the inventive concept will become more apparent by describing exemplary embodiments of the inventive concept in detail with reference to the accompanying drawings.

[0008] Figure 1A 、 Figure 1B 、 Figure 1C and Figure 1D are diagrams showing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0009] Figure 2 are diagrams showing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0010] Figure 3A and Figure 3B are diagrams showing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0011] Figure 4 、Figure 5 , Figure 6A , Figure 6B , Figure 6C and Figure 6D are diagrams showing semiconductor devices according to exemplary embodiments of the inventive concept.

[0012] Figure 7 , Figure 8A and Figure 8B are diagrams showing semiconductor devices according to exemplary embodiments of the inventive concept.

[0013] Figure 9 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0014] Figure 10 is a cross-sectional view showing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0015] Figure 11 and Figure 12 are diagrams showing semiconductor devices according to exemplary embodiments of the inventive concept.

[0016] Figure 13 and Figure 14 are diagrams showing semiconductor devices according to exemplary embodiments of the inventive concept.

[0017] Figure 15 are diagrams showing semiconductor devices according to exemplary embodiments of the inventive concept.

[0018] Figure 16 and Figure 17 are diagrams showing semiconductor devices according to exemplary embodiments of the inventive concept.

[0019] Figure 18 and Figure 19 are diagrams showing semiconductor devices according to exemplary embodiments of the inventive concept.

[0020] Figure 20 , Figure 21 and Figure 22 are diagrams showing semiconductor devices according to exemplary embodiments of the inventive concept.

[0021] Figure 23 is a flowchart showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0022] Figure 24 is a flowchart showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Detailed Description

[0023] Hereinafter, terms such as "upper", "middle", "center", "lower", etc. may be replaced with other terms such as "first", "second", "third", etc. to describe elements of the specification. Although terms such as "first", "second", "third", etc. may be used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the spirit and scope of the inventive concept, the "first element" may be referred to as the "second element".

[0024] Reference will be made to Figure 1A , Figure 1B , Figure 1C and Figure 1D to describe a semiconductor device according to an exemplary embodiment of the inventive concept. In Figures 1A to 1D , Figure 1A is a perspective view of a data storage system including a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 1B is a perspective view of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 1C is a block diagram of a data storage system including a semiconductor device according to an exemplary embodiment of the inventive concept, and Figure 1D is a block diagram of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0025] Referring to Figure 1A , a data storage system 1 according to an exemplary embodiment of the inventive concept may include a main board 5 and a controller 10, one or more semiconductor packages 15, and a dynamic random access memory (DRAM) 20 mounted on the main board 5. The semiconductor packages 15 and the DRAM 20 may be connected to the controller 10 through a line pattern 25 formed on the main board 5.

[0026] The main board 5 may include a connector 30, and the connector 30 includes a plurality of pins coupled to an external host ( Figure 1C HOST in

[0027] ). The number and arrangement of the plurality of pins in the connector 30 may vary according to a communication interface between the data storage system 1 and the external host HOST.

[0028] In an exemplary embodiment of the inventive concept, the data storage system 1 may communicate with an external host according to an interface such as a universal serial bus (USB), a peripheral component interconnect express (PCI-Express), a serial advanced technology attachment (SATA), and an M-Phy for a universal flash storage (UFS). Figure 1C In an exemplary embodiment of the inventive concept, the data storage system 1 may be operated by power supplied from an external host (

[0029] The data storage system 1 may include, for example, a power management integrated circuit (PMIC) that distributes power supplied from an external host HOST to the controller 10 and the semiconductor package 15.

[0030] The controller 10 may write data to or read data from the semiconductor package 15, and may increase the operation speed of the data storage system 1.

[0031] The DRAM 20 may be configured as a buffer memory to mitigate the speed difference between the semiconductor package 15 as a data storage space and the external host. The DRAM 20 included in the data storage system 1 may operate as a cache memory and may also provide a space for temporarily storing data during control operations performed on the semiconductor package 15. When the data storage system 1 includes the DRAM 20, in addition to the NAND controller ( Figure 2 1220 in) for controlling the semiconductor package 15, the controller 10 may further include a DRAM controller for controlling the DRAM 20.

[0032] The semiconductor package 15 may include a first semiconductor package 15a and a second semiconductor package 15b spaced apart from each other. Each of the first semiconductor package 15a and the second semiconductor package 15b may be configured as a semiconductor package including a plurality of semiconductor devices CH. The semiconductor device CH may also be referred to as a semiconductor chip.

[0033] Each of the first semiconductor package 15a and the second semiconductor package 15b may include a package substrate 50, semiconductor devices CH on the package substrate 50, an adhesive layer 60 respectively disposed on the lower surfaces of the semiconductor devices CH, a connection structure 70 configured to electrically connect the semiconductor devices CH and the package substrate 50 to each other, and a molding layer 80 covering the semiconductor devices CH and the connection structure 70 on the package substrate 50.

[0034] The package substrate 50 may be configured as a printed circuit board including package upper pads 55. Each of the semiconductor devices CH may include input / output pads IOP.

[0035] In an exemplary embodiment of the inventive concept, the connection structure 70 may be a bonding wire that electrically connects the input / output pad IOP to the on-package pad 55. Accordingly, in each of the first semiconductor package 15a and the second semiconductor package 15b, the semiconductor devices CH may be electrically connected to each other by using a bonding wire method and may be electrically connected to the on-package pad 55 of the package substrate 50. In an exemplary embodiment of the inventive concept, in each of the first semiconductor package 15a and the second semiconductor package 15b, the semiconductor devices CH may be electrically connected to each other by a connection structure including through-silicon vias (TSVs, or “vias through silicon”) instead of the connection structure 70 using a bonding wire method.

[0036] In an exemplary embodiment of the inventive concept, the controller 10 and the semiconductor devices CH may be included in a package. For example, the controller 10 and the semiconductor devices CH may be mounted on an interposer substrate different from the main board 5, and the controller 10 and the semiconductor devices CH may be connected to each other through lines formed on the interposer substrate.

[0037] In an exemplary embodiment of the inventive concept, in each of the semiconductor devices CH, the first structure ST1 may include an input / output pad IOP. In an exemplary embodiment of the inventive concept, the input / output pad IOP may be disposed in the second structure ST2.

[0038] Hereinafter, with reference to Figure 1B 、 Figure 1C and Figure 1D and Figure 1A , each of the semiconductor devices CH may have a first structure ST1 and a second structure ST2 vertically stacked with the first structure ST1 in the vertical direction Z.

[0039] In each of the semiconductor devices CH, the first structure ST1 may include a plurality of memory mats MAT (e.g., MAT1 and MAT2) spaced apart from each other.

[0040] In the following description, exemplary embodiments will be described based on the semiconductor device CH.

[0041] The first structure ST1 may have a first side surface S1 and a second side surface S2 facing each other. In the first structure ST1, the plurality of memory mats MAT1 and MAT2 may be disposed between the first side surface S1 and the second side surface S2.

[0042] The plurality of memory mats MAT1 and MAT2 may include a first memory mat MAT1 adjacent to the first side surface S1 and a second memory mat MAT2 adjacent to the second side surface S2.

[0043] In an exemplary embodiment of the inventive concept, the direction from the first side surface S1 toward the second side surface S2 may be defined as the +X direction, and the direction from the second side surface S2 toward the first side surface S1 may be defined as the -X direction. The +X direction may be referred to as the first horizontal direction or the first direction, and the -X direction may be referred to as the second horizontal direction or the second direction.

[0044] The +X direction and the -X direction may be perpendicular to the vertical direction Z.

[0045] The first memory cluster MAT1 and the second memory cluster MAT2 may be sequentially arranged in the +X direction.

[0046] The first memory cluster MAT1 and the second memory cluster MAT2 may have a mirror-symmetric structure.

[0047] The first memory cluster MAT1 may include a plurality of first memory blocks BLK1, and the second memory cluster MAT2 may include a plurality of second memory blocks BLK2.

[0048] Each of the plurality of first memory blocks BLK1 may have a line shape or a bar shape extending in the +X direction. For example, each of the plurality of first memory blocks BLK1 may have a rectangular shape. Each of the plurality of second memory blocks BLK2 may have a line shape or a bar shape extending in the +X direction. For example, each of the plurality of second memory blocks BLK2 may have a rectangular shape.

[0049] The plurality of first memory blocks BLK1 may be spaced apart from each other in the Y direction. The plurality of second memory blocks BLK2 may be spaced apart from each other in the Y direction.

[0050] The Y direction may be perpendicular to the +X direction, the -X direction, and the vertical direction Z. The Y direction may also be referred to as the third horizontal direction or the third direction.

[0051] Each of the plurality of first memory blocks BLK1 may include a first connection region R1a, a first memory cell array region M1, and a second connection region R1b sequentially arranged in the +X direction. Each of the plurality of second memory blocks BLK2 may include a third connection region R2b, a second memory cell array region M2, and a fourth connection region R2a sequentially arranged in the +X direction. The second connection region R1b of the first memory block BLK1 among the plurality of first memory blocks BLK1 may be adjacent to the third connection region R2b of the second memory block BLK2 among the plurality of second memory blocks BLK2. The second connection regions R1b may be adjacent to each other, and the third connection regions R2b may be adjacent to each other.

[0052] Since the first structure ST1 may include a first memory block BLK1 and a second memory block BLK2, the first structure ST1 may include a first connection region R1a, a first memory cell array region M1, a second connection region R1b, a third connection region R2b, a second memory cell array region M2, and a fourth connection region R2a that are sequentially arranged in the +X direction.

[0053] The first connection region R1a may be referred to as a first external connection region, and the fourth connection region R2a may be referred to as a second external connection region.

[0054] The second connection region R1b and the third connection region R2b may be referred to as a first intermediate connection region and a second intermediate connection region, respectively.

[0055] In an exemplary embodiment of the inventive concept, the first memory cell array region M1 and the second memory cell array region M2 may have the same length as each other in the +X direction.

[0056] In an exemplary embodiment of the inventive concept, in the +X direction, the length of each of the first memory cell array region M1 and the second memory cell array region M2 may be greater than the length of each of the first to fourth connection regions R1a, R1b, R2b, and R2a.

[0057] In an exemplary embodiment of the inventive concept, the first connection region R1a and the fourth connection region R2a may have the same length in the +X direction.

[0058] In an exemplary embodiment of the inventive concept, in the +X direction, the second connection region R1b and the third connection region R2b may be adjacent to each other and may have the same length as each other.

[0059] In an exemplary embodiment of the inventive concept, in the +X direction, the length of each of the second connection region R1b and the third connection region R2b may be greater than the length of each of the first connection region R1a and the fourth connection region R2a.

[0060] In an exemplary embodiment of the inventive concept, the first to fourth connection regions R1a, R1b, R2b, and R2a may have substantially the same width as each other in the Y direction.

[0061] In an exemplary embodiment of the inventive concept, in the Y direction, the width of each of the first to fourth connection regions R1a, R1b, R2b, and R2a may be substantially the same as the width of each of the first memory cell array region M1 and the second memory cell array region M2.

[0062] In an exemplary embodiment of the inventive concept, the "length" in the +X direction may be referred to as the "width" in the +X direction.

[0063] The controller 10 may write data DATA into the semiconductor device CH or may read the data DATA stored in the semiconductor device CH. The controller 10 may send a command CMD, an address ADDR, a control signal CTRL, and data DATA to the semiconductor device CH to write the data DATA into the semiconductor device CH. The controller 10 may send a command CMD, an address ADDR, and a control signal CTRL to the semiconductor device CH to read the data DATA stored in the semiconductor device CH.

[0064] The semiconductor device CH may include a non-volatile memory device (such as a NAND flash memory, a phase change memory (PRAM), a resistive memory (ReRAM), a magnetoresistive memory (MRAM), or a ferroelectric memory (FRAM)). The semiconductor device CH may perform operations of writing, reading, and erasing data DATA in response to signals received from the controller 10.

[0065] Each of the first memory cluster MAT1 and the second memory cluster MAT2 may include a memory cell array MCA including memory cells arranged in a three-dimensional manner. For example, in the first structure ST1, each of a first memory cell array region M1 of a first memory block BLK1 and a second memory cell array region M2 of a second memory block BLK2 may include memory cells arranged in a three-dimensional manner and storing data.

[0066] Memory cells may be arranged in a three-dimensional manner in the first memory cell array region M1 of the first memory cluster MAT1, and memory cells may be arranged in a three-dimensional manner in the second memory cell array region M2 of the second memory cluster MAT2.

[0067] The second structure ST2 may include a peripheral circuit PC. The peripheral circuit PC may include an address decoder 93, a control logic 94, a page buffer 95, an input / output (I / O) circuit 96, and a voltage generation circuit 97. Accordingly, in the semiconductor device CH, the first structure ST1 may include the memory cell array MCA, and the second structure ST2 may include the peripheral circuit PC.

[0068] The first structure ST1 may further include a word line WL, a string select line SSL, a ground select line GSL, a bit line BL, an erase control line ECL, and a common source line CSL.

[0069] The memory cell arrays MCA of the first memory cluster MAT1 and the second memory cluster MAT2 can be electrically connected to the address decoder 93 of the peripheral circuit PC via word lines WL, string selection lines SSL, ground selection lines GSL, and a common source line CSL, and can be electrically connected to the page buffer 95 of the peripheral circuit PC via bit lines BL.

[0070] The address decoder 93 can select one of the first memory block BLK1 and the second memory block BLK2. The address decoder 93 can select one of the word lines WL of the selected memory block. The address decoder 93 can send the voltage provided by the voltage generation circuit 97 to the word line WL or the string selection lines SSL and the ground selection lines GSL of the selected memory block. The address decoder 93 can transfer a programming voltage of a positive (+) high voltage to the selected word line during a programming operation, and can transfer an erase voltage of a positive (+) high voltage to the bulk of the selected memory block during an erase operation.

[0071] The control logic 94 can receive a command CMD and a control signal CTRL from the controller 10, and can control the address decoder 93, the page buffer 95, and the input / output circuit 96 in response to the received signals. The control logic 94 can control the voltage generation circuit 97 configured to generate various voltages required for the operation of the semiconductor device CH. For example, when performing a memory operation such as a programming operation or an erase operation, the control logic 94 can adjust the voltage levels provided to the word lines WL and the bit lines BL.

[0072] The voltage generation circuit 97 can generate voltages of various levels (such as multiple select read voltages, multiple unselect read voltages, multiple programming pulses, multiple pass voltages, and multiple erase pulses) under the control of the control logic 94. In addition, the voltage generation circuit 97 can supply the voltages to the address decoder 93 and the first memory block BLK1 and the second memory block BLK2. For example, the voltage generation circuit 97 can generate a positive (+) high voltage corresponding to multiple programming pulses or multiple erase pulses. The voltage generation circuit 97 can include a charge pump including at least one pumping capacitor to generate voltages of various levels as described above.

[0073] The page buffer 95 may operate as a write driver or a sense amplifier according to an operation mode. During a read operation, the page buffer 95 may sense a bit line BL of a selected memory cell among memory cells three-dimensionally arranged in a first memory block BLK1 and a second memory block BLK2 under the control of the control logic 94. The sensed data may be stored in a latch provided in the page buffer 95. The page buffer 95 may dump data stored in the latch to the input / output circuit 96 under the control of the control logic 94.

[0074] The input / output circuit 96 may temporarily store a command CMD, an address ADDR, a control signal CTRL, and data DATA provided from an external entity of the semiconductor device CH through an input / output pad IOP. The input / output circuit 96 may temporarily store read data of the semiconductor device CH and output the data to an external entity or an external device through the input / output pad IOP at a specified time.

[0075] Reference will be made to Figure 2 and the above Figures 1A to 1D to describe an example of the above-described data storage system 1. Figure 2 FIG. is a diagram showing a data system including a semiconductor device according to an exemplary embodiment of the inventive concept.

[0076] Reference Figure 2 and Figures 1A to 1D and, the data storage system 1 may include a semiconductor device CH (e.g., one or more semiconductor devices 1100) and a controller 1200 electrically connected to the semiconductor device CH. The data storage system 1 may be implemented as a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1 may be implemented as a solid state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0077] The second structure ST2 may be configured as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130.

[0078] The first structure ST1 may include a bit line BL, a common source CSL, a word line WL, a first upper gate line ULa, a second upper gate line ULb, a first lower gate line LLa, a second lower gate line LLb, and a memory cell string CSTR between the bit line BL and the common source CSL.

[0079] In Figure 2In the first structure ST1 shown in the figure, the bit line BL, the common source line CSL, the word line WL, the first upper gate line ULa, the second upper gate line ULb, the first lower gate line LLa, the second lower gate line LLb, and the memory cell string CSTR may be included in one memory block in a memory block in one of the plurality of memory clusters MAT1 and MAT2. For example, Figure 2 The bit line BL, the common source line CSL, the word line WL, the first upper gate line ULa, the second upper gate line ULb, the first lower gate line LLa, the second lower gate line LLb, and the memory cell string CSTR shown in the figure may be included in a second memory block BLK2 in the second memory cluster MAT2. Since the first memory cluster MAT1 and the second memory cluster MAT2 may be mirror-symmetric to each other, Figure 2 The bit line BL, the common source line CSL, the word line WL, the first upper gate line ULa, the second upper gate line ULb, the first lower gate line LLa, the second lower gate line LLb, and the memory cell string CSTR shown in the figure may be included in one of the first memory block BLK1 and the second memory block BLK2.

[0080] The first lower gate line LLa may be disposed at a height higher than the height of the common source line CSL. The second lower gate line LLb may be disposed at a height higher than the height of the first lower gate line LLa. The word line WL may be disposed at a height higher than the height of the second lower gate line LLb. The first upper gate line ULa may be disposed at a height higher than the height of the word line WL. The second upper gate line ULb may be disposed at a height higher than the height of the first upper gate line ULa.

[0081] In the first structure ST1, each memory cell string CSTR may include lower transistors LTa and LTb adjacent to the common source line CSL, upper transistors UTa and UTb adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LTa and LTb and the upper transistors UTa and UTb.

[0082] In an exemplary embodiment of the inventive concept, the number of the lower transistors LTa and LTb and the number of the upper transistors UTa and UTb may vary. The plurality of memory cell transistors MCT may include a data storage area for storing data DATA.

[0083] In an exemplary embodiment of the inventive concept, the upper transistors UTa and UTb may include string selection transistors, and the lower transistors LTa and LTb may include ground selection transistors. The lower gate lines LLa and LLb may be gate electrodes of the lower transistors LTa and LTb, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines ULa and ULb may be gate electrodes of the upper transistors UTa and UTb, respectively.

[0084] In an exemplary embodiment of the inventive concept, the lower transistors LTa and LTb may include a first lower transistor LTa and a second lower transistor LTb on the first lower transistor LTa. The first lower transistor LTa and the second lower transistor LTb may be connected in series with each other. The first lower transistor LTa may be a lower erase control transistor, and the second lower transistor LTb may be a lower selection transistor (e.g., a ground selection transistor). The first lower gate line LLa may be a lower erase control gate electrode of the lower erase control transistor LTa, and the second lower gate line LLb may be a lower selection gate electrode of the lower selection transistor LTb.

[0085] The first lower gate line LLa, the second lower gate line LLb, the word line WL, the first upper gate line ULa, and the second upper gate line ULb may be gate electrodes.

[0086] In an exemplary embodiment of the inventive concept, the upper transistors UTa and UTb may include a first upper transistor UTa and a second upper transistor UTb on the first upper transistor UTa. The first upper transistor UTa and the second upper transistor UTb may be connected in series with each other.

[0087] In an exemplary embodiment of the inventive concept, the first upper transistor UTa may be an upper erase control transistor, and the second upper transistor UTb may be an upper selection transistor (e.g., a string selection transistor). In this case, the first upper gate line ULa may be an upper erase control gate electrode of the upper erase control transistor UTa, and the second upper gate line ULb may be a string selection gate electrode of the string selection transistor UTb. At least one of the lower erase control transistor LTa and the upper erase control transistor UTa may be used in an erase operation to erase data stored in the memory cell transistor MCT by using the gate-induced drain leakage (GIDL) phenomenon.

[0088] In an exemplary embodiment of the inventive concept, the first upper transistor UTa may be an upper selection transistor (e.g., a string selection transistor), and the second upper transistor UTb may be an upper erase control transistor. In this case, the first upper gate line ULa may be a string selection gate electrode of the string selection transistor UTa, and the second upper gate line ULb may be an upper erase control gate electrode of the upper erase control transistor UTb.

[0089] In an exemplary embodiment of the inventive concept, a common source line CSL, a first lower gate line LLa, a second lower gate line LLb, a word line WL, a first upper gate line ULa, and a second upper gate line ULb may be electrically connected to a decoder circuit 1110 through routing wiring structures 1115a and 1115b extending from a first structure ST1 to a second structure ST2.

[0090] In an exemplary embodiment of the inventive concept, the routing wiring structures 1115a and 1115b may be connected to pad regions of the first lower gate line LLa and the second lower gate line LLb, a pad region of the word line WL, and pad regions of the first upper gate line ULa and the second upper gate line ULb.

[0091] The decoder circuit 1110 may include a first circuit 1110a electrically connected to the second upper gate line ULb, a second circuit 1110b electrically connected to the first upper gate line ULa, a third circuit 1110c electrically connected to the word line WL, a fourth circuit 1110d electrically connected to the second lower gate line LLb, a fifth circuit 1110e electrically connected to the first lower gate line LLa, and a sixth circuit 1110f electrically connected to the common source line CSL.

[0092] In an exemplary embodiment of the inventive concept, the routing wiring structures 1115a and 1115b may include a first routing wiring structure 1115a electrically connected to the common source line CSL, the first lower gate line LLa, the second lower gate line LLb, and the word line WL, and a second routing wiring structure 1115b electrically connected to the first upper gate line ULa and the second upper gate line ULb.

[0093] In an exemplary embodiment of the inventive concept, the common source line CSL, the first lower gate line LLa, the second lower gate line LLb, and the word line WL may be electrically connected to the decoder circuit 1110 through the first routing wiring structure 1115a, and the first upper gate line ULa and the second upper gate line ULb may be electrically connected to the decoder circuit 1110 through the second routing wiring structure 1115b.

[0094] In an exemplary embodiment of the inventive concept, the second upper gate line ULb may be electrically connected to the first circuit 1110a of the decoder circuit 1110 through the first routing wiring structure 1115a.

[0095] In an exemplary embodiment of the inventive concept, the second upper gate line ULb may be electrically connected to the first circuit 1110a of the decoder circuit 1110 through the first routing wiring structure 1115a and the second routing wiring structure 1115b.

[0096] In an exemplary embodiment, the first upper gate line ULa may be electrically connected to the second circuit 1110b of the decoder circuit 1110 through the first wiring line structure 1115a and the second wiring line structure 1115b.

[0097] In an exemplary embodiment of the inventive concept, the word line WL may include a lower word line and an upper word line disposed at a height higher than the height of the lower word line. The lower word line may be connected to the decoder circuit 1110 through the first wiring line structure 1115a, and the upper word line may be electrically connected to the third circuit 1110c of the decoder circuit 1110 through the second wiring line structure 1115b.

[0098] The bit line BL may be electrically connected to the page buffer 1120 through a third wiring line structure 1125 extending from the second structure ST2 to the first structure ST1.

[0099] In the second structure ST2, the decoder circuit 1110 and the page buffer 1120 may perform control operations on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130.

[0100] The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad IOP electrically connected to the logic circuit 1130. The input / output pad IOP may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure ST1 to the second structure ST2.

[0101] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230.

[0102] The processor 1210 may control the overall operation of the data storage system 1 including the controller 1200. The processor 1210 may operate according to a predetermined firmware and may access the semiconductor device CH (e.g., the semiconductor device 1100) by controlling the NAND controller 1220. The NAND controller 1220 may include a controller interface (I / F) 1221 that processes communication with the semiconductor device CH. Through the controller interface 1221, control commands for controlling the semiconductor device CH, data to be written to the memory cell transistors MCT of the semiconductor device CH, and data to be read from the memory cell transistors MCT of the semiconductor device CH may be transmitted. The host interface 1230 may provide a communication function between the data storage system 1 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the semiconductor device CH in response to the control command.

[0103] As described above, each of the plurality of first memory blocks (BLK1 in Figure 1B ) in the first memory cluster MAT1 may include a first connection region R1a, a first memory cell array region M1, and a second connection region R1b sequentially arranged in the +X direction, and each of the plurality of second memory blocks (BLK2 in Figure 1B ) in the second memory cluster MAT2 may include a third connection region R2b, a second memory cell array region M2, and a fourth connection region R2a sequentially arranged in the +X direction. The peripheral circuit PC of the second structure ST2 may include a first peripheral circuit (PC1 in Figure 3A ) configured to be electrically connected to the first memory cluster MAT1 and a second peripheral circuit (PC2 in Figure 3A ) configured to be electrically connected to the second memory cluster MAT2.

[0104] In the following description, with reference to Figure 3A and Figure 3B , the electrical connection relationship between one of the plurality of first memory blocks (BLK1 in Figure 1B ) and the first peripheral circuit (PC1 in Figure 3A ) will be described, and the electrical connection relationship between one of the plurality of second memory blocks (BLK2 in Figure 1B ) and the second peripheral circuit (PC2 in Figure 3A ) will be described. Figure 3A is a diagram showing an example of the semiconductor device CH including the first structure ST1 and the second structure ST2 described above, and Figure 3B is a diagram showing the circuits in the first memory cell array region M1 of the first memory cluster MAT1 and the circuits in the second memory cell array region M2 of the second memory cluster MAT2 in Figure 3A .

[0105] With reference to Figure 3A and Figure 3B and Figures 1A to 1D and Figure 2 , as described above, the first connection region R1a, the first memory cell array region M1, the second connection region R1b, the third connection region R2b, the second memory cell array region M2, and the fourth connection region R2a may be sequentially arranged in the +X direction.

[0106] The first memory cluster MAT1 of the first structure ST1 may include a first common source line CSL1 corresponding to the common source line CSL described in Figure 2 , a first lower gate line LL1a and a second lower gate line LL1b corresponding to the first lower gate line LLa and the second lower gate line LLb described in Figure 2 respectively, andFigure 2 The first word line WL1 corresponding to the word line WL described in Figure 2 The first upper gate line UL1a and the second upper gate line UL1b corresponding to the first upper gate line ULa and the second upper gate line ULb described in Figure 2 And the first bit line BL1 corresponding to the bit line BL described in

[0107] The first gate electrode of the first memory cluster MAT1 of the first structure ST1 may include a first lower gate line LL1a, a second lower gate line LL1b, a first word line WL1, a first upper gate line UL1a, and a second upper gate line UL1b.

[0108] The second memory cluster MAT2 of the first structure ST1 may include Figure 2 A second common source CSL2 corresponding to the common source CSL shown in Figure 2 And a third lower gate line LL2a and a fourth lower gate line LL2b corresponding to the first lower gate line LLa and the second lower gate line LLb described in Figure 2 The second memory cluster MAT2 of the first structure ST1 may further include a second word line WL2 corresponding to the word line WL described in Figure 2 A third upper gate line UL2a and a fourth upper gate line UL2b corresponding to the first upper gate line ULa and the second upper gate line ULb described in Figure 2 And a second bit line BL2 corresponding to the bit line BL described in

[0109] The second gate electrode of the second memory cluster MAT2 of the first structure ST1 may include a third lower gate line LL2a, a fourth lower gate line LL2b, a second word line WL2, a third upper gate line UL2a, and a fourth upper gate line UL2b.

[0110] The first memory cluster MAT1 may include Figure 2 A first memory cell string CSTR1 corresponding to the memory cell string CSTR described in Figure 2 And the second memory cluster MAT2 may include a second memory cell string CSTR2 corresponding to the memory cell string CSTR described in

[0111] The first memory cell string CSTR1 may be disposed in the first memory cell array region M1, and the second memory cell string CSTR2 may be disposed in the second memory cell array region M2.

[0112] In the following description, exemplary embodiments of the inventive concept will be described based on one first memory cell string in the first memory cell string CSTR1 and one second memory cell string in the second memory cell string CSTR2.

[0113] Each of the first memory cell string CSTR1 and the second memory cell string CSTR2 may be substantially the same as the memory cell string CSTR described in Figure 2 .

[0114] The first memory cell string CSTR1 may include a first lower transistor LT1a and a second lower transistor LT1b corresponding to the first lower transistor and the second lower transistor ( Figure 2 LTa and LTb in), a first memory cell transistor MCT1 corresponding to a plurality of memory cell transistors ( Figure 2 MCT in), and a first upper transistor UT1a and a second upper transistor UT1b corresponding to the first upper transistor and the second upper transistor ( Figure 2 UTa and UTb in).

[0115] The second memory cell string CSTR2 may include a third lower transistor LT2a and a fourth lower transistor LT2b corresponding to the first lower transistor and the second lower transistor ( Figure 2 LTa and LTb in), a second memory cell transistor MCT2 corresponding to a plurality of memory cell transistors ( Figure 2 MCT in), and a third upper transistor UT2a and a fourth upper transistor UT2b corresponding to the first upper transistor and the second upper transistor ( Figure 2 UTa and UTb in).

[0116] The second structure ST2 may include a first peripheral circuit PC1 electrically connected to the first memory cluster MAT1 and a second peripheral circuit PC2 electrically connected to the second memory cluster MAT2.

[0117] For example, each of the first peripheral circuit PC1 and the second peripheral circuit PC2 may include a first circuit 1110a, a second circuit 1110b, a third circuit 1110c, a fourth circuit 1110d, and a fifth circuit 1110e as described in Figure 2 .

[0118] In the first peripheral circuit PC1, the first circuit 1110a may be electrically connected to the second upper gate line UL1b. In addition, the second circuit 1110b may be electrically connected to the first upper gate line UL1a, and the third circuit 1110c may be electrically connected to the first word line WL1. In addition, the fourth circuit 1110d may be electrically connected to the second lower gate line LL1b, and the fifth circuit 1110e may be electrically connected to the first lower gate line LL1a.

[0119] In the second peripheral circuit PC2, the first circuit 1110a can be electrically connected to the fourth upper gate line UL2b, and the second circuit 1110b can be electrically connected to the third upper gate line UL2a. In addition, the third circuit 1110c can be electrically connected to the second word line WL2, and the fourth circuit 1110d can be electrically connected to the fourth lower gate line LL2b. In addition, the fifth circuit 1110e can be electrically connected to the third lower gate line LL2a.

[0120] The semiconductor device CH may include wiring line structures 1115a1, 1115a2, 1115b1, and 1115b2 corresponding to the wiring line structures 1115a and 1115b described in Figure 2 . For example, the wiring line structures 1115a1, 1115a2, 1115b1, and 1115b2 may include a first wiring line structure 1115a1, a second wiring line structure 1115b1, a third wiring line structure 1115a2, and a fourth wiring line structure 1115b2.

[0121] The first wiring line structure 1115a1 and the second wiring line structure 1115b1 may be configured to electrically connect the first memory cluster MAT1 to the first peripheral circuit PC1. The third wiring line structure 1115a2 and the fourth wiring line structure 1115b2 may be configured to electrically connect the second memory cluster MAT2 to the second peripheral circuit PC2.

[0122] The first wiring line structure 1115a1 may contact and be electrically connected to the gate pads P1a of the first lower gate line LL1a, the second lower gate line LL1b, and the first word line WL1. For example, the first wiring line structure 1115a1 is connected to the gate pads P1a of the first lower gate line LL1a and the second lower gate line LL1b. The second wiring line structure 1115b1 may contact and be electrically connected to the gate pads P1b of the first upper gate line UL1a and the second upper gate line UL1b. The third wiring line structure 1115a2 may contact and be electrically connected to the gate pads P2a of the third lower gate line LL2a, the fourth lower gate line LL2b, and the second word line WL2. The fourth wiring line structure 1115b2 may contact and be electrically connected to the gate pads P2b of the third upper gate line UL2a and the fourth upper gate line UL2b.

[0123] The gate pads P1a of the first lower gate line LL1a, the second lower gate line LL1b, and the first word line WL1 may be disposed in the second connection region R1b. The gate pads P1b of the first upper gate line UL1a and the second upper gate line UL1b may be disposed in the first connection region R1a. The gate pads P2a of the third lower gate line LL2a, the fourth lower gate line LL2b, and the second word line WL2 may be disposed in the third connection region R2b. The gate pads P2b of the third upper gate line UL2a and the fourth upper gate line UL2b may be disposed in the fourth connection region R2a.

[0124] For programming operations, read operations, and erase operations of the first memory cell transistor MCT1 for the first memory cell string CSTR1 and the second memory cell transistor MCT2 for the second memory cell string CSTR2, voltages of various conditions may be applied to the first bit line BL1, the second bit line BL2, the first common source CSL1, the second common source CSL2, the first gate lines LL1a, LL1b, WL1, UL1a, and UL1b, and the second gate lines LL2a, LL2b, WL2, UL2a, and UL2b.

[0125] For example, when data is programmed in a selected memory cell among the memory cells of the first memory cell transistor MCT1 or when data stored in the selected memory cell is read, in order to turn on the second upper transistor UT1b that may be a string select transistor and the second lower transistor LT1b that may be a ground select transistor, a first operating voltage may be applied to the second upper gate line UL1b, and a second operating voltage may be applied to the second lower gate line LL1b. Accordingly, a current may be generated between the first bit line BL1 and the first common source CSL1.

[0126] Each of the first memory cell transistors MCT1 may be controlled by the first word line WL1. For example, a programming voltage may be applied to a selected word line among the first word lines WL1, and a pass voltage may be applied to unselected word lines.

[0127] During an erase operation of erasing data stored in the memory cells of the first memory cell transistor MCT1, an erase voltage may be applied to the first upper gate line UL1a and / or the first lower gate line LL1a of the first upper transistor UT1a and / or the first lower transistor LT1a that may be an erase control transistor.

[0128] To operate the first lower transistor LT1a of the first memory cell string CSTR1 (for example, to turn on the first lower transistor LT1a), a first voltage V LT1a may be applied to the first lower gate line LL1a in the -X direction through the gate pad P1a of the first lower gate line LL1a.

[0129] To operate the second lower transistor LT1b of the first memory cell string CSTR1, the second voltage V LT1b can be applied to the second lower gate line LL1b in the -X direction through the gate pad P1a of the second lower gate line LL1b.

[0130] To operate the first memory cell transistor MCT1 of the first memory cell string CSTR1, the third voltage V WL1 can be applied to the first word line WL1 in the -X direction through the gate pad P1a of the first word line WL1. For example, the application of the third voltage V WL1 can include applying a programming voltage to the selected word lines among the first word lines WL1, and applying a pass voltage to one or more unselected word lines among the first word lines WL1.

[0131] To operate the first upper transistor UT1a of the first memory cell string CSTR1, the fourth voltage V UL1a can be applied to the first upper gate line UL1a in the +X direction through the gate pad P1b of the first upper gate line UL1a.

[0132] To operate the second upper transistor UT1b of the first memory cell string CSTR1, the fifth voltage V UL1b can be applied to the second upper gate line UL1b in the +X direction through the gate pad P1b of the second upper gate line UL1b.

[0133] To operate the third lower transistor LT2a of the second memory cell string CSTR2, the sixth voltage V LT2a can be applied to the third lower gate line LL2a in the +X direction through the gate pad P2a of the third lower gate line LL2a. The amount of the sixth voltage V LT2a can be substantially the same as the amount of the first voltage V LT1a

[0134] To operate the fourth lower transistor LT2b of the second memory cell string CSTR2, the seventh voltage V LT2b can be applied to the fourth lower gate line LL2b in the +X direction through the gate pad P2a of the fourth lower gate line LL2b. The amount of the seventh voltage V LT2b can be substantially the same as the amount of the second voltage V LT1b

[0135] To operate the second memory cell transistor MCT2 of the second memory cell string CSTR2, the eighth voltage V WL2 can be applied to the second word line WL2 in the +X direction through the gate pad P2a of the second word line WL2. The amount of the eighth voltage V WL2 can be the same as the amount of the third voltage V​​WL1 are substantially the same amount.

[0136] To operate the third upper transistor UT2a of the second memory cell string CSTR2, the ninth voltage V UL2a can be applied to the third upper gate line UL2a in the -X direction through the gate pad P2b of the third upper gate line UL2a. The amount of the ninth voltage V UL2a can be substantially the same amount as the fourth voltage V UL1a are substantially the same amount.

[0137] To operate the fourth upper transistor UT2b of the second memory cell string CSTR2, the tenth voltage V UL2b can be applied to the fourth upper gate line UL2b in the -X direction through the gate pad P2b of the fourth upper gate line UL2b. The amount of the tenth voltage V UL2b can be substantially the same amount as the fifth voltage V UL1b are substantially the same amount.

[0138] In the first memory cluster MAT1, an erase voltage can be applied to the first upper gate line UL1a in the +X direction so that gate-induced drain leakage can occur in the first upper transistor UT1a that can serve as an upper erase transistor, and the erase voltage can be applied to the first lower gate line LL1a in the -X direction so that gate-induced drain leakage can occur in the first lower transistor LT1a that can serve as a lower erase transistor.

[0139] In the second memory cluster MAT2, the erase voltage can be applied to the third upper gate line UL2a in the -X direction so that gate-induced drain leakage can occur in the third upper transistor UT2a that can serve as an upper erase transistor, and the erase voltage can be applied to the third lower gate line LL2a in the +X direction so that gate-induced drain leakage can occur in the third lower transistor LT2a that can serve as a lower erase transistor.

[0140] In the following description, an element referred to as a "gate contact plug" can be a part of the wiring line structures 1115a1, 1115a2, 1115b1, and 1115b2, and can contact and be electrically connected to the gate pads P1a, P1b, P2a, and P2b. Accordingly, a voltage can be applied to the gate pads P1a, P1b, P2a, and P2b through the element referred to as a "gate contact plug".

[0141] The above-mentioned first lower gate line LL1a, second lower gate line LL1b, first word line WL1, first upper gate line UL1a, and second upper gate line UL1b may be first-side conductive layers LL1a, LL1b, WL1, UL1a, and UL1b disposed in the first connection region R1a, the first memory cell array region M1, and the second connection region R1b. The third lower gate line LL2a, fourth lower gate line LL2b, second word line WL2, third upper gate line UL2a, and fourth upper gate line UL2b may be second-side conductive layers LL2a, LL2b, WL2, UL2a, and UL2b disposed in the third connection region R2b, the second memory cell array region M2, and the fourth connection region R2a.

[0142] The first-side conductive layers LL1a, LL1b, WL1, UL1a, and UL1b may extend from the first connection region R1a to the second connection region R1b. The first-side conductive layers LL1a, LL1b, WL1, UL1a, and UL1b may include a first lower conductive group LL1a, LL1b, and WL1 and a first upper conductive group UL1a and UL1b. The first lower conductive group LL1a, LL1b, and WL1 has a first lower pad P1a arranged in a stepped shape in the second connection region R1b. The first upper conductive group UL1a and UL1b is disposed at a height higher than the height of the first lower conductive group LL1a, LL1b, and WL1 and has a first upper pad P1b arranged in a stepped shape in the first connection region R1a.

[0143] Among the first-side conductive layers LL1a, LL1b, WL1, UL1a, and UL1b, the number of the first-side conductive layers of the first lower conductive group LL1a, LL1b, and WL1 may be larger than the number of the first-side conductive layers of the first upper conductive group UL1a and UL1b.

[0144] The second-side conductive layers LL2a, LL2b, WL2, UL2a, and UL2b may extend from the third connection region R2b to the fourth connection region R2a. The second-side conductive layers LL2a, LL2b, WL2, UL2a, and UL2b may include a second lower conductive group LL2a, LL2b, and WL2 and a second upper conductive group UL2a and UL2b. The second lower conductive group LL2a, LL2b, and WL2 is disposed at the same height as the first lower conductive group LL1a, LL1b, and WL1 and has a second lower pad P2a arranged in a stepped shape in the third connection region R2b. The second upper conductive group UL2a and UL2b is disposed at the same height as the first upper conductive group UL1a and UL1b and has a second upper pad P2b arranged in a stepped shape in the fourth connection region R2a.

[0145] Hereinafter, reference will be made to Figure 4 、Figure 5 , Figure 6A , Figure 6B , Figure 6C and Figure 6D and the above Figures 1A to 3B describe examples of the semiconductor device CH. In Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C and Figure 6D , Figure 4 is a top view showing an example of the semiconductor device CH, and Figure 5 is a cross-sectional view showing a region taken along line I-I' in Figure 4 . Figure 6A is an enlarged view showing the region “A” in Figure 5 , and Figure 6B is an enlarged view showing the region “B” in Figure 5 . Figure 6C is an enlarged view showing the region “B” in Figure 5 , and Figure 6D is an enlarged view showing the region “D” in Figure 5 .

[0146] In an exemplary embodiment of the inventive concept, the first memory cluster MAT1 and the second memory cluster MAT2 may have a mirror-symmetric structure. Accordingly, the structure of the second memory cluster MAT2 may be understood from the following description of the structure of the first memory cluster MAT1. Accordingly, in the following description, exemplary embodiments of the inventive concept will be described based on the structure of the first memory cluster MAT1.

[0147] Referring to Figures 4 to 6D and Figures 1A to 3B , the width of each of the second connection region R1b and the third connection region R2b in the +X direction may be greater than the width of each of the first connection region R1a and the fourth connection region R2a in the +X direction.

[0148] The semiconductor device CH may further include a separation structure SP disposed between the first memory blocks BLK1 to space the first memory blocks BLK1 apart from each other in the Y direction, and disposed between the second memory blocks BLK2 to space the second memory blocks BLK2 apart from each other in the Y direction. Each of the separation structures SP may be disposed between the first memory blocks BLK1 adjacent to each other in the Y direction, and disposed between the second memory blocks BLK2 adjacent to each other in the Y direction.

[0149] The separation structure SP may extend from a portion disposed between the first memory blocks BLK1 to a region between the second memory blocks BLK2.

[0150] The first structure ST1 may further include a substrate 103, a plate pattern 106 on the substrate 103, and an insulating pattern 109 on a side surface of the plate pattern 106.

[0151] The substrate 103 may include an insulating material. The plate pattern 106 may include at least one of a semiconductor material and a conductive material. For example, at least a part of the plate pattern 106 may include a conductive material (such as doped silicon). For example, at least a part of the plate pattern 106 may include polysilicon having N-type conductivity. In an exemplary embodiment of the inventive concept, the plate pattern 106 may include a doped polysilicon layer and a metal layer vertically stacked on the doped polysilicon layer. The insulating pattern 109 may include an insulating material (such as silicon oxide). At least a part of the plate pattern 106 may be the above-described first common source ( Figure 3A and Figure 3B CSL1 in).

[0152] In an exemplary embodiment of the inventive concept, the plate pattern 106 may be referred to as a source structure or a common source.

[0153] Each of the first memory bank MAT1 and the second memory bank MAT2 may include a gate electrode GE. For example, in each of the first memory bank MAT1 and the second memory bank MAT2, the first structure ST1 may include gate electrodes GE spaced apart from each other in a vertical direction Z. Each of the gate electrodes GE may be formed of, for example, W, Ru, Mo, Nb, Ni, Co, Ti, Ta, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof, but the inventive concept is not limited thereto. For example, each of the gate electrodes GE may include a single layer or multiple layers formed of the above materials.

[0154] In an example, the gate electrode GE may include a gate electrode formed of a first material and one or more gate electrodes formed of a second material different from the first material.

[0155] In an example, the gate electrodes GE may be formed of the same material.

[0156] The gate electrode GE may include a lower gate electrode GE_L, an intermediate gate electrode GE_M on the lower gate electrode GE_L, and an upper gate electrode GE_U on the intermediate gate electrode GE_M.

[0157] The lower gate electrode GE_L may include a first lower gate electrode GE_La and a second lower gate electrode GE_Lb provided on the first lower gate electrode GE_La.

[0158] The first lower gate electrode GE_La may be the above-described first lower gate line (Figure 3A and Figure 3B in LL1a) above, and the second lower gate electrode GE_Lb may be the second lower gate line above ( Figure 3A and Figure 3B in LL1b) above.

[0159] The middle gate electrode GE_M may include a first middle gate electrode GE_Ma and a second middle gate electrode GE_Mb on the first middle gate electrode GE_Ma. The middle gate electrode GE_M may include the first word line above ( Figure 3A and Figure 3B in WL1).

[0160] The upper gate electrode GE_U may include a first upper gate electrode GE_Ua and a second upper gate electrode GE_Ub disposed on the first upper gate electrode GE_Ua. At least one of the first upper gate electrodes GE_Ua may be the first upper gate line above ( Figure 3A and Figure 3B in UL1a). For example, among the first upper gate electrodes GE_Ua, the gate electrode disposed at a relatively higher height may be the first upper gate line above ( Figure 3A and Figure 3B in UL1a), while the gate electrode disposed at a relatively lower height may be a dummy gate electrode. The second upper gate electrode GE_Ub may be the second upper gate line above ( Figure 3A and Figure 3B in UL1b).

[0161] In an example, the second upper gate electrode GE_Ub may be the string selection gate line of the above string selection transistor, and at least one of the first upper gate electrodes GE_Ua may be the erase control gate line of the above erase control transistor.

[0162] The first structure ST1 may include a stacked structure GS. The stacked structure GS may include a first stacked structure GS1 and a second stacked structure GS2 disposed on the first stacked structure GS1.

[0163] The first stacked structure GS1 may include a lower gate electrode GE_L and a first middle gate electrode GE_Ma. The second stacked structure GS2 may include a second middle gate electrode GE_Mb and an upper gate electrode GE_U.

[0164] The first structure ST1 may further include interlayer insulating layers ILDa and ILDb. The interlayer insulating layers ILDa and ILDb may include a first interlayer insulating layer ILDa and a second interlayer insulating layer ILDb. The first interlayer insulating layer ILDa may be alternately stacked with a gate electrode including a lower gate electrode GE_L and a first intermediate gate electrode GE_Ma. The second interlayer insulating layer ILDb may be alternately stacked with a gate electrode including a second intermediate gate electrode GE_Mb and a first upper gate electrode GE_Ua.

[0165] The gate electrodes GE may be stacked in the vertical direction Z and spaced apart from each other in the first memory cell array region M1, and may extend from the first memory cell array region M1 to the first connection region R1a and the second connection region R1b.

[0166] In the first memory cell array region M1, each of the lower gate electrodes GE_L may have a first thickness T1, and each of the intermediate gate electrodes GE_M may have a second thickness T2. In addition, each of the first upper gate electrodes GE_Ua may have a third thickness T3, and the second upper gate electrode GE_Ub may have a fourth thickness T4.

[0167] The third thickness T3 may be greater than at least one of the first thickness T1 and the second thickness T2. For example, the third thickness T3 may be greater than each of the first thickness T1 and the second thickness T2. For example, the fourth thickness T4 may be greater than the third thickness T3. For example, the fourth thickness T4 may be greater than each of the first thickness T1, the second thickness T2, and the third thickness T3.

[0168] The lower gate electrode GE_L and the intermediate gate electrode GE_M may have gate pads ( Figure 6D G_P2a1 in Figure 6C G_P2a2 in Figure 6D G_P2b1 in Figure 6C and G_P2b2 in Figure 6D G_P2a1 in Figure 6C G_P2a2 in Figure 6D G_P2b1 in Figure 6C and G_P2b2 in Figure 6A in the second connection region R1b). The thickness of each of the gate pads (

[0169] G_P2a1 in Figure 6B G_P1a in Figure 5 G_P1b in Figure 6BThe thickness of each of G_P1a) therein may be greater than a third thickness ( Figure 6A T3) therein. The gate pad of the second upper gate electrode GE_Ub ( Figure 5 G_P1b) therein may have a fourth thickness ( Figure 6A T4) therein.

[0170] The gate pad of the upper gate electrode GE_U ( Figure 6B G_P1a and Figure 5 G_P1b) therein may be Figure 3A the gate pad P1b of the first upper gate line UL1a and the second upper gate line UL1b described in

[0171] The gate pads of the lower gate electrode GE_L and the middle gate electrode GE_M ( Figure 6D G_P2a1, Figure 6C G_P2a2, Figure 6D G_P2b1, Figure 6C G_P2b2) therein may be Figure 3A the gate pad P1a of the first lower gate line LL1a, the second lower gate line LL1b, and the first word line WL1 described in

[0172] The gate pad of the gate electrode GE may include: a first lower gate pad ( Figure 6D G_P2a1) therein, having a stepped structure that decreases sequentially in the +X direction as the gate pad is further set; a second lower gate pad ( Figure 6C G_P2a2) therein, having a stepped structure that decreases sequentially in the +X direction; a first upper gate pad ( Figure 6D G_P2b1) therein, having a stepped structure that decreases sequentially in the +X direction as the gate pad is further set; a second upper gate pad ( Figure 6C G_P2b2) therein, having a stepped structure that decreases sequentially in the +X direction as the gate pad is further set; and a third upper gate pad ( Figure 6B G_P1a) therein, having a stepped structure that decreases sequentially in the -X direction as the gate pad is further set.

[0173] The first lower gate pad ( Figure 6D G_P2a1) therein may include the gate pad of the first middle gate electrode and the gate pad of the lower gate electrode GE_L provided in the lower part of the first middle gate electrode GE_Ma. The second lower gate pad ( Figure 6C G_P2a2) therein may include the gate pad of the first middle gate electrode provided in the upper part of the first middle gate electrode GE_Ma. The first upper gate pad ( Figure 6D G_P2b1) therein may include the gate pad of the second middle gate electrode provided in the lower part of the second middle gate electrode GE_Mb. The second upper gate pad (Figure 6C The G_P2b2) in may include a gate pad of the second intermediate gate electrode provided in the upper portion of the second intermediate gate electrode GE_Mb. The third upper gate pad ( Figure 6B The G_P1a) in may include a gate pad of the first upper gate electrode GE_Ua.

[0174] The second lower gate pad ( Figure 6C The G_P2a2) in may be provided at a height higher than the height of the first lower gate pad ( Figure 6D The G_P2a1) in. The first upper gate pad ( Figure 6D The G_P2b1) in may be provided at a height higher than the height of the second lower gate pad ( Figure 6C The G_P2a2) in. The second upper gate pad ( Figure 6C The G_P2b2) in may be provided at a height higher than the height of the first upper gate pad ( Figure 6D The G_P2b1) in. The third upper gate pad ( Figure 6B The G_P1a) in may be provided at a height higher than the height of the second upper gate pad ( Figure 6C The G_P2b2) in.

[0175] The first lower gate pad ( Figure 6D The G_P2a1) in, the second lower gate pad ( Figure 6C The G_P2a2) in, the first upper gate pad ( Figure 6D The G_P2b1) in, and the second upper gate pad ( Figure 6C The G_P2b2) in may not overlap with each other in the vertical direction Z.

[0176] The first lower gate pad ( Figure 6D The G_P2a1) in may be further provided at a position more spaced apart from the first memory cell array region M1 compared to the second lower gate pad ( Figure 6C The G_P2a2) in. The first upper gate pad ( Figure 6D The G_P2b1) in may be provided at a position more spaced apart from the first memory cell array region M1 compared to the second upper gate pad ( Figure 6C The G_P2b2) in.

[0177] In an exemplary embodiment of the inventive concept, the first lower gate pad ( Figure 6D The G_P2a1) in, the second lower gate pad ( Figure 6C The G_P2a2) in, the first upper gate pad ( Figure 6D The G_P2b1) in, and the second upper gate pad ( Figure 6C The G_P2b2) in are not limited to the positions spaced apart from the first memory cell array region M1 shown in Figure 5 The example shown in, but may vary.

[0178] The first structure ST1 may further include an insulating cover structure (INS_C in Figure 4 ). The insulating cover structure (INS_C in Figure 4 ) may be disposed between the first memory cluster MAT1 and the second memory cluster MAT2.

[0179] The insulating cover structure (INS_C in Figure 4 ) may include a first lower insulating cover pattern (INS_C1c in Figure 6D ), a second lower insulating cover pattern (INS_C1b in Figure 6C ), a first upper insulating cover pattern (INS_C2c in Figure 6D ), and a second upper insulating cover pattern (INS_C2b in Figure 6C ).

[0180] The first lower insulating cover pattern (INS_C1c in Figure 6D ) and the second lower insulating cover pattern (INS_C1b in Figure 6C ) may be disposed at a height lower than the height of the second stacked structure GS2. For example, the first lower insulating cover pattern (INS_C1c in Figure 6D ) and the second lower insulating cover pattern (INS_C1b in Figure 6C ) may be disposed at a height lower than the height of the lowermost second intermediate gate electrode among the second intermediate gate electrodes GE_Mb.

[0181] The first lower insulating cover pattern (INS_C1c in Figure 6D ) may be disposed on the first lower gate pad (G_P2a1 in Figure 6D ), and may penetrate the gate electrode and the interlayer insulating layer at a height higher than the height of the first lower gate pad (G_P2a1 in Figure 6D ) in the vertical direction Z. In addition, the first lower insulating cover pattern (INS_C1c in Figure 6D ) may penetrate the first lower gate electrode GE_La. Accordingly, the end portions of the lower gate electrode GE_L and the first intermediate gate electrode GE_Ma disposed in the +X direction may be adjacent to the first lower insulating cover pattern (INS_C1c in Figure 6D ).

[0182] The second lower insulating cover pattern (INS_C1b in Figure 6C ) may be disposed on the second lower gate pad (G_P2a2 in Figure 6C ), and may penetrate the gate electrode and the interlayer insulating layer at a height higher than the height of the second lower gate pad (G_P2a2 in Figure 6C ) in the vertical direction Z.

[0183] The first upper insulating cover pattern ( Figure 6D INS_C2c in) and the second upper insulating cover pattern ( Figure 6C INS_C2b in) can be set at a height higher than the height of the uppermost first intermediate gate electrode in the first intermediate gate electrode GE_Ma.

[0184] The first upper insulating cover pattern ( Figure 6D INS_C2c in) can be set on the first upper gate pad ( Figure 6D G_P2b1 in) and can cover the first upper gate pad ( Figure 6D G_P2b1 in) in the vertical direction Z. In addition, the first upper insulating cover pattern ( Figure 6D INS_C2c in) can penetrate the second intermediate gate electrode GE_Mb and the first upper gate electrode GE_Ua.

[0185] The second upper insulating cover pattern ( Figure 6C INS_C2b in) can be set on the second upper gate pad ( Figure 6C G_P2b2 in) and can penetrate the gate electrode and the interlayer insulating layer at a height higher than the height of the gate pad of the second upper gate pad ( Figure 6C G_P2b2 in) in the vertical direction Z.

[0186] The gate electrode GE in the first memory cluster MAT1 can be spaced apart from the gate electrode GE in the second memory cluster MAT2.

[0187] The lower gate electrode GE_L, the intermediate gate electrode GE_M, and the first upper gate electrode GE_Ua in the first memory cluster MAT1 can be spaced apart from the lower gate electrode GE_L, the intermediate gate electrode GE_M, and the first upper gate electrode GE_Ua in the second memory cluster MAT2 by the first lower insulating cover pattern ( Figure 6D INS_C1c in), the second lower insulating cover pattern ( Figure 6C INS_C1b in), the first upper insulating cover pattern ( Figure 6D INS_C2c in), and the second upper insulating cover pattern ( Figure 6C INS_C2b in).

[0188] Among the gate electrodes GE, the gate electrode GE_F provided between the lower gate electrode GE_L, the intermediate gate electrode GE_M, and the first upper gate electrode GE_Ua in the first memory cluster MAT1 and the lower gate electrode GE_L, the intermediate gate electrode GE_M, and the first upper gate electrode GE_Ua in the second memory cluster MAT2 can be an electrically isolated dummy gate electrode. For example, in Figure 6C and Figure 6D the dummy gate electrode GE_F can be the one provided in the second lower insulating cover pattern ( Figure 6CThe gate electrode GE on the right side of INS_C1b) in, the gate electrode GE on the right side of INS_C2c) in the Figure 6D and the gate electrode GE on the right side of INS_C2b) in the Figure 6C . Figure 6D The gate electrode GE on the right side of INS_C2c) in, and the gate electrode GE on the right side of INS_C2b) in the . Figure 6C The gate electrode GE on the right side of INS_C2b) in the .

[0189] The first structure ST1 may further include an external cover insulation structure ( Figure 6B INS_C1a and INS_C2a) in the Figure 6B .

[0190] The external cover insulation structure ( Figure 6B INS_C1a and INS_C2a) in the Figure 6B may be arranged to at least partially surround the outer surfaces of the lower gate electrode GE_L, the middle gate electrode GE_M, and the first upper gate electrode GE_Ua of the first memory cluster MAT1 and the second memory cluster MAT2. For example, a part of the external cover insulation structure ( Figure 6B INS_C1a and INS_C2a) in the Figure 6B may be arranged on the outer surfaces of the lower gate electrode GE_L, the middle gate electrode GE_M, and the first upper gate electrode GE_Ua, and may cover the third upper gate pad ( Figure 6B G_P1a) in the Figure 6B .

[0191] The insulation cover structure ( Figure 4 INS_C) in the Figure 4 may include a first lower insulation cover pattern ( Figure 6D INS_C1c) in the Figure 6D , a second lower insulation cover pattern ( Figure 6C INS_C1b) in the Figure 6C , a first upper insulation cover pattern ( Figure 6D INS_C2c) in the Figure 6D , and a second upper insulation cover pattern ( Figure 6C INS_C2b) in the Figure 6C .

[0192] The external cover insulation structure ( Figure 6B INS_C1a and INS_C2a) in the Figure 6B may include a first external cover insulation structure ( Figure 6B INS_C1a) in the Figure 6B and a second external cover insulation structure ( Figure 6B INS_C2a) in the Figure 6B .

[0193] The first external cover insulation structure ( Figure 6B INS_C1a) in the Figure 6B may be arranged on the insulation pattern 109, and may be arranged on the outer surfaces of the lower gate electrode GE_L, the middle gate electrode GE_M (e.g., the first middle gate electrode GE_Ma), and the first interlayer insulation layer ILDa.

[0194] The second external cover insulation structure ( Figure 6B INS_C2a) in the Figure 6B may be arranged on the first external cover insulation structure ( Figure 6Bon INS_C1a) in, and can be disposed on the outer surface of the first upper gate electrode GE_Ua and the second interlayer insulating layer ILDb. In the example, the second outer cover insulating structure ( Figure 6B in INS_C2a) can be disposed on the outer surface of the first upper gate electrode GE_Ua, the second intermediate gate electrode GE_Mb, and the second interlayer insulating layer ILDb. In addition, the second outer cover insulating structure ( Figure 6B in INS_C2a) can cover the third upper gate pad ( Figure 6B in G_P1a).

[0195] The outer cover insulating structure ( Figure 6B in INS_C1a and INS_C2a), the first upper insulating cover pattern ( Figure 6D in INS_C2c) and the second upper insulating cover pattern ( Figure 6C in INS_C2b) can have their upper surfaces disposed at a height higher than the height of the uppermost first upper gate electrode among the first upper gate electrodes GE_Ua.

[0196] The outer cover insulating structure ( Figure 6B in INS_C1a and INS_C2a), the first upper insulating cover pattern ( Figure 6D in INS_C2c) and the second upper insulating cover pattern ( Figure 6C in INS_C2b) can have their upper surfaces substantially coplanar with the upper surface of the uppermost second interlayer insulating layer among the second interlayer insulating layers ILDb.

[0197] The first structure ST1 can further include a buffer insulating layer 120, and the buffer insulating layer 120 is disposed on the upper surfaces of the outer cover insulating structure ( Figure 6B in INS_C1a and INS_C2a), the first upper insulating cover pattern ( Figure 6D in INS_C2c) and the second upper insulating cover pattern ( Figure 6C in INS_C2b) and on the upper surface of the uppermost second interlayer insulating layer among the second interlayer insulating layers ILDb. The buffer insulating layer 120 can be an etch stop layer. For example, the buffer insulating layer 120 can include an insulating material (such as SiN, SiCN, or SiBN). The second upper gate electrode GE_Ub can be disposed at a height higher than the height of the buffer insulating layer 120.

[0198] The first structure ST1 can further include a vertical memory structure VS that penetrates the gate electrode GE. For example, the vertical memory structure VS can be disposed in the first memory cell array region M1 and the second memory cell array region M2.

[0199] Each of the vertical memory structures VS may include a first vertical memory structure VS_L, a second vertical memory structure VS_U, and a connection structure VS_C.

[0200] The first vertical memory structure VS_L may penetrate the lower gate electrode GE_L, the intermediate gate electrode GE_M, the first upper gate electrode GE_Ua, the first interlayer insulating layer ILDa, and the second interlayer insulating layer ILDb, and may contact the plate pattern 106.

[0201] The first vertical memory structure VS_1 may include a first insulating core region 116, a first channel layer 114 disposed on a side surface of the first insulating core region 116 and connected to the plate pattern 106, and a data storage structure 112 disposed on an outer surface of the first channel layer 114.

[0202] The first vertical memory structure VS_1 may further include a first pad pattern 118 disposed on the first insulating core region 116 and connected to the first channel layer 114.

[0203] The first insulating core region 116 may include an insulating material such as silicon oxide.

[0204] The first channel layer 114 may cover a side surface and a lower surface of the first insulating core region 116. The first channel layer 114 may include a semiconductor material such as polysilicon, single-crystalline silicon, or an oxide semiconductor. A portion of the plate pattern 106 in contact with the first channel layer 114 may include at least doped silicon. For example, the plate pattern 106 may include polysilicon having N-type conductivity. In an exemplary embodiment of the inventive concept, the plate pattern 106 may include polysilicon having N-type conductivity and polysilicon having P-type conductivity.

[0205] The data storage structure 112 may include a first dielectric layer 112a, a second dielectric layer 112c, and a data storage layer 112b disposed between the first dielectric layer 112a and the second dielectric layer 112c. The second dielectric layer 112c may contact the first channel layer 114.

[0206] The first dielectric layer 112a may be a blocking dielectric layer. The first dielectric layer 112a may include at least one of silicon oxide and a high-κ dielectric. The second dielectric layer 112c may be a tunneling dielectric layer. The second dielectric layer 112c may include, for example, silicon oxide or silicon oxide doped with impurities.

[0207] The data storage layer 112b may include a material capable of storing data by capturing charges, such as silicon nitride. The data storage layer 112b may include a region capable of storing data in a semiconductor device such as a flash memory device.

[0208] In an exemplary embodiment of the inventive concept, the data storage structure 112 may include a data storage layer 112b that can capture charge and store data, but the inventive concept is not limited thereto. For example, the data storage structure 112 may be a data storage structure used in a ferroelectric memory, and the ferroelectric memory may store data using remnant polarization via dipoles.

[0209] The first pad pattern 118 may be disposed at a height higher than the height of the first upper gate electrode GE_Ua. The first pad pattern 118 may include, for example, polysilicon. For example, the first pad pattern 118 may include doped polysilicon.

[0210] The first vertical memory structure VS_L may include a lower vertical portion VS_La, an upper vertical portion VS_Lc disposed on the lower vertical portion VS_La, and a junction portion VS_Lb disposed between the lower vertical portion VS_La and the upper vertical portion VS_Lc.

[0211] In the first vertical memory structure VS_L, the junction portion VS_Lb may be disposed at a height higher than the height of the uppermost first intermediate gate electrode among the first intermediate gate electrodes GE_Ma and at a height lower than the height of the lowermost second intermediate gate electrode among the second intermediate gate electrodes GE_Mb.

[0212] The junction portion VS_Lb may have side surfaces that are curved from the side surfaces of the lower vertical portion VS_La and the upper vertical portion VS_Lc. For example, the side surfaces of the junction portion VS_Lb may not be flat (even).

[0213] The connection structure VS_C may penetrate the buffer insulating layer 120 and may be connected to the first pad pattern 118 and the first channel layer 114. The connection structure VS_C may include, for example, polysilicon. The vertical central axis of the connection structure VS_C and the vertical central axis of the first vertical memory structure VS_L may not be aligned.

[0214] The vertical central axis of the second vertical memory structure VS_U may not be aligned with the vertical central axis of the first vertical memory structure VS_L.

[0215] The second vertical memory structure VS_U may penetrate the second upper gate electrode GE_Ub and may be connected to the connection structure VS_C.

[0216] The second vertical memory structure VS_U may include a second insulating core region 126, a second channel layer 124 disposed on a side surface of the second insulating core region 126 and connected to a connection structure VS_C, a gate dielectric layer 122 disposed on an outer surface of the second channel layer 124, and a second pad pattern 128 disposed on the second insulating core region 126.

[0217] The second channel layer 124 may include at least one material layer. For example, the second channel layer 124 may include a first layer 124a and a second layer 124b. The second layer 124b may cover a side surface and a lower surface of the second insulating core region 126 and may be connected to the connection structure VS_C. The first layer 124a may be disposed between the second layer 124b and the gate dielectric layer 122.

[0218] The gate dielectric layer 122 may include at least one of, for example, silicon oxide and a high-κ dielectric.

[0219] The first layer 124a and the second layer 124b of the second channel layer 124 may include a semiconductor material (such as polysilicon, single-crystalline silicon, or an oxide semiconductor). The first layer 124a and the second layer 124b may be formed of the same semiconductor material as each other, but the inventive concept is not limited thereto. For example, the first layer 124a and the second layer 124b may be formed of different semiconductor materials from each other.

[0220] In an exemplary embodiment of the inventive concept, the second channel layer 124 may be formed as a single layer.

[0221] The second pad pattern 128 may include, for example, polysilicon. For example, the second pad pattern 128 may include doped polysilicon having N-type conductivity.

[0222] The first structure ST1 may further include a gate contact plug 160 and an upper gate contact plug 163.

[0223] The gate contact plug 160 may include a first gate contact plug 160a and a second gate contact plug 160b. The first gate contact plug 160a may be electrically connected to a third upper gate pad of the first upper gate electrode GE_Ua ( Figure 6B G_P1a in). The second gate contact plug 160b may be electrically connected to gate pads of the lower gate electrode GE_L and the intermediate gate electrode GE_M ( Figure 6D G_P2a1 in, Figure 6C G_P2a2 in, Figure 6D G_P2b1 in, and Figure 6C G_P2b2 in).

[0224] The gate contact plug 160 may include a gate pad ( Figure 6D G_P2a1 in,Figure 6C G_P2a2 in Figure 6D G_P2b1 in Figure 6C and G_P2b2 in

[0225] Since the gate pads ( Figure 6D G_P2a1 in Figure 6C G_P2a2 in Figure 6D G_P2b1 in Figure 6C and G_P2b2 in Figure 6D G_P2a1 in Figure 6C G_P2a2 in Figure 6D G_P2b1 in Figure 6C and G_P2b2 in

[0226] can be set at different heights from each other, the connection plug portions 160P that contact and connect to the gate pads ( Figure 6D G_P2a1 in Figure 6C G_P2a2 in Figure 6D G_P2b1 in Figure 6C and G_P2b2 in

[0227] can also be set at different heights from each other.

[0228] For example, each of the gate contact plugs 160 may include a connection plug portion 160P, a lower plug portion 160_La extending downward from the connection plug portion 160P, and a first upper plug portion 160_Lb extending upward from the connection plug portion 160P. Each of the gate contact plugs 160 may include a second upper plug portion 160_U extending upward from the first upper plug portion 160_Lb.

[0229] In each of the gate contact plugs 160, the width of the connection plug portion 160P may be greater than the width of the lower plug portion 160_La adjacent to the connection plug portion 160P, and may be greater than the width of the first upper plug portion 160_Lb adjacent to the connection plug portion 160P.

[0230] In each of the gate contact plugs 160, the width of the second upper plug portion 160_U and the width of the first upper plug portion 160_Lb may be different from each other. For example, the width of the second upper plug portion 160_U adjacent to the first upper plug portion 160_Lb may be greater than the width of the first upper plug portion 160_Lb adjacent to the second upper plug portion 160_U.

[0231] The connection plug portion 160P of the first gate contact plug 160a connected to the third upper gate pad ( Figure 6B G_P1a in Figure 6D connected to the first upper gate electrode GE_Ua) may be disposed at a height higher than the height of the connection plug portion 160P of the second gate contact plug 160b connected to the gate pads ( Figure 6C G_P2a1 in Figure 6D connected to the lower gate electrode GE_L and the middle gate electrode GE_M, Figure 6C G_P2b1 in

[0232] Each of the gate contact plugs 160 may have a lower surface disposed at a height lower than the height of the lowest gate electrode GE_La among the gate electrodes GE and an upper surface disposed at a height higher than the height of the uppermost gate electrode GE_Ub among the gate electrodes GE.

[0233] Each of the gate contact plugs 160 may continuously extend from the lower surface to the upper surface. For example, each of the gate contact plugs 160 may include a conductive layer continuously extending from a height lower than the height of the lowest gate electrode GE_La among the gate electrodes GE to a height higher than the height of the uppermost gate electrode GE_Ub among the gate electrodes GE.

[0234] The first structure ST1 may further include a separation insulating layer 158. The separation insulating layer 158 may be disposed between the gate electrode GE that may not be electrically connected to the gate contact plug 160 and the gate contact plug 160. For example, the separation insulating layer 158 may be disposed between the lower plug portion 160_La and the gate electrode GE and between the first upper plug portion 160_Lb and the gate electrode GE. The separation insulating layer 158 may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0235] The upper gate contact plug 163 may be disposed on the gate pad G_P1b of the second upper gate electrode GE_Ub. The upper gate contact plug 163 may be in contact with and electrically connected to the gate pad G_P1b of the second upper gate electrode GE_Ub. The lower surface of the upper gate contact plug 163 may be in contact with the gate pad G_P1b of the second upper gate electrode GE_Ub and may be disposed at a height higher than the height of the lower surface of the gate pad G_P1b.

[0236] The above bit line BL can be disposed at a height higher than the heights of the second upper gate electrode GE_Ub and the gate contact plug 160.

[0237] The first structure ST1 may further include a bit line stud BLP disposed between the bit line BL and the vertical memory structure VS and electrically connected to the bit line BL and the vertical memory structure VS. Accordingly, the bit line BL can be electrically connected to the second pad pattern 128 of the vertical memory structure VS through the bit line stud BLP.

[0238] The first structure ST1 may include a gate stud 166 disposed on the gate contact plug 160 and electrically connected to the gate contact plug 160.

[0239] The first structure ST1 may further include lower wiring line structures 169, 172, and 175. The lower wiring line structures 169, 172, and 175 may include a first horizontal line 169, a first via 172, and a first bonding pad 175. The first bonding pad 175 may be disposed at a height higher than the heights of the first horizontal line 169 and the first via 172.

[0240] The first structure ST1 may further include a first insulating structure INS_U. The first insulating structure INS_U may be disposed on the buffer insulating layer 120 and may have an upper surface coplanar with the upper surface of the first bonding pad 175.

[0241] The second structure ST2 may include a substrate 206, a peripheral active region 209a below the substrate 206, and a peripheral device isolation region 209s defining the peripheral active region 209a below the substrate 206. The substrate 206 may be implemented as a semiconductor substrate.

[0242] The second structure ST2 may further include a peripheral device PTR, upper wiring line structures 220 and 225, and a second insulating structure (also referred to as an upper insulating structure) 230 disposed below the substrate 206.

[0243] The peripheral device PTR may be included in the above-mentioned peripheral circuit PC.

[0244] The peripheral device PTR may include a peripheral transistor, which includes peripheral source / drain regions PTR_S / D spaced apart from each other in the peripheral active region 209a, a peripheral channel region PTR_CH between the peripheral source / drain regions PTR_S / D, and a peripheral gate PTR_G below the peripheral active region 209a.

[0245] The upper wiring line structures 220 and 225 may be buried in the upper insulating structure 230 and may be electrically connected to the peripheral device PTR. The upper wiring line structures 220 and 225 may include a line portion 220 and a second bonding pad 225. The line portion 220 includes a horizontal portion and a vertical portion. The second bonding pad 225 is below the line portion 220 and has a lower surface substantially coplanar with the lower surface of the second insulating structure 230. The first bonding pad 175 and the second bonding pad 225 may be bonded to each other through a metal indirect bonding process. The lower wiring line structures 169, 172, and 175, the upper wiring line structures 220 and 225, the gate contact plug 160, the gate post 166, and the upper gate contact plug 163 may be included in the above-described wiring line structures ( Figure 2 in 1115a and 1115b).

[0246] In the following description, various modified examples of the above-described exemplary embodiments for increasing the integration degree and increasing the reliability of the semiconductor device CH will be described with reference to Figures 9 to 22 Various modified examples of the elements of the above-described exemplary embodiments will be described based on modified elements, replacement elements, or added elements. In addition, the elements that can be modified or replaced in the various modified examples described below may be combined with each other or combined with the above-described elements and may be included in the semiconductor device of the exemplary embodiment according to the inventive concept.

[0247] Figure 7 is a cross-sectional view showing a region taken along line I-I' in the semiconductor device according to an exemplary embodiment of the inventive concept, ​ and ​ is an enlarged view showing the region “Aa” in ​ , and ​ is an enlarged view showing the region “Ba” in ​ .

[0248] With reference to ​ , ​ , ​ and ​ , in the above-described semiconductor device CH, the second upper gate electrode described with reference to ​ may not be provided ( ​ and ​ in GE_Ub). Accordingly, the above-described first upper gate electrode ( ​ in GE_Ua) may be referred to as the upper gate electrode GE_U'. Accordingly, the upper gate electrode GE_U' may have a gate pad G_P1' substantially the same as the above-described gate pad ( ​ in G_P1a).

[0249] In an exemplary embodiment of the inventive concept, the second upper gate electrode ( ​ and​ GE_Ub) in the above, and the upper gate electrode GE_U' may include a select gate electrode and an erase control gate electrode. The select gate electrode may be the string select gate line of the above-described string select transistor, and the erase control gate electrode may be the erase control gate line of the above-described erase control transistor. For example, among the upper gate electrodes GE_U', the topmost gate electrode and the second-highest gate electrode may be the erase control gate electrodes that can serve as the erase control gate lines of the above-described erase control transistors, and the gate electrode below the erase control gate electrode may be the select gate electrode that can serve as the string select gate line of the above-described string select transistor.

[0250] The above-described vertical memory structure ( ​ and 6A VS) in may be replaced with a vertical memory structure VS' as shown in ​ and ​ For example, in the vertical memory structure ( ​ and ​ VS), the second vertical memory structure VS_U and the connection structure VS_C may not be provided. Therefore, the cross-sectional structure of the vertical memory structure VS' may be substantially the same as the cross-sectional structure of the first vertical memory structure VS_1 in ​ The previously described bit line pillar BLP may be connected to the first pad pattern 118 of the vertical memory structure VS'.

[0251] ​ is a cross-sectional view showing a region taken along the line I-I' in a semiconductor device according to an exemplary embodiment of the inventive concept. ​ in

[0252] In a modified example, referring to ​ and ​ , the gate pads ( ​ G_P2a1 in ​ G_P2a2 in ​ G_P2b1 in ​ G_P2b2 in ​ ) of the second intermediate gate electrode GE_Mb, the first intermediate gate electrode GE_Ma, and the lower gate electrode GE_L provided in the second connection region R1b may be replaced with gate pads GP_2b' and GP_2a' arranged in a stepped shape as shown in

[0253] The above-described first lower insulating cover pattern ( ​ INS_C1c in ​ INS_C1b in ​The lower insulating cover pattern INS_C3a of the gate pad GP_2a' covering the first intermediate gate electrode GE_Ma and the lower gate electrode GE_L as shown.

[0254] The above-mentioned first upper insulating cover pattern ( ​ INS_C2c in) and the second upper insulating cover pattern ( ​ INS_C2b in) can be modified into the upper insulating cover pattern INS_C3b of the gate pad GP_2b' covering the second intermediate gate electrode GE_Mb.

[0255] The upper insulating cover pattern INS_C3b can be disposed on the lower insulating cover pattern INS_C3a and can be in contact with the lower insulating cover pattern INS_C3a.

[0256] The connection plug portion 160P of the above-mentioned second gate contact plug 160b can be arranged according to the arrangement shapes of the gate pads GP_2b' and GP_2a'. Therefore, the connection plug portion 160P of the second gate contact plug 160b can be arranged to sequentially decrease in the +X direction.

[0257] ​ is a cross-sectional view showing a region taken along the line I-I' in the semiconductor device showing an exemplary embodiment according to the inventive concept. ​ in.

[0258] Referring to ​ and ​ , the second intermediate gate electrode GE_Mb, the first intermediate gate electrode GE_Ma, and the lower gate electrode GE_L provided in the second connection region R1b can have gate pads GP_2bb and GP_2aa, and the gate pads GP_2bb and GP_2aa are arranged to sequentially decrease in the +X direction as the gate pads GP_2bb and GP_2aa are further provided. The first upper gate electrode GE_Ua can have a gate pad GP_1 arranged in a stepped shape similar to the above-mentioned gate pad ( ​ G_P1a in), and this stepped shape decreases in the -X direction as the gate pad GP_1 is further provided.

[0259] The above-mentioned gate contact plug ( ​The 160) in can be modified into a gate contact plug 260, and the gate contact plug 260 does not penetrate the gate electrode disposed at a height lower than the height of the gate pad in the vertical direction Z. The gate contact plug 260 may have a lower surface in contact with the gate pad. For example, the above-described first gate contact plug 160a may be modified into a first gate contact plug 260a disposed on the gate pad GP_1 of the first upper gate electrode GE_Ua, and the above-described second gate contact plug 160b may be modified into a second gate contact plug 260b disposed on the gate pads GP_2bb and GP_2aa of the second intermediate gate electrode GE_Mb, the first intermediate gate electrode GE_Ma, and the lower gate electrode GE_L.

[0260] ​ is a cross-sectional view showing a region taken along line I-I' of a semiconductor device according to an exemplary embodiment of the inventive concept, and ​ the cross-sectional view shows a region taken along line I-I' of the semiconductor device, and ​ is a view showing ​ an enlarged view of the region "Ab" in.

[0261] In the modification example, referring to ​ 、 ​ and ​ , the above-described first structure ST1 and second structure ST2 may be modified into a first structure ST1a and a second structure ST2a as shown in ​ and ​ .

[0262] The second structure ST2a may be disposed below the first structure ST1a.

[0263] The second structure ST2a may include a substrate 206', a peripheral active region 209a' on the substrate 206', a peripheral device isolation region 209s' defining the peripheral active region 209a' on the substrate 206', a peripheral device PTR on the substrate 206', an upper wiring line structure 220', and a second insulating structure (also referred to as an upper insulating structure) 230'. As described above, the peripheral device PTR may include a peripheral transistor, and the peripheral transistor may include peripheral source / drain regions PTR_S / D spaced apart from each other in the peripheral active region 209a', a peripheral channel region PTR_CH between the peripheral source / drain regions PTR_S / D, and a peripheral gate PTR_G on the peripheral channel region PTR_CH.

[0264] The upper wiring line structure 220' may be buried in the upper insulating structure 230' and may be electrically connected to the peripheral device PTR. The upper wiring line structure 220' may include a horizontal portion and a vertical portion. The upper surface of the upper insulating structure 230' may be disposed at a height higher than the height of the upper surface of the upper wiring line structure 220'.

[0265] The first structure ST1a may be disposed on the upper insulating structure 230'.

[0266] The first structure ST1a may include a plate pattern 306 and an insulating pattern 309 on a side surface of the plate pattern 306. The first structure ST1a may include a stacked structure GS substantially the same as the above example. For example, the first structure ST1a may include a gate electrode GE and interlayer insulating layers ILDa and ILDb as in one of the above example embodiments. Gate electrodes GE_L, GE_M, GE_Ua, and GE_Ub may be disposed on the plate pattern 306 and the insulating pattern 309. Accordingly, the gate electrodes GE_L, GE_M, GE_Ua, and GE_Ub may have gate pads according to one of the above example embodiments.

[0267] The above vertical memory structure VS may be modified to a vertical memory structure VS'' as shown in ​ . Accordingly, the first structure ST1a may include the vertical memory structure VS''.

[0268] The vertical memory structure VS'' may include a first vertical memory structure VS_L' whose lower region is modified from the above first vertical memory structure VS_L. Accordingly, the vertical memory structure VS'' may include the first vertical memory structure VS_L' and the above second vertical memory structure VS_U and a connection structure VS_C.

[0269] The plate pattern 306 may include a first layer 306a, a second layer 306b disposed on the first layer 306a, and a third layer 306c disposed on the second layer 306b. At least one of the first to third layers 306a, 306b, and 306c may include, for example, polysilicon. For example, the second layer 306b may include a polysilicon layer having N-type conductivity.

[0270] As described above, the first vertical memory structure VS_L' may include an insulating core region 116, a channel layer 114 covering side and lower surfaces of the insulating core region 116, and a data storage structure 112 disposed on an outer surface of the channel layer 114. The first vertical memory structure VS_L' may further include a dummy data storage structure 112' covering a lower surface of the channel layer 114 and side surfaces of a lower region of the channel layer 114. The dummy data storage structure 112' may be formed of a material layer same as the material layer of the data storage structure 112. The channel layer 114 may be spaced apart from the first layer 306a by the dummy data storage structure 112'.

[0271] The second layer 306b may pass between the data storage structure 112 and the dummy data storage structure 112' and may be in contact with the channel layer 114.

[0272] The first structure ST1a may include a gate contact plug 360 configured to be electrically connected to gate pads of a lower gate electrode GE_L, an intermediate gate electrode GE_M, and a first upper gate electrode GE_Ua. The first structure ST1a may further include an upper gate contact plug 163 configured to be electrically connected to a gate pad of a second upper gate electrode GE_Ub and an upper gate connection line 169' disposed on the upper gate contact plug 163.

[0273] The gate contact plug 360 may be configured to be electrically connected to an upper wiring line structure 220'. For example, the gate contact plug 360 may extend downward from a gate contact plug 160 as shown in ​ and ​ and may penetrate an insulating pattern 309, and may be electrically connected to a pad portion of the upper wiring line structure 220'. Accordingly, the gate contact plug 360 may have a shape extending downward from the shape of the gate contact plug 160 as shown in ​ and ​ .

[0274] ​ is a diagram showing a semiconductor device according to an exemplary embodiment of the inventive concept. For example, ​ the diagram of ​ may be a modified example of the exemplary embodiment in ​ is a cross-sectional view showing a region taken along line I-I' of a semiconductor device according to an exemplary embodiment of the inventive concept. ​ in

[0275] In the modified example, among ​ and ​ , referring to Figure 13 , Figure 3A the first upper gate line UL1a of the first memory cluster MAT1 described in Figure 3A may be modified to a first upper gate line UL1a' having a gate pad P1b in a first connection region R1a and a gate pad P1a in a second connection region R1b.

[0276] The third upper gate line UL2a of the second memory cluster MAT2 described in

[0276] may be modified to a third upper gate line UL2a' having a gate pad P2a in a third connection region R2b and a gate pad P2b in a fourth connection region R2a.Therefore, voltage can be applied to the first upper gate line UL1a' in the +X direction and -X direction through the wiring line structure 1115b1 electrically connected to the gate pad P1b in the first connection region R1a and the wiring line structure 1115a1 electrically connected to the gate pad P1a in the second connection region R1b. And voltage can be applied to the third upper gate line UL2a' in the +X direction and -X direction through the wiring line structure 1115a2 electrically connected to the gate pad P2a in the third connection region R2b and the wiring line structure 1115b2 electrically connected to the gate pad P2b in the fourth connection region R2a. Therefore, since voltage can be applied to the entire first upper gate line UL1a' and the third upper gate line UL2a' more rapidly, the performance of the transistor including the first upper gate line UL1a' and the third upper gate line UL2a' as the gate electrode can be improved. Refer to Figure 13 and Figure 14 among Figure 14 , the above-mentioned first upper gate electrode ( Figure 5 GE_Ua in) can be modified to the first upper gate electrode GE_Ua' having gate pads on both sides as shown in Figure 14 . For example, the first upper gate electrode GE_Ua' can have a first side gate pad G_P1a disposed in the first connection region R1a and a second side gate pad G_P1a' disposed in the second connection region R1b. The first side gate pad G_P1a can be arranged in a stepped shape that sequentially decreases in the -X direction as the first side gate pad G_P1a is further arranged. The second side gate pad G_P1a' can be arranged in a stepped shape that sequentially decreases in the +X direction as the second side gate pad G_P1a' is further arranged. The first upper gate electrode GE_Ua' can correspond to Figure 13 the first upper gate line UL1a' described in. In Figure 14 , regions "A", "B", "C", and "D" can be substantially the same as the amplification parts in the above-mentioned Figure 6A , Figure 6B , Figure 6C and Figure 6D .

[0277] The above-mentioned gate contact plug 160 can further include a third gate contact plug 160c connected to the second side gate pad G_P1a' of the first upper gate electrode GE_Ua'. Therefore, voltage can be applied to the first upper gate electrode GE_Ua' through the first gate contact plug 160a electrically connected to the first side gate pad G_P1a disposed in the first connection region R1a and the third gate contact plug 160c electrically connected to the second side gate pad G_P1a' disposed in the second connection region R1b. The first upper gate electrode GE_Ua' can be the same as the first upper gate line ( Figure 13corresponds to UL1a' in []. Therefore, the performance of a transistor including the first upper gate electrode GE_Ua' as a gate electrode can be improved.

[0278] Figure 15 is a diagram showing a semiconductor device according to an exemplary embodiment of the inventive concept. For example, Figure 15 The diagram of [] can be a modified example of the exemplary embodiment in the above [] Figure 3A In the modified example, referring to []

[0279] In the modified example, referring to [] Figure 15 , Figure 3A the second upper gate line UL1b of the first memory cluster MAT1 shown in [] can be modified to a second upper gate line UL1b' having a gate pad P1a disposed in the second connection region R1b. Figure 3A the fourth upper gate line UL2b of the second memory cluster MAT2 described in [] can be modified to a fourth upper gate line UL2b' having a gate pad P2a disposed in the third connection region R2b.

[0280] Therefore, a voltage can be applied to the second upper gate line UL1b' in the -X direction through a wiring line structure 1115a1 electrically connected to the gate pad P1a in the second connection region R1b, and a voltage can be applied to the fourth upper gate line UL2b' in the +X direction through a wiring line structure 1115a2 electrically connected to the gate pad P2a in the third connection region R2b. Therefore, the directions in which the voltage is applied to the first upper gate line UL1a and the second upper gate line UL1b' can be different, and the directions in which the voltage is applied to the third upper gate line UL2a and the fourth upper gate line UL2b' can be different. The above-described second upper gate electrode ( Figure 5 GE_Ub in []) corresponding to the second upper gate line UL1b' can be modified to a second upper gate electrode having a gate pad disposed in the second connection region R1b.

[0281] Figure 16 is a diagram showing a semiconductor device according to an exemplary embodiment of the inventive concept. For example, Figure 16 The diagram of [] can be a modified example of the exemplary embodiment in the above [] Figure 3A and Figure 17 is a cross-sectional view showing a region taken along the line I-I' of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 4 in [].

[0282] In the modified example, referring to [] Figure 16 and Figure 17 among [] Figure 16 , Figure 3AThe first upper gate line UL1a and the second upper gate line UL1b described in [reference] can be modified to the first upper gate line UL1a' and the second upper gate line UL1b' having a gate pad P1b in the first connection region R1a and a gate pad P1a in the second connection region R1b. Figure 3A The third upper gate line UL2a and the fourth upper gate line UL2b of the second memory bank MAT2 described in [reference] can be modified to the third upper gate line UL2a' and the fourth upper gate line UL2b' having a gate pad P2a in the third connection region R2b and a gate pad P2b in the fourth connection region R2a.

[0283] Therefore, voltage can be applied to the first upper gate line UL1a' and the second upper gate line UL1b' in the +X direction and -X direction through the wiring line structures 1115a1 and 1115b1 electrically connected to the gate pad P1b in the first connection region R1a and the gate pad P1a in the second connection region R1b respectively, and voltage can be applied to the third upper gate line UL2a' and the fourth upper gate line UL2b' in the +X direction and -X direction through the wiring line structures 1115a2 and 1115b2 electrically connected to the gate pad P2a in the third connection region R2b and the gate pad P2b in the fourth connection region R2a respectively.

[0284] Referring to Figure 17 and Figure 16 , as described in Figure 14 , the first upper gate electrode GE_Ua' can have a first side gate pad G_P1a in the first connection region R1a and a second side gate pad G_P1a' in the second connection region R1b. Figure 14 The second upper gate electrode GE_Ub in [reference] can be modified to the second upper gate electrode GE_Ub' having a first side gate pad G_P1b disposed in the first connection region R1a and a second side gate pad G_P1b' disposed in the second connection region R1b.

[0285] Voltage can be applied to both sides of the second upper gate electrode GE_Ub' through the first upper gate contact plug 163 disposed on the first side gate pad G_P1b and the second upper gate contact plug 163' disposed on the second side gate pad G_P1b', where the first side gate pad G_P1b is disposed in the first connection region R1a and the second side gate pad G_P1b' is disposed in the second connection region R1b.

[0286] The first side gate pads G_P1a and G_P1b disposed in the first connection region R1a may be arranged in a stepped structure that sequentially decreases in the -X direction as the first side gate pads G_P1a and G_P1b are further arranged. The second side gate pads G_P1a' and G_P1b' disposed in the second connection region R1b may be arranged in a stepped structure that sequentially decreases in the +X direction as the second side gate pads G_P1a' and G_P1b' are further arranged.

[0287] The first upper gate electrode GE_Ua' may correspond to the first upper gate line ( Figure 16 UL1a' in), and the second upper gate electrode GE_Ub' may correspond to the second upper gate line ( Figure 16 UL1b' in). Accordingly, the performance of a transistor including the first upper gate electrode GE_Ua' and the second upper gate electrode GE_Ub' as gate electrodes may be improved.

[0288] Figure 18 is a diagram showing a semiconductor device according to an exemplary embodiment of the present inventive concept. For example, Figure 18 The diagram of may be a modified example of the exemplary embodiment in the above Figure 3A above. Figure 19 is a cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present inventive concept, showing a region taken along the line I-I' in Figure 4 above.

[0289] In the modified example, with reference to Figure 18 and Figure 19 among Figure 18 above, the above-described first word line ( Figure 3A WL1 in) may be modified to a first lower word line WL1_L having a gate pad P1a disposed in the second connection region R1b and a first upper word line WL1_U having a gate pad P1b disposed in the first connection region R1a. For example, the above-described first word line ( Figure 3A WL1 in) may be modified to a first word line WL1' including the first lower word line WL1_L and the first upper word line WL1_U. The first upper word line WL1_U may be disposed at a height higher than the height of the first lower word line WL1_L.

[0290] Voltage may be applied to the first lower word line WL1_L in the -X direction from the second connection region R1b toward the first memory cell array region M1, and voltage may be applied to the first upper word line WL1_U in the +X direction from the first connection region R1a to the first memory cell array region M1.

[0291] The above-described second word line ( Figure 3AThe WL2) in can be modified to have a second lower word line WL2_L with a gate pad P2a disposed in the third connection region R2b and a second upper word line WL2_U with a gate pad P2b disposed in the fourth connection region R2a. For example, the above-described second word line ( Figure 3A The WL2) in can be modified to a second word line WL2' including a second lower word line WL2_L and a second upper word line WL2_U.

[0292] A voltage can be applied to the second lower word line WL2_L in the +X direction from the third connection region R2b toward the second memory cell array region M2, and a voltage can be applied to the second upper word line WL2_U in the -X direction from the fourth connection region R2a to the second memory cell array region M2.

[0293] Referring to Figure 19 and Figure 18 , as described above, the first intermediate gate electrode GE_Ma can have gate pads G_P2a1 and G_P2a2 disposed in the second connection region R1b as described above.

[0294] The above-described second intermediate gate electrode GE_Mb can be modified to a second intermediate gate electrode GE_Mb', the second intermediate gate electrode GE_Mb' including a 2-1 intermediate gate electrode GE_Mb_L having a gate pad G_P2b1 disposed in the second connection region R1b and a 2-2 intermediate gate electrode GE_Mb_U having a gate pad G_P1aa disposed in the first connection region R1a.

[0295] The 2-2 intermediate gate electrode GE_Mb_U and the first upper gate electrode GE_Ua can have gate pads G_P1aa arranged in a stepped shape that sequentially decreases in the -X direction as the gate pad G_P1aa is further arranged. The gate pad G_P1aa can be electrically connected to the first gate contact plug 160a.

[0296] In an exemplary embodiment of the inventive concept, the first intermediate gate electrode GE_Ma and the 2-1 intermediate gate electrode GE_Mb_L can be or correspond to Figure 18 the first lower word line WL1_L described in, and the 2-2 intermediate gate electrode GE_Mb_U can be or correspond to Figure 18 the first upper word line WL1_U described in.

[0297] Figure 20 is a diagram showing a semiconductor device according to an exemplary embodiment of the inventive concept. For example, Figure 20 the diagram of can be a modified example of the exemplary embodiment described above in Figure 3A . Figure 21 is a diagram showing a semiconductor device according to an exemplary embodiment of the inventive concept. For example,Figure 21 The graph can be the above Figure 4 A modified example of the exemplary embodiment in . Figure 22 It is shown Figure 5 A modified example of the cross-sectional structure is shown along Figure 21 A cross-sectional view of the area taken along line Ia-Ia'.

[0298] In the modified example, refer to Figure 20 , Figure 21 and Figure 22 Among Figure 20 , the first connection region R1a may be modified to a first connection region R1aa having an increased width in the +X direction, and the second connection region R1b may be modified to a second connection region R1bb having a decreased width in the +X direction. In addition, the third connection region R2b may be modified to a third connection region R2bb having a decreased width in the +X direction, and the fourth connection region R2a may be modified to a fourth connection region R2aa having an increased width in the +X direction. In the +X direction, the width of each of the first connection region R1aa and the fourth connection region R2aa may be greater than the width of each of the second connection region R1bb and the third connection region R2bb.

[0299] Figure 3A The first and second lower gate lines LL1a and LL1b described in the accompanying drawings may be modified into first and second lower gate lines LL1a'' and LL1b'' having gate pads P1aa disposed in the first connection region R1aa.

[0300] Figure 3A The first word line WL1 described in may be modified into a first word line WL1 ″ having a gate pad P1aa disposed in the first connection region R1aa.

[0301] Figure 3A The first and second upper gate lines UL1a and UL1b described in 3D may be modified into first and second upper gate lines UL1a'' and UL1b'' having gate pads P1bb disposed in the second connection region R1bb.

[0302] Figure 3A The third and fourth lower gate lines LL2a and LL2b described in the accompanying drawings may be modified into third and fourth lower gate lines LL2a'' and LL2b'' having the gate pad P2aa disposed in the fourth connection region R2aa.

[0303] Figure 3A The second word line WL2 described in can be modified to a second word line WL2'', and the second word line WL2'' has a gate pad P2aa disposed in the fourth connection region R2aa.

[0304] Figure 3A The third upper gate line UL2a and the fourth upper gate line UL2b described in can be modified to a third upper gate line UL2a'' and a fourth upper gate line UL2b'', and the third upper gate line UL2a'' and the fourth upper gate line UL2b'' have a gate pad P2bb disposed in the third connection region R2bb.

[0305] Referring to Figure 21 and Figure 22 as well as Figure 20 , the above-described first connection region R1a can be modified to a first connection region R1aa having an increased width in the +X direction. In addition, the above-described second connection region R1b can be modified to a second connection region R1bb having a decreased width in the +X direction, and the above-described third connection region R2b can be modified to a third connection region R2bb having a decreased width in the +X direction. In addition, the above-described fourth connection region R2a can be modified to a fourth connection region R2aa having an increased width in the +X direction.

[0306] In the +X direction, the width of each of the first connection region R1aa and the fourth connection region R2aa can be greater than the width of each of the second connection region R1bb and the third connection region R2bb.

[0307] In an exemplary embodiment of the inventive concept, referring to Figure 21 and Figure 22 , the cross-sectional structure of the second memory cluster MAT2 in the +X direction can be substantially the same as the cross-sectional structure in Figure 5 . Figure 22 The cross-sectional structure in Figure 5 can be substantially the same as a structure that is mirror-symmetric with the cross-sectional structure in

[0308] in the +X direction or -X direction. Accordingly, in the first memory cluster MAT1, the gate pads of the lower gate electrode GE_L and the middle gate electrode GE_M can be disposed in the first connection region R1aa, and the gate pads of the first upper gate electrode GE_Ua and the second upper gate electrode GE_Ub can be disposed in the second connection region R1bb. Figure 21 In Figure 20 , the lower gate electrode GE_L can correspond to the first lower gate line LL1a'' and the second lower gate line LL1b'' in Figure 20The first word line WL1 '' corresponds to the first word line WL1 '', and the first upper gate electrode GE_Ua and the second upper gate electrode GE_Ub can be connected to Figure 20 The first upper gate line UL1a'' corresponds to the second upper gate line UL1b''.

[0309] exist Figure 22 In the example, region "Ca" can have Figure 6C The enlarged view of the part in is modified to be the same structure as the structure formed by mirror symmetry in the +X direction, and the area "Da" can have the same structure as that formed by Figure 6D The enlarged view of the portion in FIG. 1 is modified to have the same structure as that formed by mirror symmetry in the +X direction.

[0310] The first outer cover insulating structure ( Figure 6B INS_C1a in the second external cover insulation structure ( Figure 6B The INS_C2a in FIG. 1 may be modified into a first cover insulating structure INS_C1a′ and a second cover insulating structure INS_C2a′ disposed between the first memory cluster MAT1 and the second memory cluster MAT2.

[0311] In the following, reference will be made to Figure 23 An example of a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts is described. Figure 23 is a flowchart illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts.

[0312] Reference Figure 23 , a lower mold structure may be formed (S10). The lower mold structure may include first interlayer insulating layers and first sacrificial gate layers that are alternately stacked. By patterning the lower mold structure, a first lower stepped shape may be formed in the intermediate connection region (S20).

[0313] The intermediate connection region may be the second connection region R1b and the third connection region R2b described above.

[0314] The first lower stepped shape may be the lower gate electrode and the first intermediate gate electrode ( Figure 6C and Figure 6D The gate pads (GE_L and GE_Ma) of Figure 6C G_P2a2 and Figure 6D The step shape of G_P2a1 in .

[0315] An upper mold structure may be formed (S30). The upper mold structure may include second interlayer insulating layers and second sacrificial gate layers alternately stacked with each other. By patterning the upper mold structure, an upper step shape may be formed in the external connection region (S40).

[0316] The external connection regions may be the first connection region R1a and the fourth connection region R2a described above.

[0317] The upper step shape may be the step shape of the gate pad ( Figure 6B G_P1a in

[0318] of the first upper gate electrode GE_Ua described in the above exemplary embodiment).

[0319] By patterning the upper molding structure, a second lower step shape (S50) may be formed in the intermediate connection region. Figure 6C and Figure 6D The second lower step shape may be the gate pads ( Figure 6C G_P2b2 in Figure 6D and

[0320] G_P2b1 in

[0321] of the second intermediate gate electrode ( Figure 7 and Figure 8A described in the above exemplary embodiment). Figure 7 and Figure 8A VS' in

[0322] In another example, when the vertical memory structure is the vertical memory structure as in Figure 5 and Figure 6A described in Figure 5 and Figure 6A the steps of forming the vertical memory structure may include: forming a first vertical memory structure ( Figure 6A VS_L in Figure 5 and Figures 6A to 6D that penetrates the lower molding structure and the upper molding structure); and forming a buffer insulating layer ( Figure 5 and Figures 6A to 6D 120 in Figure 6A and Figure 6A on the upper molding structure). The steps of forming the vertical memory structure may further include: forming a connection structure ( Figure 5 and Figures 6A to 6D VS_C in Figure 5 and Figure 6A that penetrates the buffer insulating layer ( Figure 5 and Figure 6AThe second vertical memory structure of GE_Ub) in Figure 6A VS_U) in

[0323] The sacrificial gate layer (S70) in the lower molding structure and the upper molding structure can be replaced with a gate electrode.

[0324] The gate electrode can be, for example, Figure 7 , Figure 8A and Figure 8B The lower gate electrode GE_L, the middle gate electrode GE_M, and the upper gate electrode GE_U' in Figure 5 and Figures 6A to 6D The lower gate electrode GE_L, the middle gate electrode GE_M, and the first upper gate electrode GE_Ua in Figure 7 , Figure 8A and Figure 8B The lower gate electrode GE_L, the middle gate electrode GE_M, and the upper gate electrode GE_U' in Figure 5 and Figures 6A to 6D The lower gate electrode GE_L, the middle gate electrode GE_M, and the first upper gate electrode GE_Ua in Figure 7 , Figure 8A and Figure 8B The steps of forming the lower gate electrode GE_L, the middle gate electrode GE_M, and the upper gate electrode GE_U' in Figure 5 and Figures 6A to 6D The lower gate electrode GE_L, the middle gate electrode GE_M, and the first upper gate electrode GE_Ua in Figure 7 , Figure 8A and Figure 8B GE_L, GE_M, and GE_U' in Figure 5 and Figures 6A to 6D GE_L, GE_M, and GE_Ua in Figure 4 SP) in

[0325] When the gate electrode is the lower gate electrode GE_L, the middle gate electrode GE_M, and the first upper gate electrode GE_Ua in Figure 5 and Figures 6A to 6D After forming the lower gate electrode GE_L, the middle gate electrode GE_M, and the first upper gate electrode GE_Ua, the above-mentioned buffer insulating layer ( Figure 5 and Figures 6A to 6D 120) in Figure 6A VS_C) in Figure 5 andFigure 6A the GE_Ub in) and the second vertical memory structure ( Figure 6A the VS_U in).

[0326] A gate contact plug (S80) that can be electrically connected to the gate pad of the gate electrode can be formed. The gate contact plug can be the gate contact plug 160 described in the above exemplary embodiment.

[0327] Hereinafter, reference will be made to Figure 24 an example of a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept will be described. Figure 24 is a flowchart showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0328] Referring to Figure 24 , a molding structure (S110) can be formed. The molding structure can include an interlayer insulating layer and a sacrificial gate layer that are alternately stacked with each other. By patterning the molding structure, an upper stepped shape can be formed in the external connection region (S120).

[0329] The external connection region can be the first connection region R1a and the fourth connection region R2a described above. The upper stepped shape can be the stepped shape of the gate pad of the first upper gate electrode ( Figure 9 and Figure 10 the GE_Ua in).

[0330] By patterning the molding structure, a lower stepped shape can be formed in the intermediate connection region (S130).

[0331] The intermediate connection region can be the second connection region R1b and the third connection region R2b described above.

[0332] The lower stepped shape can be the stepped shape of the gate pads of the lower gate electrode and the first intermediate gate electrode ( Figure 9 and Figure 10 the GE_L and GE_Ma in) ( Figure 9 the G_P2a' and G_P2b' in and Figure 10 the G_P2aa and G_P2bb in).

[0333] In an embodiment of the inventive concept, by patterning the molding structure, a second lower stepped shape can also be formed in the intermediate connection region.

[0334] The second lower stepped shape can be the stepped shape of the gate pad of the second intermediate gate electrode ( Figure 9 and Figure 10 the GE_Mb in) ( Figure 9 the G_P2b' in and Figure 10 the GP_2bb in).

[0335] By the same process as in Figure 23 a vertical memory structure (S140) penetrating the molded structure can be formed.

[0336] By the same process as in Figure 23 the sacrificial gate layer in the molded structure can be replaced with a gate electrode (S150).

[0337] By the same process as in Figure 23 a gate contact plug (S160) electrically connected to the gate pad of the gate electrode can be formed.

[0338] According to the above exemplary embodiments of the inventive concept, a semiconductor device and a data storage system including the semiconductor device can be provided. The semiconductor device includes connection regions provided on both sides of a memory cell array region, in which gate pads are disposed. By providing connection regions on both sides of the memory cell array region, the space for disposing the gate pads can be reduced and optimized, thereby increasing the integration degree of the semiconductor device.

[0339] In addition, by providing a first connection region in which a gate pad provided with an upper gate electrode is disposed on one side of the memory cell array region, and a second connection region in which a gate pad provided with a word line is disposed on the other side of the memory cell array region, a peripheral circuit electrically connected to the upper gate electrode and the word line can be effectively provided, and the distance between the upper gate electrode and the word line and the peripheral circuit can be reduced, thereby increasing the signal transmission speed. Accordingly, the performance of the semiconductor device can be improved.

[0340] Although the inventive concept has been described with reference to embodiments of the inventive concept, those of ordinary skill in the art will understand that various changes in form and detail can be made thereto without departing from the spirit and scope of the inventive concept.

Claims

1. A semiconductor device comprising: a first structure having a first side surface and a second side surface facing away from each other and including a first memory block and a second memory block sequentially arranged in a first direction from the first side surface to the second side surface; as well as a second structure including a peripheral circuit and stacked with the first structure, wherein the first memory block has a first connection region, a first memory cell array region, and a second connection region sequentially arranged in a first direction, wherein the second memory block has a third connection region, a second memory cell array region, and a fourth connection region sequentially arranged in the first direction, wherein the first memory block includes first gate electrodes that are spaced apart from each other and extend from the first connection region to the second connection region, wherein the second memory block includes second gate electrodes that are spaced apart from each other and extend from the third connection region to the fourth connection region, wherein the first gate electrode of the first memory block includes a first word line and a first upper gate line, the first word line has a first word line pad disposed in the second connection region, the first upper gate line has a first upper gate pad disposed in the first connection region and is disposed on the first word line, wherein the second gate electrode of the second memory block includes a second word line and a second upper gate line, the second word line has a second word line pad disposed in the third connection region, the second upper gate line has a second upper gate pad disposed in the fourth connection region and is disposed on the second word line, and The first structure includes a first word line contact plug connected to the first word line pad, a first upper gate contact plug connected to the first upper gate pad, a second word line contact plug connected to the second word line pad, and a second upper gate contact plug connected to the second upper gate pad.

2. The semiconductor device according to claim 1, wherein A first word line contact plug penetrates the first word line pad and contacts the first word line pad, wherein the first upper gate contact plug penetrates the first upper gate pad and contacts the first upper gate pad, wherein the second word line contact plug penetrates the second word line pad and contacts the second word line pad, and The second upper gate contact plug penetrates the second upper gate pad and contacts the second upper gate pad.

3. The semiconductor device according to claim 1, wherein The first upper gate line also has a first inner upper gate pad disposed in the second connection region, The second upper gate line further has a second inner upper gate pad disposed in the third connection region. The first structure further includes a first inner upper gate contact plug connected to the first inner upper gate pad and a second inner upper gate contact plug connected to the second inner upper gate pad.

4. The semiconductor device according to claim 1, wherein The first gate electrode further includes a third upper gate line disposed on the first upper gate line, Wherein, the second gate electrode further includes a fourth upper gate line arranged on the second upper gate line, The first structure further includes a third upper gate contact plug connected to the third upper gate line and a fourth upper gate contact plug connected to the fourth upper gate line.

5. The semiconductor device according to claim 4, wherein: The third upper gate line includes a third upper gate pad disposed in the first connection region and in contact with the third upper gate contact plug, The fourth upper gate line includes a fourth upper gate pad disposed in the fourth connection region and in contact with the fourth upper gate contact plug, and The third upper gate contact plug is connected to the third upper gate pad, and the fourth upper gate contact plug is connected to the fourth upper gate pad.

6. The semiconductor device according to claim 4, wherein: The third upper gate line includes a third upper gate pad disposed in the second connection region and in contact with the third upper gate contact plug, and The fourth upper gate line includes a fourth upper gate pad disposed in the third connection region and in contact with the fourth upper gate contact plug.

7. The semiconductor device according to claim 4, wherein: Each of the first word line and the second word line has a first thickness, and Wherein, each of the first upper gate electrode and the second upper gate electrode has a second thickness greater than the first thickness.

8. The semiconductor device according to claim 7, wherein: Each of the third upper gate electrode and the fourth upper gate electrode has a third thickness greater than the second thickness.

9. The semiconductor device according to claim 1, wherein: The first gate electrode further includes: a third word line disposed at a height higher than that of the first word line and at a height lower than that of the first upper gate line, The second gate electrode further includes: a fourth word line, which is arranged at a height higher than that of the second word line and at a height lower than that of the second upper gate line, The third word line has a third word line pad disposed in the first connection region, wherein the fourth word line has a fourth word line pad disposed in the fourth connection region, and The first structure further includes a third word line contact plug connected to the third word line pad and a fourth word line contact plug connected to the fourth word line pad.

10. The semiconductor device according to claim 1, wherein The first gate electrode of the first memory block further includes a first lower gate line disposed at a height lower than that of the first word line, wherein the second gate electrode of the second memory block further includes a second lower gate line disposed at a height lower than that of the second word line, wherein the first lower gate line has a first lower gate pad disposed in the second connection region, wherein the second lower gate line has a second lower gate pad disposed in the third connection region, and The first structure further includes a first lower gate contact plug connected to the first lower gate pad and a second lower gate contact plug connected to the second lower gate pad.

11. The semiconductor device according to claim 1, further comprising: A cover insulating structure is provided between the first memory block and the second memory block, wherein a portion of the cover insulating structure covers the first word line pad, and The first word line contact plug penetrates a portion of the capping insulating structure and contacts the first word line pad.

12. A semiconductor device comprising: a first structure having a first side surface and a second side surface facing away from each other, and comprising a first connection region, a first memory cell array region, a second connection region, a third connection region, a second memory cell array region, and a fourth connection region arranged sequentially in a first direction from the first side surface toward the second side surface; as well as a second structure including a peripheral circuit and stacked with the first structure, The first structure includes: a first side conductive layer, which is arranged in a first connection area, a first memory cell array area, and a second connection area; a first vertical memory structure, which penetrates the first side conductive layer in the first memory cell array area; a second side conductive layer, which is arranged in a third connection area, a second memory cell array area, and a fourth connection area; and a second vertical memory structure, which penetrates the second side conductive layer in the second memory cell array area. wherein the first side conductive layer includes a first lower conductive group and a first upper conductive group, the first lower conductive group having a first lower pad arranged in a step shape in the second connection region, the first upper conductive group being disposed at a height higher than that of the first lower conductive group and having a first upper pad arranged in a step shape in the first connection region, Wherein, the second side conductive layer includes a second lower conductive group and a second upper conductive group, the second lower conductive group is set at the same height as the first lower conductive group and has a second lower pad arranged in a step shape in the third connection area, and the second upper conductive group is set at the same height as the first upper conductive group and has a second upper pad arranged in a step shape in the fourth connection area.

13. The semiconductor device according to claim 12, wherein: Among the first-side conductive layers, the number of the first-side conductive layers of the first lower conductive group is greater than the number of the first-side conductive layers of the first upper conductive group.

14. The semiconductor device according to claim 12, wherein: Among the first side conductive layers, the first side conductive layer of the first lower conductive group includes a first lower word line and a second lower word line, the first lower word line having a first lower word line pad, the second lower word line being disposed at a height higher than that of the first lower word line and having a second lower word line pad, and The first structure further includes a dummy conductive layer which is arranged at the same height as the second lower word line and vertically overlaps with the first lower word line pad.

15. The semiconductor device according to claim 12, further comprising: a first gate contact plug connected to a corresponding one of the first and second subpads; as well as A second gate contact plug is connected to a corresponding upper pad of the first upper pad and the second upper pad.

16. The semiconductor device according to claim 12, wherein: The thickness of at least one of the first side conductive layers of the first lower conductive group is greater than the thickness of at least one of the first side conductive layers of the first upper conductive group.

17. The semiconductor device according to claim 12, wherein: The first upper conductive group has third upper pads arranged in a step shape in the second connection region, and The second upper conductive group has fourth upper pads arranged in a step shape in the third connection region.

18. A data storage system comprising: A semiconductor device including an input / output pad; as well as a controller electrically connected to the semiconductor device through an input / output pad and controlling the semiconductor device, The semiconductor device includes: a first structure having a first side surface and a second side surface facing away from each other and including a first memory block and a second memory block sequentially arranged in a first direction; and a second structure including a peripheral circuit and overlapping the first structure, wherein the first memory block has a first connection region, a first memory cell array region, and a second connection region sequentially arranged in a first direction, wherein the second memory block has a third connection region, a second memory cell array region, and a fourth connection region sequentially arranged in the first direction, wherein the first memory block includes first gate electrodes that are spaced apart from each other in a vertical direction and extend from the first connection region to the second connection region, wherein the second memory block includes second gate electrodes that are spaced apart from each other in the vertical direction and extend from the third connection region to the fourth connection region, wherein the first gate electrode of the first memory block includes a first word line and a first upper gate line, the first word line has a first word line pad disposed in the second connection region, the first upper gate line has a first upper gate pad disposed in the first connection region and is disposed on the first word line, wherein the second gate electrode of the second memory block includes a second word line and a second upper gate line, the second word line has a second word line pad disposed in the third connection region, the second upper gate line has a second upper gate pad disposed in the fourth connection region and is disposed on the second word line, The first structure includes a first word line contact plug connected to the first word line pad, a first upper gate contact plug connected to the first upper gate pad, a second word line contact plug connected to the second word line pad, and a second upper gate contact plug connected to the second upper gate pad.

19. The data storage system according to claim 18, in, The first upper gate line further includes a first inner upper gate pad disposed in the second connection region, Wherein, the second upper gate line further includes a second inner upper gate pad disposed in the third connection region, and The first structure further includes a first inner upper gate contact plug connected to the first inner upper gate pad and a second inner upper gate contact plug connected to the second inner upper gate pad.

20. The data storage system according to claim 18, wherein: The thickness of each of the first upper gate line and the second upper gate line is greater than the thickness of each of the first word line and the second word line.

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