Display panel and display device

Abstract

The application relates to a display panel and a display device, and relates to the technical field of display. The display panel comprises a pixel circuit, a light-emitting element and a signal line; the signal line comprises a gate reset signal line, an anode reset signal line and a power supply signal line; the gate reset signal line comprises a first gate reset signal line extending along a first direction and a second gate reset signal line extending along a second direction; the first gate reset signal line comprises a plurality of first sub-segments extending along the first direction; the first direction intersects the second direction; the anode reset signal line comprises a first anode reset signal line extending along the first direction and a second anode reset signal line extending along the second direction; wherein the first anode reset signal line comprises a plurality of second sub-segments extending along the first direction; and the power supply signal line comprises a first power supply signal line extending along the first direction and arranged along the second direction. The application can improve display uniformity.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, display products are gradually moving towards higher resolutions. However, higher resolutions lead to a gradual compression of design space, making it impossible to fully accommodate the grid design of some signal lines, resulting in poor display uniformity of display products. Summary of the Invention

[0003] This application provides a display panel and display device that can realize a gridded design of the gate reset signal line and the anode reset signal line, which helps to improve display uniformity.

[0004] In a first aspect, embodiments of this application provide a display panel, including: pixel circuitry, light-emitting elements, and signal lines;

[0005] The pixel circuit includes a driving transistor, a gate reset transistor, and an anode reset transistor; the signal lines include a gate reset signal line, an anode reset signal line, and a power supply signal line; the first terminal of the gate reset transistor is electrically connected to the gate reset signal line, the second terminal of the gate reset transistor is electrically connected to the gate of the driving transistor, the first terminal of the anode reset transistor is electrically connected to the anode reset signal line, the second terminal of the anode reset transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the power supply signal line; wherein...

[0006] The gate reset signal line includes a first gate reset signal line extending along a first direction and a second gate reset signal line extending along a second direction; wherein, the first gate reset signal line includes a plurality of first sub-segments extending along the first direction, and the first sub-segments are electrically connected to the second gate reset signal line; the first direction intersects the second direction;

[0007] The anode reset signal line includes a first anode reset signal line extending along a first direction and a second anode reset signal line extending along a second direction; wherein, the first anode reset signal line includes a plurality of second sub-segments extending along the first direction, and the second sub-segments are electrically connected to the second anode reset signal line;

[0008] The power signal line includes a first power signal line extending in a first direction and arranged in a second direction.

[0009] Secondly, embodiments of this application also provide a display device, which includes the aforementioned display panel.

[0010] The display panel and display device provided in this application embodiment, by setting the gate reset signal line to include a first gate reset signal line and a second gate reset signal line extending in different directions, and setting the first gate reset signal to include a plurality of first segments extending in a first direction and disconnected, and a second gate reset signal line extending in a second direction and connected, and electrically connecting the first segments to the second gate reset signal line, not only realizes the layout design of the gate reset signal line, but also realizes the grid design of the gate reset signal line, which helps to improve the distribution uniformity of the gate reset signal line, thereby improving the uniformity of the gate reset signal in the display panel and helping to improve the display effect of the display panel; in addition, by setting the anode reset signal line to include a first anode reset signal line and a second anode reset signal line extending in different directions, and setting the first anode reset signal to include a plurality of second ..., and electrically connecting the first segments to the second gate reset signal line, not only realizes the layout design of the gate reset signal line, but also realizes the grid design of the gate reset signal line, which helps to improve the distribution uniformity of the The second anode reset signal line extends in two directions and is connected to the second anode reset signal line through a second segment. This not only realizes the layout design of the anode reset signal line, but also the grid design of the anode reset signal line, which helps to improve the distribution uniformity of the anode reset signal line, thereby improving the uniformity of the gate reset signal in the display panel and thus improving the display effect of the display panel. In addition, by setting the power signal line including the first power signal line extending in the first direction and arranged in the second direction, the layout design of the power signal line is realized, which provides support for the display panel to realize the display function. In this way, the layout design of the gate reset signal line, anode reset signal line and power signal line is realized, and the grid design of the gate reset signal line and anode reset signal line is also realized, which helps to improve the wiring uniformity in the display panel, thereby helping to improve the signal uniformity of the display panel, and thus helping to improve the display effect. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0012] Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of this application;

[0013] Figure 3 This application provides a schematic diagram of the structure of a pixel circuit and a light-emitting element according to an embodiment of the present application.

[0014] Figure 4 This is a schematic diagram of the layout structure of a display panel provided in an embodiment of this application;

[0015] Figure 5 This application provides a schematic diagram of the layout structure of a first active layer according to an embodiment of the present application.

[0016] Figure 6This is a schematic diagram of the layout structure of a first conductive layer provided in an embodiment of this application;

[0017] Figure 7 This is a schematic diagram of the layout structure of a second conductive layer provided in an embodiment of this application;

[0018] Figure 8 This is a schematic diagram of the layout structure of a third conductive layer provided in an embodiment of this application;

[0019] Figure 9 A schematic diagram of the layout structure of another display panel provided in an embodiment of this application;

[0020] Figure 10 A schematic diagram of the layout structure of another display panel provided in an embodiment of this application;

[0021] Figure 11 This is a schematic diagram of another layout structure of the first active layer provided in an embodiment of this application;

[0022] Figure 12 This is a schematic diagram of another layout structure of the first conductive layer provided in an embodiment of this application;

[0023] Figure 13 This is a schematic diagram of another layout structure of the second conductive layer provided in an embodiment of this application;

[0024] Figure 14 This is a schematic diagram of another layout structure of the third conductive layer provided in an embodiment of this application;

[0025] Figure 15 A schematic diagram of the layout structure of another display panel provided in an embodiment of this application;

[0026] Figure 16 This is a schematic cross-sectional view of a display panel provided in an embodiment of this application;

[0027] Figure 17 This is a schematic diagram of the structure of another display panel provided in an embodiment of this application;

[0028] Figure 18 This is a schematic diagram of another display panel provided in an embodiment of this application;

[0029] Figure 19 A schematic diagram of the layout structure of another display panel provided in an embodiment of this application;

[0030] Figure 20 A schematic diagram of the layout structure of another display panel provided in an embodiment of this application;

[0031] Figure 21 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] 1. Display panel; 2. Display device; 100. Pixel circuit; 101. First sub-pixel; 102. Second sub-pixel; 103. Third sub-pixel; 011. Buffer layer; 012. First active layer; 013. First gate insulating layer; 014. First conductive layer; 015. Interlayer dielectric layer; 016. Second conductive layer; 017. Second gate insulating layer; 018. Second active layer; 019. Third gate insulating layer; 020. Second gate metal layer; 021. Passivation layer; 022. Third conductive layer; 023. First auxiliary planarization layer; 024. Fourth conductive layer; 025. Second auxiliary planarization layer; 026. Second auxiliary metal layer; 027. Planarization layer; 028. Reflective electrode layer; 029. Light-emitting material layer; 030. Counter electrode layer; 031. Encapsulation layer; 41. First connection portion; 42. Second connection portion. Detailed Implementation

[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0037] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0038] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0039] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0040] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0041] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0042] As described in the background section, display panels in related technologies suffer from poor uniformity. It is understood that a display panel may include signal lines, such as gate reset signal lines, anode reset signal lines, and power signal lines. In some display panels, due to limited space, a grid-like design for the gate reset signal lines, anode reset signal lines, and power signal lines cannot be achieved during layout, resulting in poor uniformity and thus, unevenness in the display panel.

[0043] Based on the aforementioned technical problems, the inventors discovered that by rearranging the signal lines in the display panel, the phenomenon of uneven display can be improved within a limited space. Based on this, the inventors further developed the technical solution of the embodiments of this application. Specifically, the display panel provided in the embodiments of this application includes pixel circuits, light-emitting elements, and signal lines; wherein, the pixel circuit includes a driving transistor, a gate reset transistor, and an anode reset transistor; the signal lines include a gate reset signal line, an anode reset signal line, and a power signal line; the first electrode of the gate reset transistor is electrically connected to the gate reset signal line, the second electrode of the gate reset transistor is electrically connected to the gate of the driving transistor, the first electrode of the anode reset transistor is electrically connected to the anode reset signal line, the second electrode of the anode reset transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the power signal line; the gate reset signal line includes a first electrode along the first direction... The system includes a first gate reset signal line extending in a first direction and a second gate reset signal line extending in a second direction. The first gate reset signal line includes multiple first segments extending in a first direction, and these first segments are electrically connected to the second gate reset signal line. The first and second directions intersect. The anode reset signal line includes a first anode reset signal line extending in a first direction and a second anode reset signal line extending in a second direction. The first anode reset signal line includes multiple second segments extending in the first direction, and these second segments are electrically connected to the second anode reset signal line. The power signal line includes first power signal lines extending in the first direction and arranged in the second direction. This arrangement achieves a reasonable layout of the gate reset signal line, anode reset signal line, and power signal line, and also realizes a gridded design for the gate reset signal line and anode reset signal line, thereby improving display uniformity.

[0044] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0045] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of this application. Figure 3 This is a schematic diagram of a pixel circuit and a light-emitting element provided in an embodiment of this application. (Combined with...) Figures 1 to 3 As shown, the display panel 1 provided in this embodiment includes a pixel circuit 100, a light-emitting element D, and signal lines.

[0046] The signal lines include the gate reset signal line Vref1, the anode reset signal line Vref2, and the power supply signal line PVEE.

[0047] The gate reset signal line Vref1 includes a first gate reset signal line Vref11 extending along a first direction and a second gate reset signal line Vref12 extending along a second direction. The display panel 1 may include multiple first gate reset signal lines Vref11, which can be arranged along the second direction; the display panel 1 may also include multiple second gate reset signal lines Vref12, which can be arranged along the first direction. The gate reset signal line Vref1, including the first gate reset signal line Vref11 and the second gate reset signal line Vref12, is respectively configured to provide a gate reset signal to the pixel circuit 100.

[0048] The first gate reset signal line Vref11 includes a plurality of first segments Vref110 extending along a first direction. The first segments Vref110 are electrically connected to the second gate reset signal line Vref12. Each first segment Vref110 can be electrically connected to at least one second gate reset signal line Vref12. The plurality of first segments Vref110 of the first gate reset signal line Vref11 can be spaced apart. That is, the first gate reset signal line Vref11 can be disconnected along the first direction, including a plurality of discontinuous first segments Vref110; the second gate reset signal line Vref12 can be continuous along a second direction.

[0049] The anode reset signal line Vref2 includes a first anode reset signal line Vref21 extending along a first direction and a second anode reset signal line Vref22 extending along a second direction. The display panel 1 may include multiple first anode reset signal lines Vref21, which can be arranged along the second direction; the display panel 1 may also include multiple second anode reset signal lines Vref22, which can be arranged along the first direction. The anode reset signal line Vref2, including the first anode reset signal line Vref21 and the second anode reset signal line Vref22, is respectively configured to provide annode reset signals to the pixel circuit 100.

[0050] The first anode reset signal line Vref21 includes a plurality of second segments Vref210 extending along a first direction. The second segments Vref210 are electrically connected to the second anode reset signal line Vref22. Each second segment Vref210 can be electrically connected to at least one second anode reset signal line Vref22. The plurality of second segments Vref210 of the first anode reset signal line Vref21 can be spaced apart. That is, the first anode reset signal line Vref21 can be broken along the first direction, including a plurality of discontinuous second segments Vref210; the second anode reset signal line Vref22 can be continuous along a second direction.

[0051] The power signal line PVEE includes a first power signal line PVEE1 extending along a first direction. The power signal line PVEE may include multiple first power signal lines PVEE1, which may be arranged along a second direction. The power signal line PVEE, including the first power signal lines PVEE1, is configured to provide a first power signal to the light-emitting element D.

[0052] Wherein, the first direction intersects the second direction. In some embodiments, the first direction is perpendicular to the second direction; for example, in Figure 1 and Figure 2 In the display panel 1 shown, the first direction is the Y-axis direction, and the second direction is the X-axis direction. In some embodiments, the first direction and the second direction intersect but are not perpendicular.

[0053] The display panel 1 may include multiple pixel circuits 100 and multiple light-emitting elements D, wherein the multiple pixel circuits 100 and the multiple light-emitting elements D may be arranged in an array. The pixel circuits 100 are configured to drive the light-emitting elements D to emit light and display, and control the brightness of the light-emitting elements D. The pixel circuits 100 may include multiple transistors, which may include a driving transistor M0, a gate reset transistor M1, and an anode reset transistor M2.

[0054] The first terminal of the gate reset transistor M1 is electrically connected to the gate reset signal line Vref1. The first terminal of the gate reset transistor M1 can also be electrically connected to the first gate reset signal line Vref11 and the second gate reset signal line Vref12. The gate reset signal line Vref1, including the first gate reset signal line Vref11 and the second gate reset signal line Vref12, can be configured to provide a gate reset signal to the first terminal of the gate reset transistor M1. The second terminal of the gate reset transistor M1 is electrically connected to the gate of the first node N1 and the gate of the driving transistor M0.

[0055] The signal line may further include a first scan signal line Scan1. The gate of the gate reset transistor M1 may be electrically connected to the first scan signal line Scan1. The first scan signal line Scan1 may be configured to provide a first scan signal to the gate of the gate reset transistor M1. In response to the enable level of the first scan signal, the gate reset transistor M1 may transmit a gate reset signal to the gate of the driving transistor M0 to reset the gate of the driving transistor M0.

[0056] The number of gate reset transistors M1 can be one or more. For example, the gate reset transistor M1 includes a first gate reset transistor and a second gate reset transistor, wherein the gates of the first and second gate reset transistors are electrically connected to the first scan signal line Scan1, the first terminal of the first gate reset transistor is electrically connected to the gate reset signal line Vref1, the second terminal of the first gate reset transistor is electrically connected to the fourth node N4 and the first terminal of the second gate reset transistor, and the second terminal of the second gate reset transistor is electrically connected to the first node N1 and the gate of the driving transistor M0.

[0057] The first terminal of the anode reset transistor M2 is electrically connected to the anode reset signal line Vref2. The first terminal of the anode reset transistor M2 can also be electrically connected to the first anode reset signal line Vref21 and the second anode reset signal line Vref22. The second terminal of the anode reset transistor M2 can be electrically connected to the sixth node N6 and the first electrode of the light-emitting element D. The anode reset signal line Vref2, including the first anode reset signal line Vref21 and the second anode reset signal line Vref22, can be configured to provide anode reset signals to the first electrode of the light-emitting element D.

[0058] The signal line may further include a second scan signal line Scan2. The gate of the anode reset transistor M2 can be connected to the second scan signal line Scan2, which can be configured to provide a second scan signal to the gate of the anode reset transistor M2. In response to the enable level of the second scan signal, the anode reset transistor M2 can transmit an anode reset signal to the first electrode of the light-emitting element D to reset the first electrode of the light-emitting element D. The number of anode reset transistors M2 can be one.

[0059] The second electrode of the light-emitting element D is electrically connected to the power signal line PVEE, wherein the power signal line PVEE can be configured to provide a first power signal to the second electrode of the light-emitting element D. The first electrode of the light-emitting element D can be an anode, and the second electrode can be a cathode; therefore, the power signal line PVEE can provide a first power signal to the cathode of the light-emitting element D.

[0060] The display panel 1 provided in this application embodiment, by setting the gate reset signal line Vref1 to include a first gate reset signal line Vref11 and a second gate reset signal line Vref12 extending in different directions, and setting the first gate reset signal to include multiple first sub-segments Vref110 extending in a first direction and disconnected, and a second gate reset signal line Vref12 extending in a second direction and connected, and electrically connecting the first sub-segments Vref110 and the second gate reset signal line Vref12, not only realizes the layout design of the gate reset signal line Vref1, but also realizes the grid design of the gate reset signal line Vref1, which helps to improve the distribution uniformity of the gate reset signal line Vref1, thereby improving the uniformity of the gate reset signal in the display panel 1 and helping to improve the display effect of the display panel 1; in addition, by setting the anode reset signal line Vref2 to include a first anode reset signal line Vref21 and a second anode reset signal line Vref22 extending in different directions, and setting the first anode reset signal to include multiple second sub-segments Vref210 extending in a first direction and disconnected, and The second anode reset signal line Vref22, extending and connected along the second direction, and electrically connected to the second anode reset signal line Vref22 via the second sub-segment Vref210, not only realizes the layout design of the anode reset signal line Vref2, but also realizes the grid design of the anode reset signal line Vref2, which helps to improve the distribution uniformity of the anode reset signal line Vref2, thereby improving the uniformity of the gate reset signal in the display panel 1 and helping to improve the display effect of the display panel 1. In addition, by setting the power signal line PVEE, including the first power signal line PVEE1 extending along the first direction and arranged along the second direction, the layout design of the power signal line PVEE is realized, providing support for the display panel 1 to realize the display function. Thus, the layout design of the gate reset signal line Vref1, the anode reset signal line Vref2, and the power signal line PVEE is realized, as well as the grid design of the gate reset signal line Vref1 and the anode reset signal line Vref2, which helps to improve the wiring uniformity in the display panel 1, thereby helping to improve the signal uniformity of the display panel 1, and thus helping to improve the display effect.

[0061] Please continue reading. Figure 1 and Figure 2 In some embodiments, the display panel 1 includes a display area AA. The display area AA includes a first gate reset signal line Vref11, a first anode reset signal line Vref21, a first power supply signal line PVEE1, a second gate reset signal line Vref12, and a second anode reset signal line Vref22.

[0062] In this configuration, along the second direction, the second gate reset signal line Vref12 and the second anode reset signal line Vref22 respectively penetrate the display area AA of the display panel 1. The lengths of the second gate reset signal line Vref12 and the second anode reset signal line Vref22 can be the same or different. For example, along the second direction, the lengths of the second gate reset signal line Vref12 and the second anode reset signal line Vref22 are respectively greater than or equal to the total width of the pixel circuit 100. In another example, along the second direction, the lengths of the second gate reset signal line Vref12 and the second anode reset signal line Vref22 are respectively greater than or equal to the width of the display area AA. Thus, by configuring the second gate reset signal line Vref12 and the second anode reset signal line Vref22 extending along the second direction as an integral structure penetrating the display area AA, the uniformity of the distribution of the second gate reset signal line Vref12 and the second anode reset signal line Vref22 in the display panel 1 can be improved, thereby improving the wiring uniformity within the display panel 1, which is beneficial for improving the overall signal consistency of the display panel 1 and enhancing the display effect.

[0063] Along a first direction, a first power signal line PVEE1 penetrates the display area AA of the display panel 1. For example, along the first direction, the length of the first power signal line PVEE1 is greater than or equal to the total length of the pixel circuit 100. In another example, along the first direction, the length of the first power signal line PVEE1 is greater than or equal to the width of the display area AA. Thus, by configuring the first power signal line PVEE1 extending along the first direction as an integral structure penetrating the display area AA, the uniformity of the distribution of the first power signal line PVEE1 in the display panel 1 can be improved, thereby improving the wiring uniformity within the display panel 1, which is beneficial for improving the overall signal consistency of the display panel 1 and enhancing the display effect.

[0064] Along both the first and second directions, the first sub-segment Vref110 and the second sub-segment Vref210 are alternately arranged. That is, along the first direction, the first sub-segment Vref110 and the second sub-segment Vref210 are alternately arranged. The first sub-segment Vref110 and the second sub-segment Vref210 can be arranged in a certain ratio; for example, alternating between one first sub-segment Vref110 and one second sub-segment Vref210 in a 1:1 ratio; or alternating between two first sub-segments Vref110 and one second sub-segment Vref210 in a 2:1 ratio; or other ratios are not limited here. This configuration can improve the uniformity of the distribution of the first sub-segment Vref110 in the display panel 1, and improve the uniformity of the distribution of the second sub-segment Vref210 in the display panel 1, thereby improving the uniformity of the distribution of the first gate reset signal line Vref11 and the first anode reset signal line Vref21 in the display panel 1, and further improving the wiring uniformity within the display panel 1, which is beneficial to improving the overall signal consistency of the display panel 1 and enhancing the display effect.

[0065] Please continue reading. Figure 1 and Figure 2 In some embodiments, along the second direction, a first power signal line PVEE1 is included between any two adjacent first sub-segments Vref110 and Vref210. That is, along the second direction, a first power signal line PVEE1 is spaced between any two adjacent first sub-segments Vref110 and Vref210.

[0066] For example, along the second direction, the first sub-segment Vref110, the first power signal line PVEE1, and the second sub-segment Vref210 are arranged in sequence; and / or, the second sub-segment Vref210, the first power signal line PVEE1, and the first sub-segment Vref110 are arranged in sequence.

[0067] With this configuration, a first power signal line PVEE1 is spaced between the first sub-segment Vref110 and the second sub-segment Vref210. This improves the wiring uniformity of both the first and second sub-segments Vref110 and Vref210, while also increasing the spacing between them and reducing their mutual interference. This, in turn, helps to improve the distribution consistency of the gate reset signal and the anode reset signal within the display panel 1, thus enhancing the display effect.

[0068] Please continue reading. Figure 1 and Figure 2 In some embodiments, the second gate reset signal line Vref12 and the second anode reset signal line Vref22 are alternately arranged along a first direction.

[0069] The second gate reset signal line Vref12 and the second anode reset signal line Vref22 can be arranged alternately in a certain ratio; for example, they can be arranged alternately in a ratio of 1:1; or, they can be arranged alternately in a ratio of 2:1; or, they can be arranged alternately in a ratio of other ratios, which are not limited here.

[0070] This configuration can improve the uniformity of the distribution of the second gate reset signal line Vref12 in the display panel 1, and improve the uniformity of the distribution of the second anode reset signal line Vref22 in the display panel 1, thereby improving the wiring uniformity within the display panel 1, which is beneficial to improving the overall signal consistency of the display panel 1 and enhancing the display effect.

[0071] Figures 4 to 15 This is a schematic diagram of the layout structure of a display panel 1 and its internal film layers provided in an embodiment of this application. (Combined with...) Figures 1 to 15 As shown, in some embodiments, the first segment Vref110 and the second gate reset signal line Vref12 overlap in a third direction.

[0072] The first sub-segment Vref110 may overlap with at least one second gate reset signal line Vref12 in a third direction. For example, the first sub-segment Vref110 may overlap with one second gate reset signal line Vref12 in a third direction; or, the first sub-segment Vref110 may overlap with two second gate reset signal lines Vref12 in a third direction; or, the first sub-segment Vref110 may overlap with three or more second gate reset signal lines Vref12 in a third direction, which is not limited here.

[0073] In various embodiments of this application, the third direction is perpendicular to the plane containing the first and second directions. The third direction can be the thickness direction of the display panel 1. Overlap can be understood as an overlap in the orthographic projection of the third direction.

[0074] In this configuration, the multiple first sub-segments Vref110 arranged along the second direction have identical overlapping second gate reset signal lines Vref12. For example, multiple first sub-segments Vref110 arranged along the second direction with the same center point in the second direction have identical overlapping second gate reset signal lines Vref12. For instance, multiple first sub-segments Vref110 arranged along the second direction with the same center point in the second direction may overlap with the same second gate reset signal line Vref12, or they may overlap with multiple identical second gate reset signal lines Vref12; this is not limited here.

[0075] by Figure 9 and Figure 15 Taking the display panel 1 shown as an example, the pixel circuits 100 in the display panel 1 are arranged in an array, with the second direction being the row direction of the pixel circuits 100. Multiple first sub-segments Vref110 arranged along the second direction, with their center points in the same direction (i.e., multiple first sub-segments Vref110 arranged in the same row), have identical overlapping second gate reset signal lines Vref12. This arrangement helps reduce the planar area occupied by the first sub-segments Vref110 and the second gate reset signal lines Vref12 in the display panel 1, thereby reducing the planar area occupied by the first gate reset signal lines Vref11 and Vref12, and further reducing the planar area occupied by the gate reset signal line Vref1 in the display panel 1. This increases the spatial density of the signal lines, improves the pixel density, and ultimately enhances the display effect.

[0076] The multiple first sub-segments Vref110 arranged along the first direction have different overlapping second gate reset signal lines Vref12. For example, the multiple first sub-segments Vref110 arranged along the first direction overlap with a second gate reset signal line Vref12, and the overlapping second gate reset signal lines Vref12 of each first sub-segment Vref110 are different.

[0077] In another example, the overlapping second gate reset signal lines Vref12 of the plurality of first sub-segments Vref110 arranged along the first direction are different. For example, the plurality of first sub-segments Vref110 arranged along the first direction overlap with two second gate reset signal lines Vref12 respectively; and, in two adjacent first sub-segments Vref110, one overlapping second gate reset signal line Vref12 is the same, while the remaining second gate reset signal lines Vref12 are different.

[0078] This configuration facilitates the electrical connection between the first sub-segment Vref110 arranged along the first direction and the second gate reset signal line Vref12, thereby reducing the trace length between the first sub-segment Vref110 and the second gate reset signal line Vref12, increasing the spatial density of the signal lines, improving the pixel density, and thus enhancing the display effect.

[0079] Please continue reading. Figures 1 to 15 As shown, in some embodiments, the second segment Vref210 and the second anode reset signal line Vref22 overlap in a third direction.

[0080] The second sub-segment Vref210 may overlap with at least one second anode reset signal line Vref22 in a third direction. For example, the second sub-segment Vref210 may overlap with one second anode reset signal line Vref22 in a third direction; or, the second sub-segment Vref210 may overlap with two second anode reset signal lines Vref22 in a third direction; or, the second sub-segment Vref210 may overlap with three or more second anode reset signal lines Vref22 in a third direction, which is not limited here.

[0081] In this configuration, the multiple second sub-segments Vref210 arranged along the second direction have identical overlapping second anode reset signal lines Vref22. For example, multiple second sub-segments Vref210 arranged along the second direction with the same center point in the second direction have identical overlapping second anode reset signal lines Vref22. For instance, multiple second sub-segments Vref210 arranged along the second direction with the same center point in the second direction may overlap with the same second anode reset signal line Vref22, or they may overlap with multiple identical second anode reset signal lines Vref22; this is not limited here.

[0082] by Figure 9 and Figure 15 Taking the display panel 1 shown as an example, the pixel circuits 100 in the display panel 1 are arranged in an array, and the second direction is the row direction of the pixel circuits 100; among them, the multiple second sub-segments Vref210 arranged along the second direction and whose center points are the same in the second direction, that is, the multiple second sub-segments Vref210 arranged in the same row, have the same overlapping second anode reset signal line Vref22.

[0083] This configuration helps to reduce the planar area occupied by the second sub-segment Vref210 and the second anode reset signal line Vref22 in the display panel 1, thereby helping to reduce the planar area occupied by the first anode reset signal line Vref21 and the second anode reset signal line Vref22 in the display panel 1, and further helping to reduce the planar area occupied by the anode reset signal line Vref2 in the display panel 1. This helps to increase the spatial density of the signal lines, improve the pixel density, and thus improve the display effect.

[0084] The multiple second sub-segments Vref210 arranged along the first direction have different overlapping second anode reset signal lines Vref22. For example, the multiple second sub-segments Vref210 arranged along the first direction each overlap with a second anode reset signal line Vref22, and the overlapping second anode reset signal lines Vref22 of each second sub-segment Vref210 are different.

[0085] In another example, the overlapping second anode reset signal lines Vref22 of the plurality of second sub-segments Vref210 arranged along the first direction are different. For example, the plurality of second sub-segments Vref210 arranged along the first direction overlap with two second anode reset signal lines Vref22 respectively; and, in two adjacent second sub-segments Vref210, one overlapping second anode reset signal line Vref22 is the same, while the remaining second anode reset signal lines Vref22 are different.

[0086] This configuration facilitates the electrical connection between the second sub-segment Vref210 arranged along the first direction and the second anode reset signal line Vref22, thereby reducing the trace length between the second sub-segment Vref210 and the second anode reset signal line Vref22, increasing the spatial density of the signal lines, improving the pixel density, and ultimately enhancing the display effect.

[0087] Please continue reading. Figure 2 , Figures 10 to 15 In some embodiments, the power signal line PVEE further includes a second power signal line PVEE2 extending along a second direction and arranged along a first direction. The display panel 1 may include multiple second power signal lines PVEE2, which are arranged sequentially at intervals along the first direction. The second power signal lines PVEE2 are electrically connected to the first power signal line PVEE1. The second power signal lines PVEE2 can provide a first power signal to the second electrode of the light-emitting element D.

[0088] Thus, the power signal line PVEE includes both the first power signal line PVEE1 extending along the first direction and the second power signal line PVEE2 extending along the second direction. The second power signal line PVEE2 and the first power signal line PVEE1 form a grid structure, which helps to improve the wiring uniformity of the power signal line PVEE on the display panel 1, thereby improving the signal uniformity of the first power signal on the display panel 1 and thus improving the display effect.

[0089] It should be noted that, when there is ample layout space, such as when the pixel size is large, the power signal line PVEE can be configured as a first power signal line PVEE1 and a second power signal line PVEE2. This allows for a gridded design of the gate reset signal line Vref1 and the anode reset signal line Vref2, as well as a gridded layout design of the power signal line PVEE, further improving the wiring uniformity of the display panel 1 and enhancing the display effect. Conversely, when layout space is limited, such as when the pixel size is small, the power signal line PVEE can be configured as a first power signal line PVEE1. This allows for a gridded design of the gate reset signal line Vref1 and the anode reset signal line Vref2 within a limited space, and also enables a layout design of the power signal line PVEE. This provides three different signals to the display panel 1, reducing the number of signal lines and thus reducing the area occupied by the signal lines, which helps achieve a narrow bezel.

[0090] The second power signal line PVEE2 is located in the display area AA. Specifically, the second power signal line PVEE2 passes through the display area AA of the display panel 1 along the second direction. For example, the length of the second power signal line PVEE2 along the second direction is greater than or equal to the total width of the pixel circuit 100. In another example, the length of the second power signal line PVEE2 along the second direction is greater than or equal to the width of the display area AA. Thus, by configuring the second power signal line PVEE2 to pass through the display area AA along the second direction, it helps to improve the uniformity of the distribution of the second power signal line PVEE2 in the display panel 1, thereby improving the uniformity of the display panel 1 and enhancing the display effect.

[0091] Please continue reading. Figure 2 , Figures 10 to 15In some embodiments, the display panel 1 further includes multiple signal line groups arranged along a first direction. The number of signal line groups can be set according to the specific needs of the display panel 1 and is not limited here. Each signal line group includes a second gate reset signal line Vref12, a second anode reset signal line Vref22, and a second power signal line PVEE2. For example, in the same signal line group, the second gate reset signal line Vref12, the second anode reset signal line Vref22, and the second power signal line PVEE2 are arranged sequentially along the first direction. In another example, the second anode reset signal line Vref22, the second gate reset signal line Vref12, and the second power signal line PVEE2 are arranged sequentially along the first direction. It should be noted that in the same signal line group, the second gate reset signal line Vref12, the second anode reset signal line Vref22, and the second power signal line PVEE2 can be freely arranged along the first direction as needed; these are all illustrative examples and are not intended to impose excessive limitations. Thus, by treating a second gate reset signal line Vref12, a second anode reset signal line Vref22, and a second power signal line PVEE2 as a signal line group, and arranging multiple signal line groups along the first direction, it helps to improve the uniformity of the distribution of the second gate reset signal, the second anode reset signal line Vref22, and the second power signal line PVEE2 in the display panel 1, thereby improving the overall signal uniformity of the display panel 1 and thus improving the display effect.

[0092] Please continue reading. Figure 2 , Figure 10 and Figure 15 In some embodiments, the first segment Vref110 overlaps with the second power signal line PVEE2 in a third direction. The first segment Vref110 may overlap with at least one second power signal line PVEE2 in a third direction. For example, the first segment Vref110 may overlap with one second power signal line PVEE2 in a third direction; or, the first segment Vref110 may overlap with two second power signal lines PVEE2 in a third direction; or, the first segment Vref110 may overlap with three or more second power signal lines PVEE2 in a third direction, which is not limited here.

[0093] Multiple first segments Vref110 arranged along the second direction have the same overlapping second power signal line PVEE2. For example, multiple first segments Vref110 arranged along the second direction with the same center point in the second direction have the same overlapping second power signal line PVEE2. For instance, multiple first segments Vref110 arranged along the second direction with the same center point in the second direction may overlap with the same second power signal line PVEE2, or they may overlap with the same multiple second anode reset signal lines Vref22; this is not limited here. Figure 2 , Figure 10 and Figure 15 Taking the display panel 1 shown as an example, the pixel circuits 100 in the display panel 1 are arranged in an array, and the second direction is the row direction of the pixel circuits 100; among them, the multiple first sub-segments Vref110 arranged along the second direction and whose center points are the same in the second direction, that is, the multiple first sub-segments Vref110 arranged in the same row, have the same overlapping second power signal line PVEE2.

[0094] The multiple first segments Vref110 arranged along the first direction have different overlapping second power signal lines PVEE2. For example, the multiple first segments Vref110 arranged along the first direction have completely different overlapping second power signal lines PVEE2. For instance, each of the multiple first segments Vref110 arranged along the first direction overlaps with one second power signal line PVEE2, and the overlapping second power signal lines PVEE2 of each first segment Vref110 are different. In another example, the multiple first segments Vref110 arranged along the first direction have different overlapping second power signal lines PVEE2. For example, each of the multiple first segments Vref110 arranged along the first direction overlaps with two second power signal lines PVEE2; and in adjacent first segments Vref110, one overlapping second power signal line PVEE2 is the same, while the remaining second power signal lines PVEE2 are different.

[0095] In the above embodiments, the first sub-segment Vref110 and the second power signal line PVEE2 overlap in the third direction; the overlapping second power signal lines PVEE2 of the multiple first sub-segments Vref110 arranged along the second direction are the same; the overlapping second power signal lines PVEE2 of the multiple first sub-segments Vref110 arranged along the first direction are different. This configuration helps to reduce the planar area occupied by the first sub-segment Vref110 and the second power signal line PVEE2 in the display panel 1, thereby helping to reduce the planar area occupied by the gate reset signal line Vref1 and the power signal line PVEE in the display panel 1, which in turn helps to increase the spatial density of the signal lines, improve the pixel density, and thus improve the display effect.

[0096] Please continue reading. Figure 2 , Figure 10 and Figure 15 In some embodiments, the second segment Vref210 overlaps with the second power signal line PVEE2 in a third direction. The second segment Vref210 may overlap with at least one second power signal line PVEE2 in a third direction. For example, the second segment Vref210 may overlap with one second power signal line PVEE2 in a third direction; or, the second segment Vref210 may overlap with two second power signal lines PVEE2 in a third direction; or, the second segment Vref210 may overlap with three or more second power signal lines PVEE2 in a third direction, which is not limited here.

[0097] Multiple second sub-segments Vref210 arranged along the second direction have identical overlapping second power signal lines PVEE2. For example, multiple second sub-segments Vref210 arranged along the second direction with the same center point in the second direction have identical overlapping second power signal lines PVEE2. For instance, multiple second sub-segments Vref210 arranged along the second direction with the same center point in the second direction may overlap with the same second power signal line PVEE2, or they may overlap with multiple identical second power signal lines PVEE2; this is not limited here. Figure 2 , Figure 10 and Figure 15 Taking the display panel 1 shown as an example, the pixel circuits 100 in the display panel 1 are arranged in an array, and the second direction is the row direction of the pixel circuits 100; among them, the multiple second sub-segments Vref210 arranged along the second direction and whose center points are the same in the second direction, that is, the multiple second sub-segments Vref210 arranged in the same row, have the same overlapping second power signal line PVEE2.

[0098] The multiple second sub-segments Vref210 arranged along the first direction have different overlapping second power signal lines PVEE2. For example, the multiple second sub-segments Vref210 arranged along the first direction overlap with one second power signal line PVEE2, and the overlapping second power signal lines PVEE2 of each second sub-segment Vref210 are different. In another example, the multiple second sub-segments Vref210 arranged along the first direction have different overlapping second power signal lines PVEE2. For example, the multiple second sub-segments Vref210 arranged along the first direction overlap with two second power signal lines PVEE2; and in adjacent second sub-segments Vref210, one overlapping second power signal line PVEE2 is the same, while the remaining second power signal lines PVEE2 are different.

[0099] In this embodiment, the second sub-segment Vref210 and the second power signal line PVEE2 overlap in a third direction; the overlapping second power signal lines PVEE2 of the multiple second sub-segments Vref210 arranged along the second direction are the same; the overlapping second power signal lines PVEE2 of the multiple second sub-segments Vref210 arranged along the first direction are different. This arrangement helps to reduce the planar area occupied by the second sub-segment Vref210 and the second power signal line PVEE2 in the display panel 1, thereby helping to reduce the planar area occupied by the anode reset signal line Vref2 and the power signal line PVEE in the display panel 1, which in turn helps to increase the spatial density of the signal lines, improve the pixel density, and thus improve the display effect.

[0100] Please continue reading. Figure 1 and Figure 2 In some embodiments, the pixel circuits 100 in the display panel 1 are arranged in an array. For example, Figure 1 and Figure 2 As shown, the column direction of the pixel circuit 100 is the first direction, and the row direction of the pixel circuit 100 is the second direction.

[0101] Along the first direction, in the same column of pixel circuits 100, the number of pixel circuits 100 is N10; the number of the first sub-segment Vref110 corresponding to this column of pixel circuits 100 is N11, and the number of the second sub-segment Vref210 is N12. Where N10 ≥ N11 + N12, that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than or equal to the total number of the corresponding first sub-segment Vref110 and second sub-segment Vref210. Where N10, N11, and N12 are all positive integers, then N10 > N11 and N10 > N12; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than the number of the corresponding first sub-segment Vref110, and the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than the number of the corresponding second sub-segment Vref210.

[0102] In the same column of pixel circuits 100, at least some pixel circuits 100 are respectively provided with at least one first sub-segment Vref110 and at least one second sub-segment Vref210. For example, N10 = N11 + N12; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is equal to the total number of the corresponding first sub-segment Vref110 and second sub-segment Vref210; for example, in the same column of pixel circuits 100, some pixel circuits 100 are respectively provided with one first sub-segment Vref110, and the remaining pixel circuits 100 are respectively provided with one second sub-segment Vref210.

[0103] For example, N10 = N11 + N12, and N11 = N12; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is equal to the total number of the corresponding first sub-segment Vref110 and second sub-segment Vref210, and the number of the first sub-segment Vref110 is the same as the number of the second sub-segment Vref210. For example, the first sub-segment Vref110 and the second sub-segment Vref210 are alternately arranged in the same column of pixel circuits 100, wherein in any two adjacent pixel circuits 100, one pixel circuit 100 is provided with one first sub-segment Vref110, and the other pixel circuit 100 is provided with one second sub-segment Vref210. This arrangement makes the distribution uniformity of the first sub-segment Vref110 and the distribution uniformity of the second sub-segment Vref210 better, which is beneficial to improving signal uniformity and display effect.

[0104] Another example is that N10 > N11 + N12; for instance, in the same column of pixel circuits 100, a first sub-segment Vref110 or a second sub-segment Vref210 can be set for some pixel circuits 100; the remaining pixel circuits 100 may not have either the first sub-segment Vref110 or the second sub-segment Vref210. For the remaining pixel circuits 100, signal lines for transmitting other signals can be laid out. This arrangement improves the display effect while also meeting the need to lay out different functional signal lines within a limited film layer.

[0105] In this embodiment of the application, the first sub-segment Vref110 corresponding to the pixel circuit 100 can be understood as the pixel circuit 100 and the first sub-segment Vref110 overlapping in a third direction; the second sub-segment Vref210 corresponding to the pixel circuit 100 can be understood as the pixel circuit 100 and the second sub-segment Vref210 overlapping in a third direction.

[0106] Please continue reading. Figure 1 and Figure 2 In some embodiments, along the second direction, in the same row of pixel circuits 100, the number of pixel circuits 100 is N20, the number of first gate reset signal lines Vref11 corresponding to that row of pixel circuits 100 is N21, the number of first anode reset signal lines Vref21 is N22, and the number of first power supply signal lines PVEE1 is N23. Wherein, N20≥N21, N20≥N22, N20≥N23, and N20, N21, N22, and N23 are all positive integers.

[0107] For example, N20 > N21, N20 > N22, N20 > N23; that is, the number of pixel circuits 100 in the same row of pixel circuits 100 is greater than the corresponding first gate reset signal line Vref11, the number of pixel circuits 100 in the same row of pixel circuits 100 is equal to the number of the corresponding first anode reset signal lines Vref21, and the number of pixel circuits 100 in the same row of pixel circuits 100 is equal to the number of the corresponding first power supply signal lines PVEE1.

[0108] For example, in each row of pixel circuits 100, some pixel circuits 100 are provided with a first gate reset signal line Vref11; the remaining pixel circuits 100 do not have a first gate reset signal line Vref11, but can be provided with a first anode reset signal line Vref21 and / or a first power signal line PVEE1. As another example, in each row of pixel circuits 100, some pixel circuits 100 are provided with a first anode reset signal line Vref21; the remaining pixel circuits 100 do not have a first anode reset signal line Vref21, but can be provided with a first gate reset signal line Vref11 and / or a first power signal line PVEE1. Yet another example, in each row of pixel circuits 100, some pixel circuits 100 are provided with a first power signal line PVEE1; the remaining pixel circuits 100 do not have a first power signal line PVEE1, but can be provided with a first gate reset signal line Vref11 and / or a first anode reset signal line Vref21.

[0109] This configuration results in better uniformity of the distribution of the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power signal line PVEE1. This is beneficial for improving signal uniformity and display effect, while also meeting the needs of laying out different functional signal lines within a limited film layer.

[0110] Please continue reading. Figure 1 and Figure 2 In some embodiments, N21 = N22 = N23, and N20 ≥ N21 + N23; that is, N20 > N21 = N22 = N23. Specifically, the number of first gate reset signal lines Vref11, the number of first anode reset signal lines Vref21, and the number of first power supply signal lines PVEE1 are the same, and the number of pixel circuits 100 in the same row of pixel circuits 100 is greater than the corresponding number of first gate reset signal lines Vref11.

[0111] For example, N20 = N21 + N23; for instance, in any two adjacent columns of pixel circuits 100, one column of pixel circuits 100 is provided with a first gate reset signal line Vref11 and a first anode reset signal line Vref21, and the other column of pixel circuits 100 is provided with a first power supply signal line PVEE1; wherein, for a column of pixel circuits 100 provided with a first gate reset signal line Vref11 and a first anode reset signal line Vref21, the first sub-segment Vref110 of the first gate reset signal line Vref11 and the second sub-segment Vref210 of the first anode reset signal line Vref21 can be arranged alternately along the first direction, and in any two adjacent pixel circuits 100, one pixel circuit 100 is provided with a first sub-segment Vref110, and the other pixel circuit 100 is provided with a second sub-segment Vref210.

[0112] Another example may include a portion of the column pixel circuit 100 that does not have a first gate reset signal line Vref11, a first anode reset signal line Vref21, or a first power supply signal line PVEE1, i.e., N20 > N21 + N23. For this portion of the column pixel circuit 100, signal lines for transmitting other signals can be arranged. This arrangement improves the display effect while also meeting the need to arrange different functional signal lines within a limited film layer.

[0113] Please continue reading. Figure 1 and Figure 2 In some embodiments, along the first direction, in the same column of pixel circuits 100, the number of pixel circuits 100 is N30, the number of second gate reset signal lines Vref12 corresponding to the column of pixel circuits 100 is N31, and the number of second anode reset signal lines Vref22 is N32; wherein, N30≥N31, N30≥N32, and N30, N31 and N32 are all positive integers.

[0114] For example, N30 = N31 = N32; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is equal to the number of corresponding second gate reset signal lines Vref12, and the number of pixel circuits 100 in the same column of pixel circuits 100 is equal to the number of corresponding second anode reset signal lines Vref22. The number of pixel circuits 100 in the same column of pixel circuits 100 can be understood as the number of rows of pixel circuits 100. That is, the number of rows of pixel circuits 100 is equal to the number of second gate reset signal lines Vref12, and the number of rows of pixel circuits 100 is equal to the number of second anode reset signal lines Vref22. For example, each row of pixel circuits 100 is respectively provided with one second gate reset signal line Vref12 and one second anode reset signal line Vref22. This arrangement results in better uniformity of distribution of the second gate reset signal lines Vref12 and the second anode reset signal lines Vref22, which is beneficial for improving signal uniformity and display effect.

[0115] In another example, N30 > N31, N30 > N32; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than the corresponding second gate reset signal line Vref12, and the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than the corresponding number of second anode reset signal lines Vref22; or, it can be understood that the number of rows of pixel circuits 100 is greater than the number of second gate reset signal lines Vref12, and the number of rows of pixel circuits 100 is greater than the number of second anode reset signal lines Vref22. For example, some rows of pixel circuits 100 are respectively provided with one second gate reset signal line Vref12 and one second anode reset signal line Vref22; the remaining rows of pixel circuits 100 are neither provided with second gate reset signal lines Vref12 nor second anode reset signal lines Vref22, and can be used to lay signal lines for transmitting other signals. This arrangement not only improves the display effect but also meets the need to lay different functional signal lines within a limited film layer.

[0116] Please continue reading. Figure 1 and Figure 2 In some embodiments, the power signal line PVEE includes a first power signal line PVEE1 and a second power signal line PVEE2 extending along a second direction and arranged along a first direction. The first power signal line PVEE1 and the second power signal line PVEE2 are described above and will not be repeated here. The number of second power signal lines PVEE2 is N33, where N30 ≥ N33, and N33 is a positive integer.

[0117] For example, N30 = N33; that is, the number of pixel circuits 100 in the same column of pixel circuits 100 is equal to the corresponding second power signal line PVEE2; or, it can be understood that the number of rows of pixel circuits 100 is equal to the number of second power signal lines PVEE2. For example, each row of pixel circuits 100 is respectively provided with one second power signal line PVEE2. This arrangement makes the distribution of the second power signal lines PVEE2 more uniform, which is beneficial to improving signal uniformity and display effect.

[0118] Another example is that N30 > N33; for instance, some pixel circuits 100 are each provided with a second power signal line PVEE2; the remaining pixel circuits 100 do not have a second power signal line PVEE2, but can be equipped with signal lines for transmitting other signals. This arrangement not only improves the display effect, but also meets the need to arrange different functional signal lines within a limited film layer.

[0119] Please continue reading. Figure 2 In some embodiments, N31 = N32 = N33; that is, the number of second gate reset signal lines Vref12, the number of second anode reset signal lines Vref22, and the number of second power supply signal lines PVEE2 are the same.

[0120] For example, N30 = N31 = N32 = N33; that is, the number of pixel circuits 100, the number of second gate reset signal lines Vref12, the number of second anode reset signal lines Vref22, and the number of second power signal lines PVEE2 are the same in the same column of pixel circuits 100. For example, each row of pixel circuits 100 is respectively provided with one second gate reset signal line Vref12, one second anode reset signal line Vref22, and one second power signal line PVEE2. This arrangement makes the distribution uniformity of the second gate reset signal lines Vref12, the second anode reset signal lines Vref22, and the second power signal lines PVEE2 better, which is beneficial to improving signal uniformity and display effect.

[0121] In another example, N30 > N31 = N32 = N33; that is, the number of second gate reset signal lines Vref12, the number of second anode reset signal lines Vref22, and the number of second power signal lines PVEE2 are the same, and the number of pixel circuits 100 in the same column of pixel circuits 100 is greater than the number of second gate reset signal lines Vref12. For example, in the same column of pixel circuits 100, some pixel circuits 100 are respectively provided with one second gate reset signal line Vref12, one second anode reset signal line Vref22, and one second power signal line PVEE2. This arrangement results in better uniformity of the distribution of the second gate reset signal lines Vref12, the second anode reset signal lines Vref22, and the second power signal lines PVEE2, which is beneficial for improving signal uniformity and display effect.

[0122] Please continue reading. Figure 1 and Figure 2 In some embodiments, the display panel 1 includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103, each emitting a different color. Each sub-pixel may include a pixel circuit 100 and a light-emitting element D. Sub-pixels of different colors can be distinguished based on the different colors emitted by different light-emitting elements D. For example, the light-emitting element D includes an anode, a light-emitting material layer, and a cathode; the light-emitting element D can emit different colors of light based on the different properties of the light-emitting material layer.

[0123] Please continue reading. Figure 1 and Figure 2 In some embodiments, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are each one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and are all different. With this configuration, the display panel 1 can achieve full-color display. For example, the first sub-pixel 101 can be a red sub-pixel R, the second sub-pixel 102 can be a blue sub-pixel B, and the third sub-pixel 103 can be a green sub-pixel G. In other embodiments, the first color, the second color, and the third color can also be other colors, which are not limited here.

[0124] Multiple first sub-pixels 101 and second sub-pixels 102 form a first virtual quadrilateral. The center of the first sub-pixel 101 is located at the first vertex of the first virtual quadrilateral, and the center of the second sub-pixel 102 is located at the second vertex of the first virtual quadrilateral. The first and second vertices are alternately arranged, and a third sub-pixel 103 is located inside the first virtual quadrilateral. Multiple third sub-pixels 103 form a second virtual quadrilateral. The centers of the multiple third sub-pixels 103 are located at the vertices of the second virtual quadrilateral, and either the first sub-pixel 101 or the second sub-pixel 102 is located inside the second virtual quadrilateral. This windmill arrangement achieves good display effects while being highly energy-efficient.

[0125] Wherein, the first power signal line PVEE1 overlaps at least with the pixel circuit 100 of the third sub-pixel 103; the first sub-segment Vref110 overlaps at least with the pixel circuit 100 of the first sub-pixel 101, and the second sub-segment Vref210 overlaps at least with the pixel circuit 100 of the second sub-pixel 102; or, the first sub-segment Vref110 overlaps at least with the pixel circuit 100 of the second sub-pixel 102, and the second sub-segment Vref210 overlaps at least with the pixel circuit 100 of the first sub-pixel 101.

[0126] For example, the first power signal line PVEE1 overlaps at least with the pixel circuit 100 of the green sub-pixel, the first sub-segment Vref110 overlaps at least with the pixel circuit 100 of the red sub-pixel, and the second sub-segment Vref210 overlaps at least with the pixel circuit 100 of the blue sub-pixel. In another example, the first power signal line PVEE1 overlaps at least with the pixel circuit 100 of the green sub-pixel, the first sub-segment Vref110 overlaps at least with the pixel circuit 100 of the blue sub-pixel, and the second sub-segment Vref210 overlaps at least with the pixel circuit 100 of the red sub-pixel.

[0127] In this embodiment, the third sub-pixel 103 (e.g., a green sub-pixel) can be arranged in a solid color column along the first direction; the first sub-pixel 101 and the second sub-pixel 102 (e.g., a red sub-pixel and a blue sub-pixel) can be arranged in a mixed color column along the first direction at intervals. Correspondingly, the continuously extending first power signal line PVEE1 can overlap with the pixel circuit 100 of the sub-pixels in the solid color column; the interval-arranged and segmented first sub-segment Vref110 and second sub-segment Vref210 can overlap with the pixel circuit 100 of the sub-pixels in the mixed color column, and the first sub-segment Vref110 and the second sub-segment Vref210 overlap with the pixel circuit 100 of sub-pixels of different colors, respectively. With this configuration, the signal lines can be set according to the arrangement rules of the sub-pixels, reducing the difficulty of signal line layout. It should be noted that in some other embodiments, the correspondence between signal line layout and sub-pixel arrangement can be other relationships, which are not limited here.

[0128] Figure 16 This is a cross-sectional structural diagram of a display panel 1 provided in an embodiment of this application. In some embodiments, the display panel 1 may include a substrate 010, a buffer layer 011, a first active layer 012, a first gate insulating layer 013, a first conductive layer 014, an interlayer dielectric layer 015, a second conductive layer 016, a second gate insulating layer 017, a second active layer 018, a third gate insulating layer 019, a second gate metal layer 020, a passivation layer 021, a third conductive layer 022, a first auxiliary planarization layer 023, a fourth conductive layer 024, a second auxiliary planarization layer 025, a second auxiliary metal layer 026, a planarization layer 027, a reflective electrode layer 028, a light-emitting material layer 029, a counter electrode layer 030, and an encapsulation layer 031, stacked sequentially. The first conductive layer 014 may be denoted as M1; the second conductive layer 016 may be denoted as MC; the third conductive layer 022 may be denoted as M2; and the fourth conductive layer 024 may be denoted as M3.

[0129] The substrate 010 is configured to support the film layer disposed thereon. The substrate 010 may include a rigid substrate, such as glass or a silicon wafer, or a flexible substrate, such as thin glass, stainless steel, polyimide, etc., which are not limited herein. The buffer layer 011 is configured to planarize and passivate the substrate 010 to facilitate the smooth deposition of subsequent functional film layers and to prevent the components in the substrate 010 from affecting the performance of subsequent film layers.

[0130] Both the first active layer 012 and the second active layer 018 are semiconductor layers; for example, the first active layer 012 may be a silicon semiconductor layer, such as a polycrystalline silicon (poly-Si) semiconductor layer; the second active layer 018 may be an oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) semiconductor layer.

[0131] The first conductive layer 014, the second conductive layer 016, the second gate metal layer 020, the third conductive layer 022, the fourth conductive layer 024, and the second auxiliary metal layer 026 can all be metal layers, and are patterned to form the pixel circuit 100, signal lines, and other conductor structures in the display panel 1. The passivation layer 021 is configured to optimize the electrical performance of the conductor structures it covers.

[0132] The reflective electrode layer 028 can be a composite film layer, such as an indium tin oxide (ITO) / silver (Ag) / ITO layer, and the counter electrode layer 030 can be a thinner metal composite layer, such as a magnesium (Mg) / silver (Ag) layer, to improve light transmittance and facilitate the emission of light generated by the light-emitting material layer 029 in the light-emitting element D. The light-emitting material layer 029 is configured to emit light with target brightness and target color based on the photoelectric effect, in response to signals provided by the reflective electrode layer 028 and the counter electrode layer 030, under the drive of the pixel circuit 100, so that the display panel 1 displays the target image.

[0133] The first gate insulating layer 013, interlayer dielectric layer 015, second gate insulating layer 017, third gate insulating layer 019, and passivation layer 021 are typically inorganic insulating layers, while the first auxiliary planarization layer 023, second auxiliary planarization layer 025, and planarization layer 027 are typically organic insulating layers. Through vias within these layers, electrical connections between corresponding conductor structures can be achieved to form the devices in the pixel circuit 100. The encapsulation layer 031 may include an inorganic layer-organic layer-inorganic layer, thereby achieving the encapsulation function.

[0134] It should be noted that the number and stacking order of the above-mentioned film layers are only illustrative and the position or order of the film layers can be added, deleted or adjusted according to actual needs; the materials of the above-mentioned film layers can also be other materials known to those skilled in the art, and can be set according to the needs of the display panel 1, and are not limited here.

[0135] Please continue reading. Figures 1 to 16 In some embodiments, the first gate reset signal line Vref11 and the second gate reset signal line Vref12 are disposed in different layers. Specifically, the first gate reset signal line Vref11 and the second gate reset signal line Vref12 are two signal lines with different extension directions constituting the gate reset signal line Vref1. The fact that these two signal lines with different extension directions are disposed in different layers, i.e., the first gate reset signal line Vref11 and the second gate reset signal line Vref12 are located in different film layers, helps to reduce the difficulty of signal line routing. For example, the first gate reset signal line Vref11 can be located in the third conductive layer 022, and the second gate reset signal line Vref12 can be located in the second conductive layer 016. As another example, the first gate reset signal line Vref11 and the second gate reset signal line Vref12 can also be disposed in other two different conductive layers, for example, the first gate reset signal line Vref11 is located in the second conductive layer 016, and the second gate reset signal line Vref12 is located in the third conductive layer 022; this is not limited to these two layers.

[0136] Please continue reading. Figures 1 to 16In some embodiments, the first anode reset signal line Vref21 and the second anode reset signal line Vref22 are disposed in different layers. Specifically, the first anode reset signal line Vref21 and the second anode reset signal line Vref22 are two signal lines with different extension directions constituting the anode reset signal line Vref2. The fact that these two signal lines with different extension directions are disposed in different layers, i.e., the first anode reset signal line Vref21 and the second anode reset signal line Vref22 are located in different film layers, helps reduce the difficulty of signal line layout. For example, the first anode reset signal line Vref21 can be located in the third conductive layer 022, and the second anode reset signal line Vref22 can be located in the second conductive layer 016. As another example, the first anode reset signal line Vref21 and the second anode reset signal line Vref22 can also be disposed in other two different conductive layers, for example, the first anode reset signal line Vref21 is located in the second conductive layer 016, and the second anode reset signal line Vref22 is located in the third conductive layer 022; this is not limited to these two layers.

[0137] Please continue reading. Figures 1 to 16 In some embodiments, the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power signal line PVEE1 are disposed in the same layer. The first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power signal line PVEE1 are electrically isolated from each other. The second gate reset signal line Vref12 and the second anode reset signal line Vref22 are disposed in the same layer. The second gate reset signal line Vref12 and the second anode reset signal line Vref22 are electrically isolated from each other. This arrangement helps reduce the total number of conductive layers occupied by the gate reset signal line Vref1, the anode reset signal line Vref2, and the power signal line PVEE, facilitating a thinner and lighter design for the display panel 1. Simultaneously, by forming at least two different signal lines within the same film layer, it improves the utilization rate of the film layer, enhances the uniformity of the film layer wiring, thereby improving the electrical performance uniformity of the display panel 1 and ultimately enhancing the display effect.

[0138] Please continue reading. Figures 1 to 16In some embodiments, the display panel 1 further includes a substrate 010, a first conductive layer 014, a second conductive layer 016, a third conductive layer 022, and a fourth conductive layer 24, which are sequentially stacked. The first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power signal line PVEE1 are located on the third conductive layer 022, and the second gate reset signal line Vref12 and the second anode reset signal line Vref22 are located on the second conductive layer 016. In other embodiments, the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power signal line PVEE1 are located on the second conductive layer 016, and the second gate reset signal line Vref12 and the second anode reset signal line Vref22 are located on the third conductive layer 022. With this configuration, by placing the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power signal line PVEE1 on the third conductive layer 022, and placing the second gate reset signal line Vref12 and the second anode reset signal line Vref22 on the second conductive layer 016, signal lines extending in the same direction are located in different conductive layers within the same conductive layer. This reduces the difficulty of routing within the same conductive layer, reduces the film layer occupancy, and facilitates the thinner and lighter design of the display panel 1.

[0139] Please continue reading. Figures 1 to 16 In some embodiments, the first power signal line PVEE1 and the second power signal line PVEE2 are arranged in different layers. The first power signal line PVEE1 and the second power signal line PVEE2 are two signal lines with different extension directions constituting the power signal line PVEE. The arrangement of these two signal lines with different extension directions in different layers, i.e., the first power signal line PVEE1 and the second power signal line PVEE2 are located in different film layers, helps to reduce the difficulty of signal line layout.

[0140] Please continue reading. Figures 1 to 16In some embodiments, the first power signal line PVEE1 is disposed in the same layer as the first gate reset signal line Vref11 and the first anode reset signal line Vref21, respectively. The first power signal line PVEE1, the first gate reset signal line Vref11, and the first anode reset signal line Vref21 are electrically insulated from each other. The second power signal line PVEE2 is disposed in the same layer as the second gate reset signal line Vref12 and the second anode reset signal line Vref22, respectively. The second power signal line PVEE2, the second gate reset signal line Vref12, and the second anode reset signal line Vref22 are electrically insulated from each other. This arrangement helps reduce the total number of conductive layers occupied by the gate reset signal line Vref1, the anode reset signal line Vref2, and the power signal line PVEE, facilitating a thinner and lighter design for the display panel 1. Simultaneously, by forming three different signal lines within the same film layer, it improves the utilization rate of the film layer, enhances the uniformity of the film layer wiring, thereby improving the electrical performance uniformity of the display panel 1 and ultimately enhancing the display effect.

[0141] Please continue reading. Figures 1 to 16 In some embodiments, the display panel 1 further includes a substrate 010, a first conductive layer 014, a second conductive layer 016, a third conductive layer 022, and a fourth conductive layer 24, which are sequentially stacked. The first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power signal line PVEE1 are located on the third conductive layer 022; the second gate reset signal line Vref12, the second anode reset signal line Vref22, and the second power signal line PVEE2 are located on the second conductive layer 016. In other embodiments, the first gate reset signal line Vref11, the first anode reset signal line Vref21, and the first power signal line PVEE1 are located on the second conductive layer 016, and the second gate reset signal line Vref12, the second anode reset signal line Vref22, and the second power signal line PVEE2 are located on the third conductive layer 022. This configuration allows signal lines extending in the same direction to be located in the same conductive layer, while signal lines extending in different directions are located in different conductive layers. This reduces the difficulty of routing within the same conductive layer, while also reducing the film layer footprint, which is beneficial for achieving a thinner and lighter design for the display panel 1.

[0142] Please continue reading. Figures 4 to 16In some embodiments, the display panel 1 further includes a first connecting portion 41. The first segment Vref 110 is electrically connected to the second gate reset signal line Vref 12 via the first connecting portion 41. For example, the first connecting portion 41 can be a via, and it can be located at the intersection of the first segment Vref 110 and the second gate reset signal line Vref 12 in a third direction. Thus, by providing the first connecting portion 41, an electrical connection between the first segment Vref 110 and the second gate reset signal line Vref 12 can be achieved. In other embodiments, the first connecting portion 41 can also have other shapes, which are not limited here.

[0143] Please continue reading. Figures 4 to 16 In some embodiments, the display panel 1 further includes a second connecting portion 42. The second segment Vref 210 is electrically connected to the second anode reset signal line Vref 22 via the second connecting portion 42. For example, the second connecting portion 42 can be a via, and it can be located at the intersection of the second segment Vref 210 and the second anode reset signal line Vref 22 in a third direction. Thus, by providing the second connecting portion 42, an electrical connection between the second segment Vref 210 and the second anode reset signal line Vref 22 can be achieved. In other embodiments, the second connecting portion 42 can also have other shapes, which are not limited here.

[0144] Figure 17 This is a schematic diagram of the structure of a display panel 1 provided in an embodiment of this application. Figure 18 This is a schematic diagram of another display panel 1 provided in an embodiment of this application. (In conjunction with...) Figure 17 and Figure 18 In some embodiments, the display panel 1 includes a display area AA and a non-display area NA, with the non-display area NA located around the periphery of the display area AA. The display area AA is used to display the image and may further include an array of sub-pixels. Each sub-pixel includes a pixel driving circuit and a light-emitting element D to achieve active light emission control, thereby realizing image display. The non-display area NA may at least partially surround the display area AA. For example, the non-display area NA may be disposed in at least a portion of the space on at least one side of the display area AA, and may be used to lay out peripheral circuits and wiring to transmit display signals such as driving signals and power signals to the display area AA. The non-display area NA is not used to display the image and can also be referred to as the bezel area. The smaller its proportion in the planar area of ​​the display panel 1, the higher the proportion of the display area AA, and the easier it is to achieve a narrow bezel full-screen display.

[0145] The display panel 1 also includes a third power signal line PVEE3 located in the non-display area NA. The first power signal line PVEE1 is electrically connected to the driver chip (Driver IC) via the third power signal line PVEE3. The driver chip generates a first power signal, and the third power signal line PVEE3 transmits this first power signal to provide a first power signal to the first electrode of the light-emitting element D. For example, the third power signal line PVEE3 can be a block-shaped or linear structure. Thus, by setting the third power signal line PVEE3 in the non-display area NA, the first power signal generated by the driver chip can be received via the third power signal line PVEE3 and transmitted to the first electrode of the light-emitting element D via the first power signal line PVEE1. This achieves the transmission of the first power signal from the driver chip to the first electrode of the light-emitting element D, which improves the display uniformity of the display panel 1 and thus enhances the display effect.

[0146] Figure 19 This is a schematic diagram of the layout structure of a display panel 1 provided in an embodiment of this application. Figure 20 This is a schematic diagram of the layout structure of a display panel 1 provided in an embodiment of this application. (In conjunction with...) Figures 17 to 20 As shown, in some embodiments, the third power signal line PVEE3 includes an electrically connected third sub-segment PVEE31 and a fourth sub-segment PVEE32. The third sub-segment PVEE31 and the fourth sub-segment PVEE32 are located in the non-display areas NA on opposite sides of the display area AA. For example, the third sub-segment PVEE31 and the fourth sub-segment PVEE32 are located in the non-display areas NA on opposite sides of the display area AA along a first direction. Specifically, the third sub-segment PVEE31 is positioned closer to the driver chip, and the fourth sub-segment PVEE32 is positioned further away from the driver chip. Figure 17 and Figure 18 Taking the display panel 1 shown as an example, the driver chip is located below the display area AA. The third sub-segment PVEE 31 is located in the non-display area NA near the lower side of the display area AA, and the fourth sub-segment PVEE 32 is located in the non-display area NA near the upper side of the display area AA. In some other embodiments, the driver chip, the third sub-segment PVEE 31, and the fourth sub-segment PVEE 32 may be located in other positions near the display area AA within the non-display area NA; this is not limited here.

[0147] In this configuration, the first end of the first power signal line PVEE1 is electrically connected to the third sub-segment PVEE31. The second end of the first power signal line PVEE1 is electrically connected to the fourth sub-segment PVEE32. For example, the first power signal line PVEE1 and the third sub-segment PVEE31 overlap, and the first power signal line PVEE1 can be electrically connected to the third sub-segment PVEE31 through a third connecting portion such as a through-hole; similarly, the first power signal line PVEE1 and the fourth sub-segment PVEE32 overlap, and the first power signal line PVEE1 can be electrically connected to the fourth sub-segment PVEE32 through a fourth connecting portion such as a through-hole. Thus, by achieving an electrical connection between the first power signal line PVEE1 and the third power signal line PVEE32, the first power signal can be transmitted from the driving chip to the first electrode of the light-emitting element D, which helps improve the display uniformity of the display panel 1 and thus enhances the display effect.

[0148] Please continue reading. Figures 16 to 20 In some embodiments, the third sub-segment PVEE31 and the fourth sub-segment PVEE32 are arranged in different layers. The third sub-segment PVEE31 and the fourth sub-segment PVEE32 are two signal lines with different extension directions constituting the third power signal line PVEE3. The third sub-segment PVEE31 and the fourth sub-segment PVEE32 are located in different film layers, which helps reduce the difficulty of signal line layout.

[0149] For example, the display panel 1 further includes a substrate 010, a first conductive layer 014, a second conductive layer 016, a third conductive layer 022, and a fourth conductive layer 24, which are stacked sequentially; wherein, the third sub-segment PVEE 31 is located in the third conductive layer 022, and the fourth sub-segment PVEE 32 is located in the fourth conductive layer 024. In some other embodiments, the third sub-segment PVEE 31 and the fourth sub-segment PVEE 32 may be located in other conductive layers of the display panel 1. For example, the third sub-segment PVEE 31 may be located in the fourth conductive layer 024, and the fourth sub-segment PVEE 32 may be located in the third conductive layer 022; this is not limited here.

[0150] The third sub-segment PVEE31 is arranged on the same layer as the first power signal line PVEE1. This arrangement allows the first power signal line PVEE1 to be directly electrically connected to the third sub-segment PVEE31, thus achieving electrical connection with the driver chip. This reduces the total number of conductive layers occupied by the third sub-segment PVEE31 and the first power signal line PVEE1, thereby reducing the number of power signal lines (PVEE). This facilitates a thinner and lighter design for the display panel 1, improves the utilization rate of the film layer, enhances the uniformity of the film layer wiring, and ultimately improves the electrical performance uniformity of the display panel 1, ultimately enhancing the display effect.

[0151] For example, the third segment PVEE31 and the first power signal line PVEE1 are located on the second conductive layer 016M2. In some other embodiments, the third segment PVEE31 and the first power signal line PVEE1 may be located on other conductive layers of the display panel 1, which is not limited here.

[0152] Please continue reading. Figure 3 In some embodiments, the pixel circuit 100 may further include a data writing transistor M3, a first light-emitting control transistor M4, a second light-emitting control transistor M5, a threshold compensation transistor M6, and a capacitor Cst. The gate of the data writing transistor M3 may be electrically connected to the second scan signal line Scan2, and the first terminal of the data writing transistor M3 may be electrically connected to the second node N2, the first terminal of the driving transistor M0, and the second terminal of the first light-emitting control transistor M4, respectively. The signal line may further include a data signal line, wherein the second terminal of the data writing transistor M3 may be electrically connected to the data signal line, and the data signal line may be configured to provide a data signal to the second terminal of the data writing transistor M3. The data writing transistor M3 may transmit the data signal to the first terminal of the driving transistor M0 in response to the enable level of the second scan signal.

[0153] The signal line may further include a light-emitting control signal line Emit, wherein the gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 can be electrically connected to the light-emitting control signal line Emit, respectively. The light-emitting control signal line Emit can be configured to provide light-emitting control signals to the gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5, respectively. The signal line may further include a fourth power supply signal line PVDD, wherein the first terminal of the first light-emitting control transistor M4 can be electrically connected to the first terminal of the capacitor Cst and the fourth power supply signal line PVDD, respectively. The fourth power supply signal line PVDD can be configured to provide a second power supply signal to the first terminal of the first light-emitting control transistor M4. The first terminal of the second light-emitting control transistor M5 is electrically connected to the third node N3, the second terminal of the driving transistor M0, and the second terminal of the threshold compensation transistor M6, respectively. The second terminal of the second light-emitting control transistor M5 is electrically connected to the second terminal of the anode reset transistor M2 and the first electrode of the light-emitting element D, respectively. The first light-emitting control transistor M4 and the second light-emitting control transistor M5 can control the light-emitting element D to emit light in response to the enable level of the light-emitting control signal. The second power supply signal is different from the first power supply signal.

[0154] The gate of the threshold compensation transistor M6 can be electrically connected to the second scan signal line Scan2, and the second scan signal line Scan2 can also be configured to provide a second scan signal to the gate of the threshold compensation transistor M6. The first terminal of the threshold compensation transistor M6 is electrically connected to the first node N1, the second terminal of the gate reset transistor M1, the gate of the driving transistor M0, and the second terminal of the capacitor Cst. The threshold compensation transistor M6 can compensate for the threshold voltage of the driving transistor M0 in response to the enable level of the third scan signal.

[0155] The threshold compensation transistor M6 can be one or more. For example, the threshold compensation transistor M6 includes a first threshold compensation transistor and a second threshold compensation transistor, wherein the gates of the first and second threshold compensation transistors are electrically connected to the second scan signal line Scan2, the first terminal of the first threshold compensation transistor is electrically connected to the first node N1, the second terminal of the first threshold compensation transistor is electrically connected to the fifth node N5 and the first terminal of the second threshold compensation transistor, and the second terminal of the second threshold compensation transistor is electrically connected to the third node N3.

[0156] Pixel circuit 100 may include P-type transistors. Alternatively, pixel circuit 100 may include both P-type and N-type transistors. Each transistor in pixel circuit 100 may be a metal-oxide-semiconductor field-effect transistor (MOS) or a thin-film transistor (TFT). For example, each transistor in pixel circuit 100 may be a P-type transistor, such as a PMOS or PTFT. As another example, the gate reset transistor M1 and threshold compensation transistor M6 in pixel circuit 100 may both be N-type transistors, such as an NMOS or NTFT; the driving transistor M0, anode reset transistor M2, data writing transistor M3, first light-emitting control transistor M4, and second light-emitting control transistor M5 may all be P-type transistors, such as a PMOS or PTFT.

[0157] Pixel circuit 100 may include low-temperature poly-silicon (LTPS) transistors. Alternatively, pixel circuit 100 may include LTPS transistors and oxide transistors; for example, the oxide may be indium gallium zinc oxide (IGZO). Exemplarily, each transistor in pixel circuit 100 may be a LTPS transistor. In another embodiment, the gate reset transistor M1 and threshold compensation transistor M6 in pixel circuit 100 may both be oxide transistors, while the drive transistor M0, anode reset transistor M2, data write transistor M3, first light-emitting control transistor M4, and second light-emitting control transistor M5 may all be LTPS transistors.

[0158] It should be noted that the pixel circuit 100 can be the 7T1C structure provided above, where "T" represents a transistor and "C" represents a capacitor Cst. The pixel circuit 100 can also be any other suitable structure, such as 8T1C, 9T1C, 7T2C, etc., without specific limitations here.

[0159] Based on the same concept, this application also provides a display device. Figure 21 This is a schematic diagram of the structure of the display device 2 provided in the embodiments of this application, as shown below. Figure 21 As shown, the display device 2 includes the display panel 1 in any of the above embodiments. Exemplarily, as... Figure 21 As shown, the display device 2 includes a display panel 1. Therefore, the display device 2 also has the beneficial effects of the display panel 1 in the above embodiments. The similarities can be understood with reference to the explanation of the display panel 1 above, and will not be repeated below.

[0160] The display device 2 provided in this embodiment can be... Figure 21 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0161] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0162] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: Pixel circuitry, light-emitting elements, and signal lines; The pixel circuit includes a driving transistor, a gate reset transistor, and an anode reset transistor; the signal lines include a gate reset signal line, an anode reset signal line, and a power supply signal line; the first terminal of the gate reset transistor is electrically connected to the gate reset signal line, the second terminal of the gate reset transistor is electrically connected to the gate of the driving transistor, the first terminal of the anode reset transistor is electrically connected to the anode reset signal line, the second terminal of the anode reset transistor is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the power supply signal line; wherein... The gate reset signal line includes a first gate reset signal line extending along a first direction and a second gate reset signal line extending along a second direction; wherein, the first gate reset signal line includes a plurality of first sub-segments extending along the first direction, and the first sub-segments are electrically connected to the second gate reset signal line; the first direction intersects the second direction; The anode reset signal line includes a first anode reset signal line extending along a first direction and a second anode reset signal line extending along a second direction; wherein, the first anode reset signal line includes a plurality of second sub-segments extending along the first direction, and the second sub-segments are electrically connected to the second anode reset signal line; The power signal line includes a first power signal line extending along a first direction and arranged along a second direction; along the first direction and the second direction, the first sub-segment and the second sub-segment are alternately arranged.

2. The display panel according to claim 1, characterized in that, Along the second direction, the second anode reset signal line and the second gate reset signal line respectively penetrate the display area of ​​the display panel; Along the first direction, the first power signal line passes through the display area of ​​the display panel.

3. The display panel according to claim 2, characterized in that, Along the second direction, a first power signal line is included between any adjacent first sub-segment and second sub-segment.

4. The display panel according to claim 1, characterized in that, The second gate reset signal line and the second anode reset signal line are alternately arranged along the first direction.

5. The display panel according to claim 1, characterized in that, The first sub-segment overlaps with the second gate reset signal line in a third direction; wherein, the third direction is perpendicular to the plane containing the first direction and the second direction; wherein, The overlapping second gate reset signal lines of the plurality of first sub-segments arranged along the second direction are identical; The overlapping second gate reset signal lines of the plurality of first sub-segments arranged along the first direction are different.

6. The display panel according to claim 1, characterized in that, The second sub-segment overlaps with the second anode reset signal line in a third direction; wherein, the third direction is perpendicular to the plane containing the first direction and the second direction; wherein, The multiple second sub-segments arranged along the second direction have the same overlapping second anode reset signal lines; The multiple second sub-segments arranged along the first direction have different overlapping second anode reset signal lines.

7. The display panel according to claim 1, characterized in that, The power signal line further includes a second power signal line extending along the second direction and arranged along the first direction, wherein the first power signal line is electrically connected to the second power signal line. Along the second direction, the second power signal line passes through the display area of ​​the display panel.

8. The display panel according to claim 7, characterized in that, The display panel also includes a plurality of signal line groups arranged along the first direction, the signal line groups including a second gate reset signal line, a second anode reset signal line and a second power supply signal line.

9. The display panel according to claim 7, characterized in that, The first sub-segment and the second sub-segment overlap with the second power signal line in a third direction; wherein, the third direction is perpendicular to the plane containing the first direction and the second direction; wherein... The overlapping second power signal lines of the plurality of first sub-segments arranged along the second direction are the same; the overlapping second power signal lines of the plurality of first sub-segments arranged along the first direction are different. The overlapping second power signal lines of the plurality of second sub-segments arranged along the second direction are the same; the overlapping second power signal lines of the plurality of second sub-segments arranged along the first direction are different.

10. The display panel according to claim 1, characterized in that, Along the first direction, in the same column of pixel circuits, the number of pixel circuits is N10; the number of the first sub-segment corresponding to the pixel circuit in that column is N11, and the number of the second sub-segment is N12; wherein, N10≥N11+N12, and N10, N11 and N12 are all positive integers.

11. The display panel according to claim 1, characterized in that, Along the second direction, in the same row of pixel circuits, the number of pixel circuits is N20, the number of the first gate reset signal lines corresponding to the pixel circuits in that row is N21, the number of the first anode reset signal lines is N22, and the number of the first power supply signal lines is N23; wherein, N20≥N21, N20≥N22, N20≥N23, and N20, N21, N22, and N23 are all positive integers.

12. The display panel according to claim 11, characterized in that, N21=N22=N23, N20≥N21+N23.

13. The display panel according to claim 1, characterized in that, Along the first direction, in the same column of pixel circuits, the number of pixel circuits is N30, the number of second gate reset signal lines corresponding to the pixel circuits in that column is N31, and the number of second anode reset signal lines is N32; wherein, N30≥N31, N30≥N32, and N30, N31, and N32 are all positive integers.

14. The display panel according to claim 13, characterized in that, The power signal line includes a first power signal line and a second power signal line extending along the second direction and arranged along the first direction, wherein the number of the second power signal lines is N33, N30≥N33, and N33 is a positive integer.

15. The display panel according to claim 14, characterized in that, N31=N32=N33.

16. The display panel according to any one of claims 1-15, characterized in that, The display panel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, each emitting a different color. The first sub-pixel and the second sub-pixel form a first virtual quadrilateral. The center of the first sub-pixel is located at the first vertex of the first virtual quadrilateral, and the center of the second sub-pixel is located at the second vertex of the first virtual quadrilateral. The first vertex and the second vertex are alternately set, and the third sub-pixel is located inside the first virtual quadrilateral. The third sub-pixel forms a second virtual quadrilateral, the center of the third sub-pixel is located at a vertex of the second virtual quadrilateral, and either the first sub-pixel or the second sub-pixel is located inside the second virtual quadrilateral; Wherein, the first power signal line overlaps at least with the pixel circuit of the third sub-pixel; the first sub-segment overlaps at least with the pixel circuit of the first sub-pixel, and the second sub-segment overlaps at least with the pixel circuit of the second sub-pixel; or, the first sub-segment overlaps at least with the pixel circuit of the second sub-pixel, and the second sub-segment overlaps at least with the pixel circuit of the first sub-pixel.

17. The display panel according to claim 16, characterized in that, The first sub-pixel, the second sub-pixel, and the third sub-pixel are each one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and each is different.

18. The display panel according to any one of claims 1-15, characterized in that, The first gate reset signal line and the second gate reset signal line are disposed on different layers; The first anode reset signal line and the second anode reset signal line are arranged in different layers.

19. The display panel according to claim 18, characterized in that, The first gate reset signal line, the first anode reset signal line, and the first power supply signal line are disposed on the same layer; The second gate reset signal line and the second anode reset signal line are disposed on the same layer.

20. The display panel according to claim 19, characterized in that, The display panel further includes a substrate, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence; in; The first gate reset signal line, the first anode reset signal line, and the first power supply signal line are respectively located in the third conductive layer; the second gate reset signal line and the second anode reset signal line are respectively located in the second conductive layer.

21. The display panel according to any one of claims 7-9, characterized in that, The first power signal line and the second power signal line are arranged on different layers.

22. The display panel according to claim 21, characterized in that, The first power signal line is disposed on the same layer as the first gate reset signal line and the first anode reset signal line, respectively; the second power signal line is disposed on the same layer as the second gate reset signal line and the second anode reset signal line, respectively.

23. The display panel according to claim 22, characterized in that, The display panel further includes a substrate, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence; in; The first gate reset signal line, the first anode reset signal line, and the first power supply signal line are respectively located in the third conductive layer; the second gate reset signal line, the second anode reset signal line, and the second power supply signal line are respectively located in the second conductive layer.

24. The display panel according to any one of claims 1-15, characterized in that, The display panel further includes a first connecting portion and a second connecting portion, wherein the first segment is electrically connected to the second gate reset signal line through the first connecting portion, and the second segment is electrically connected to the second anode reset signal line through the second connecting portion.

25. The display panel according to any one of claims 1-15, characterized in that, The display panel includes a display area and a non-display area, wherein the non-display area is located around the periphery of the display area; wherein... The display panel also includes a third power signal line located in the non-display area, and the first power signal line is electrically connected to the driver chip through the third power signal line.

26. The display panel according to claim 25, characterized in that, The third power signal line includes a third sub-segment and a fourth sub-segment electrically connected. The third sub-segment and the fourth sub-segment are respectively located on opposite sides of the non-display area of ​​the display area. The third sub-segment is positioned closer to the driver chip, and the fourth sub-segment is positioned further away from the driver chip. The first end of the first power signal line is electrically connected to the third sub-segment, and the second end of the first power signal line is electrically connected to the fourth sub-segment.

27. The display panel according to claim 26, characterized in that, The third sub-segment and the fourth sub-segment are arranged on different layers; the third sub-segment is arranged on the same layer as the first power signal line.

28. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 27.

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