Storage device

Abstract

The invention provides a storage device with high reliability of data reading. In a memory device including a first transistor and a second transistor in a memory cell, a vertical transistor having a channel formation region on a side surface of an opening provided in an insulating layer and occupying a small area is used as two transistors. According to the present invention, the transistor and the wiring used in the memory cell have an appropriate structure, so that the electrostatic capacitance of the parasitic capacitance generated between the data holding node and the wiring can be reduced, and the reliability of data reading can be improved.

Description

Technical Field

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a storage device, and an electronic device. In addition, one aspect of the present invention relates to a method for manufacturing a semiconductor device. In addition, one aspect of the present invention relates to a semiconductor wafer and a module.

[0002] Note that, in this specification and the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are also one aspect of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc. sometimes include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Background Art

[0004] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on printed circuit boards and the like and are used as one of the components of various electronic devices. In addition, a technique of forming a transistor using a semiconductor thin film has attracted attention. This transistor has been applied to electronic devices such as image display devices (sometimes simply referred to as display devices), and its application to the above semiconductor circuits is expected.

[0005] As a semiconductor thin film that can be applied to a transistor, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention. It is known that the current flowing when a transistor using an oxide semiconductor is in a non-conducting state (off state) is extremely small.

[0006] For example, Patent Document 1 discloses a storage device and the like that utilize the characteristic of small leakage current of a transistor using an oxide semiconductor to achieve long-term retention of stored content.

[0007] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high density of integrated circuits has increased. For example, Patent Document 2 and Non-Patent Document 1 disclose a technique in which a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film are stacked, and a plurality of storage units are overlapped to increase the density of the integrated circuit.

[0008] Also, if a vertical transistor can be realized, high density of an integrated circuit can be achieved. For example, Patent Document 3 discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode with a gate insulator interposed therebetween. [Prior Art Documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 2] International Patent Application Publication No. 2021 / 053473 [Patent Document 3] Japanese Patent Application Laid-Open No. 2013-211537 [Non-Patent Documents]

[0010] [Non-Patent Document 1] M. Oota, et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53 Summary of the Invention Technical Problem to be Solved by the Invention

[0011] The memory cell disclosed in Patent Document 1 includes a writing transistor and a reading transistor. By flowing a current corresponding to a data potential held in the gate through the reading transistor, the potential of a bit line (read line) is changed.

[0012] This memory cell does not require a large-capacity capacitor to be provided in the cell as in DRAM, and thus a highly integrated memory device (memory) can be formed. By appropriately arranging the components included in the memory cell in a two-dimensional manner and a three-dimensional manner, the integration degree can be further improved, and thus a memory device (memory) with a large storage capacity can be formed.

[0013] On the other hand, by increasing the miniaturization and integration degree of the memory cell, the influence of parasitic capacitance due to overlap of wirings or the like becomes larger. Sometimes, the data potential held changes due to capacitive coupling of the parasitic capacitance, thereby reducing the reliability of data reading.

[0014] Accordingly, one of the objectives of one embodiment of the present invention is to provide a storage device with high reliability in data reading. Additionally, one of the objectives of one embodiment of the present invention is to provide a storage device that can achieve high integration. Additionally, one of the objectives of one embodiment of the present invention is to provide a storage device with good electrical characteristics. Additionally, one of the objectives of one embodiment of the present invention is to provide a storage device with high reliability. Additionally, one of the objectives of one embodiment of the present invention is to provide a storage device with low power consumption. Additionally, one of the objectives of one embodiment of the present invention is to provide a novel storage device. Additionally, one of the objectives of one embodiment of the present invention is to provide a novel semiconductor device, etc.

[0015] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the present invention does not need to achieve all of the above objectives. Note that objectives other than the above can be known and extracted from the descriptions in the specification, drawings, claims, etc. Means for Solving Technical Problems

[0016] One embodiment of the present invention is a storage device, which includes a storage cell, a first wiring, a second wiring, and a third wiring. The storage cell includes a first transistor and a second transistor. The second transistor is disposed above the first transistor. The first transistor includes a first semiconductor, a first insulator, and a first conductor. The first semiconductor has a region formed on the side surface of a first opening that penetrates the first wiring, a second insulator, and the second wiring. The first insulator has a region that covers the first opening in contact with the first semiconductor. The first conductor is disposed in such a manner that it is embedded in the first opening in contact with the first insulator. The second transistor includes a second semiconductor. The second semiconductor has a region disposed on the side surface of a second opening that penetrates a third insulator and the third wiring. The second semiconductor has a region that contacts the first conductor at the bottom of the second opening.

[0017] The second wiring can be disposed on the second insulator, and the second insulator can be disposed on the first wiring.

[0018] The second transistor can include a fourth insulator and a second conductor. The fourth insulator can have a region that covers the second opening in contact with the second semiconductor. The second conductor can be disposed in such a manner that it is embedded in the second opening in contact with the fourth insulator.

[0019] The third wiring can be disposed on the third insulator, and the third insulator can be disposed on the first conductor.

[0020] The first wiring may have a region serving as one of the source electrode and the drain electrode of the first transistor, the second wiring may have a region serving as the other of the source electrode and the drain electrode of the first transistor, the third wiring may have a region serving as one of the source electrode and the drain electrode of the second transistor, and the first conductor may have a region serving as the gate electrode of the first transistor and a region serving as the other of the source electrode and the drain electrode of the second transistor.

[0021] Another aspect of the present invention is a storage device including a storage cell, a first wiring, a second wiring, and a third wiring. The storage cell includes a first transistor and a second transistor. The second transistor is disposed above the first transistor. The first transistor includes a first semiconductor, a first insulator, and a first conductor. The first semiconductor has a region formed on a side surface of a first opening penetrating the first wiring, a second insulator, the second wiring, and a third insulator. The first insulator has a region covering the first opening in contact with the first semiconductor. The first conductor is disposed to be embedded in the first opening in contact with the first insulator. The second transistor includes a second semiconductor. The second semiconductor has a region disposed on a side surface of a second opening penetrating a fourth insulator and the third wiring. The second semiconductor has a region in contact with the first conductor at the bottom of the second opening.

[0022] The third insulator may be disposed on the second wiring, the second wiring may be disposed on the second insulator, and the second insulator may be disposed on the first wiring.

[0023] The second transistor may include a fifth insulator and a second conductor. The fifth insulator may have a region covering the second opening in contact with the second semiconductor. The second conductor may be disposed to be embedded in the second opening in contact with the fifth insulator.

[0024] The third wiring may be disposed on the fourth insulator, and the fourth insulator may be disposed on the first conductor.

[0025] The first wiring may have a region serving as one of the source electrode and the drain electrode of the first transistor, the second wiring may have a region serving as the other of the source electrode and the drain electrode of the first transistor, the third wiring may have a region serving as one of the source electrode and the drain electrode of the second transistor, and the first conductor may have a region serving as the gate electrode of the first transistor and a region serving as the other of the source electrode and the drain electrode of the second transistor.

[0026] Another aspect of the present invention is a storage device, which includes a storage unit, a first wiring, a second wiring, a third wiring, and a fourth wiring. The storage unit includes a first transistor, a second transistor, and a capacitor. The capacitor is disposed between the first transistor and the second transistor. The first transistor includes a first semiconductor, a first insulator, and a first conductor. The first semiconductor has a region formed on the side surface of a first opening penetrating through the first wiring, a second insulator, and the second wiring. The first insulator has a region covering the first opening in contact with the first semiconductor. The first conductor is disposed in a manner of being embedded in the first opening in contact with the first insulator. The capacitor includes a third insulator and a second conductor. The third insulator has a region formed on the side surface of a second opening penetrating through a fourth insulator and the third wiring. The second conductor is disposed in a manner of being embedded in the second opening in contact with the third insulator. The second conductor has a region in contact with the first conductor at the bottom of the second opening. The second transistor includes a second semiconductor. The second semiconductor has a region disposed on the side surface of a third opening penetrating through a fifth insulator and the fourth wiring. The second semiconductor has a region in contact with the second conductor at the bottom of the third opening.

[0027] The second wiring may be disposed on the second insulator, the second insulator may be disposed on the first wiring, and the third wiring may be disposed on the fourth insulator.

[0028] The second transistor may include a sixth insulator and a third conductor. The sixth insulator may have a region covering the third opening in contact with the second semiconductor. The third conductor may be disposed in a manner of being embedded in the third opening in contact with the sixth insulator.

[0029] The fourth wiring may be disposed on the fifth insulator, and the fifth insulator may be disposed on the second conductor.

[0030] The first wiring may have a region serving as one of the source electrode and the drain electrode of the first transistor. The second wiring may have a region serving as the other of the source electrode and the drain electrode of the first transistor. The third wiring has a region serving as one electrode of the capacitor. The fourth wiring may have a region serving as one of the source electrode and the drain electrode of the second transistor. The first conductor may have a region serving as the gate electrode of the first transistor. The second conductor may have a region serving as the other electrode of the capacitor and a region serving as the other of the source electrode and the drain electrode of the second transistor.

[0031] In the above storage device, preferably, both the first semiconductor and the second semiconductor are oxide semiconductors, and the oxide semiconductor contains any one or more selected from In, Ga, and Zn. Advantages of the Invention

[0032] According to one aspect of the present invention, a storage device with high reliability in data reading can be provided. In addition, according to one aspect of the present invention, a storage device capable of achieving high integration can be provided. In addition, according to one aspect of the present invention, a storage device having good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a storage device with high reliability can be provided. In addition, according to one aspect of the present invention, a storage device with low power consumption can be provided. In addition, according to one aspect of the present invention, a novel storage device can be provided. In addition, according to one aspect of the present invention, a novel semiconductor device or the like can be provided.

[0033] Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the descriptions in the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a diagram illustrating the storage device. Figures 2A to 2C is a circuit diagram illustrating the memory cell. Figure 3 is a timing diagram illustrating the operation of the memory cell. Figure 4 is a timing diagram illustrating the operation of the memory cell. Figure 5 is a timing diagram illustrating the operation of the memory cell. Figure 6A and Figure 6B is a perspective view illustrating the memory cell. Figure 7A and Figure 7B is a top view illustrating the memory cell. Figures 7C to 7E is a cross-sectional view illustrating the memory cell. Figure 8A is a perspective view illustrating the memory cell. Figure 8B and Figure 8C is a cross-sectional view illustrating the memory cell. Figure 9A is a perspective view illustrating the memory cell. Figure 9B and Figure 9C is a cross-sectional view illustrating the memory cell. Figure 10A is a sectional perspective view illustrating the memory cell. Figure 10B and Figure 10C is a cross-sectional view illustrating the memory cell. Figure 11A and Figure 11B is a perspective view illustrating the memory cell. Figure 12A is a sectional perspective view illustrating the memory cell.Figure 12B and Figure 12C is a cross-sectional view illustrating a memory cell. Figure 13A and Figure 13B is a perspective view illustrating a memory cell. Figure 14A and Figure 14B is a view illustrating a transistor. Figure 15A and Figure 15B is a view illustrating a structural example of a memory device. Figure 16A and Figure 16B is a view illustrating an example of an electronic component. Figure 17A and Figure 17B is a view illustrating an example of an electronic device. Figures 17C to 17E is a view illustrating an example of a mainframe computer. Figure 18 is a view illustrating an example of a space device. Figure 19 is a view illustrating an example of a storage system that can be used in a data center. Mode for Carrying Out the Invention

[0035] Hereinafter, embodiments will be described with reference to the drawings. Note that it is easily understandable to those of ordinary skill in the art that the embodiments can be implemented in multiple different forms, and the ways and details thereof can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the embodiments shown below.

[0036] In addition, in the drawings, the same reference numerals are sometimes used commonly between different drawings to denote the same parts or parts having the same functions, and the repeated description thereof is omitted. Further, when denoting parts having the same functions, the same hatching is sometimes used without particularly attaching reference numerals.

[0037] Note that in this specification and the like, oxynitride refers to a substance having more oxygen content than nitrogen content in its composition. Examples of oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride. In addition, nitride oxide refers to a substance having more nitrogen content than oxygen content in its composition. Examples of nitride oxide include silicon oxynitride, aluminum nitride oxide, and hafnium nitride oxide.

[0038] In addition, in this specification and the like, "insulator" can be replaced with insulating film or insulating layer. In addition, "conductor" can be replaced with conductive film or conductive layer. In addition, "semiconductor" can be replaced with semiconductor film or semiconductor layer.

[0039] In addition, in this specification and the like, "parallel" means a state where the angle formed by two straight lines is -10 degrees or more and 10 degrees or less. Therefore, it also includes the state where the angle is -5 degrees or more and 5 degrees or less. In addition, "substantially parallel" means a state where the angle formed by two straight lines is -30 degrees or more and 30 degrees or less. Further, "perpendicular" means a state where the angle formed by two straight lines is 80 degrees or more and 100 degrees or less. Therefore, it also includes the state where the angle is 85 degrees or more and 95 degrees or less. In addition, "substantially perpendicular" means a state where the angle formed by two straight lines is 60 degrees or more and 120 degrees or less. Further, "orthogonal" means a state where two straight lines cross or connect at an angle of 80° or more and 100° or less. Therefore, it also includes the state where the angle is 85° or more and 95° or less. Further, "substantially orthogonal" means a state where two straight lines cross or connect at an angle of 60° or more and 120° or less.

[0040] Note that sometimes arrows indicating the X direction, Y direction, and Z direction are attached to the drawings in this specification. Note that in this specification and the like, the "X direction" means the direction along the X axis, and except in cases where it is clearly specified, the forward and reverse directions are sometimes not distinguished. The same applies to the "Y direction" and "Z direction". In addition, the X direction, Y direction, and Z direction are directions that cross each other. Specifically, the X direction, Y direction, and Z direction are directions that are orthogonal to each other. In this specification and the like, the X direction, Y direction, or Z direction is sometimes referred to as the "first direction". In addition, sometimes the other one is referred to as the "second direction". In addition, sometimes the remaining one is referred to as the "third direction".

[0041] In addition, in this specification and the like, for convenience, words and phrases indicating configuration such as "upper" and "lower" are used to describe the positional relationship of the constituent elements with reference to the drawings. In addition, the positional relationship of the constituent elements is appropriately changed according to the directions describing each configuration. Therefore, it is not limited to the words and phrases described in the specification, and the words and phrases can be appropriately changed according to the situation.

[0042] (Embodiment 1) In this embodiment, a storage device according to one aspect of the present invention will be described. In the storage device according to one aspect of the present invention, the storage unit includes a first transistor and a second transistor.

[0043] As the two transistors, vertical transistors having channel formation regions along the side surfaces of the openings in the insulator are used. Since the vertical transistors can have a structure with a short channel length and a long channel width, the on-state current can be increased. In addition, the vertical transistors can reduce the occupied area when viewed from above. Therefore, by using vertical transistors for the storage unit, a storage device capable of high-speed operation and high integration can be formed.

[0044] A memory cell is connected to a plurality of wirings, and parasitic capacitances are generated between the respective wirings and the data holding section of the memory cell. Due to the capacitive coupling of these parasitic capacitances, the potential of the data holding section sometimes varies with the change in the potential of the wiring, thereby reducing the reliability of data readout. In a memory device according to one embodiment of the present invention, by adopting an appropriate structure of the memory cell, the electrostatic capacitance of the parasitic capacitance can be reduced, and thereby the reliability of data readout can be improved.

[0045] Figure 1 FIG. 4 is a perspective view showing a part of a memory device according to one embodiment of the present invention, showing a plurality of memory cells 150 (transistors 100, transistors 200). The transistors 100 and 200 are vertical transistors, and the transistor 200 is provided above the transistor 100. The memory cell 150 is electrically connected to the wirings 110, 140, 240, and 210. Note that, in Figure 1 FIG. 4, for clarity, the interlayer film and other insulators are not shown, and the topmost wiring 210 is shown by a dashed line.

[0046] The transistor 100 includes, as constituent elements, the wiring 110, the wiring 140, and the conductor 120. The transistor 200 includes, as constituent elements, the conductor 120, the wiring 240, and the conductor 220.

[0047] The wiring 110 has a region serving as one of the source electrode and the drain electrode of the transistor 100. The wiring 140 has a region serving as the other of the source electrode and the drain electrode of the transistor 100.

[0048] The conductor 120 has a region serving as the gate electrode of the transistor 100 and a region serving as one of the source electrode and the drain electrode of the transistor 200. In other words, the conductor 120 has a region serving both as the gate electrode of the transistor 100 and as one of the source electrode and the drain electrode of the transistor 200.

[0049] The wiring 240 has a region serving as the other of the source electrode and the drain electrode of the transistor 200.

[0050] The conductor 220 has a region serving as the gate electrode of the transistor 200 and is electrically connected to the wiring 210 formed on the conductor 220. In addition, the conductor 220 and the wiring 210 may be formed as the same constituent element. The structure and connection shape of each transistor will be described in detail later.

[0051] Note that Figure 1 FIG. 4 shows an example in which the memory cells 150 are arranged at equal intervals in the X direction and the Y direction, but a staggered arrangement in which the memory cells 150 are arranged in a manner of being alternately staggered one by one may also be adopted.

[0052] Figure 2AThis is a diagram showing an example of the circuit diagram of the storage cell 150. The transistor 100 has the function of reading out data. The transistor 200 has the function of writing data.

[0053] One of the source and drain of the transistor 200 is connected to the gate of the transistor 100. In Figure 1 the conductor 120 has this connection structure. Figure 2A In the storage cell 150 shown, it can also be said that the conductor 120 is a component of the node SN that holds the data potential.

[0054] The wiring 210 connected to the gate of the transistor 200 is the wiring that supplies the write word signal to the storage cell 150, and the wiring 210 is also called the write word line (WWL). The write word signal is a signal that controls the timing of writing data to the storage cell 150.

[0055] The wiring 240 connected to the other of the source and drain of the transistor 200 is the wiring that supplies the potential corresponding to the data signal (data) to the storage cell 150, and the wiring 240 is also called the write bit line (WBL). The data signal is a signal represented by two values of high level (also called "1" or V H ) or low level (also called "0" or V L ).

[0056] The wiring 110 connected to one of the source and drain of the transistor 100 is the wiring that supplies the read word signal to the storage cell 150, and the wiring 110 is also called the read word line (RWL). The read word signal is a signal that controls the timing of reading data from the storage cell 150.

[0057] The wiring 140 connected to the other of the source and drain of the transistor 100 is the wiring that reads the potential corresponding to the data signal (data) held in the storage cell 150, and the wiring 140 is also called the read bit line (RBL). Corresponding to the data ("1" or "0") written to the storage cell 150, current flows in the transistor 100 and the potential of the pre-charged wiring 140 changes. By inputting this potential to the read amplifier, data can be read out.

[0058] Here, the parasitic capacitance generated between the node SN and each wiring is described. As Figure 1 shown, when the conductor 120, which is a component of the node SN, is taken as the center, insulators (not shown) are provided between the conductor 120 and each wiring, and it can be said that a plurality of parasitic capacitances are formed.

[0059] Here, for simplicity of explanation, the parasitic capacitance generated between the node SN and one wiring is regarded as one parasitic capacitance for explanation. As Figure 2BAs shown, parasitic capacitance Cp1 is generated between node SN and wiring 210. Parasitic capacitance Cp2 is generated between node SN and wiring 240. Parasitic capacitance Cp3 is generated between node SN and wiring 110. Parasitic capacitance Cp4 is generated between node SN and wiring 140. Additionally, the constituent elements of each parasitic capacitance include the constituent elements of transistor 100 or transistor 200.

[0060] Since node SN is in a floating state, when the potential of each wiring changes, one or more of parasitic capacitances Cp1 to Cp4 are affected, and the potential of node SN also changes due to capacitive coupling. The amplitude of the change in the potential of node SN varies according to the amount of change in the potential of each wiring and the electrostatic capacitance of each parasitic capacitance. However, when the change in the potential of node SN is too large, transistor 100 cannot operate properly, and data may not be read accurately.

[0061] As one method for countering the effects of these parasitic capacitances, there is Figure 2C as shown, capacitor 300 is provided with one electrode connected to one of the source and drain of transistor 200 and the gate of transistor 100. The other electrode of capacitor 300 is connected to a wiring supplied with a fixed potential. By providing capacitor 300, the potential change of node SN due to parasitic capacitance can be suppressed to a small value, thereby improving the reading accuracy. Additionally, the data retention ability can be improved.

[0062] Note that one embodiment of the present invention can be applied to Figure 2A the circuit structure shown in Figure 2C and any one of the circuit structures shown in

[0063] Next, with reference to Figure 3 the operation of memory cell 150 will be described. Here, the ideal operation excluding the effects of each parasitic capacitance will be described. Figure 3 is to explain Figure 2A the timing diagram of an operation example of memory cell 150 shown in

[0064] During Figure 3 it shows: the potentials supplied to wiring 210 (WWL), wiring 240 (WBL), and wiring 110 (RWL); the potential read out to wiring 140 (RBL); and the potential of node SN. Additionally, during Figure 3 the standby state of wiring 240 (WBL) is set to a low level (V L ).

[0065] Period T1 is a preparation period. Period T2 is a write period. Period T3 is a preparation period. Periods T4 to T5 are read periods. Period T6 is a preparation period. Note that during Figure 3In [the figure], the data “1” or “0” written to the memory cell 150 (node SN) through the wiring 240 (WBL) is shown. As the data written to the memory cell 150, the data is “1” at a high level and the data is “0” at a low level.

[0066] Figure 3 The data “1” or “0” read out from the memory cell 150 through the wiring 140 (RBL) is shown. The wiring 140 (RBL) is pre-charged to a high-level potential (e.g., a high power supply potential such as VDD) during readout, and the data is read out to an external readout circuit connected to the wiring 140 (RBL) according to the change in the pre-charged potential.

[0067] When the data held in the memory cell 150 (node SN) is the data “1”, the current flowing through the transistor 100 is large, so the potential of the wiring 140 (RBL) decreases. When the data held in the memory cell 150 (node SN) is the data “0”, the current flowing through the transistor 100 is small, so the potential change of the wiring 140 (RBL) is small. Thus, when the data held in the memory cell 150 (node SN) is the data “1”, the potential of the wiring 140 (RBL) becomes a low level. In addition, when the data held in the memory cell 150 (node SN) is the data “0”, the potential of the wiring 140 (RBL) becomes a high level (the pre-charged potential).

[0068] During the period T1, the wiring 210 (WWL) is at a low level, the wiring 240 (WBL) is at a low level (V L ), the wiring 110 (RWL) is at a high level, and the wiring 140 (RBL) is at a high level. At this time, the transistor 200 becomes a non-conducting state. In addition, since the terminals between which the transistor 100 becomes a source or a drain are at an equal potential, no current flows. Also, the potential of the gate (node SN) of the transistor 100 is the potential V H or V L written during the previous write period.

[0069] During the period T2, the wiring 210 (WWL) is at a high level, the wiring 240 (WBL) is a signal according to the data (V H or V L ), the wiring 110 (RWL) is at a high level, and the wiring 140 (RBL) is at a high level. At this time, the transistor 200 becomes a conducting state, and the potential of the gate (node SN) of the transistor 100 becomes a potential according to the data. Since the terminals between which the transistor 100 becomes a source or a drain are at an equal potential, no current flows regardless of the potential of the gate.

[0070] During the period T3, the wiring 210 (WWL) is at a low level, the wiring 240 (WBL) is at a low level (VL ) The wiring 110 (RWL) is at a high level and the wiring 140 (RBL) is at a high level. At this time, the transistors 100 and 200 become non-conductive states. During the period T3, the potential written to the gate (node SN) of the transistor 100 is maintained. Since the terminals between which the source or drain of the transistor 100 becomes are at the same potential, no current flows regardless of the potential of the gate.

[0071] During the period T4, the wiring 210 (WWL) is at a low level and the wiring 240 (WBL) is at a low level (V L ) The wiring 110 (RWL) is at a high level. The wiring 140 (RBL) is pre-charged to a high level (also referred to as the pre-charge potential V PRE ). At this time, the transistor 200 becomes non-conductive. The pre-charge potential V PRE is, for example, VDD, that is, at the same potential as the high level of the wiring 140 (RBL). Since the terminals between which the source or drain of the transistor 100 becomes are at the same potential, no current flows regardless of the potential of the gate (node SN). That is, the potential of the wiring 140 does not change.

[0072] During the period T5, the wiring 210 (WWL) is at a low level and the wiring 240 (WBL) is at a low level (V L ), and the wiring 110 (RWL) is at a low level. At this time, the transistor 200 becomes non-conductive. In addition, during the period T5, the wiring 140 (RBL) is in a floating state. That is, the potential changes according to the current flowing through the transistor 100 of the memory cell 150.

[0073] During the period T5, since a potential difference is generated between the terminals between which the source or drain of the transistor 100 becomes, a current flows according to the potential of the gate (node SN) of the transistor 100. When the data held in the memory cell 150 is data "1", the current flowing through the transistor 100 is large and the potential of the wiring 140 (RBL) decreases to a low level. This change in the potential of the wiring 140 (RBL) can read out the data of the memory cell 150 selected by activating the sense amplifier connected to the wiring 140 (RBL) to the outside.

[0074] In addition, when the data held in the memory cell 150 is data "0", the current flowing through the transistor 100 is small and the potential of the wiring 140 (RBL) hardly changes from the high level (the pre-charged potential).

[0075] During the period T5, in the memory cells 150 of the non-selected row, the wiring 110 (RWL) is at a high level. Since the terminals between which the source or drain of the transistor 100 becomes are at the same potential, no current flows regardless of the potential of the gate.

[0076] During period T6, the wiring 210 (WWL) is at a low level, the wiring 240 (WBL) is at a low level (V L ), the wiring 110 (RWL) is at a high level, and the wiring 140 (RBL) is at a high level. At this time, the transistor 200 becomes non-conductive. Since the terminals that become the source or drain of the transistor 100 are at the same potential, no current flows regardless of the potential of the gate.

[0077] Through the above operations, data can be read from the memory cell 150 of the selected row.

[0078] Next, the influence of the parasitic capacitances Cp1 to Cp4 in the same operation will be described with reference to the Figure 4 shown timing chart. Note that although the actual electrostatic capacitances of the parasitic capacitances Cp1 to Cp4 are different, they are regarded as approximately equal here. In addition, Figure 3 the behavior of the potential change of the node SN due to the parasitic capacitance shown in Figure 4 is only an example, and sometimes it is slightly different from the actual change in magnitude and timing deviation, etc.

[0079] The process up to the data writing operation to the node SN in period T2 is the same as Figure 3 . Note that the potential of the node SN in period T1 is the potential corresponding to the potential written in the previous writing period.

[0080] In period T2, when the wiring 210 (WWL) is at a high level, the node SN becomes the potential corresponding to the data supplied to the wiring 240 (WBL) (“1” (V H ) or “0” (V L )).

[0081] And, in period T3, when the wiring 210 (WWL) is switched to a low level, the potential of the node SN decreases due to the capacitive coupling of the parasitic capacitance Cp1 (the parasitic capacitance between the node SN and the wiring 210 (WWL)).

[0082] Furthermore, when the data is data “1”, in period T3, the wiring 240 (WWL) is lowered to a low level (V L ), so the potential of the node SN corresponding to the data “1” further decreases due to the capacitive coupling using the parasitic capacitance Cp2 (the parasitic capacitance between the node SN and the wiring 240 (WBL)). Note that when the data is data “0”, the potential of the wiring 240 (WWL) remains unchanged, so the potential of the node SN remains unchanged.

[0083] During period T5, when the potential of wiring 110 (RWL) switches from high level to low level, the potential of node SN decreases due to capacitive coupling of parasitic capacitance Cp3 (the parasitic capacitance between node SN and wiring 110 (WWL)).

[0084] Furthermore, when the data is data "1", wiring 140 (RBL) decreases in a manner close to the low level (V L ), so the potential of node SN corresponding to data "1" gradually decreases due to capacitive coupling using parasitic capacitance Cp4 (the parasitic capacitance between node SN and wiring 140 (WBL)). Note that when the data is data "0", the potential of wiring 140 (WWL) remains unchanged, so the potential of node SN remains unchanged.

[0085] Furthermore, when the potential of wiring 110 (RWL) switches to high level, the potential of node SN rises due to capacitive coupling of parasitic capacitance Cp3.

[0086] In addition, when the data is data "1", when wiring 140 (RBL) becomes high level, the potential of node SN corresponding to data "1" rises due to capacitive coupling using parasitic capacitance Cp4. Note that when the data is data "0", the potential of wiring 140 (WWL) remains unchanged, so the potential of node SN remains unchanged.

[0087] In this way, the potential of node SN varies under the influence of parasitic capacitances Cp1 to Cp4. In particular, when writing data "1", until the data is read out, the potential of node SN decreases under the influence of all of parasitic capacitances Cp1 to Cp4, so the reliability of the read data may sometimes decrease.

[0088] In addition, in Figure 4 , the standby state of wiring 240 (WBL) is set to low level (V L ), but by setting the standby state to high level (V H ), the influence of a part of the parasitic capacitance can be avoided.

[0089] Figure 5 is the timing diagram when the standby state of wiring 240 (WBL) is set to high level (V H ).

[0090] At the start of period T3, until the potential of node SN decreases due to capacitive coupling of parasitic capacitance Cp1, it is the same as Figure 4 .

[0091] When the data is data "1", during period T3, the potential of wiring 240 (WWL) remains unchanged, so the potential of node SN remains unchanged. In addition, when the data is data "0", wiring 240 (WWL) switches to high level (VH ), so the potential of node SN corresponding to data "0" rises due to the capacitive coupling of parasitic capacitance Cp2.

[0092] Here, when the data is "0", since the potential of node SN decreased due to the capacitive coupling of parasitic capacitance Cp1 before, the capacitive coupling of parasitic capacitance Cp2 acts in the direction to offset the potential decrease of parasitic capacitance Cp1.

[0093] The subsequent potential variation of node SN due to parasitic capacitance is the same as Figure 4 the explanation of. Therefore, by setting the standby state of wiring 240 (WBL) to high level (V H ), the potential variation of node SN can be reduced.

[0094] When the data is "1", it is affected by parasitic capacitances Cp1, Cp3, and Cp4 until the data is read out. In addition, when the data is "0", it is affected by parasitic capacitances Cp1, Cp2, and Cp3 until the data is read out. Note that when the data is "0", parasitic capacitances Cp1 and Cp2 act to offset the potential variation of node SN due to each of parasitic capacitances Cp1 and Cp2, so it can also be said that it is only affected by parasitic capacitance Cp3.

[0095] Therefore, regardless of whether the data is "1" or "0", it can be said that the parasitic capacitance that most affects the potential variation of node SN is parasitic capacitance Cp3, and it is preferable to reduce the capacitance of parasitic capacitance Cp3. In addition, in order to reduce the influence when reading out data "1", it is preferable to also reduce the capacitance of parasitic capacitance Cp4.

[0096] <Example structure 1 of the memory cell> Next, an example structure of memory cell 150 will be described. Figure 6A is a perspective view showing Example structure 1 of memory cell 150. Note that for clarity, insulating layers such as interlayer films are not shown, and a part of wiring 110, wiring 140, and wiring 240 and wiring 210 are shown by dashed lines.

[0097] Figure 6A The shown memory cell 150 has the following structure: In transistor 100, a semiconductor layer (oxide semiconductor 170) is provided in the opening of wiring 110, and the side surface of wiring 110 in this opening is in contact with this semiconductor layer.

[0098] Note, Figure 6A shows an example where the width of wiring 110 is constant in the long side direction, but as Figure 6B shown, a structure where the width of wiring 110 becomes wider near the opening can also be adopted. The same structure can also be used for wiring 140 and wiring 240.

[0099] Figure 7A is a top view showing the transistor 100, Figure 7B is a top view showing the transistor 200. Note that, in the top view, some constituent elements are omitted for clarity. In addition, Figure 7A and Figure 7B the top views shown are the same in the structural examples of the other memory cells 150 described in the present embodiment.

[0100] Figure 7C corresponds to a cross-sectional view along the Figure 7A and Figure 7B shown line segment A1 - A2. Figure 7D corresponds to a cross-sectional view along the Figure 7A and Figure 7B shown line segment B1 - B2.

[0101] The memory cell 150 includes an insulator 160 on a substrate (not shown), a transistor 100 provided on the insulator 160, and a transistor 200 provided on the transistor 100. In addition, between the transistors and between various wirings, insulators 180, 185, 280, 285, etc. that serve as interlayer films can be provided.

[0102] The transistor 100 includes an oxide semiconductor 170, an insulator 130, and a conductor 120. The oxide semiconductor 170 is used as a semiconductor layer, the insulator 130 is used as a gate insulator, and the conductor 120 is used as a gate electrode. In addition, the wiring 110 has a region that serves as one of the source electrode and the drain electrode of the transistor 100. In addition, the wiring 140 has a region that serves as the other of the source electrode and the drain electrode of the transistor 100.

[0103] An opening 190 reaching the insulator 160 is provided so as to penetrate the wiring 140, the insulator 180, and the wiring 110. The top surface of the opening 190 has a substantially circular columnar shape. By adopting such a structure, miniaturization or high integration of the memory cell can be achieved. Note that the side surface of the opening 190 is preferably perpendicular to the top surface of the insulator 160.

[0104] At least a part of the oxide semiconductor 170 is disposed in the opening 190. The oxide semiconductor 170 has a region in contact with the side surface of the wiring 110 in the opening 190, a region in contact with the side surface of the wiring 140, a region in contact with the top surface of the insulator 160, and a region in contact with the side surface of the insulator 180.

[0105] The insulator 130 is arranged so as to cover at least a part of the opening 190. The conductor 120 is arranged so that at least a part of it is located in the opening 190. Note that the conductor 120 is preferably arranged to be embedded in the opening 190, and in order to improve the integration degree, the shape of its top surface is preferably substantially circular.

[0106] By adopting such a structure, the capacitance of the parasitic capacitance Cp3 between the conductor 120 (node SN) and the wiring 110 can be reduced.

[0107] As Figure 7E shown, when the opening 190 is not formed in the wiring 110, the top surface of the wiring 110 is exposed at the bottom of the opening 190. Therefore, a parasitic capacitance Cp3b is generated near the bottom of the opening 190. This parasitic capacitance Cp3b uses a region of the conductor 120 as one electrode, a region of the insulator 130 as the dielectric, and a region of the wiring 110 opposite to the bottom surface of the conductor 120 as the other electrode. At this time, the oxide semiconductor 170 is used as one or both of the dielectric and the other electrode.

[0108] In one mode of the present invention, by arranging the opening 190 so as to penetrate the wiring 110, a state can be formed in which there is no region of the wiring 110 opposite to the bottom surface of the conductor 120. That is to say, in the capacitance formula C = ε×S / d (ε: dielectric constant, S: electrode area, d: thickness of the dielectric), the value of the electrode area S is reduced (S becomes 0), and thus the value of C is reduced.

[0109] In Figure 7E the region where the parasitic capacitance Cp3b is formed as shown, the value of the thickness d of the dielectric is small, and the parasitic capacitance Cp3b becomes a relatively large capacitance. Since the parasitic capacitance Cp3b is a part of the parasitic capacitance Cp3, by adopting a structure in which the parasitic capacitance Cp3b is not formed, the capacitance of the parasitic capacitance Cp3 can be reduced.

[0110] Note that a region of the oxide semiconductor 170 opposite to the bottom surface of the conductor 120 does not contact the n-type components (such as the wiring 110), so its conductivity type is i-type (intrinsic) and the resistance is high. Therefore, it can be said that a region of the oxide semiconductor 170 opposite to the bottom surface of the conductor 120 is not easily a component (the other electrode) of the parasitic capacitance.

[0111] The transistor 200 includes an oxide semiconductor 270, an insulator 230, and a conductor 220. The oxide semiconductor 270 is used as a semiconductor layer, the insulator 230 is used as a gate insulator, and the conductor 220 is used as a gate electrode. In addition, the conductor 120 has a region that serves as one of the source electrode and the drain electrode of the transistor 200. In addition, the wiring 240 has a region that serves as the other of the source electrode and the drain electrode of the transistor 200.

[0112] An opening 290 reaching the conductor 120 is provided so as to penetrate the wiring 240 and the insulator 280. The top surface of the opening 290 has a substantially circular columnar shape. By adopting such a structure, miniaturization or high integration of the memory cell can be achieved. Note that the side surface of the opening 290 is preferably perpendicular to the top surface of the conductor 120.

[0113] At least a part of the oxide semiconductor 270 is disposed in the opening 290. The oxide semiconductor 270 has a region in contact with the top surface of the conductor 120, a region in contact with the side surface of the wiring 240, and a region in contact with the side surface of the insulator 280 in the opening 290.

[0114] The insulator 230 is disposed so as to cover at least a part of the opening 290. The conductor 220 is disposed so that at least a part of it is located in the opening 290. Note that the conductor 220 is preferably provided in a manner of being embedded in the opening 290, and for improving integration, the shape of its top surface is preferably substantially circular. In addition, a wiring 210 is disposed on the conductor 220. Note that the conductor 220 and the wiring 210 may also be formed as the same component.

[0115] The diameter of the opening 190 is substantially the same as the diameter of the opening 290, and the opening 190 and the opening 290 are preferably provided so as to overlap. In addition, in the memory cell 150, the width of the wiring 110 is substantially the same as the width of the wiring 210, and the wiring 110 and the wiring 210 are preferably provided so as to overlap. In addition, in the memory cell 150, the width of the wiring 140 is substantially the same as the width of the wiring 240, and the wiring 140 and the wiring 240 are preferably provided so as to overlap.

[0116] By adopting such a structure, two transistors can be provided without significantly increasing the cell area, so that the memory cells 150 can be arranged at a high density to increase the storage capacity of the storage device. In other words, high integration of the storage device can be achieved.

[0117] In addition, one of the source electrode and the drain electrode of the transistor 200 also serves as the gate electrode of the transistor 100, that is, the transistor 200 is directly connected to the transistor 100 instead of being connected through a wiring or the like. As a result, the resistance between the two can be minimized, and data writing and the like can be performed quickly.

[0118] <Example 2 of the structure of the storage cell> Next, Example 2 of the structure of the storage cell 150 will be described. Figure 8A FIG. is a perspective view showing Example 2 of the structure of the storage cell 150. For clarity, insulators such as the interlayer film are not shown, and a part of the wirings 110, 140, and 240 and the wiring 210 are shown by dashed lines.

[0119] Figure 8B is equivalent to Figure 7A 、 Figure 7B a cross-sectional view of the line segment A1 - A2 shown in FIG. Figure 8C is equivalent to Figure 7A 、 Figure 7B a cross-sectional view of the line segment B1 - B2 shown in FIG. Note that the description of the constituent elements common to Example 1 is omitted.

[0120] In Example 2, an opening 190 is formed in the wiring 110 in the same manner as in Example 1, and the electrostatic capacitance of the parasitic capacitance generated between the top of the conductor 120 and the wiring 110 is further reduced.

[0121] Since the conductor 120 is formed in such a manner as to be embedded in the opening 190, the diameter of the top of the conductor 120 is preferably larger than the diameter of the opening 190. In addition, since the conductor 120 is also used as one of the source electrode and the drain electrode of the transistor 200, it is preferable to increase the contact area with the oxide semiconductor 270. That is, the diameter of the top of the conductor 120 is preferably larger than the diameter of the opening 290.

[0122] Therefore, the top of the conductor 120 becomes one of the elements that increase the electrostatic capacitance of the parasitic capacitance generated between the conductor 120 and other wirings. In the transistor 100 of Example 2, the insulator 180 is made thicker to increase the depth value of the opening 190.

[0123] In Example 1, a structure in which the opening 190 and the opening 290 are substantially the same is shown, but in Example 2, the depth value of the opening 190 is larger than the depth value of the opening 290. In a vertical transistor, increasing the depth value of the opening 190 is equivalent to increasing the channel length, so it is effective when the on-state current characteristics of the transistor 100 are sufficiently high.

[0124] By adopting such a structure, the distance between the wiring 110 and the top of the conductor 120 can be physically increased, and the electrostatic capacitance of the parasitic capacitance Cp3 formed between the wiring 110 and the conductor 120 (node SN) with the insulator 180 or the like as the dielectric can be reduced. That is, in the electrostatic capacitance C = ε×S / d, the value of the dielectric thickness d is increased to reduce the value of C.

[0125] <Example 3 of the structure of the memory cell> Next, Example 3 of the structure of the memory cell 150 will be described. Figure 9A FIG. is a perspective view showing Example 3 of the structure of the memory cell 150. For clarity, insulators such as the interlayer film are not shown, and a part of the wirings 140 and 240 and the wiring 210 are shown by dashed lines.

[0126] Figure 9B is equivalent to Figure 7A 、 Figure 7B a diagram of a cross section of the line segment A1 - A2 shown. Figure 9C is equivalent to Figure 7A 、 Figure 7B a diagram of a cross section of the line segment B1 - B2 shown. Note that the description of each component common to Example 1 of the structure is omitted.

[0127] Similar to Example 1 of the structure, Example 3 of the structure has a structure in which an opening 190 is formed in the wiring 110 and the depth value of the opening 190 is increased by providing the insulator 181, and the parasitic capacitance electrostatic capacitance generated between the top of the conductor 120 and the wiring 140 is reduced. In Example 3 of the structure, the insulator 181 is formed on the wiring 140, and the opening 190 is formed so as to penetrate the insulator 181, the wiring 140, the insulator 180, and the wiring 110 and reach the insulator 160.

[0128] By adopting this structure, similar to Example 2 of the structure, the effect of reducing the electrostatic capacitance of the parasitic capacitance Cp3 can be obtained. In addition, by providing the insulator 181 between the top of the wiring 140 and the conductor 120, compared with Example 2 of the structure, the electrostatic capacitance of the parasitic capacitance Cp4 formed between the wiring 140 and the conductor 120 (node SN) can be further reduced. That is, in the electrostatic capacitance C = ε×S / d, the value of the dielectric thickness d is increased and the value of C is decreased.

[0129] In addition, in Example 2 of the above structure, the distance between the wiring 110 and the top of the conductor 120 and the distance between the wiring 110 and the wiring 140 are greatly affected by the thickness of the insulator 180. Therefore, when the distance between the wiring 110 and the top of the conductor 120 is increased, the distance between the wiring 110 (one of the source electrode and the drain electrode) and the wiring 140 (the other of the source electrode and the drain electrode) also becomes larger. This structure is equivalent to the case where the channel length in a vertical transistor becomes longer. When the channel length is long, the current value becomes small, so the degree of freedom in circuit design may sometimes become low.

[0130] On the other hand, in Structural Example 3, the channel length can be adjusted according to the thickness of the insulator 180. In addition, the distance between the wiring 110 and the top of the conductor 120 can be adjusted according to the total thickness of the insulators 180 and 181. Therefore, the degree of freedom in circuit design can be improved.

[0131] <Structural Example 4 of the Memory Cell> Next, Structural Example 4 of the memory cell 150 will be described. Figure 10A FIG. is a cross-sectional perspective view illustrating Structural Example 4 of the memory cell 150. For clarity, insulators such as the interlayer film are not shown, and the wiring 210 is represented by a dashed line. In addition, the capacitor 300 is divided in the Z direction, and a cross section is shown.

[0132] Figure 10B is equivalent to Figure 7A 、 Figure 7B a view of the cross section of the line segment A1 - A2 shown. Figure 10C is equivalent to Figure 7A 、 Figure 7B a view of the cross section of the line segment B1 - B2 shown. In addition, Figure 10B 、 Figure 10C the breaking position of the capacitor 300 shown is indicated by a dotted line. Note that the description of each component common to Structural Example 1 is omitted. Figure 10A

[0133] Figure 2C Structural Example 4 includes a capacitor 300 between the transistor 100 and the transistor 200 in addition to the structure of Structural Example 1. This structure can be used for Figure 2C the memory cell 150 in the circuit diagram shown.

[0134] The capacitor 300 includes a conductor 320, an insulator 330, and a wiring 310. The conductor 320 is used as one electrode, the insulator 330 is used as a dielectric, and the wiring 310 is used as the other electrode.

[0135] An insulator 380 is provided on the transistor 100, and the wiring 310 is provided on the insulator 380. An opening 390 is provided so as to penetrate the wiring 310 and the insulator 380, and the insulator 330 is provided so as to cover the opening 390. At the bottom of the opening 390, an opening reaching the conductor 120 is provided in the insulator 330. The conductor 320 is provided so as to be embedded in the opening 390 and contacts the conductor 120 at the bottom of the opening 390. Outside the opening 390, an insulator 385 serving as an interlayer film is provided on the insulator 330.

[0136] The insulator 385 and the conductor 320 are provided with a transistor 200. The oxide semiconductor 270 of the transistor 200 has a region in contact with the conductor 320 at the bottom of the opening 290. In other words, it can be said that the conductor 320 also has a region serving as one of the source electrode and the drain electrode of the transistor 200. In addition, the conductor 320 can also be said to be a conductor having a function of a wiring connecting one of the source electrode and the drain electrode of the transistor 200 to the gate electrode (conductor 120) of the transistor 100.

[0137] By providing the capacitor 300, the electrostatic capacitance of the node SN becomes larger, so that the potential fluctuation caused by the capacitive coupling of each parasitic capacitance can be suppressed. Thereby, the reliability of the read data can be improved.

[0138] Note that, Figures 10A to 10C shows a structure in which the capacitor 300 is added to the structural example 1, but as shown in the perspective view of Figure 11A , the capacitor 300 can also be added to the structural example 2. In addition, as shown in the perspective view of Figure 11B , the capacitor 300 can also be added to the structural example 3.

[0139] <Structural Example 5 of the Memory Cell> Next, the structural example 5 of the memory cell 150 will be described. Figure 12A is a perspective view for explaining the structural example 5 of the memory cell 150. For clarity, insulators such as the interlayer film are not shown, and the wiring 210 is represented by a dotted line. In addition, the capacitor 300 is divided in the Z direction, and a cross section is shown.

[0140] Figure 12B is equivalent to Figure 7A , Figure 7B a cross-sectional view of the line segment A1 - A2 shown. Figure 12C is equivalent to Figure 7A , Figure 7B a cross-sectional view of the line segment B1 - B2 shown. In addition, Figure 12B , Figure 12C shows the breaking position of the capacitor 300 shown in Figure 12A with a dotted line. Note that the description of the components common to the structural example 1 and the structural example 4 is omitted.

[0141] The structural example 5 is an example in which a capacitor 300 having a structure different from that of the structural example 4 is provided. The insulator 380, the wiring 310, the opening 390, and the insulator 330 have the same structure as the structural example 4, and the conductor 320 is formed so as to cover the wiring 310 and the opening 390.

[0142] By adopting such a structure, a capacitor can also be formed outside the opening portion 390 as follows: using the wiring 310 as one electrode; using the insulator 330 as the dielectric; and using the conductor 320 as the other electrode. That is to say, it is equivalent to increasing the value of the electrode area S in the capacitance C = ε×S / d to increase the value of C.

[0143] Note that Figures 12A to 12C shows the structure in which the capacitor 300 is added to the structural example 1, but as shown in the perspective view of Figure 13A , the capacitor 300 can also be added to the structural example 2. In addition, as shown in the perspective view of Figure 13B , the capacitor 300 can also be added to the structural example 3.

[0144] [Transistors 100, 200] Next, the transistors 100 and 200 will be described in detail. Note that, as described above, the wiring connection forms of the transistor 100 and the transistor 200 are different, but they basically have the same structure in the working part, so the transistor 200 will be described here.

[0145] As shown in Figure 7C , Figure 7D etc., the transistor 200 may include a conductor 120, a wiring 240 on an insulator 280, an oxide semiconductor 270 provided in contact with at least a part of the top surface of the conductor 120 exposed in the opening portion 290, the side surface of the insulator 280 in the opening portion 290, the side surface of the wiring 240 in the opening portion 290, and the top surface of the wiring 240, an insulator 230 provided in contact with the top surface of the oxide semiconductor 270, and a conductor 220 provided in contact with the top surface of the insulator 230.

[0146] At least a part of the components of the transistor 200 is disposed in the opening portion 290. Here, the bottom of the opening portion 290 is the top surface of the conductor 120, and the side surface of the opening portion 290 is also the side surface of the insulator 280 and the side surface of the wiring 240.

[0147] The top surface of the opening portion 290 has a substantially circular columnar shape. By adopting such a structure, miniaturization or high integration of the storage device can be achieved. Note that the side surface of the opening portion 290 is preferably perpendicular to the top surface of the wiring 110.

[0148] In order to increase the overlapping area between the transistor 200 and the transistor 100, it is preferable that the top surface shape of the opening portion 290 is the same shape or a similar shape as the top surface shape of the opening portion 190 forming the transistor 100.

[0149] The arrangement of the oxide semiconductor 270, the insulator 230, and the conductor 220 in the opening 290 reflects the shape of the opening 290. Therefore, the oxide semiconductor 270 is disposed so as to cover the bottom and the side surfaces of the opening 290, the insulator 230 is disposed so as to cover the oxide semiconductor 270, and the conductor 220 is disposed so as to be embedded in the recess of the insulator 230 that reflects the shape of the opening 290.

[0150] Note that, in the present embodiment, an example in which the shapes of the opening 290 and the conductor 220 in a plan view are substantially circular is shown, but the present invention is not limited thereto. For example, the shapes of the opening 290 and the conductor 220 in a plan view may be an elliptical shape, a polygonal shape such as a quadrangular shape, or a shape in which the corners of a polygon such as a quadrangular shape are rounded. In this case, the maximum width of the opening 290 may be appropriately calculated according to the shape of the opening 290 in a plan view. In addition, the maximum width of the conductor 220 may be appropriately calculated according to the shape of the conductor 220 in a plan view.

[0151] For example, when the opening 290 is a quadrangle in a plan view, the maximum width of the opening 290 is preferably the diagonal length of the quadrangle. In addition, when the conductor 220 is a quadrangle in a plan view, the maximum width of the conductor 220 may be the diagonal length of the quadrangle. In addition, for example, when the opening 290 and the conductor 220 in a plan view are an elliptical shape, a polygonal shape, or a shape in which the corners of a polygon are rounded, the maximum widths of the opening 290 and the conductor 220 may be the diameter of the smallest circle (also referred to as the minimum circumscribed circle) that includes the shape of the opening 290 in a plan view.

[0152] The description of the shape of the above-mentioned opening 290 can also be applied to the opening 190. In addition, the description of the shape of the above-mentioned conductor 220 can be applied to the conductor 120.

[0153] Here, Figure 14A is shown Figure 7C , Figure 7D an enlarged view of the oxide semiconductor 270 and its vicinity as shown. In addition, Figure 14B a cross-sectional view of the XY plane including the wiring 240 is shown.

[0154] As Figure 14A shown, the oxide semiconductor 270 has a region 270i, regions 270na and 270nb disposed so as to sandwich the region 270i.

[0155] Region 270na is the region in the oxide semiconductor 270 that contacts the conductor 120. At least a part of region 270na is used as one of the source region and the drain region of the transistor 200. Region 270nb is the region in the oxide semiconductor 270 that contacts the wiring 240. At least a part of region 270nb is used as the other of the source region and the drain region of the transistor 200. As Figure 14B shown, the wiring 240 contacts the entire outer periphery of the oxide semiconductor 270. Therefore, it is possible that the other of the source region and the drain region of the transistor 200 is formed on the entire outer periphery of the portion of the oxide semiconductor 270 formed in the same layer as the wiring 240.

[0156] Region 270i is the region between region 270na and region 270nb in the oxide semiconductor 270. At least a part of region 270i is used as the channel formation region of the transistor 200. That is, the channel formation region of the transistor 200 is formed in a part of the oxide semiconductor 270 in the region located between the conductor 120 and the wiring 240. In addition, it can also be said that the channel formation region of the transistor 200 is located in the region where the oxide semiconductor 270 contacts the insulator 280 or in the region near it.

[0157] The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined according to the thickness of the insulator 280 on the conductor 120. In Figure 14A it, the channel length L of the transistor 200 is indicated by a double arrow of a dotted line. When viewed from the cross section, the channel length L is the distance between the end of the region where the oxide semiconductor 270 and the conductor 120 contact and the end of the region where the oxide semiconductor 270 and the wiring 240 contact. That is, the channel length L corresponds to the length of the side on the opening 290 side of the insulator 280 when viewed from the cross section.

[0158] In existing transistors, the channel length is set according to the exposure limit of photolithography, but in the present invention, the channel length can be set according to the thickness of the insulator 280. Therefore, the channel length of the transistor 200 can be set to a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less and 1 nm or more or 5 nm or more). Therefore, the on-state current of the transistor 200 becomes larger, and thus the frequency characteristics can be improved. Thereby, a storage device with a high operating speed can be provided.

[0159] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 290. Therefore, compared with a conventional transistor in which the channel formation region, the source region, and the drain region are separately provided in the XY plane, the occupation area of the transistor 200 can be reduced. As a result, the storage device can be highly integrated, so that the storage capacity per unit area can be increased.

[0160] In this way, a transistor having a channel formation region along the side surface of the insulator 280 in the opening 290 is also referred to as a vertical transistor.

[0161] In addition, similar to Figure 14B In the XY plane including the channel formation region of the oxide semiconductor 270, the oxide semiconductor 270, the insulator 230, and the conductor 220 are arranged in concentric circles. Therefore, the side surface of the conductor 220 provided at the center faces the side surface of the oxide semiconductor 270 with the insulator 230 therebetween. In other words, the entire outer periphery of the oxide semiconductor 270 becomes a channel formation region in a plan view. At this time, for example, the channel width of the transistor 200 is determined according to the length of the outer periphery of the oxide semiconductor 270. That is to say, it can be said that the channel width of the transistor 200 is determined according to the size of the maximum width of the opening 290 (the maximum diameter in the case where the shape of the opening 290 in a plan view is circular). In Figure 14A and Figure 14B the maximum width D of the opening 290 is indicated by a double-headed arrow of a dashed-dotted line. In Figure 14B the channel width W of the transistor 200 is indicated by a double-headed arrow of a dotted line. By increasing the size of the maximum width D of the opening 290, the channel width per unit area can be increased to increase the on-state current.

[0162] When the opening 290 is formed by a photolithography method, the maximum width D of the opening 290 is set according to the exposure limit of the photolithography method. In addition, the maximum width D of the opening 290 is set according to the respective thicknesses of the oxide semiconductor 270, the insulator 230, and the conductor 220 provided in the opening 290. The maximum width D of the opening 290 is preferably 5 nm or more, 10 nm or more, or 20 nm or more and 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less, for example. Note that in the case where the shape of the opening 290 in a plan view is circular, the maximum width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D×π".

[0163] In addition, in the storage device according to one embodiment of the present invention, the channel length L of the transistor 200 is preferably at least smaller than the channel width W of the transistor 200. In one embodiment of the present invention, the channel length L of the transistor 200 is 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, of the channel width W of the transistor 200. By adopting such a structure, a transistor having good electrical characteristics and high reliability can be realized.

[0164] In addition, by forming the opening 290 so as to have a substantially circular shape in a plan view, the oxide semiconductor 270, the insulator 230, and the conductor 220 are arranged in concentric circles. As a result, the distance between the conductor 220 and the oxide semiconductor 270 is substantially uniform, so that a gate electric field can be applied to the oxide semiconductor 270 substantially uniformly.

[0165] In the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer, preferably, compared with the source region and the drain region, there are fewer oxygen vacancies or lower impurity concentrations of hydrogen, nitrogen, metal elements, etc. In addition, hydrogen near the oxygen vacancy sometimes forms a defect in which hydrogen enters the oxygen vacancy (hereinafter, sometimes referred to as V O H) and generates electrons that become carriers, so V O H is also preferably reduced in the channel formation region. Thus, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0166] In addition, the source region and the drain region of a transistor using an oxide semiconductor for a semiconductor layer are regions where the carrier concentration increases due to more oxygen vacancies, more V O H, or higher impurity concentrations of hydrogen, nitrogen, metal elements, etc. compared with the channel formation region, and thus the resistance is lowered. That is, compared with the channel formation region, the source region and the drain region of the transistor are n-type regions with a higher carrier concentration and a lower resistance.

[0167] Note that in Figure 14A etc., the opening 290 is provided such that the side surface of the opening 290 is perpendicular to the top surface of the wiring 110, but the present invention is not limited thereto. For example, the side surface of the opening 290 may have an inverted conical shape.

[0168] The bandgap of the metal oxide used as the oxide semiconductor 270 is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a large bandgap as the oxide semiconductor 270, the off-state current of the transistor can be reduced. By using a transistor with a small off-state current for the memory cell, the stored content can be retained for a long time. In other words, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced. In addition, the frequency of the refresh operation required for a general DRAM is about once every 60 msec, and the frequency of the refresh operation of the memory device according to one embodiment of the present invention can be about once every 10 sec, that is, a refresh operation frequency of 10 times or more or 100 times or more can be achieved. In addition, by using the memory device according to one embodiment of the present invention, the frequency of the refresh operation can be set to 1 time / 1 sec or more and 1 time / 100 sec or less, preferably 1 time / 5 sec or more and 1 time / 50 sec or less.

[0169] In addition, as the oxide semiconductor 270, a single layer or a stack of the metal oxides described in [Metal Oxide] to be described later can be used.

[0170] Specifically, as the oxide semiconductor 270, a metal oxide having the following composition can be used: In:M:Zn = 1:3:2 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:3:4 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:0.5 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:1 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn = 1:1:2 [atomic ratio] or a composition in the vicinity thereof, or In:M:Zn = 4:2:3 [atomic ratio] or a composition in the vicinity thereof. Note that the vicinity of the composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M.

[0171] In addition, when depositing the metal oxide by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide, but can also be the atomic ratio of the sputtering target used for depositing the metal oxide.

[0172] For the analysis of the composition of the metal oxide used for the oxide semiconductor 270, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, multiple of the above methods can be combined for analysis. Note that elements with low content rates are sometimes affected by the analysis accuracy, and the actual content rate may be different from the content rate obtained by analysis. For example, when the content rate of element M is low, the content rate of element M obtained by analysis may be lower than the actual content rate.

[0173] The metal oxide can be appropriately formed by sputtering or atomic layer deposition (ALD). Note that when the metal oxide is formed by sputtering, the composition of the formed metal oxide is sometimes different from the composition of the sputtering target. In particular, the content rate of zinc in the formed metal oxide sometimes decreases to about 50% of the content rate of zinc in the sputtering target.

[0174] The oxide semiconductor 270 preferably has crystallinity. Examples of the oxide semiconductor having crystallinity include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductor, single crystal oxide semiconductor, etc. CAAC-OS or nc-OS is preferably used for the oxide semiconductor 270, and CAAC-OS is particularly preferably used.

[0175] CAAC-OS preferably has multiple layered crystal regions and its c-axis is oriented in the normal direction of the formed surface. For example, the oxide semiconductor 270 preferably has layered crystals substantially parallel to the side walls of the opening 290, particularly layered crystals substantially parallel to the side surfaces of the insulator 280. By adopting such a structure, the layered crystals of the oxide semiconductor 270 are substantially parallel to the channel length direction of the transistor 200, so the on-state current of the transistor can be increased.

[0176] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies, etc.). In particular, by performing heat treatment at a temperature at which the metal oxide is not polycrystallized (e.g., 400 °C or higher and 600 °C or lower) after forming the metal oxide, CAAC-OS can have a denser structure with higher crystallinity. Thus, by further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0177] In addition, distinct grain boundaries are not easily observed in CAAC-OS, so a decrease in electron mobility due to grain boundaries does not easily occur. Therefore, the physical properties of the metal oxide having CAAC-OS are stable. Therefore, the metal oxide having CAAC-OS has heat resistance and high reliability.

[0178] In addition, when a crystalline oxide such as CAAC-OS is used as the oxide semiconductor 270, oxygen extraction from the oxide semiconductor 270 by the source electrode or the drain electrode can be suppressed. Thus, even when heat treatment is performed, oxygen extraction from the oxide semiconductor 270 can be suppressed, so the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0179] The crystallinity of the oxide semiconductor 270 can be analyzed, for example, by an X-ray diffraction (XRD) pattern, a transmission electron microscope (TEM) image, or an electron diffraction (ED) pattern. Alternatively, it is also possible to analyze by combining a plurality of the above methods.

[0180] Note that Figure 7C and Figure 7D etc. show a structure in which the oxide semiconductor 270 is a single layer, and the present invention is not limited thereto. The oxide semiconductor 270 may also have a stacked structure of a plurality of oxide layers having different chemical compositions. For example, a structure in which a plurality of types selected from the above metal oxides are appropriately stacked may also be employed.

[0181] When the oxide semiconductor 270 has a three-layer stacked structure, for example, metal oxides having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or near it, metal oxides having a composition of In:Zn = 1:1 [atomic ratio] or near it, or metal oxides having a composition of In:Zn = 4:1 [atomic ratio] or near it, and metal oxides having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or near it can be sequentially provided from the side of the conductor 120. By adopting such a structure, the on-state current of the transistor 200 can be increased, and thus a transistor structure with less non-uniformity and high reliability can be achieved.

[0182] As the insulator 230, a single layer or a stack of insulators described in [insulator] to be described later can be used. As the insulator 230, for example, silicon oxide or silicon oxynitride can be used. Silicon oxide and silicon oxynitride have thermal stability, so they are preferred.

[0183] In addition, as the insulator 230, a material having a high relative dielectric constant, that is, a so-called high-k material, described in [insulator] to be described later can also be used. For example, hafnium oxide or aluminum oxide can also be used.

[0184] The thickness of the insulator 230 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and further preferably 0.5 nm or more and 10 nm or less. At least a part of the insulator 230 may be a region having the above thickness.

[0185] The impurity concentration of water, hydrogen, etc. in the insulator 230 is preferably reduced. Thereby, the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 270 can be suppressed.

[0186] As shown in Figure 7C and Figure 7D , a part of the insulator 230 is located outside the opening 290, that is, on the wiring 240 and the insulator 280. At this time, the insulator 230 preferably covers the side end portion of the oxide semiconductor 270. Thereby, a short circuit between the conductor 220 and the oxide semiconductor 270 can be prevented. In addition, the insulator 230 preferably covers the side end portion of the wiring 240. Thereby, a short circuit between the conductor 220 and the wiring 240 can be prevented.

[0187] Note that, in Figure 7C and Figure 7D , a structure in which the insulator 230 is a single layer is shown, but the present invention is not limited thereto. The insulator 230 may also have a stacked structure.

[0188] As the conductor 220, a single layer or a laminate of the conductors described in [Conductor] which will be described later can be used. As the conductor 220, for example, a highly conductive material such as tungsten can be used.

[0189] In addition, as the conductor 220, a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion is preferably used. As such a conductive material, a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride, etc.) and a conductive material containing oxygen (for example, ruthenium oxide, etc.) can be cited. Thereby, a decrease in the conductivity of the conductor 220 can be suppressed.

[0190] Note that in Figure 7C and Figure 7D a structure in which the conductor 220 is a single layer is shown, but the present invention is not limited thereto. The conductor 220 may also have a laminated structure.

[0191] As the wiring 240, a single layer or a laminate of the conductors described in [Conductor] which will be described later can be used. As the wiring 240, for example, a highly conductive material such as tungsten can be used.

[0192] Similar to the conductor 220, the wiring 240 also preferably uses a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. By adopting such a structure, over-oxidation of the wiring 240 by the oxide semiconductor 270 can be suppressed.

[0193] In addition, for example, a structure in which tungsten is laminated on titanium nitride can also be provided. By laminating tungsten in this way, the conductivity of the wiring 240 can be improved.

[0194] Furthermore, when the wiring 240 has a laminated structure of a first conductor and a second conductor, for example, a highly conductive material can be used to form the first conductor and a conductive material containing oxygen can be used to form the second conductor. By using a conductive material containing oxygen as the second conductor of the wiring 240 in contact with the insulator 230, oxygen diffusion from the insulator 230 into the first conductor of the wiring 240 can be suppressed. For example, tungsten is preferably used as the first conductor of the wiring 240, and indium tin oxide added with silicon is preferably used as the second conductor of the wiring 240.

[0195] When the oxide semiconductor 270 comes into contact with the conductor 120, a metal compound or oxygen vacancies are formed, and the region 270na of the oxide semiconductor 270 is made to have a lower resistance. By making the oxide semiconductor 270 in contact with the conductor 120 have a lower resistance, the contact resistance between the oxide semiconductor 270 and the conductor 120 can be reduced. Similarly, when the oxide semiconductor 270 comes into contact with the wiring 240, the region 270nb of the oxide semiconductor 270 is made to have a lower resistance. Thereby, the contact resistance between the oxide semiconductor 270 and the wiring 240 can be reduced.

[0196] The insulator 280 is used as an interlayer film, so its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the electrostatic capacitance of the parasitic capacitance generated between the wirings can be reduced. As the insulator 280, a single layer or a stack of insulators containing a material with a low relative dielectric constant described in [Insulator] to be described later can be used. Silicon oxide and silicon oxynitride have thermal stability, so they are preferred.

[0197] In addition, the impurity concentrations of water, hydrogen, etc. in the insulator 280 are preferably reduced. Thereby, the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 270 can be suppressed.

[0198] In addition, as the insulator 280, an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) is preferably used. By performing heat treatment on the insulator 280 containing excess oxygen, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 270, and oxygen vacancies and V O H can be reduced. Thereby, the electrical characteristics of the transistor 200 can be stabilized and the reliability can be improved.

[0199] Furthermore, as the insulator 280, an insulator having a function of capturing or fixing hydrogen described in [Insulator] to be described later can also be used. By adopting such a structure, the hydrogen of the oxide semiconductor 270 can be captured or fixed, and the hydrogen concentration of the oxide semiconductor 270 can be reduced. As the insulator 280, magnesium oxide, aluminum oxide, etc. can be used.

[0200] Note that in Figure 7C and Figure 7D a structure in which the insulator 280 is a single layer is shown, but the present invention is not limited thereto. The insulator 280 can also have a stacked structure.

[0201] <Constituent Materials of the Storage Device> Hereinafter, the constituent materials that can be used for the storage device will be described.

[0202] [Substrate] As a substrate for forming the transistor 100 and the transistor 200, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. As the insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttrium-stabilized zirconia substrate), a resin substrate, etc. can be cited. In addition, as the semiconductor substrate, for example, a semiconductor substrate made of silicon, germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. can be cited. Further, a semiconductor substrate having an insulator region inside the above semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. can be cited. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Or, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. In addition, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can be cited. Or, a substrate having elements provided thereon can also be used. As the elements provided on the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a storage element, etc. can be cited.

[0203] [Insulator] As the insulator, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, metal nitrides, etc. having insulating properties.

[0204] For example, when miniaturizing and highly integrating a transistor, due to the thinning of the gate insulator, problems such as leakage current sometimes occur. By using a high-k material as the insulator used as the gate insulator, low voltage operation of the transistor can be achieved while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced. On the other hand, by using a material with a low relative dielectric constant as the insulator used as the interlayer film, the electrostatic capacitance of the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulator. In addition, a material with a low relative dielectric constant is also a material with a high dielectric strength.

[0205] As materials with a high relative dielectric constant (high-k), for example, alumina, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium, etc. can be cited.

[0206] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate, and acrylic resin. In addition, examples of inorganic insulating materials with a low relative dielectric constant other than the above include silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen. In addition, silicon oxide with pores can be cited. In addition, these silicon oxides may also contain nitrogen.

[0207] In addition, by surrounding a transistor using a metal oxide with an insulator having a function of suppressing the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the permeation of impurities and oxygen, for example, a single layer or a stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. Specifically, as an insulator having a function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc., and metal nitrides such as aluminum nitride, silicon oxynitride, silicon nitride, etc. can be used.

[0208] In addition, an insulator in contact with a semiconductor such as a gate insulator or an insulator provided near a semiconductor layer is preferably an insulator having a region containing excess oxygen. For example, when an insulator having a region containing excess oxygen is in contact with a semiconductor layer, or when an insulator having a region containing excess oxygen is provided near a semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of an insulator that easily forms a region containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide with pores.

[0209] In addition, examples of insulators having an oxygen barrier property include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride. In addition, examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0210] In addition, examples of insulators having a hydrogen barrier property include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride.

[0211] Insulators having an oxygen barrier property and insulators having a hydrogen barrier property can be said to be insulators having a barrier property against one or both of oxygen and hydrogen.

[0212] In addition, as an insulator having a function of capturing or fixing hydrogen, oxides containing magnesium or oxides containing one or both of aluminum and hafnium can be cited. Further, these oxides preferably have an amorphous structure. Oxides having an amorphous structure sometimes have the following property: oxygen atoms have dangling bonds and capture or fix hydrogen by these dangling bonds. In addition, these oxides preferably have an amorphous structure, but a part of them may form a crystalline region.

[0213] Note that, in this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. In addition, the barrier property refers to the property of not easily diffusing a corresponding substance (also referred to as the property of not easily permeating a corresponding substance, the property of low permeability of a corresponding substance, or the function of suppressing the diffusion of a corresponding substance). In addition, the function of capturing or fixing (also referred to as gettering) a corresponding substance can be equivalently called a barrier property. In addition, the hydrogen as the corresponding substance, for example, refers to at least one of hydrogen atoms, hydrogen molecules, water molecules, and substances hydrogen-bonded such as OH - and the like. In addition, unless otherwise stated, the impurities as the corresponding substance refer to impurities in the channel formation region or the semiconductor layer, and for example, refer to at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, and the like. In addition, the oxygen as the corresponding substance, for example, refers to at least one of oxygen atoms, oxygen molecules, and the like. Specifically, the oxygen barrier property refers to the property of not easily diffusing at least one of oxygen atoms, oxygen molecules, and the like.

[0214] [Conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy containing the above metal element as a component, or an alloy combining the above metal elements. As the alloy containing the above metal element as a component, a nitride or an oxide of the alloy can also be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, highly conductive semiconductors represented by polysilicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0215] In addition, conductive materials containing nitrogen such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, or titanium and aluminum nitride, conductive materials containing oxygen such as ruthenium oxide, strontium and ruthenium oxide, or lanthanum and nickel oxide, and materials containing metal elements such as titanium, tantalum, or ruthenium are conductive materials that are not easily oxidized, conductive materials with a function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Note that as conductive materials containing oxygen, indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide added with silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide can be cited. In this specification and the like, a conductive film formed by depositing a conductive material containing oxygen is sometimes referred to as an oxide conductive film.

[0216] In addition, conductive materials mainly composed of tungsten, copper, or aluminum have high conductivity, so they are preferred.

[0217] In addition, multiple conductive layers formed of the above materials can be laminated. For example, a laminated structure combining a material containing the above metal element and a conductive material containing oxygen can be adopted. In addition, a laminated structure combining a material containing the above metal element and a conductive material containing nitrogen can be adopted. In addition, a laminated structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen can be adopted.

[0218] In addition, when a metal oxide is used in the channel formation region of a transistor, the conductor used as the gate electrode preferably adopts a laminated structure combining a material containing the above metal element and a conductive material containing oxygen. In this case, it is preferable to dispose the conductive material containing oxygen on the channel formation region side. By disposing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0219] In particular, as the conductor used as the gate electrode, a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel is preferably used. In addition, a conductive material containing the above metal element and nitrogen can also be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride can be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, it is sometimes possible to capture hydrogen contained in the metal oxide forming the channel. Or, it is sometimes possible to capture hydrogen mixed in from an external insulator or the like.

[0220] [Metal Oxide] Metal oxides sometimes have lattice defects. Lattice defects refer to point defects such as atomic vacancies and foreign atoms, line defects such as dislocations, plane defects such as grain boundaries, and volume defects such as voids. In addition, the main causes of the generation of lattice defects include differences in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms) and impurities, etc.

[0221] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause the generation or trapping of carriers, etc. Therefore, when a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, it is preferable that the lattice defects in the metal oxide used for the semiconductor layer of a transistor are few.

[0222] In a transistor using a metal oxide, especially, if there are oxygen vacancies (V O ) and impurities in the channel formation region of the metal oxide, the electrical characteristics are likely to vary and sometimes the reliability is reduced. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H), and electrons that become carriers may be generated. Thus, when the channel formation region in the metal oxide contains oxygen vacancies, the transistor tends to have normally-on characteristics. Thus, in the channel formation region of the metal oxide, it is preferable to minimize oxygen vacancies and impurities as much as possible. In other words, it is preferable that the carrier concentration in the channel formation region of the metal oxide is reduced and it is i-type (intrinsic) or substantially i-type.

[0223] The types of lattice defects that are likely to exist in a metal oxide and the amount of lattice defects present differ depending on the structure of the metal oxide or the deposition method of the metal oxide, etc.

[0224] The structure of a metal oxide is classified into a single crystal structure and other structures (non-single crystal structures). As non-single crystal structures, for example, there are CAAC structures, polycrystalline structures, nc structures, amorphous-like (a-like) structures, and amorphous structures, etc. The a-like structure has a structure between the nc structure and the amorphous structure. Note that the classification of crystal structures will be described later.

[0225] In addition, voids or low-density regions exist in the metal oxides having an a-like structure and the metal oxides having an amorphous structure. In other words, the crystallinity of the metal oxides having an a-like structure and the metal oxides having an amorphous structure is lower than that of the metal oxides having an nc structure and the metal oxides having a CAAC structure. In addition, the hydrogen concentration in the metal oxides of the metal oxides having an a-like structure is higher than that of the metal oxides having an nc structure and the metal oxides having a CAAC structure. Therefore, lattice defects are likely to be generated in the metal oxides having an a-like structure and the metal oxides having an amorphous structure.

[0226] Therefore, it is preferable to use a metal oxide having high crystallinity for the semiconductor layer of the transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a single crystal structure. By using this metal oxide for the transistor, a transistor having good electrical characteristics can be achieved. In addition, a transistor having high reliability can be achieved.

[0227] In addition, a metal oxide that increases the on-state current of the transistor is preferably used for the channel formation region of the transistor. In order to increase the on-state current of the transistor, it is only necessary to increase the mobility of the metal oxide used for the transistor. In order to increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce the scattering factors that affect the transport of carriers. In addition, carriers flow from the source electrode to the drain electrode through the channel formation region. Therefore, by providing a channel formation region in which carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0228] Here, a metal oxide having a channel formation region preferably uses a metal oxide having high crystallinity. Furthermore, the crystal preferably has a crystal structure in which a plurality of layers (for example, a first layer, a second layer, and a third layer) are stacked. In other words, the crystal has a layered crystal structure (also referred to as a layered crystal or a layered structure). At this time, the c-axis direction of the crystal is the direction in which a plurality of layers are stacked. Metal oxides having such a crystal include, for example, single crystal oxide semiconductors, CAAC-OS, and the like.

[0229] In addition, the c-axis of the above crystal is preferably oriented in the normal direction of the formed surface or the film surface of the metal oxide. As a result, a plurality of layers are arranged in parallel or substantially parallel to the formed surface or the film surface of the metal oxide. That is, a plurality of layers extend in the channel length direction.

[0230] For example, the above-described three-layered crystal structure has the following structure. The first layer has an atomic coordination structure of an oxygen octahedron with the metal contained in the first layer at the center. In addition, the second layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal contained in the second layer at the center. In addition, the third layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal contained in the third layer at the center.

[0231] As the crystal structure of the above crystal, for example, there are YbFe2O4-type structures, Yb2Fe3O7-type structures, and their deformed structures.

[0232] Furthermore, it is preferable that the first to third layers are each composed of one metal element or a plurality of metal elements having the same valence and oxygen. Note that it is preferable that the valence of one or more metal elements constituting the first layer is the same as the valence of one or more metal elements constituting the second layer. In addition, the first layer and the second layer may also contain the same metal element. In addition, it is preferable that the valence of one or more metal elements constituting the first layer is different from the valence of one or more metal elements constituting the third layer.

[0233] By adopting the above structure, the crystallinity of the metal oxide can be improved, and the mobility of the metal oxide can be increased. Thus, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.

[0234] As the metal oxide of one aspect of the present invention, for example, indium oxide, gallium oxide, and zinc oxide can be cited. The metal oxide of one aspect of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Note that element M is a metal element or a metalloid element having a high bonding energy with oxygen, for example, a metal element or a metalloid element having a higher bonding energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony can be cited. Element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. When element M included in the metal oxide is gallium, the metal oxide of one aspect of the present invention preferably contains any one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements are sometimes collectively referred to as "metal elements", and the "metal elements" described in this specification and the like sometimes include metalloid elements.

[0235] As a metal oxide semiconductor according to an aspect of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. may be used. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. may be mentioned.

[0236] By increasing the atomic number ratio of indium with respect to the total number of atomic numbers of all metal elements in the metal oxide, the field-effect mobility of the transistor can be increased.

[0237] Note that the metal oxide may also contain one or more metal elements with a large period number instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large period number in addition to indium. There is a tendency that the larger the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide. Therefore, by containing a metal element with a large period number, the field-effect mobility of the transistor can sometimes be increased. As the metal element with a large period number, metal elements belonging to the fifth period and metal elements belonging to the sixth period, etc. may be mentioned. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium, etc. may be mentioned. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0238] In addition, the metal oxide may also contain one or more non-metal elements. By the metal oxide containing a non-metal element, the field-effect mobility of the transistor can sometimes be increased. As the non-metal element, for example, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen, etc. may be mentioned.

[0239] In addition, by increasing the atomic number ratio of zinc with respect to the total number of atomic numbers of all metal elements in the metal oxide, the metal oxide can be made to have high crystallinity, whereby the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed and the reliability can be improved.

[0240] In addition, by increasing the atomic number ratio of element M with respect to the total number of atomic numbers of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, and a transistor with a small off-state current can be realized. In addition, the variation in the electrical characteristics of the transistor is suppressed, and the reliability can be improved.

[0241] In addition, by increasing the atomic number ratio of In with respect to the total number of atomic numbers of all metal elements in the metal oxide, the transistor can obtain a large on-state current and high-frequency characteristics.

[0242] In the present embodiment, as the metal oxide, In-Ga-Zn oxide may be described as an example.

[0243] In order to form a metal oxide having the above-described layered crystal structure, it is preferable to deposit atoms layer by layer. In the deposition method of the metal oxide according to one aspect of the present invention, since the ALD method is used, a metal oxide having the above-described layered crystal structure can be easily formed.

[0244] Examples of the ALD method include a thermal ALD (Thermal ALD) method in which a precursor and a reactant are reacted using only heat energy, and a plasma ALD (PEALD: Plasma Enhanced ALD) method in which a reactant excited by plasma is used.

[0245] The ALD method can deposit atoms layer by layer, and thus has the following effects: it can deposit an extremely thin film; it can deposit on a structure with a high aspect ratio; it can deposit with few defects such as pinholes; it can deposit with high coverage; it can deposit at a low temperature, etc. In addition, in the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferable. In addition, the precursor used in the ALD method sometimes contains elements such as carbon or chlorine. Therefore, the film formed by the ALD method sometimes contains more elements such as carbon or chlorine than the film formed by other deposition methods. In addition, the quantification of these elements can be performed using XPS or SIMS (Secondary Ion Mass Spectrometry). Note that, although the deposition method of the metal oxide according to one aspect of the present invention uses the ALD method, the amount of carbon and chlorine contained in the film is sometimes smaller than that in the case of using the ALD method without adopting the above conditions because of one or both of the conditions of a high substrate temperature during deposition and an impurity removal treatment.

[0246] The ALD method is a film-forming method that forms a film due to the reaction on the surface of the object to be processed, different from deposition methods that deposit particles released from a target or the like. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of openings with a high aspect ratio, etc. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferably used in combination with other deposition methods such as a sputtering method or a CVD method with a high deposition rate. For example, a method of depositing a first metal oxide by a sputtering method and depositing a second metal oxide by the ALD method on the first metal oxide can be cited. For example, when the first metal oxide has a crystalline part, the second metal oxide sometimes grows crystallinity with the crystalline part as a nucleus.

[0247] The ALD method can control the composition of the obtained film according to the introduction amount of the source gas. For example, when using the ALD method, a film of any composition can be deposited by adjusting the introduction amount of the source gas, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time), etc. In addition, for example, when using the ALD method, a film with a continuously changing composition can be deposited by changing the source gas while depositing. When depositing while changing the source gas, since the time required for transferring or adjusting the pressure is not required, the deposition time can be shortened compared with the case of depositing using multiple deposition chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0248] [[Transistor including an oxide semiconductor]] Next, the case of using a metal oxide (oxide semiconductor) for a transistor will be described. Hereinafter, a transistor using an oxide semiconductor in the semiconductor layer may sometimes be referred to as an OS transistor, and a transistor using silicon in the semiconductor layer may be referred to as an Si transistor.

[0249] By using the metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with a high field-effect mobility can be realized. In addition, a transistor with high reliability can be realized. In addition, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.

[0250] It is preferable to use an oxide semiconductor with a low carrier concentration for the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor can be 1×10 18 cm -3 Hereinafter, it is preferably 1×10 17 cm -3 Hereinafter, it is more preferably 1×10 15 cm -3Hereinafter, it is more preferably 1×10 13 cm -3 Hereinafter, it is more preferably 1×10 11 cm -3 Hereinafter, it is further preferably less than 1×10 10 cm -3 and is 1×10 -9 cm -3 or more. Note that, when aiming to reduce the carrier concentration of the oxide semiconductor, it is sufficient to reduce the impurity concentration in the oxide semiconductor to reduce the density of defect states. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0251] Since the density of defect states in a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is low, the density of trap states is sometimes also low.

[0252] In addition, it takes a long time for the charge trapped in the trap states of the oxide semiconductor to disappear and sometimes acts like a fixed charge. Therefore, the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states are sometimes unstable.

[0253] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of the impurity include hydrogen, carbon, nitrogen, etc. Note that the impurity in the oxide semiconductor refers to an element other than the main components constituting the oxide semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity.

[0254] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor with a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0255] In addition, in Si transistors, the short-channel effect (also referred to as Short Channel Effect: SCE) appears as the transistors are miniaturized. Therefore, it is difficult to miniaturize Si transistors. One of the reasons for the occurrence of the short-channel effect is that the band gap of silicon is small. On the other hand, OS transistors use an oxide semiconductor as a semiconductor material with a large band gap, thereby suppressing the short-channel effect. In other words, OS transistors are transistors without the short-channel effect or with very little short-channel effect.

[0256] In addition, the short-channel effect refers to the degradation of electrical characteristics that occurs as transistors are miniaturized (the channel length is reduced). Specific examples of the short-channel effect include a decrease in the threshold voltage, an increase in the subthreshold swing value (sometimes denoted as the S value), and an increase in the leakage current. Here, the S value refers to the change in the gate voltage in the subthreshold region where the drain current value changes by one digit with a fixed drain voltage.

[0257] Furthermore, as an index of the tolerance to the short-channel effect, the characteristic length is widely used. The characteristic length is an index of the curvature of the potential in the channel formation region. The smaller the characteristic length, the steeper the potential rises, so it can be said that the ability to resist the short-channel effect is high.

[0258] OS transistors are accumulation-mode transistors, and Si transistors are inversion-mode transistors. Therefore, compared with Si transistors, the characteristic lengths between the source region and the channel formation region and between the drain region and the channel formation region of OS transistors are smaller. Therefore, compared with Si transistors, OS transistors have a higher ability to resist the short-channel effect. That is to say, when manufacturing transistors with a short channel length, OS transistors are more preferable than Si transistors.

[0259] When the carrier concentration of the oxide semiconductor is reduced until the channel formation region becomes i-type or substantially i-type, in short-channel transistors, due to the Conduction-Band-Lowering (CBL) effect, the lower end of the conduction band in the channel formation region drops, whereby the energy difference between the lower end of the conduction band between the source region or the drain region and the channel formation region may be reduced to more than 0.1 eV and less than 0.2 eV. Thus, OS transistors can also be regarded as an n - -type region where the channel formation region becomes an n + -type region and the source region and the drain region become n + / n - / n + accumulation-mode junction-less transistor structure or an n + / n - / n + accumulation-mode non-junction transistor structure.

[0260] With the OS transistor having the above structure, good electrical characteristics can be achieved even when the storage device is miniaturized or highly integrated. For example, even when the channel length or gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less and 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. On the other hand, in Si transistors, the short-channel effect occurs, and thus it is sometimes difficult to set the gate length to 20 nm or less or 15 nm or less. Therefore, compared with Si transistors, OS transistors can be applied to transistors with a short channel length. Note that the gate length refers to the length of the gate electrode in the direction in which carriers migrate in the channel formation region during transistor operation.

[0261] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cut-off frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cut-off frequency of the transistor can be 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more.

[0262] As described above, the OS transistor has better effects than Si transistors, such as a small off-state current and the ability to fabricate transistors with a short channel length.

[0263] [[Impurities in metal oxides]] Here, the effects of various impurities in the metal oxide (oxide semiconductor) are described.

[0264] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 3×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, more preferably 3×10 18 atoms / cm 3 or less, further preferably 1×10 18 atoms / cm 3 or less. In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 or less, preferably 5×10 19atoms / cm 3 Hereinafter, it is more preferably 3 × 10 19 atoms / cm 3 Hereinafter, it is more preferably 1 × 10 19 atoms / cm 3 Hereinafter, it is more preferably 3 × 10 18 atoms / cm 3 Hereinafter, it is further preferably 1 × 10 18 atoms / cm 3 Hereinafter.

[0265] In addition, when the oxide semiconductor contains nitrogen, electrons are generated as carriers, increasing the carrier concentration and making it easily n-type. As a result, when the oxide semiconductor containing nitrogen is used for a semiconductor transistor, it is likely to have a normally-on characteristic. Or, when the oxide semiconductor contains nitrogen, trap states are sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1 × 10 20 atoms / cm 3 Hereinafter, it is preferably 5 × 10 19 atoms / cm 3 Hereinafter, it is more preferably 1 × 10 19 atoms / cm 3 Hereinafter, it is more preferably 5 × 10 18 atoms / cm 3 Hereinafter, it is more preferably 1 × 10 18 atoms / cm 3 Hereinafter, it is further preferably 5 × 10 17 atoms / cm 3 Hereinafter.

[0266] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, so oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancies, electrons are sometimes generated as carriers. In addition, sometimes electrons are generated as carriers because a part of hydrogen bonds with oxygen bonded to metal atoms. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have a normally-on characteristic. Thus, it is preferable to minimize hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to be less than 1 × 10 20 atoms / cm 3 , preferably less than 5 × 10 19 atoms / cm 3 , more preferably less than 1 × 10 19 atoms / cm 3, more preferably less than 5×10 18 atoms / cm 3 , further preferably less than 1×10 18 atoms / cm 3 .

[0267] In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal easily has a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Hereinafter, it is preferably 2×10 16 atoms / cm 3 Hereinafter.

[0268] By using an oxide semiconductor with sufficiently reduced impurities for the channel formation region of the transistor, the transistor can have stable electrical characteristics.

[0269] [Other semiconductor materials] The oxide semiconductor 270 can be replaced with a semiconductor layer having a channel formation region of a transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the above metal oxides. As the semiconductor layer, a semiconductor material having a band gap (a semiconductor material that is not a zero-bandgap semiconductor) can also be used. For example, it is preferable to use a single-element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) as the semiconductor material.

[0270] Here, in this specification, etc., the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by a bond weaker than covalent bonds and ionic bonds such as van der Waals forces. The layered material has high conductivity in the unit layer, that is, has high two-dimensional conductivity. By using a material that is used as a semiconductor and has high two-dimensional conductivity for the channel formation region, a transistor with a large on-state current can be provided.

[0271] Examples of the single-element semiconductor that can be used for the semiconductor material include silicon and germanium. Examples of the silicon that can be used for the semiconductor layer include single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of the polycrystalline silicon include low-temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon).

[0272] As compound semiconductors that can be used for semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, boron arsenide, etc. can be cited. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably contains crystals having a cubic crystal structure.

[0273] As layered materials, there are graphene, silicene, boron carbonitride, chalcogenides, etc. In boron carbonitride as a layered material, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane. A chalcogenide is a compound containing a chalcogen element. In addition, chalcogen elements are a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited.

[0274] As the semiconductor layer, for example, it is preferably used a transition metal chalcogenide used as a semiconductor. Specifically, as transition metal chalcogenides that can be used as the semiconductor layer, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited. By using the above transition metal chalcogenides for the semiconductor layer, a storage device with a large on-state current can be provided.

[0275] According to one aspect of the present invention, a novel transistor, a novel semiconductor device, and a novel storage device can be provided. In addition, a storage device capable of miniaturization or high integration can be provided. In addition, a storage device with good frequency characteristics can be provided. In addition, a storage device with a high operating speed can be provided. In addition, a storage device with high reliability can be provided. In addition, a storage device with low power consumption can be provided. In addition, a storage device including a transistor with a large on-state current can be provided. In addition, a storage device with small non-uniformity of transistor characteristics can be provided. In addition, a storage device with good electrical characteristics can be provided.

[0276] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments.

[0277] (Embodiment 2) In this embodiment, a structural example of a storage device according to one aspect of the present invention will be described with reference to the drawings.

[0278] Figure 15A A three-dimensional schematic diagram of a storage device according to one aspect of the present invention is shown.Figure 15B A block diagram of a storage device showing one embodiment of the present invention.

[0279] Figure 15A and Figure 15B The storage device 750 shown includes a drive circuit layer 701 and n storage layers 700 (n is an integer of 1 or more). Each of the storage layers 700 includes a memory cell array 10. The memory cell array 10 includes a plurality of memory cells 11.

[0280] The n storage layers 700 are provided on the drive circuit layer 701. By providing the n storage layers 700 on the drive circuit layer 701, the occupied area of the storage device 750 can be reduced. In addition, the storage capacity per unit area can be increased.

[0281] In the present embodiment, the first storage layer 700 is denoted as storage layer 700_1, the second storage layer 700 is denoted as storage layer 700_2, and the third storage layer 700 is denoted as storage layer 700_3. In addition, the k-th storage layer 700 (k is an integer of 1 or more and n or less) is denoted as storage layer 700_k, and the n-th storage layer 700 is denoted as storage layer 700_n. In addition, in the present embodiment and the like, when explaining matters related to the entire n storage layers 700 or matters common to the respective layers of the n storage layers 700, it is sometimes simply denoted as "storage layer 700".

[0282] The drive circuit layer 701 includes PSW22 (power switch), PSW23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32 (Control Circuit), and a voltage generation circuit 33.

[0283] In the storage device 750, the above-described respective circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals can be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and the signal RDA is a signal output to the outside.

[0284] The signal CLK is a clock signal. The signals BW, CE, and GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are signals for power gating control. In addition, the signals PON1 and PON2 can also be generated in the control circuit 32.

[0285] The control circuit 32 is a logic circuit that functions to control the overall operation of the storage device 750. For example, the control circuit performs logical operations on the signals CE, GW, and BW to determine the operating mode of the storage device 750 (e.g., write operation, read operation). Alternatively, the control circuit 32 generates control signals for the peripheral circuit 41 to execute the above-mentioned operating modes.

[0286] The voltage generation circuit 33 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when a signal of H level is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.

[0287] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cell 11. The peripheral circuit 41 includes a row decoder 42 (Row Decoder), a column decoder 44 (Column Decoder), a row driver 43 (Row Driver), a column driver 45 (Column Driver), an input circuit 47 (Input Cir.), an output circuit 48 (Output Cir.), and a sense amplifier 46 (Sense Amplifier).

[0288] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to be accessed, and the column decoder 44 is a circuit for specifying the column to be accessed. The row driver 43 has the function of selecting the wiring WWL (write word line) or the wiring RWL (read word line) specified by the row decoder 42. The column driver 45 has the following functions: the function of writing data to the memory cell 11; the function of reading data from the memory cell 11; the function of holding the read data, etc. The column driver 45 has the function of selecting the wiring WBL (write bit line) or the wiring RBL (read bit line) specified by the column decoder 44.

[0289] The input circuit 47 has the function of holding the signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory cell 11. The data (Dout) read from the memory cell 11 by the column driver 45 is output to the output circuit 48. The output circuit 48 has the function of holding Dout. In addition, the output circuit 48 has the function of outputting Dout to the outside of the storage device 750. The data output from the output circuit 48 is the signal RDA.

[0290] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the storage device 750 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage used to make the word line high level, which is higher than VDD. The on / off of PSW22 is controlled by the signal PON1, and the on / off of PSW23 is controlled by the signal PON2. In Figure 15B the number of power domains supplied with VDD in the peripheral circuit 31 is 1, but it can also be multiple. At this time, a power switch can be set for each power domain.

[0291] An example of the structure of the n-layer storage layer 700 will be described. Each of the n-layer storage layers 700 includes a memory cell array 10. In addition, the memory cell array 10 includes a plurality of memory cells 11. In Figure 15A and Figure 15B an example is shown in which the memory cell array 10 includes a plurality of memory cells 11 configured in a matrix of p rows and q columns (p and q are integers of 2 or more).

[0292] In addition, the rows and columns extend in directions orthogonal to each other. In the present embodiment, the X direction is set as "row" and the Y direction is set as "column", but the X direction can also be set as "column" and the Y direction can be set as "row".

[0293] In Figure 15B the memory cell 11 provided in the first row and the first column is denoted as the memory cell 11[1, 1], and the memory cell 11 provided in the p-th row and the q-th column is denoted as the memory cell 11[p, q]. In addition, the memory cell 11 provided in the i-th row and the j-th column (i is an integer of 1 or more and p or less, and j is an integer of 1 or more and q or less) is denoted as the memory cell 11[i, j].

[0294] As an example of the circuit structure of the memory cell 11, the structure (memory cell 150) described in the above embodiment can be used.

[0295] In addition, when the storage layer 700 adopts a stacked structure, it is preferable to arrange the wiring WBL and the wiring RBL in a direction perpendicular to the substrate surface. By arranging the wiring WBL and the wiring RBL in a direction perpendicular to the substrate surface, the signal transmission distance between them and the sense amplifier connected to the wiring WBL and the wiring RBL can be shortened, and the resistance and parasitic capacitance of the wiring WBL and the wiring RBL can be greatly reduced, thereby reducing power consumption and signal delay.

[0296] The configurations, structures, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments and examples.

[0297] (Embodiment 3) In this embodiment, electronic components, electronic devices, mainframes, space devices, and data centers (also referred to as DCs) that can use the storage device described in the above embodiments will be described. The use of the electronic components, electronic devices, mainframes, space devices, and data centers of one aspect of the present invention is effective for achieving high performance such as low power consumption.

[0298] [Electronic Component] Figure 16A A perspective view of a substrate (circuit board 704) on which an electronic component 709 is mounted is shown. Figure 16A The shown electronic component 709 includes a storage device 710 within a mold 711. In Figure 16A , a part of the electronic component 709 is omitted from the description to show its interior. The electronic component 709 includes lands 712 outside the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the storage device 710 through leads 714. The electronic component 709 is mounted on, for example, a printed circuit board 702. By combining a plurality of such electronic components and electrically connecting them to the printed circuit board 702 respectively, the circuit board 704 is completed.

[0299] In addition, the storage device 710 includes a drive circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the drive circuit layer 715 and the storage layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding are not required to connect between layers. When the drive circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0300] In addition, by adopting the on-chip memory structure, compared with technologies using through-electrodes such as TSV, the size of connection wirings and the like can be reduced, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, and thus the memory bandwidth (also referred to as memory bandwidth) can be increased.

[0301] In addition, preferably, a plurality of memory cell arrays in the memory layer 716 are formed using OS transistors, and the plurality of memory cell arrays are stacked in a monolithic manner. When the plurality of memory cell arrays are monolithically stacked, either or both of the bandwidth of the memory and the access latency of the memory can be improved. The bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time between access and the start of data exchange. When Si transistors are used in the memory layer 716, it is more difficult to implement a monolithic stacking structure compared to OS transistors. Therefore, in a monolithic stacking structure, OS transistors are superior to Si transistors.

[0302] In addition, the storage device 710 may be referred to as a die. In this specification and the like, a die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also referred to as a wafer) or the like in the manufacturing process of a semiconductor chip and cutting it into rectangular small pieces. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also referred to as a silicon wafer) is sometimes referred to as a silicon die.

[0303] Next, Figure 16B A perspective view of the electronic component 730 is shown. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 710 are provided on the interposer 731.

[0304] The electronic component 730 shows an example of using the storage device 710 as a high bandwidth memory (HBM: High Bandwidth Memory). In addition, the semiconductor device 735 can be used for integrated circuits such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0305] The package substrate 732 can use, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can use, for example, a silicon interposer or a resin interposer.

[0306] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are composed of a single layer or multiple layers. In addition, the interposer 731 has a function to electrically connect the integrated circuits provided on the interposer 731 to the electrodes provided on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or an "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through this through electrode. In addition, in the case of using a silicon interposer, TSV can also be used as the through electrode.

[0307] In HBM, in order to achieve a wide memory bandwidth, many wirings need to be connected. For this purpose, it is required that fine wirings can be formed at a high density on the interposer on which HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer for mounting HBM.

[0308] In addition, in SiP, MCM, etc. that use a silicon interposer, it is not easy to cause a decrease in reliability due to the difference in the coefficient of thermal expansion between the integrated circuit and the interposer. In addition, due to the high surface flatness of the silicon interposer, it is not easy to generate a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer. It is particularly preferable to use a silicon interposer for a 2.5D package (2.5D mounting), in which multiple integrated circuits are arranged horizontally and configured on the interposer.

[0309] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer and TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when trying to reduce the size of the electronic component 730, the width of the above terminal pitch becomes a problem, and it is sometimes difficult to set a large number of wirings required to achieve a wide memory bandwidth. Thus, as described above, a structure of a monolithic stack using OS transistors is preferable. In addition, a composite structure that combines a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be adopted.

[0310] In addition, a heat sink (heat dissipation plate) can also be provided overlapping the electronic component 730. In the case of providing a heat sink, it is preferable to make the heights of the integrated circuits provided on the interposer 731 the same. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the storage device 710 and the semiconductor device 735 the same.

[0311] In order to mount the electronic component 730 on another substrate, electrodes 733 can also be provided at the bottom of the package substrate 732. Figure 16BAn example of forming the electrode 733 with solder balls is shown. By arranging solder balls in a matrix at the bottom of the package substrate 732, the installation of BGA (Ball Grid Array) can be achieved. In addition, the electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix at the bottom of the package substrate 732, the installation of PGA (Pin Grid Array) can be achieved.

[0312] The electronic component 730 can be installed on other substrates by various installation methods, not limited to BGA and PGA. As installation methods, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package) can be cited.

[0313] [Electronic device] Next, Figure 17A A perspective view of the electronic device 6500 is shown. Figure 17A The shown electronic device 6500 is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, buttons 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, etc. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. The storage device of one aspect of the present invention can be used for the display unit 6502, the control device 6509, etc.

[0314] Figure 17B The shown electronic device 6600 is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, etc. The control device 6616 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. The storage device of one aspect of the present invention can be used for the display unit 6615, the control device 6616, etc. In addition, by using the storage device of one aspect of the present invention for the above control device 6509 and control device 6616, power consumption can be reduced, so it is preferable.

[0315] [Mainframe computer] Next, Figure 17CA perspective view of a mainframe computer 5600 is shown. In Figure 17C In the shown mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. In addition, the mainframe computer 5600 may also be referred to as a supercomputer.

[0316] The computer 5620 may, for example, have Figure 17D the structure of the perspective view shown. In Figure 17D it, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals, etc. A personal computer card 5621 is inserted into the slot 5631. And, the personal computer card 5621 includes connection terminals 5623, 5624, 5625, which are connected to the motherboard 5630.

[0317] Figure 17E The shown personal computer card 5621 is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and a connection terminal 5629. Note that Figure 17E a perspective view shows semiconductor devices other than the semiconductor devices 5626, 5627, and 5628. For the description of these semiconductor devices, refer to the description of the semiconductor devices 5626, 5627, and 5628 described below.

[0318] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the specifications of the connection terminal 5629 may include PCIe, etc.

[0319] The connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for supplying power to the personal computer card 5621 or inputting signals, etc. In addition, for example, it can be used as an interface for outputting signals calculated by the personal computer card 5621, etc. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. In addition, when outputting a video signal from the connection terminals 5623, 5624, and 5625, examples of the specifications include HDMI (registered trademark), etc.

[0320] The semiconductor device 5626 includes terminals (not shown) for inputting and outputting signals. By inserting these terminals into sockets (not shown) included in the board 5622, the semiconductor device 5626 and the board 5622 can be electrically connected.

[0321] The semiconductor device 5627 includes a plurality of terminals. For example, by soldering these terminals to the wiring included in the board 5622 by reflow soldering, the semiconductor device 5627 and the board 5622 can be electrically connected. Examples of the semiconductor device 5627 include FPGA, GPU, CPU, etc. As the semiconductor device 5627, for example, the electronic component 730 can be used.

[0322] The semiconductor device 5628 includes a plurality of terminals. For example, by soldering these terminals to the wiring included in the board 5622 by reflow soldering, the semiconductor device 5628 and the board 5622 can be electrically connected. Examples of the semiconductor device 5628 include storage devices, etc. As the semiconductor device 5628, for example, the electronic component 709 can be used.

[0323] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

[0324] [Space equipment] The storage device according to one aspect of the present invention can be applied to space equipment such as devices for processing and storing information.

[0325] A storage device according to one embodiment of the present invention may include an OS transistor. The OS transistor has a small change in electrical characteristics due to irradiation with radiation. In other words, it has high resistance to radiation, so it can be appropriately used even in an environment where radiation may be incident. For example, the OS transistor can be appropriately used when used in outer space.

[0326] In Figure 18 , as an example of a space device, a satellite 6800 is shown. The satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In addition, Figure 18 An example of a planet 6804 in outer space is shown. Note that outer space generally refers to an altitude of 100 km or more, but the outer space shown in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0327] In addition, although Figure 18 not shown in the figure, a battery management system (also referred to as BMS) or a battery control circuit may be provided in the secondary battery 6805. When the OS transistor is used in the above battery management system or battery control circuit, the power consumption is low and high reliability can be achieved even in outer space, so it is preferred.

[0328] In addition, outer space is an environment where the radiation dose is 100 times or more that of the ground. As radiation, for example, electromagnetic waves (electromagnetic radiation) represented by X-rays and γ-rays can be cited; and particle radiation represented by α-rays, β-rays, neutron rays, proton rays, heavy ion rays, meson rays, etc.

[0329] When sunlight irradiates the solar panel 6802, the power required for the satellite 6800 to operate is generated. However, for example, when sunlight does not irradiate the solar panel or when the amount of sunlight irradiating the solar panel is small, the amount of generated power decreases. Therefore, it may not be possible to generate the power required for the satellite 6800 to operate. In order to make the satellite 6800 operate even when the generated power is small, it is preferred to provide a secondary battery 6805 in the satellite 6800. In addition, the solar panel is sometimes referred to as a solar cell module.

[0330] The satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803 and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that receives the signal can be measured. Thus, the satellite 6800 can constitute a satellite positioning system.

[0331] In addition, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is constituted by, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, it is preferable to use the storage device of one aspect of the present invention for the control device 6807. Compared with Si transistors, the OS transistor has less change in electrical characteristics due to irradiation with radiation. That is, the OS transistor has high reliability even in an environment where radiation may enter and can be appropriately used.

[0332] In addition, the artificial satellite 6800 may include sensors. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected by an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays released from the earth's surface. Thus, the artificial satellite 6800 can be used as, for example, an earth observation satellite.

[0333] Note that in the present embodiment, an artificial satellite is shown as an example of a space device, but it is not limited thereto. For example, the storage device of one aspect of the present invention can be appropriately applied to space devices such as spacecraft, space capsules, and space probes.

[0334] As described above, compared with Si transistors, the OS transistor has excellent effects such as being able to achieve a wider memory bandwidth and high radiation resistance.

[0335] [Data Center] For example, the storage device of one aspect of the present invention can be applied to a storage system adopted in a data center or the like. A data center is required to ensure data immutability and perform long-term management of data. When performing long-term management of data, it is necessary to make the facility large-scale, such as setting up storage and servers for storing a huge amount of data, ensuring stable power to maintain data, or ensuring cooling equipment required during data retention.

[0336] By using the storage device of one aspect of the present invention for the storage system adopted in a data center, it is possible to reduce the power required for data retention and miniaturize the storage device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, and reduce the scale of the cooling equipment. Thus, it is possible to save space in the data center.

[0337] In addition, the power consumption of the storage device of one aspect of the present invention is small, so the circuit heat generation can be reduced. Thus, the negative impacts on the circuit itself, the peripheral circuit, and the module caused by this heat generation can be reduced. In addition, by using the storage device of one aspect of the present invention, it is possible to realize a data center that operates stably even in a high-temperature environment. Therefore, the reliability of the data center can be improved.

[0338] Figure 19 Shows a storage system that can be used in a data center. Figure 19 The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (illustrated as a main computer). In addition, as storage 7003 (illustrated as storage), it includes a plurality of storage devices 7003md. The form in which the host 7001 and the storage 7003 are connected through a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as a storage controller) is shown.

[0339] The host 7001 is equivalent to a computer that accesses data stored in the storage 7003. The hosts 7001 can also be connected to each other through a network.

[0340] In the storage 7003, by using a flash memory, the access speed of data is shortened, that is, the time required for data storage and output is shortened. However, this time is much longer than the time required for DRAM that can be used as a cache memory in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is generally set in the storage to shorten data storage and output.

[0341] The above cache memory is used in the storage control circuit 7002 and the storage 7003. The data exchanged between the host 7001 and the storage 7003 is output to the host 7001 or the storage 7003 after being stored in the cache memory in the storage control circuit 7002 and the storage 7003.

[0342] When an OS transistor is used as a transistor for storing the data of the above cache memory to maintain the potential corresponding to the data, the refresh frequency can be reduced to lower the power consumption. In addition, miniaturization can be achieved by stacking the memory cell arrays.

[0343] Note that by using the storage device of one embodiment of the present invention for any one or more selected from electronic components, electronic devices, mainframes, space devices, and data centers, an effect of reducing power consumption can be expected. Therefore, currently, it is considered that as the performance or integration of storage devices increases, the energy demand also increases. By using the storage device of one embodiment of the present invention, the emissions of greenhouse gases represented by carbon dioxide (CO2) can also be reduced. In addition, the storage device of one embodiment of the present invention has low power consumption, so it is also effective as a measure against global warming.

[0344] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments, etc. [Symbol Description]

[0345] 11: Memory cell, 22: PSW, 23: PSW, 31: Peripheral circuit, 32: Control circuit, 33: Voltage generation circuit, 41: Peripheral circuit, 42: Row decoder, 43: Row driver, 44: Column decoder, 45: Column driver, 46: Sense amplifier, 47: Input circuit, 48: Output circuit, 100: Transistor, 110: Wiring, 120: Conductor, 130: Insulator, 140: Wiring, 150: Memory cell, 160: Insulator, 170: Oxide semiconductor, 180: Insulator, 181: Insulator, 185: Insulator, 190: Opening, 200: Transistor, 210: Wiring, 220: Conductor, 230: Insulator, 240: Wiring, 270i: Region, 270na: Region, 270nb: Region, 270: Oxide semiconductor, 280: Insulator, 285: Insulator, 290: Opening, 300: Capacitor, 310: Wiring, 320: Conductor, 330: Insulator, 380: Insulator, 385: Insulator, 390: Opening, 700_1: Storage layer, 700_2: Storage layer, 700_3: Storage layer, 700_k: Storage layer, 700_n: Storage layer, 700: Storage layer, 701: Driver circuit layer, 702: Printed circuit board, 704: Circuit board, 709: Electronic component, 710: Storage device, 711: Die, 712: Land, 713: Electrode pad, 714: Lead, 715: Driver circuit layer, 716: Storage layer, 730: Electronic component, 731: Daughter board, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 750: Storage device, 5600: Mainframe computer, 5610: Rack, 5620: Computer, 5621: Personal computer card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6509: Control device, 6600: Electronic device, 6611: Housing, 6612: Keyboard, 6613: Pointing device, 6614: External connection port, 6615: Display unit, 6616: Control device, 6800: Satellite, 6801: Body, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7000: Storage system, 7001sb: Server, 7001: Host, 7002: Storage control circuit, 7003md: Storage device, 7003: Storage

Claims

1. A storage device, comprising: Memory cell; First wiring; Second wiring; And Third wiring, wherein the memory cell includes a first transistor and a second transistor, the second transistor is disposed above the first transistor, the first transistor includes a first semiconductor, a first insulator, and a first conductor, the first semiconductor has a region formed on a side surface of a first opening penetrating the first wiring, a second insulator, and the second wiring, the first insulator has a region covering the first opening in contact with the first semiconductor, the first conductor is disposed to be embedded in the first opening in contact with the first insulator, the second transistor includes a second semiconductor, the second semiconductor has a region disposed on a side surface of a second opening penetrating a third insulator and the third wiring, and the second semiconductor has a region in contact with the first conductor at a bottom of the second opening.

2. The storage device according to claim 1, wherein the second wiring is disposed on the second insulator and the second insulator is disposed on the first wiring.

3. The storage device according to claim 1, wherein the second transistor includes a fourth insulator and a second conductor, the fourth insulator has a region covering the second opening in contact with the second semiconductor, and the second conductor is disposed in a manner of being embedded in the second opening in contact with the fourth insulator.

4. The storage device according to claim 1, wherein the third wiring is disposed on the third insulator and the third insulator is disposed on the first conductor.

5. The storage device according to claim 1, wherein the first wiring has a region serving as one of the source electrode and the drain electrode of the first transistor, the second wiring has a region serving as the other of the source electrode and the drain electrode of the first transistor, the third wiring has a region serving as one of the source electrode and the drain electrode of the second transistor, and the first conductor has a region serving as the gate electrode of the first transistor and a region serving as the other of the source electrode and the drain electrode of the second transistor.

6. A storage device, comprising: Memory cell; First wiring; Second wiring; And Third wiring, wherein the memory cell includes a first transistor and a second transistor, the second transistor is disposed above the first transistor, the first transistor includes a first semiconductor, a first insulator, and a first conductor, the first semiconductor has a region formed on a side surface of a first opening penetrating the first wiring, a second insulator, the second wiring, and a third insulator, the first insulator has a region covering the first opening in contact with the first semiconductor, the first conductor is disposed to be embedded in the first opening in contact with the first insulator, the second transistor includes a second semiconductor, the second semiconductor has a region disposed on a side surface of a second opening penetrating a fourth insulator and the third wiring, and the second semiconductor has a region in contact with the first conductor at a bottom of the second opening.

7. The storage device according to claim 6, wherein the third insulator is disposed on the second wiring, the second wiring is disposed on the second insulator, and the second insulator is disposed on the first wiring.

8. The storage device according to claim 6, wherein the second transistor includes a fifth insulator and a second conductor, the fifth insulator has a region covering the second opening in contact with the second semiconductor, and the second conductor is disposed to be embedded in the second opening in contact with the fifth insulator.

9. The storage device according to claim 6, wherein the third wiring is disposed on the fourth insulator, and the fourth insulator is disposed on the first conductor.

10. The storage device according to claim 6, wherein the first wiring has a region serving as one of the source electrode and the drain electrode of the first transistor, the second wiring has a region serving as the other of the source electrode and the drain electrode of the first transistor, the third wiring has a region serving as one of the source electrode and the drain electrode of the second transistor, and the first conductor has a region serving as the gate electrode of the first transistor and a region serving as the other of the source electrode and the drain electrode of the second transistor.

11. A storage device, comprising: Memory cell; First wiring; Second wiring; Third wiring; And Fourth wiring, wherein the memory cell includes a first transistor, a second transistor, and a capacitor, the capacitor is disposed between the first transistor and the second transistor, the first transistor includes a first semiconductor, a first insulator, and a first conductor, the first semiconductor has a region formed on a side surface of a first opening penetrating the first wiring, a second insulator, and the second wiring, the first insulator has a region covering the first opening in contact with the first semiconductor, the first conductor is disposed to be embedded in the first opening in contact with the first insulator, the capacitor includes a third insulator and a second conductor, the third insulator has a region formed on a side surface of a second opening penetrating a fourth insulator and the third wiring, the second conductor is disposed to be embedded in the second opening in contact with the third insulator, the second conductor has a region in contact with the first conductor at a bottom of the second opening, the second transistor includes a second semiconductor, the second semiconductor has a region disposed on a side surface of a third opening penetrating a fifth insulator and the fourth wiring, Moreover, the second semiconductor has a region that contacts the second conductor at the bottom of the third opening.

12. The storage device according to claim 11, wherein the second wiring is provided on the second insulator, the second insulator is provided on the first wiring, and the third wiring is provided on the fourth insulator.

13. The storage device according to claim 11, wherein the second transistor includes a sixth insulator and a third conductor, the sixth insulator has a region covering the third opening in contact with the second semiconductor, and the third conductor is provided in such a manner as to be embedded in the third opening in contact with the sixth insulator.

14. The storage device according to claim 11, wherein the fourth wiring is provided on the fifth insulator and the fifth insulator is provided on the second conductor.

15. The storage device according to claim 11, wherein the first wiring has a region serving as one of the source electrode and the drain electrode of the first transistor, the second wiring has a region serving as the other of the source electrode and the drain electrode of the first transistor, the third wiring has a region serving as one electrode of the capacitor, the fourth wiring has a region serving as one of the source electrode and the drain electrode of the second transistor, the first conductor has a region serving as the gate electrode of the first transistor, And the second conductor has a region serving as the other electrode of the capacitor and a region serving as the other of the source electrode and the drain electrode of the second transistor.

16. The storage device according to any one of claims 1 to 15, wherein the first semiconductor and the second semiconductor are both oxide semiconductors, and the oxide semiconductor contains one or more selected from In, Ga, and Zn.

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