Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a display area and a peripheral area, the peripheral area comprises a plurality of fillet areas; a plurality of stages of effective shift registers arranged in sequence and a first virtual shift register arranged in front of the last stage of effective shift register are arranged in the fillet area; the first virtual shift register is used for connecting the adjacent stage of effective shift register and enabling the adjacent stage of effective shift register to be arranged in parallel and correspondingly; each stage of effective shift register comprises a first number of effective shift register units; the first virtual shift register comprises a first number of virtual shift register units; in the fillet area of the at least one peripheral area, one side, far away from the display area, of the last stage of effective shift register lacks a second number of effective shift register units; the side, away from the display area, of the first virtual shift register lacks a second number of virtual shift register units and comprises a second number of effective shift register units.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the increasing demand of consumers for a larger screen-to-body ratio, narrow-bezel screens are becoming the mainstream in the market development. However, with the narrowing of the bezel part, the requirements for the driving control unit (GOA) are getting higher and higher during the design process, and the requirements for optimizing the spatial layout of the GOA are also getting higher and higher. Summary of the Invention

[0003] In view of this, the purpose of the present application is to provide a display panel and a display device.

[0004] Based on the above purpose, the present application provides a display panel, including: a display area; and a peripheral area disposed around the display area;

[0005] Wherein, the peripheral area includes a plurality of rounded corner areas; a multi-stage effective shift register arranged in sequence is disposed in the rounded corner area, and a first virtual shift register is disposed before the last-stage effective shift register; the first virtual shift register is used to connect adjacent-stage effective shift registers and make the adjacent-stage effective shift registers parallel and correspondingly arranged; each stage of the effective shift register respectively includes a first number of effective shift register units; the first virtual shift register includes a first number of virtual shift register units;

[0006] Wherein, in the rounded corner area of at least one of the peripheral areas, a second number of effective shift register units are missing on the side of the last-stage effective shift register away from the display area; a second number of virtual shift register units are missing on the side of the first virtual shift register away from the display area, and the first virtual shift register includes a second number of effective shift register units; the second number is less than the first number; the second number of effective shift register units in the first virtual shift register are connected to the remaining effective shift register units in the last-stage effective shift register.

[0007] In some embodiments, the missing second number of effective shift register units is missing one effective shift register unit; the missing second number of virtual shift register units is missing one virtual shift register unit.

[0008] In some embodiments, the missing second number of effective shift register units is missing multiple effective shift register units; the missing second number of virtual shift register units is missing multiple virtual shift register units;

[0009] Among them, the arrangement of the second number of effective shift register units included in the first virtual shift register is the same as that of the second number of effective shift register units on the side away from the display area in the effective shift registers except for the last-stage effective shift register.

[0010] In some embodiments, only the effective shift register units near the display area and connected to the gate lines of the display area are included in the last-stage effective shift register.

[0011] In some embodiments, the structure of the second number of effective shift register units included in the first virtual shift register is the same as that of the second number of effective shift register units on the side away from the display area in the effective shift registers except for the last-stage effective shift register.

[0012] In some embodiments, the output ends of the effective shift register units in the first virtual shift register are jump-connected to the gate lines of the display area.

[0013] In some embodiments, the first number is three, four, or five; the multi-stage effective shift registers are respectively used to drive multiple rows of pixels.

[0014] In some embodiments, the first number is four, and the number of pixel rows driven by the remaining effective shift register units in the last-stage effective shift register is less than the number of pixel rows driven by the missing second number of effective shift register units.

[0015] In some embodiments, at least one second virtual shift register is further included in the rounded corner area of the peripheral area, and the second virtual shift register is alternately arranged with a preset number of effective shift registers, so that the multi-stage effective shift registers are arranged in parallel and corresponding one by one.

[0016] In some embodiments, the second virtual shift register and the first virtual shift register are arranged adjacent to each other and alternately arranged with two-stage effective shift registers.

[0017] In some embodiments, the at least one rounded corner area of the peripheral area includes a plurality of rounded corner areas.

[0018] In some embodiments, among the plurality of rounded corner areas, the number of the second number of effective shift register units missing on the side away from the display area in the last-stage effective shift register is the same.

[0019] In some embodiments, among the plurality of rounded corner areas, the number of the second number of effective shift register units missing on the side away from the display area in the last-stage effective shift register is different.

[0020] In some of these embodiments, data traces are further included, and part of the data traces are disposed in the region between the end of the last-stage active shift register away from the display area and the border of the peripheral area away from the display area.

[0021] An embodiment of the present application further provides a display device, including the display panel as shown in any of the previous items.

[0022] As can be seen from the above, the display panel provided by the present application includes: a display area; and a peripheral area disposed around the display area; wherein the peripheral area includes a plurality of rounded corner areas; a multi-stage active shift register arranged in sequence is disposed in the rounded corner area, and a first virtual shift register is disposed before the last-stage active shift register; the first virtual shift register is used to connect adjacent-stage active shift registers and make the adjacent-stage active shift registers parallel and correspondingly arranged; each stage of active shift register respectively includes a first number of active shift register units; the first virtual shift register includes a first number of virtual shift register units; wherein, in the rounded corner area of at least one of the peripheral areas, a second number of active shift register units are missing on the side of the last-stage active shift register away from the display area; a second number of virtual shift register units are missing on the side of the first virtual shift register away from the display area, and the first virtual shift register includes a second number of active shift register units; the second number is less than the first number; the second number of active shift register units in the first virtual shift register are connected to the remaining active shift register units in the last-stage active shift register, thereby increasing the width of the VSS area of the rounded corner part, and to a certain extent solving the problem of excessive current caused by too narrow part of the VSS traces, resulting in adverse problems such as burning. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 Schematic diagram of the regional distribution of an exemplary display panel according to an embodiment of the present application;

[0025] Figure 2 Schematic diagram of an exemplary display area according to an embodiment of the present application;

[0026] Figure 3 Another schematic diagram of the regional distribution of an exemplary display panel according to an embodiment of the present application;

[0027] Figure 4a An exemplary schematic diagram of the alternating arrangement of an effective shift register and a virtual shift register according to an embodiment of the present application;

[0028] Figure 4b Another exemplary schematic diagram of the alternating arrangement of an effective shift register and a virtual shift register according to an embodiment of the present application;

[0029] Figure 4c Another exemplary schematic diagram of the alternating arrangement of an effective shift register and a virtual shift register according to an embodiment of the present application;

[0030] Figure 4d An exemplary schematic diagram of the alternating arrangement of an effective shift register and a virtual shift register without missing effective shift register units according to an embodiment of the present application;

[0031] Figure 5a An exemplary schematic diagram of an effective shift register without missing a second quantity of effective shift register units according to an embodiment of the present application;

[0032] Figure 5b An exemplary schematic diagram of an effective shift register missing a second quantity of effective shift register units according to an embodiment of the present application;

[0033] Figure 5c Another exemplary schematic diagram of an effective shift register missing a second quantity of effective shift register units according to an embodiment of the present application. Detailed implementation manners

[0034] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0035] It should be noted that unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the ordinary meanings understood by those of ordinary skill in the field to which the present application belongs. The "first", "second" and similar terms used in the embodiments of the present application do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0036] As people's requirements for display screens are getting higher and higher, such as a larger screen-to-body ratio, etc., the development trend of displays such as mobile phones is to have an increasingly large display area ratio. Therefore, the bezels of mobile phones tend to gradually narrow. At the same time, in order to meet higher requirements for the display effect of the display screen, such as refresh rate and contrast, the structure of the driving control circuit (Gate Driver on Array, GOA) becomes more and more complex, and it will occupy more space in the layout. In the related art, at the rounded corners of the bezel, due to the too small space, there may often be a situation where the remaining routing space of the VSS power line after the GOA layout is too narrow, resulting in too small a width of the VSS routing. After the process is completed, there will be a situation where the current in the VSS routing part of the rounded corner area is too large, resulting in adverse problems such as burns.

[0037] Based on this, the embodiment of the present application provides a display panel. By optimizing the GOA arrangement in the rounded corner area, omitting part of the EM GOA units in the last row of effective GOA in the GOA, and replacing part of the EM GOA units in the dummy GOA before the last row of effective GOA in the GOA unit with the omitted part of the EM GOA units in the last row of effective GOA, it is possible to optimize the layout and arrangement of part of the GOA, thereby increasing the width of the VSS area in the rounded corner part, and to a certain extent solving the adverse problems such as burns caused by too large current due to too narrow part of the VSS routing.

[0038] Figures 1 to 3 The structural schematic diagram of an exemplary display panel according to the embodiment of the present application is shown.

[0039] As Figure 1 shown, the embodiment of the present application can be as Figure 1 shown. The above display panel 100 includes: a display area 11 (active area, AA; hereinafter referred to as the AA area; also referred to as the effective display area 11) and a peripheral area 12 disposed around the display area 11 in a circle. The display panel can be an Organic Light Emitting Diode (OLED) display panel, a Quantum Dot Light Emitting Diodes (QLED) display panel, a Micro Light Emitting Diodes (Micro LED) display panel, etc. The present invention does not make specific limitations in this regard. In some embodiments, the display panel can be a flexible display panel.

[0040] The following embodiments will be described by taking the display panel as a flexible organic light emitting diode display panel as an example.

[0041] As Figure 2As shown, the display area 11 is an area corresponding to the pixel array, which may further include a plurality of pixel areas 111 arranged in an array. The pixel area 111 may further include a plurality of sub-pixels 112. It should be noted that Figure 2 This is only an exemplary illustration of the relative positional relationship of the sub-pixels 112 in the pixel area 111 and the arrangement of the pixel area 111 in the display area 1110. It can be understood that in actual products, the arrangement of the sub-pixels 112, the size of the pixel area 111, and the arrangement method, etc. can all be adjusted according to actual needs.

[0042] In some embodiments, the pixel area 111 may include a plurality of sub-pixels 112. For example, three sub-pixels 112. These three sub-pixels 112 may further include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Thus, the pixel area 111 can achieve full-color display under the drive of the pixel circuit. It can be understood that in order to achieve different effects or functions, the number and colors of the sub-pixels 112 in the pixel area 111 can be selected by those skilled in the art, not limited to the examples given here.

[0043] In some embodiments, the display area 11 may further include a plurality of gate lines and a plurality of data lines arranged crosswise. The gate lines are used to provide an enable signal, and the data lines are used to provide a data signal. Thus, the pixel circuit can use this data signal to drive the sub-pixels 112. A gate driving circuit 121 connected to the gate lines and a data driving circuit connected to the data lines may be provided in the peripheral area 12.

[0044] In some embodiments, the gate driving circuit 121 may be provided on a side along the extending direction of the gate lines, and the data driving circuit may be provided on a side along the extending direction of the data lines.

[0045] In some embodiments, in order to reduce the manufacturing cost of the display panel and narrow the border width of the display device, the gate driving circuit 121 may be a GOA circuit, that is, the above-mentioned gate driving circuit 121 is directly integrated in the array substrate of the display panel.

[0046] In some embodiments, as Figure 3 shown, the display panel may be provided with GOA circuits on two sides along the extending direction of the gate lines in the peripheral area 12, and the respective gate lines are driven row by row simultaneously from both sides by the two gate driving circuits 121, that is, bilateral simultaneous driving. In some other embodiments, the display panel may also be provided with a GOA circuit on only one side along the extending direction of the gate lines in the peripheral area 12. Among them, the gate driving circuit 121 may include a plurality of stages of shift registers arranged in sequence.

[0047] Figures 4a to 4dA schematic diagram showing a plurality of cascaded shift registers in a rounded corner region 122 of an exemplary peripheral region 12 of an embodiment of the present application is shown.

[0048] As Figures 4a to 4c shown, in some embodiments, in the rounded corner regions 122 (such as the upper rounded corner region and the lower rounded corner region, etc.) of the peripheral region 12, a plurality of shift registers cascaded in a first direction can generally be included. Among them, the plurality of cascaded shift registers may include: a plurality of stages of active shift registers 123 arranged in sequence, and dummy shift registers (dummy GOA) alternately arranged with a preset number of stages of active shift registers 123. Among them, the dummy shift registers can be used to connect the adjacent active shift registers 123 and to fill the gaps between the adjacent active shift registers 123, so that the multi-stage active shift registers 123 in the rounded corner region 122 can be arranged in parallel and corresponding one by one.

[0049] Among them, the composition and structure of the active shift register unit included in each stage of the dummy shift register for connecting the dummy shift register unit can be the same as those of the active shift register unit included in the active shift register 123, except that each stage of the dummy shift register is not connected to the gate lines of the display region 11. In addition, there will be transistors with interrupted signals among the plurality of transistors in the dummy shift register, so that the dummy shift register only serves to connect the upper-stage active shift register 123 and the lower-stage active shift register 123. Specifically, when patterning using a mask process, the specific pattern for forming the dummy shift register unit can be the same as the specific pattern for forming the active shift register unit 1231 of the active shift register 123.

[0050] Among them, each level of valid shift register 123 is respectively connected to the gate lines of the display area 11. The output signal of the current level of valid shift register 123 can be output to the previous level of valid shift register 123 (if any) through the previous level of virtual shift register (if any), serving as the reset signal of the previous level of valid shift register 123; it can also be output to the next level of valid shift register 123 (if any) through the next level of virtual shift register (if any), serving as the input signal of the next level of valid shift register 123. Among them, the input end of the first level of valid shift register 123 is connected to the start signal end. Except for the first level of valid shift register 123, the signal input end of any level of valid shift register 123 is connected to the signal output end of the valid shift register 123 at its previous level through a virtual shift register (if any) or directly (for example, there is no virtual shift register between adjacent levels of valid shift register 123); except for the last level of valid shift register 123, the reset signal end of any level of valid shift register 123 is connected to the signal output end of the valid shift register 123 at its next level through a virtual shift register (if any) or directly (for example, there is no virtual shift register between adjacent levels of valid shift register 123). In some possible embodiments, the reset signal end of the last level of valid shift register 123 can be connected through a reset control circuit. The reset control circuit can be configured to generate the reset signal of the last level of valid shift register 123.

[0051] Generally, there can be various ways of alternately arranging the virtual shift register and the valid shift register 123. Exemplarily, for example, Figure 4a As shown, two valid shift registers 123 and two virtual shift registers are alternately arranged. Exemplarily, for example, Figure 4b As shown, one valid shift register 123 and one virtual shift register are alternately arranged. Or, exemplarily, as Figure 4c As shown, two valid shift registers 123 and one virtual shift register are alternately arranged. In possible implementation manners, it can also be three or more valid shift registers 123 and one virtual shift register alternately arranged, etc. Specifically, it can be determined according to the size of the R corner of the rounded corner area 122 and the specific number of transistors and capacitors included in the valid shift register 123, etc., as long as the multi-level valid shift registers 123 arranged in the rounded corner area 122 can be arranged in parallel and correspondingly.

[0052] In some embodiments, the virtual shift register includes at least a first virtual shift register 124 disposed before the last-stage active shift register 123. The composition and structure of the virtual shift register cells included in the first virtual shift register 124 may be the same as those of the active shift register cells included in the active shift register 123. In other embodiments, the virtual shift register further includes at least one second virtual shift register 125, and the second virtual shift register 125 is alternately disposed with a preset number of active shift registers 123 so that the multi-stage active shift registers 123 are arranged in parallel and corresponding one by one. Among them, before the subsequent-stage active shift register 123, two levels of virtual shift registers may be included. For example, it includes one level of the second virtual shift register 125, and this one level of the second virtual shift register 125 may be disposed adjacent to the first virtual shift register 124 and alternately disposed with two levels of active shift registers 123.

[0053] In some embodiments, the active shift register 123 may include a plurality of (e.g., a first number of) active shift register cells 1231, and each active shift register cell 1231 may be respectively connected to different control signal lines. Each active shift register 123 may be respectively used to drive multiple rows (e.g., two rows) of pixels. The number of active shift register cells included in the active shift register 123 may be determined according to the type of the pixel circuit in the display area 11. Among them, the plurality of active shift register cells may respectively provide different types of turn-on signals for the pixel circuit and are respectively connected to the gate lines of the display area. For example, it may be connected to the gate lines of the display area through an adapter. For example, for a pixel circuit with transistors being low-temperature polysilicon transistors (LTPSTFTs), such as a 3T1C (including 3 thin-film transistors tft and 1 capacitor) pixel circuit, each stage of the active shift register 123 may include 3 active shift register cells. For example, for a pixel circuit with transistors being 7T1C (including 7 thin-film transistors tft and 1 capacitor), each stage of the active shift register 123 may include 4 active shift register cells. For example, for a pixel circuit with transistors being 8T2C (including 8 thin-film transistors tft and 2 capacitors), each stage of the active shift register 123 may include 5 active shift register cells, etc. Correspondingly, the first virtual shift register 124 may include a plurality of (e.g., a first number of) virtual shift register cells. For example, it may include 3 virtual shift register cells, 4 virtual shift register cells or 5 virtual shift register cells, etc. It can be specifically set according to different project requirements.

[0054] In some of these embodiments, in the rounded corner region 122 of at least one of the peripheral regions 12, on the side of the last-stage effective shift register 123 away from the display region 11, a second quantity of effective shift register units 1232 is missing; on the side of the first virtual shift register 124 away from the display region 11, a second quantity of virtual shift register units 1242 is missing, and it includes a second quantity of effective shift register units 1232; the second quantity is less than the first quantity; the second quantity of effective shift register units 1232 in the first virtual shift register 124 is connected to the remaining effective shift register units 1231 in the last-stage effective shift register. In this way, the width of the region between the end of the last-stage effective shift register 123 (i.e., the end away from the display region 11) and the border of the peripheral region 12 away from the display region 11 can be increased (e.g., from Figures 4d to 4a ), thereby increasing the width of the data traces (such as vss traces) provided in this region.

[0055] In some of these embodiments, the structure of the second quantity of effective shift register units 1232 included in the first virtual shift register 124 can be the same as the structure of the second quantity of effective shift register units 1232 on the side of the effective shift register 123 away from the display region 11 except for the last-stage effective shift register 123. During fabrication, the same pattern as that of the effective shift register 123 can be used, so as to simplify the fabrication process.

[0056] Among them, the remaining effective 1231 shift register units in the last-stage effective shift register 123 are used to connect the gate lines of the display region 11. The specific quantity of the missing second quantity of effective shift register units 1232 in the last-stage effective shift register 123 can be set according to specific requirements. The specific quantity of the missing second quantity of effective shift register units 1232 in the last-stage effective shift register 123 has a lower limit of one and an upper limit of all the effective shift register units included in the effective shift register 123 except for the effective shift register units 1231 connected to the gate lines on the side close to the display region 11. It can be specifically determined according to project requirements.

[0057] In some of these embodiments, for example Figure 5bAs shown, the missing second quantity of valid shift register units is one missing valid shift register unit 1232; the missing second quantity of virtual shift register units is one missing virtual shift register unit 1242. One valid shift register unit 1232 in the first virtual shift register 124 is connected (e.g., in parallel) to the remaining valid shift register units 1231 in the last-stage valid shift register 123. In this way, it is convenient to connect the first virtual shift register 124 to the last-stage valid shift register 123.

[0058] In some other embodiments, for example Figure 5c As shown, the missing second quantity of valid shift register 123 units is multiple missing valid shift register units 1232; the missing second quantity of virtual shift register units is multiple missing virtual shift register units 1242; wherein, the arrangement of the second quantity of valid shift register units 1232 included in the first virtual shift register 124 is the same as the arrangement of the second quantity of valid shift register units 1232 on the side away from the display area 11 in the valid shift registers other than the last-stage valid shift register 123. The multiple valid shift register units 1232 in the first virtual shift register 124 are connected (e.g., in parallel) to the remaining valid shift register units 1231 in the last-stage valid shift register 123. In this way, the width of the area between the end of the last-stage valid shift register 123 (i.e., the end away from the display area 11) and the border of the peripheral area 12 away from the display area 11 can be increased more, thereby increasing the width of the data traces (e.g., vss traces) arranged in this area.

[0059] Furthermore, only the third quantity (e.g., two) of valid shift register units 1231 near the display area side and connected to the gate lines of the display area 11 are included in the last-stage valid shift register 123. In this way, the width of the area between the end of the last-stage valid shift register 123 (i.e., the end away from the display area 11) and the border of the peripheral area 12 away from the display area 11 can be maximally increased, thereby increasing the width of the data traces (e.g., vss traces) arranged in this area.

[0060] Taking the case where the valid shift register 123 includes 4 valid shift register units and the first virtual shift register 124 includes 4 virtual shift register units as an example for illustration. In some embodiments, such as Figure 5aAs shown, before the second quantity of valid shift register units 1232 are missing, the valid shift register 123 may include 4 valid shift register units. Two valid shift register units 1241 near the display area 11 are respectively used to connect to the gate lines of the display area 11, and can be respectively connected to the clock signal line PCB and the clock signal line PCK, and are respectively used to drive one row of pixels in one-to-one correspondence. The two valid shift register units 1232 far from the display area 11 can be respectively connected to the clock signal line CB and the clock signal line CK, and are respectively used to drive two rows of pixels in one-to-one correspondence. That is, the first quantity is four, and the number of pixel rows driven by the remaining valid shift register units 1231 in the last-stage valid shift register 123 is less than the number of pixel rows driven by the missing second quantity of valid shift register units 1232. The number of pixel rows driven by the remaining valid shift register units 1231 in the last-stage valid shift register 123 can be one row, and the number of pixel rows driven by the missing second quantity of valid shift register units 1232 can be two rows.

[0061] Correspondingly, the virtual shift register (such as the first virtual shift register 124 or the second virtual shift register 125) may include 4 virtual shift register units. The specific structure in each virtual shift register unit (such as the first virtual shift register unit 1241 and the second virtual shift register unit 1242) can be respectively the same as the structure in the 4 valid shift registers 123 in one-to-one correspondence, and the specific arrangement can also be the same. The specific quantity of the second quantity of missing virtual shift register units 1242 in the first virtual shift register 124 has a lower limit of one (such as Figure 5b ), and an upper limit of two (such as Figure 5c ), that is, all the virtual shift register units 1242 except the virtual shift register unit 1241 arranged on the side close to the display area 11 are missing.

[0062] In some embodiments, the rounded corner area 122 of the at least one peripheral area 12 may include a plurality of rounded corner areas 122. For example, it may only include the lower rounded corner area 122 (such as at least one of the lower left rounded corner area 122 and the lower right rounded corner area 122). It may also only include the upper rounded corner area 122 (such as at least one of the upper left rounded corner area 122 and the upper right rounded corner area 122). It may also include both the lower rounded corner area 122 (such as at least one of the lower left rounded corner area 122 and the lower right rounded corner area 122) and the upper rounded corner area 122 (such as at least one of the upper left rounded corner area 122 and the upper right rounded corner area 122). Specifically, it can be set according to the actual requirements of the project.

[0063] In some of these embodiments, among the plurality of rounded corner regions 122, the number of the second quantity of valid shift register units 1232 missing from the side of the last-stage valid shift register 123 away from the display region 11 can be the same, which can simplify the process.

[0064] In some of these embodiments, among the plurality of rounded corner regions 122, the number of the second quantity of valid shift register units 1232 missing from the side of the last-stage valid shift register 123 away from the display region 11 can also be different. In this way, personalized setting requirements can be achieved to meet different requirements of different rounded corner regions 122, etc.

[0065] In some of these embodiments, the output end of the valid shift register unit 1232 in the first virtual shift register 124 is connected to the gate line jumper 126 of the display region. Among them, the jumper 126 can be understood as a kind of connecting wire. The connecting wire between it and the output end of the valid shift register unit 1232 in the first virtual shift register 124 and the connecting wire to the input end of the remaining valid shift register units 1231 in the last-stage valid shift register 123 are respectively arranged in different film layers. By adopting the connection method of the jumper 126, static electricity caused by too long connecting wires can be avoided.

[0066] In some of these embodiments, data traces may also be included. Part of the data traces (such as vss traces) are arranged in the region between the end of the last-stage valid shift register 123 away from the display region 11 and the border of the peripheral region 12 away from the display region 11. In this way, the width of the region between the end of the last-stage valid shift register 123 (i.e., the end away from the display region 11) and the border of the peripheral region 12 away from the display region 11 can be increased more, so as to increase the width of the data traces (such as vss traces) arranged in this region and avoid defects such as burns caused by too narrow width of the data traces (such as vss traces).

[0067] Based on the same inventive concept, corresponding to the method of any of the above embodiments, the present application also provides a display device. The display device can be a television, a mobile phone, a computer, a laptop computer, a tablet computer, a personal digital assistant (PDA), an in-vehicle computer, etc. The display device may include a frame, a display panel arranged in the frame, a circuit board, a display driving IC, and other electronic accessories, etc.

[0068] The device of the above embodiments includes the corresponding display panel in any of the foregoing embodiments and has the beneficial effects of the corresponding display panel embodiments, which will not be elaborated here.

[0069] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; within the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present application as described above, and for the sake of brevity, they are not provided in detail.

[0070] In addition, for simplicity of explanation and discussion, and in order not to make the embodiments of the present application difficult to understand, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Further, the devices may be shown in block diagram form in order to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (i.e., these details should be fully within the understanding of those skilled in the art). In cases where specific details (such as circuits) are set forth to describe exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application may be implemented without these specific details or with variations of these specific details. Accordingly, these descriptions should be considered illustrative rather than restrictive.

[0071] Although the present application has been described in connection with specific embodiments of the present application, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (such as dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0072] The embodiments of the present application are intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of the present application shall be included within the protection scope of the present application.

Claims

1. A display panel, characterized in that, Comprising: A display area; And a peripheral area provided on the periphery of the display area; Wherein, the peripheral area includes a plurality of rounded corner areas; in the rounded corner areas, there are arranged in sequence a multi-stage effective shift register and a first virtual shift register provided before the last-stage effective shift register; the first virtual shift register is used to connect adjacent-stage effective shift registers and make the adjacent-stage effective shift registers arranged in parallel and corresponding; each stage of the effective shift register respectively includes a first number of effective shift register units; the first virtual shift register includes a first number of virtual shift register units; Wherein, in the rounded corner area of at least one of the peripheral areas, on the side of the last-stage effective shift register away from the display area, a second number of effective shift register units are missing; on the side of the first virtual shift register away from the display area, a second number of virtual shift register units are missing, and it includes a second number of effective shift register units; the second number is less than the first number; the second number of effective shift register units in the first virtual shift register are connected to the remaining effective shift register units in the last-stage effective shift register.

2. The display panel according to claim 1, characterized in that, The missing second number of effective shift register units is missing one effective shift register unit; the missing second number of virtual shift register units is missing one virtual shift register unit.

3. The display panel according to claim 1, characterized in that, The missing second number of effective shift register units is missing a plurality of effective shift register units; the missing second number of virtual shift register units is missing a plurality of virtual shift register units. Wherein, the arrangement mode of the second number of effective shift register units included in the first virtual shift register is the same as the arrangement mode of the second number of effective shift register units on the side of the effective shift register away from the display area except for the last-stage effective shift register.

4. The display panel according to claim 2 or 3, characterized in that, In the last-stage effective shift register, only the effective shift register units close to the display area and connected to the gate lines of the display area are included.

5. The display panel according to claim 1, characterized in that, The structure of the second number of effective shift register units included in the first virtual shift register is the same as the structure of the second number of effective shift register units on the side of the effective shift register away from the display area except for the last-stage effective shift register.

6. The display panel according to claim 4, characterized in that, The output ends of the effective shift register units in the first virtual shift register are jump-connected to the gate lines of the display area.

7. The display panel according to claim 1, characterized in that, The first number is three, four or five; the multi-stage effective shift registers are respectively used to drive multiple rows of pixels.

8. The display panel according to claim 7, characterized in that, The first number is four, and the number of pixel rows driven by the remaining effective shift register units in the last-stage effective shift register is less than the number of pixel rows driven by the missing second number of effective shift register units.

9. The display panel according to claim 1, characterized in that, In the rounded corner area of the peripheral area, there is also included at least one second virtual shift register, and the second virtual shift register is alternately arranged with a preset number of effective shift registers to make the multi-stage effective shift registers arranged in parallel and corresponding one by one.

10. The display panel according to claim 9, characterized in that, The second virtual shift register and the first virtual shift register are arranged adjacent to each other and are alternately arranged with two - stage effective shift registers.

11. The display panel according to claim 1, characterized in that, The rounded - corner area of the at least one peripheral area includes a plurality of rounded - corner areas.

12. The display panel according to claim 11, characterized in that, Among the plurality of rounded - corner areas, the number of the second - quantity of effective shift - register units missing from the side of the last - stage effective shift register away from the display area is the same.

13. The display panel according to claim 11, characterized in that, Among the plurality of rounded - corner areas, the number of the second - quantity of effective shift - register units missing from the side of the last - stage effective shift register away from the display area is different.

14. The display panel according to claim 1, characterized in that, It further includes data traces, and part of the data traces are arranged in the area between the end of the last - stage effective shift register away from the display area and the border of the peripheral area away from the display area.

15. A display device, comprising the display panel according to any one of claims 1-14.

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