Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a central area, a first area and a second area, the central area is located between the first area and the second area in the first direction, and the central area comprises a cascade circuit; and / or, the display panel comprises a first type of signal lines extending along a second direction, the cascade circuit of the display panel comprises a plurality of shift registers arranged and cascaded along the second direction, the first type of signal lines are electrically connected with the shift registers, and in the first direction, the first type of signal lines are electrically connected with the shift registers. The distance between the shift register and the edge of the display panel is smaller than the distance between the first type signal line and the edge of the display panel, and the first direction intersects with the second direction. According to the display panel and the display device provided by the embodiment of the invention, the cascade circuit can be prevented from being damaged when the display panel is cut, so that the cut display panel is prevented from being damaged.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the development of display technologies, display panels are increasingly widely used, and more and more requirements are imposed on display panels. For example, the demand for special-shaped display panels is increasing day by day.

[0003] In related technologies, for display panels of different sizes and shapes, different photomasks need to be manufactured to meet the requirements, which increases the product development cost and development cycle.

[0004] The inventors have found through research that a rectangular display panel can be cut to obtain display panels of different sizes and shapes. However, this easily leads to the risk of short circuit or open circuit in the structure inside the display panel, resulting in damage to the entire display panel. Summary of the Invention

[0005] Embodiments of the present application provide a display panel and a display device, which can avoid damaging the cascade circuit when cutting the display panel, thereby avoiding damage to the cut display panel.

[0006] In a first aspect, an embodiment of the present application provides a display panel, including: a central region, a first region, and a second region. In a first direction, the central region is located between the first region and the second region, and the central region includes a cascade circuit; and / or, the display panel includes first-type signal lines extending in a second direction. The cascade circuit of the display panel includes a plurality of shift registers arranged and cascaded in the second direction. The first-type signal lines are electrically connected to the shift registers. In the first direction, the distance between the shift register and the edge of the display panel is less than the distance between the first-type signal line and the edge of the display panel. The first direction and the second direction intersect.

[0007] In a second aspect, an embodiment of the present application provides a display device, including the display panel described in the first aspect embodiment.

[0008] According to the display panel and the display device provided in this embodiment, the conventional design concept is broken. The cascade circuit is no longer limited to the edge region of the display panel, but is arranged close to or even at the center of the display panel. In this way, when the display panel is cut to obtain display panels of other sizes or shapes, it is not easy to cut the cascade circuit, thereby protecting the cascade circuit from the risk of short circuit or open circuit, and avoiding abnormalities in the cascade circuit of the cut display panel. Description of the Drawings

[0009] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which like or similar reference numerals denote like or similar features, and the drawings are not drawn to scale.

[0010] Figure 1 Fig. 1 shows a schematic diagram of a cutting of a display panel provided by an embodiment of the present application;

[0011] Figure 2 Fig. 2 shows a schematic structural diagram of a display panel provided by an embodiment of the present application;

[0012] Figure 3 Fig. 3 shows another schematic structural diagram of a display panel provided by an embodiment of the present application;

[0013] Figure 4 Fig. 4 shows yet another schematic structural diagram of a display panel provided by an embodiment of the present application;

[0014] Figure 5 Fig. 5 shows a schematic structural diagram of a partial area of a display panel provided by an embodiment of the present application;

[0015] Figure 6 Fig. 6 shows yet another schematic structural diagram of a display panel provided by an embodiment of the present application;

[0016] Figure 7 Fig. 7 shows yet another schematic structural diagram of a display panel provided by an embodiment of the present application;

[0017] Figure 8 Fig. 8 shows a schematic connection diagram of a pixel circuit and a light-emitting element in a display panel provided by an embodiment of the present application;

[0018] Figure 9 Fig. 9 shows yet another schematic structural diagram of a display panel provided by an embodiment of the present application;

[0019] Figure 10 Fig. 10 shows yet another schematic structural diagram of a display panel provided by an embodiment of the present application;

[0020] Figure 11 Fig. 11 shows yet another schematic structural diagram of a display panel provided by an embodiment of the present application;

[0021] Figure 12 Fig. 12 shows yet another schematic structural diagram of a display panel provided by an embodiment of the present application;

[0022] Figure 13 Fig. 13 shows a schematic wiring structure diagram of a display panel provided by an embodiment of the present application;

[0023] Figure 14 Fig. 14 shows another schematic wiring structure diagram of a display panel provided by an embodiment of the present application;

[0024] Figure 15 Shows another wiring structure schematic diagram of the display panel provided by the embodiment of the present application;

[0025] Figure 16 Shows another wiring structure schematic diagram of the display panel provided by the embodiment of the present application;

[0026] Figure 17 Shows another wiring structure schematic diagram of the display panel provided by the embodiment of the present application;

[0027] Figure 18 Shows another wiring structure schematic diagram of the display panel provided by the embodiment of the present application;

[0028] Figure 19 Shows another wiring structure schematic diagram of the display panel provided by the embodiment of the present application;

[0029] Figure 20 Shows another wiring structure schematic diagram of the display panel provided by the embodiment of the present application;

[0030] Figure 21 Shows various shape schematic diagrams of the display panel provided by the embodiment of the present application;

[0031] Figure 22 Shows another structure schematic diagram of the display panel provided by the embodiment of the present application;

[0032] Figure 23 Shows a structure schematic diagram of the display device provided by the embodiment of the present application. Detailed implementation manners

[0033] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only for providing a better understanding of the present application by showing examples of the present application.

[0034] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0035] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "on top of" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or this region will be "below" or "beneath" the other layer or another region.

[0036] It should be understood that the term "and / or" used in this text is only a relational term describing associated objects, indicating that three relationships may exist. For example, A and / or B may mean: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " in this text generally indicates that the associated objects before and after are in an "or" relationship.

[0037] The term "connected" may refer to "electrically connected" or "electrically connected without passing through an intermediate transistor". The term "insulated" may refer to "electrically insulated" or "electrically isolated". The term "driven" may refer to "controlled" or "operated". The term "portion" may refer to "local". The term "end" may refer to "end segment" or "end edge". The display panel may be a display device or a module / portion of a display device.

[0038] Without departing from the spirit or scope of the present application, various modifications and variations can be made to the present application, which will be obvious to those skilled in the art. Therefore, the present application is intended to cover modifications and variations of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0039] As Figure 1As shown, for display panels of different sizes and shapes, the conventional display panel 100' can be cut to obtain display panels 101', 102', 103', 104', 105' of different sizes and shapes. However, limited by the structure of the conventional display panel 100', the structure inside the display panel is extremely likely to be short-circuited or open-circuited during cutting, resulting in damage to the entire display panel.

[0040] In view of this, the embodiments of the present application provide a display panel and a display device. The embodiments of the display panel and the display device will be described below with reference to the accompanying drawings.

[0041] As Figure 2 shown, the display panel 100 provided by the embodiments of the present application includes a central region Q0, a first region Q1, and a second region Q2. In the first direction X, the central region Q0 is located between the first region Q1 and the second region Q2. The central region Q0 includes a cascaded circuit 1. The first region Q1 and the second region Q2 are edge regions of the display panel.

[0042] Exemplarily, the central region Q0, the first region Q1, and the second region Q2 are all display regions. The central region Q0, the first region Q1, and the second region Q2 all include pixel circuits and light-emitting elements ( Figure 2 not shown in the figure), and the central region Q0, the first region Q1, and the second region Q2 can all display images.

[0043] Exemplarily, in the embodiments of the present application, the display panel can be a narrow-bezel or even borderless display panel, that is, in the first direction X, the non-display regions on the sides of the first region Q1 and the second region Q2 away from the central region Q0 are very small, and there may even be no non-display regions.

[0044] Exemplarily, Figure 2 the figure also shows a plurality of sub-pixel regions Q3. Among them, a small rectangular frame represents a sub-pixel region Q3, and a pixel circuit is arranged in one sub-pixel region Q3. The plurality of sub-pixel regions Q3 are arranged in an array in the intersecting first direction X and second direction Y. For example, the first direction X can be the row direction, and the second direction Y can be the column direction.

[0045] The cascaded circuit 1 is electrically connected to the pixel circuit. The pixel circuit generates a driving current under the control of the cascaded circuit 1 to drive the light-emitting element to emit light. It should be noted that in the drawings of the present application, in order to clearly show the approximate position of the cascaded circuit 1, the connection relationship between the pixel circuit and the cascaded circuit 1 is not shown.

[0046] The cascaded circuit 1 is located in the central region Q0.

[0047] Exemplarily, the display panel includes a first center line L1 that extends along the second direction Y. The display panel includes a first edge s1 and a second edge s2 that are opposite to each other in the first direction X, and the first edge s1 and the second edge s2 extend along the second direction Y. In the first direction X, the width of the display panel is D, the distance between the first center line L1 and the first edge s1 is D / 2, and the distance between the first center line L1 and the second edge s2 is D / 2. The cascade circuit 1 is disposed adjacent to the first center line L1. For example, the central axis of at least one cascade circuit 1 coincides with the first center line L1.

[0048] It should be noted that the first center line is located in the display area, and the first center line and the first edge are parallel or substantially parallel. The first center line does not represent an actual trace of the display panel and can be understood as a virtual defined position center line of the display panel, that is, the first center line is used to represent the position. In addition, the two or more parameters "equal", "equals", "=" defined in this article are not absolutely equal and allow a certain error. It should be noted that the equal distances mentioned in this disclosure refer to the distance values being equal within the allowable range of the error (±5%).

[0049] For example, in order to obtain a display panel with other sizes or shapes, it is necessary to cut the display panel along the Figure 2 cutting lines L11 and L12 shown in the figure. Since the cascade circuit 1 is located in the central area Q0, it is not easy to cut the cascade circuit 1, thereby protecting the cascade circuit 1 from the risk of short circuit or open circuit, and avoiding abnormalities in the cascade circuit 1 of the cut display panel.

[0050] In other words, as Figure 3 shown in the figure, the display panel includes a first type of signal line 3 that extends along the second direction Y. The cascade circuit 1 includes a plurality of cascaded shift registers VSR arranged along the second direction Y, and the first type of signal line 3 is electrically connected to the shift register VSR. The first type of signal line 3 provides signals to the shift register VSR to drive the shift register VSR to operate. For example, the first type of signal line 3 includes a high-level signal line, a low-level signal line, a clock signal line, etc. The high-level signal line is used to provide a high-level signal line, the low-level signal line is used to provide a low-level signal line, and the clock signal line is used to provide a clock signal.

[0051] In the first direction X, the distance between the shift register VSR and the edge of the display panel is less than the distance between the first type of signal line 3 and the edge of the display panel.

[0052] Exemplarily, in the first direction X, at least one first type of signal line 3 is provided on each side of the shift register VSR. For the convenience of distinction, the first type of signal line on the side of the shift register VSR facing the first edge s1 is called the first first type of signal line 3_1, and the first type of signal line on the side of the shift register VSR facing the second edge s2 is called the second first type of signal line 3_2. In the first direction X, the distance between the shift register VSR and the first edge s1 is less than the distance between the first first type of signal line 3_1 and the first edge s1, and the distance between the shift register VSR and the second edge s2 is less than the distance between the second first type of signal line 3_2 and the second edge s2.

[0053] It can be understood that in this embodiment, in the first direction X, the shift register VSR is arranged close to the center of the display panel, so as to avoid placing the shift register in the edge area of the display panel.

[0054] For example, in order to obtain display panels of other sizes or shapes, it is necessary to cut the display panel along Figure 3 the cutting lines L11 and L12. Since the cascading circuit 1 is close to or even located at the center of the display panel, it is not easy to cut the cascading circuit 1, thereby protecting the cascading circuit 1 from the risks of short circuit or open circuit, and avoiding abnormalities in the cascading circuit 1 of the cut display panel.

[0055] According to the display panel provided in this embodiment, it breaks the conventional design concept, no longer confines the cascading circuit 1 to the edge area of the display panel, but arranges the cascading circuit 1 close to or even at the center of the display panel. In this way, when the display panel is cut to obtain display panels of other sizes or shapes, it is not easy to cut the cascading circuit 1, thereby protecting the cascading circuit 1 from the risks of short circuit or open circuit, and avoiding abnormalities in the cascading circuit 1 of the cut display panel.

[0056] In some embodiments, as Figure 4 shown, the display panel includes a display area AA and a bonding area BA. In the second direction Y, the bonding area BA is located on one side of the display area AA. The display area AA includes a cascading circuit 1 and pixel circuits. The bonding area BA includes bonding terminals (not shown in the figure), and the bonding terminals are used to electrically connect the cascading circuit 1, the pixel circuits, and the driving chip. The driving signals provided by the driving chip are transmitted to the cascading circuit 1 and the pixel circuits through the bonding terminals.

[0057] The cascaded circuit 1 includes n cascaded shift registers VSR arranged along the second direction Y, where n is an integer greater than 1. The first shift register to the nth shift register are sequentially labeled as VSR_1 to VSR_n. In the second direction Y, the nth shift register VSR_n among the n shift registers is closest to the bonding area BA of the display panel. The nth shift register VSR_n is connected to a bonding terminal in the bonding area BA through a trigger signal line STV. The bonding terminal connected by the trigger signal line STV is used to transmit a trigger signal, and the trigger signal is used to start the shift register to work.

[0058] Each shift register includes a trigger signal terminal in and an output signal terminal out. The output signal terminal out of the shift register VSR is electrically connected to the pixel circuit. The output signal terminal out of the jth shift register VSR is electrically connected to the trigger signal terminal in of the (j - 1)th shift register VSR, where 2 ≤ j ≤ n and j is an integer. That is to say, the signal output by the jth shift register VSR serves as the trigger signal for the (j - 1)th shift register VSR, thereby realizing the step-by-step transmission of the trigger signal from the nth shift register VSR_n to the first shift register VSR_1. If the cascading direction from the first shift register VSR_1 to the nth shift register VSR_n is the forward direction, then the cascading direction from the nth shift register VSR_n to the first shift register VSR_1 is the reverse direction.

[0059] Since the bonding area BA needs to be electrically connected to the driving chip, in order to obtain display panels of other sizes or shapes, the bonding area BA will be retained during cutting, and the part far from the bonding area BA in the second direction Y will be cut off. That is to say, the upper shift registers (the first shift register VSR_1 to the ith shift register) may be cut off. In this embodiment, the n shift registers of the cascaded circuit are cascaded with each other, and the nth shift register VSR_n closest to the bonding area BA is connected to a bonding terminal in the bonding area BA through a trigger signal line STV. The trigger signal is input from the lowermost nth shift register VSR_n, realizing the reverse scan design of the cascaded circuit, ensuring that the remaining shift registers can still work normally when the upper shift registers are cut off, so as to ensure the normal function of the cut display panel.

[0060] In some embodiments, as Figure 5 shown, the display panel further includes a first cutting mark 41. In the first direction X, the first cutting mark 41 is located on the side of the shift register VSR close to the edge of the display panel.

[0061] The display panel includes a first edge s1 and a second edge s2 that are opposite to each other in the first direction X. On both sides of the shift register VSR in the first direction X, first cutting marks 41 are provided. For easy distinction, the first cutting mark on the side of the shift register VSR close to the first edge s1 is marked as 41_1, and the first cutting mark on the side of the shift register VSR close to the second edge s2 is marked as 41_2. The side of the shift register VSR close to the first edge s1 includes a plurality of first cutting marks arranged in the second direction Y and marked as 41_1, and the side of the shift register VSR close to the second edge s2 includes a plurality of first cutting marks arranged in the second direction Y and marked as 41_2.

[0062] It can be understood that during cutting, the first cutting mark 41 can be recognized.

[0063] In this embodiment, by providing the first cutting mark 41, damage to the shift register VSR can be avoided during subsequent cutting.

[0064] Exemplarily, the first cutting mark 41 can be made of a material with low ductility (i.e., high hardness). In this way, when the first cutting mark 41 is cut, the possibility of short circuit can be reduced.

[0065] The material of the first cutting mark 41 includes but is not limited to semiconductor materials, and semiconductor materials include but are not limited to polysilicon poly.

[0066] Exemplarily, the shape of the first cutting mark 41 can be designed to be easily recognizable. For example, the orthographic projection shape of the first cutting mark 41 on the plane of the display panel includes but is not limited to a "cross" shape, etc.

[0067] Exemplarily, to improve the recognition accuracy of the first cutting mark 41, a clearance area is included around the first cutting mark 41. Here, the "clearance area" can be understood as: no circuit structure and / or no other structures that affect cutting recognition are provided around the first cutting mark 41.

[0068] In some embodiments, as Figure 5 shown, the display panel further includes a first cutting mark 41. In the second direction Y, the first cutting mark 41 is located between adjacent shift registers VSR.

[0069] It should be noted that in the second direction Y, the first cutting mark 41 does not overlap with the shift register VSR.

[0070] For the same side of the shift register VSR in the first direction X, a plurality of shift registers VSR and a plurality of first cutting marks 41 can be arranged in one-to-one correspondence. For example, a plurality of shift registers VSR and a plurality of first cutting marks 41_1 are arranged in one-to-one correspondence, and a plurality of shift registers VSR and a plurality of first cutting marks 41_2 are arranged in one-to-one correspondence. In the second direction Y, one first cutting mark 41_1 and one first cutting mark 41_2 are arranged on each side of every two adjacent shift registers VSR.

[0071] In this embodiment, first cutting marks 41 are arranged on both sides of adjacent shift registers VSR, which can better avoid damaging the shift registers VSR during subsequent cutting.

[0072] In some embodiments, as Figure 5 shown, in the second direction Y, the distance between the first cutting mark 41 and two adjacent shift registers VSR is equal.

[0073] Exemplarily, a plurality of shift registers VSR are arranged uniformly in the second direction Y, a plurality of first cutting marks 41_1 are arranged uniformly on the first side (the left side in the first side) of the plurality of shift registers VSR, and a plurality of first cutting marks 41_2 are arranged uniformly on the second side (the right side in the first side) of the plurality of shift registers VSR. Figure 5 In the left side), a plurality of first cutting marks 41_2 are arranged uniformly on the second side (the right side in the first side) of the plurality of shift registers VSR. Figure 5 In the right side).

[0074] Exemplarily, the center line of two adjacent shift registers VSR is L2, and the corresponding first cutting mark 41_1 and first cutting mark 41_2 of the two adjacent shift registers VSR are arranged along the center line L2.

[0075] In this embodiment, the distance between the first cutting mark 41 and two adjacent shift registers VSR is equal. After recognizing the first cutting mark 41, the position of the shift register can be determined better, so as to better avoid damaging the shift register VSR during subsequent cutting.

[0076] In some embodiments, as Figure 6 shown, the display panel includes a plurality of pixel circuit rows 2a arranged along the second direction Y, and the pixel circuit rows 2a include a plurality of pixel circuits 2 arranged along the first direction X. Exemplarily, the pixel circuit 2 is located in the sub-pixel region Q3.

[0077] The cascade circuit includes a plurality of cascaded shift registers VSR, and the shift register VSR is used to output a scan signal scan. A plurality of pixel circuit rows 2a are connected to the same light emission control signal terminal EM.

[0078] The display panel includes scan signal lines SL and emission control signal lines EL. The output terminal of the shift register VSR is electrically connected to the scan signal lines SL, and the scan signal lines SL are electrically connected to the pixel circuits 2. The emission control signal lines EL are electrically connected to the pixel circuits 2, and multiple emission control signal lines EL are electrically connected to the same emission control signal terminal EM.

[0079] Exemplarily, the emission control signal terminal EM is located in the bonding area BA. Both ends of the bonding area BA each include at least one emission control signal terminal EM. The left end of the emission control signal line EL is electrically connected to the left emission control signal terminal EM, and the right end of the emission control signal line EL is electrically connected to the right emission control signal terminal EM.

[0080] Figure 6 Taking the emission control signal line EL extending along the first direction X as an example, this is not used to limit the present application. For example, in other examples, the emission control signal line EL may also extend along the second direction Y, and multiple pixel circuits 2 in the same column may be electrically connected to the same emission control signal line EL.

[0081] The scan signal scan output by the shift register VSR is used to control the writing of the data signal data of the pixel circuits 2. The emission control signal provided by the emission control signal terminal EM is used to control whether the light-emitting elements electrically connected to the pixel circuits 2 emit light.

[0082] Multiple cascaded shift registers VSR can output scan signals step by step to achieve progressive scanning of multiple rows of pixel circuits 2a, so that multiple rows of pixel circuits 2a can write the data signal data row by row. Multiple rows of pixel circuits 2a are electrically connected to the same emission control signal terminal EM, and the emission control signal output by the emission control signal terminal EM can control multiple light-emitting elements electrically connected to multiple rows of pixel circuits 2a to emit light simultaneously. The emission control signal provided by the emission control signal terminal EM can be called a global control signal, that is, it can control all the light-emitting elements of the display panel to emit light simultaneously.

[0083] The more the number of cascaded circuits, the greater the risk of the cascaded circuits being cut. In this embodiment, multiple rows of pixel circuits 2a are connected to the same emission control signal terminal EM. In this way, only cascaded circuits for outputting scan signals need to be set in the display area, and cascaded circuits for outputting emission control signals do not need to be set, which can reduce the number of cascaded circuits, thereby better ensuring that the functions of the cut display panel are not damaged.

[0084] In some embodiments, still taking Figure 6 as an example, the display panel includes multiple rows of pixel circuits 2a arranged along the second direction Y, and the pixel circuits 2a include multiple pixel circuits 2 arranged along the first direction X. In the second direction Y, the shift register VSR is located between adjacent rows of pixel circuits 2a.

[0085] The positive projection of the shift register VSR on the plane where the display panel is located does not overlap with the positive projection of the pixel circuit 2 on the plane where the display panel is located.

[0086] Exemplarily, different pixel circuits 2 have the same size. For example, the sizes of the pixel circuits in the entire display area are all reduced. After the sizes of the pixel circuits are reduced, there is a certain space between adjacent pixel circuit rows 2a, and the shift register VSR is arranged in the gap between adjacent pixel circuit rows 2a.

[0087] If only the sizes of the pixel circuits in some areas are reduced, it will cause different driving capabilities of the pixel circuits in different areas, resulting in poor display uniformity. In the embodiments of the present application, the sizes of the pixel circuits in the entire display area are reduced as a whole, and the sizes of the reduced pixel circuits are still the same. Therefore, the driving capabilities of the pixel circuits in each area are still consistent, and the display uniformity will not be affected. Moreover, after the sizes of the pixel circuits are reduced, there is space between adjacent pixel circuit rows 2a for arranging the shift register VSR.

[0088] In some embodiments, please continue to refer to Figure 6 , the display panel includes m pixel circuit rows 2a arranged along the second direction Y, where m is an integer greater than 1, and are respectively marked as the first pixel circuit row 2a_1 to the mth pixel circuit row 2a_m, and the mth pixel circuit row 2a_m is closest to the bonding area BA of the display panel. In the second direction Y, the shift register VSR is located on the side of the first pixel circuit row 2a_1 facing the bonding area BA.

[0089] Exemplarily, one shift register VSR of the same cascading circuit is arranged between every two adjacent pixel circuit rows 2. The nth shift register VSR_n is the shift register closest to the bonding area BA, and the nth shift register VSR_n is located on the side of the mth pixel circuit row 2a_m close to the bonding area BA. Exemplarily, no shift register is arranged on the side of the first pixel circuit row 2a_1 away from the bonding area BA.

[0090] For example, in the second direction Y, the bonding area BA is located at the lower part of the display panel. In this embodiment, space is reserved below the pixel circuit row 2a for placing the shift register VSR. In this way, even if the area above the first pixel circuit row 2a_1 is cut off, or even the first pixel circuit row 2a_1 is cut off, the shift register VSR will not be damaged, thereby ensuring that the cascading circuit in the cut display panel can still work normally.

[0091] In some embodiments, such as Figure 7As shown, the display panel includes a common signal line PVEE. In the first direction X, the first type of signal lines 3 are located between the common signal line PVEE and the cascade circuit 1.

[0092] Both the common signal line PVEE and the first type of signal lines 3 extend along the second direction Y. A plurality of shift registers of the cascade circuit 1 are arranged along the second direction Y.

[0093] Exemplarily, in the first direction X, at least one first type of signal line 3 is provided on each side of the cascade circuit 1, and at least one common signal line PVEE is provided on each side of the cascade circuit 1. Relative to the cascade circuit 1 and the first type of signal lines 3, the common signal line PVEE is closer to the edge of the display panel.

[0094] The common signal line PVEE is used to provide a common voltage. In the first direction X, the outermost signal lines have a relatively high risk of being cut and damaged. Compared with other signal lines, if the common signal line PVEE is cut and damaged, the impact on the performance of the display panel is relatively small.

[0095] In this embodiment, in the first direction X, the cascade circuit 1 and the first type of signal lines 3 are arranged inside the common signal line PVEE. The common signal line PVEE limits the minimum non-cuttable area in the second direction Y to ensure that the structure inside the common signal line PVEE will not be cut during cutting, thereby ensuring that the cascade circuit 1 and the first type of signal lines 3 are not damaged.

[0096] Exemplarily, as Figure 8 shown, the first pole of the light-emitting element 5 is electrically connected to the pixel circuit 2, the second pole of the light-emitting element 5 is electrically connected to the common signal line PVEE, and the pixel circuit 2 is also electrically connected to the power supply signal line PVDD. For example, the voltage on the power supply signal line PVDD is greater than the voltage on the common signal line PVEE.

[0097] Exemplarily, the signal transmitted by the common signal line PVEE is a global signal. The common signal line PVEE is electrically connected to the second poles of each light-emitting element 5 in the display area. For example, the display panel is an organic light-emitting diode (OLED) display panel, and the second poles of each light-emitting element 5 are an integral body, that is, the second pole of the light-emitting element 5 is a surface electrode, and the common signal line PVEE is electrically connected to the surface electrode. Another example is that the display panel is a micro light-emitting diode (micro LED) or a mini light-emitting diode (miniLED) display panel. The display panel may further include a grid-shaped common connection line covering the display area. The common connection line is electrically connected to the second poles of each light-emitting element 5, and the common signal line PVEE is electrically connected to the common connection line. Of course, the above are only some examples, and the electrical connection between the common signal line PVEE and the second pole of the light-emitting element 5 can also be realized in other ways.

[0098] It should be noted that the present application does not limit the specific circuit structure of the pixel circuit 2.

[0099] In some embodiments, as Figure 7 shown, Figure 7 As shown in the figure, a plurality of sub-pixel regions Q3 arranged in an array are shown. One pixel circuit 2 is provided in one sub-pixel region Q3. The plurality of pixel circuits 2 in the plurality of sub-pixel regions Q3 arranged in a column in the second direction Y form a pixel circuit column 2b. The display panel includes a plurality of pixel circuit columns 2b arranged along the first direction X. In the first direction X, at least one pixel circuit column 2b is provided between the common signal line PVEE and the edge of the display panel.

[0100] For example, Figure 7 In the figure, a common signal line PVEE is provided in each of the left half screen and the right half screen. There is at least one pixel circuit column 2b between the common signal line PVEE in the left half screen and the first edge s1, and there is at least one pixel circuit column 2b between the common signal line PVEE in the right half screen and the second edge s2.

[0101] In this embodiment, although the common signal line PVEE is provided outside the cascade circuit 1 and the first type of signal lines 3 (i.e., on the side close to the edge), the common signal line PVEE is not located on the outermost side. In this way, even if the left and right edge regions of the display panel in the first direction X are cut off, it can be ensured that the common signal line PVEE still exists in the cut display panel.

[0102] In some embodiments, as Figure 7 shown, the first type of signal lines 31 includes a high-level signal line VGH and a low-level signal line VGL. The high-level signal line VGH is located on the first side of the cascade circuit 1 in the first direction X, and the low-level signal line VGL is located on the second side of the cascade circuit 1 in the first direction X.

[0103] The high-level signal line VGH is used to provide a high-level signal, and the low-level signal line VGL is used to provide a low-level signal. The high-level signal is, for example, a positive voltage, and the low-level signal is, for example, a negative voltage. The high-level signal and the low-level signal are used to drive the cascade circuit 1 to work.

[0104] The cascade circuit 1 includes a plurality of cascaded shift registers, and each shift register is electrically connected to both the high-level signal line VGH and the low-level signal line VGL.

[0105] For example, the cascading circuit 1 is located at the center of the display panel in the first direction X. In this embodiment, the high-level signal line VGH and the low-level signal line VGL are distributed on both sides of the cascading circuit 1, which can make both the high-level signal line VGH and the low-level signal line VGL close to the center of the display panel, so as to ensure that the high-level signal line VGH and the low-level signal line VGL are not damaged during cutting as much as possible. In addition, the voltage difference between the high-level signal line VGH and the low-level signal line VGL is usually relatively large. Distributing the high-level signal line VGH and the low-level signal line VGL on both sides of the cascading circuit 1 can make the high-level signal line VGH and the low-level signal line VGL not affect each other.

[0106] In some embodiments, as Figure 7 shown, the display panel includes a power supply signal line PVDD, and power supply signal lines PVDD are provided on both sides of the cascading circuit 1 in the first direction X.

[0107] Or, as Figure 7 shown, the display panel further includes a reset signal line Vref, and reset signal lines Vref are provided on both sides of the cascading circuit 1 in the first direction X.

[0108] Or, as Figure 9 shown, the display panel further includes a power supply signal line PVDD and a reset signal line Vref. Power supply signal lines PVDD are provided on both sides of the cascading circuit 1 in the first direction X, and reset signal lines Vref are provided on both sides of the cascading circuit 1 in the first direction X.

[0109] The power supply signal line PVDD is electrically connected to the pixel circuit 2. The reset signal line Vref is electrically connected to the pixel circuit 2, and the reset signal on the reset signal line Vref is used to reset the driving transistor of the pixel circuit 2 and / or to reset the first pole of the light-emitting element.

[0110] Exemplarily, the power supply signal lines PVDD provided on both sides in the first direction X can be symmetrically arranged about the center of the display panel.

[0111] The reset signal lines Vref provided on both sides in the first direction X can be symmetrically arranged about the center of the display panel.

[0112] For example, on the same side of the cascaded circuit 1 in the first direction X, the power supply signal line PVDD is located between the common signal line PVEE and the first type of signal lines 3, and / or the reset signal line Vref is located between the common signal line PVEE and the first type of signal lines 3. Also for example, on the same side of the cascaded circuit 1 in the first direction X, the reset signal line Vref is located between the power supply signal line PVDD and the first type of signal lines 3. In these examples, in the first direction X, the first type of signal lines 3, the power supply signal line PVDD, and / or the reset signal line Vref are arranged inside the common signal line PVEE, and the common signal line PVEE limits the minimum non-cuttable area in the second direction Y to ensure that the structure inside the common signal line PVEE will not be cut during cutting, thereby ensuring that the first type of signal lines 3, the power supply signal line PVDD, and / or the reset signal line Vref will not be damaged.

[0113] Exemplarily, as Figure 10 shown, the display panel further includes a first connection line 51. The first connection line 51 extends along the first direction X. The first connection line 51 is electrically connected to the common signal line PVEE and is also electrically connected to the second pole of the light-emitting element. When the first connection line 51 and the common signal line PVEE are located in different metal layers, they are connected through vias.

[0114] Exemplarily, Figure 10 the first connection line 51 in the lower middle is the connection line close to the bonding area, and the first connection line 51 is electrically connected to the common signal terminal in the bonding area.

[0115] The number of the first connection lines 51 can be multiple.

[0116] Exemplarily, as Figure 10 shown, the display panel further includes a second connection line 52. The second connection line 52 extends along the first direction X. The second connection line 52 is electrically connected to the power supply signal line PVDD. When the second connection line 52 and the power supply signal line PVDD are located in different metal layers, they are connected through vias.

[0117] Exemplarily, Figure 10 the second connection line 52 in the lower middle is the connection line close to the bonding area, and the second connection line 52 is electrically connected to the power supply signal terminal in the bonding area.

[0118] The number of the second connection lines 52 can be multiple.

[0119] In some embodiments, as Figure 11 shown, the first type of signal lines 3 includes a clock signal line CK and other signal lines 3_n. In the first direction X, the clock signal line CK is located between the other signal lines 3_n and the cascaded circuit 1.

[0120] For example, one side of the cascade circuit 1 close to the first edge s1 includes at least one clock signal line CK and at least one other signal line 3_n, and one side of the cascade circuit 1 close to the second edge s2 includes at least one clock signal line CK and at least one other signal line 3_n.

[0121] For example, the clock signal line CK includes a first clock signal line CK1 and a second clock signal line CK2, and the other signal line 3_n includes a high-level signal line VGH and a low-level signal line VGL. The first clock signal line CK1 and the second clock signal line CK2 are distributed on both sides of the cascade circuit 1, and the high-level signal line VGH and the low-level signal line VGL are distributed on both sides of the cascade circuit 1. In the first direction X, the first clock signal line CK1 is located between the high-level signal line VGH and the cascade circuit 1, and the second clock signal line CK2 is located between the low-level signal line VGL and the cascade circuit 1.

[0122] The clock signal line CK and the other signal line 3_n in the first type of signal line 3 are electrically connected to the cascade circuit 1 evenly. The clock signal transmitted by the clock signal line CK has a greater impact on the cascade circuit 1 than the signal transmitted by the other signal line 3_n. In this embodiment, setting the clock signal line CK inside the other signal line 3_n can avoid the clock signal line CK being cut during cutting, so as to better ensure the performance of the cascade circuit 1 in the display panel after cutting.

[0123] In some embodiments, as Figure 12 shown, the display panel includes m pixel circuit rows 2a arranged along the second direction Y, where m is an integer greater than 1, and are respectively marked as the first pixel circuit row 2a_1 to the mth pixel circuit row 2a_m, and the mth pixel circuit row 2a_m is closest to the bonding area BA of the display panel.

[0124] Exemplarily, the pixel circuit 2 is located in the sub-pixel area Q3.

[0125] The display panel further includes an electrostatic discharge circuit ESD, and the electrostatic discharge circuit ESD is located between the mth pixel circuit row 2a_m and the bonding area BA.

[0126] The electrostatic discharge circuit ESD is used to release the static electricity on the target structure. For example, the electrostatic discharge circuit ESD is electrically connected to the data line DL to release the static electricity on the data line DL. The data line DL is electrically connected to the pixel circuit 2, and the data line DL is used to transmit the data signal data to the pixel circuit 2.

[0127] For example, in the second direction Y, the binding area BA is located at the lower part of the display panel. In this embodiment, a space is reserved below the m-th pixel circuit row 2a_m for placing the electrostatic discharge circuit ESD. In this way, even if the upper area is cut off, the electrostatic discharge circuit ESD will not be damaged, thus ensuring that the electrostatic discharge circuit ESD in the cut display panel can still work properly.

[0128] In some embodiments, as Figure 12 shown, the display panel further includes a second cutting mark 42. In the second direction Y, the second cutting mark 42 is located on the side of the electrostatic discharge circuit ESD facing the binding area BA of the display panel.

[0129] It can be understood that the second cutting mark 42 can be recognized during cutting.

[0130] In this embodiment, by setting the second cutting mark 42, it is possible to avoid damaging the electrostatic discharge circuit ESD during subsequent cutting.

[0131] Exemplarily, the second cutting mark 42 can be made of a material with low ductility (i.e., high hardness). In this way, when the second cutting mark 42 is cut, the possibility of short circuit can be reduced.

[0132] The material of the second cutting mark 42 includes but is not limited to semiconductor materials, and semiconductor materials include but are not limited to polysilicon poly.

[0133] Exemplarily, the shape of the second cutting mark 42 can be designed to be easily recognizable. For example, the orthographic projection shape of the second cutting mark 42 on the plane of the display panel includes but is not limited to a "cross" shape, etc.

[0134] Exemplarily, to improve the recognition accuracy of the second cutting mark 42, a clearance area is included around the second cutting mark 42.

[0135] In some embodiments, as Figure 13 shown, the display panel includes a plurality of signal traces 60, Figure 13 and the distance between at least some adjacent signal traces 60 that are located in the same film layer and have parallel extension directions is greater than a first threshold.

[0136] The signal traces 60 include signal lines electrically connected to the pixel circuit 2. For example, the signal traces 60 include scan signal lines, light emission control signal lines, data lines, power signal lines, common signal lines, etc.

[0137] Exemplarily, the signals transmitted by adjacent signal traces 60 can be different.

[0138] Figure 13 The traces with the same filling pattern indicate the signal traces located in the same film layer.Figure 13 Taking the example that three signal traces 60 are located in the same film layer, the spacing between adjacent signal traces 60 is greater than the first threshold.

[0139] Exemplarily, for adjacent signal traces 60 located in the same film layer, the spacing in the first direction X is d1, and the spacing in the second direction Y is d2. Both d1 and d2 are greater than the first threshold.

[0140] Exemplarily, the first threshold is a preset spacing threshold at which a short - circuit risk is likely to occur. Exemplarily, the first threshold is 10 um (micrometers). For example, both d1 and d2 are greater than 10 micrometers and both d1 and d2 are less than 20 um.

[0141] Since the signal traces have a certain ductility, if the spacing between adjacent signal traces in the same film layer is too small, short - circuits are likely to occur between the signal traces that are too close during cutting. In this embodiment, the spacing between adjacent signal traces in the same film layer is designed to be greater than the first threshold to increase the spacing between adjacent signal traces in the same film layer and reduce the possibility of short - circuits occurring in the signal traces during cutting.

[0142] Exemplarily, the signal trace 60 can be electrically connected to the pixel circuit and the cascading circuit, and the signals transmitted by adjacent signal traces 60 can be different.

[0143] As an example, the cascading circuit includes a first cascading circuit for outputting a scan signal scan and a second cascading circuit for outputting a light - emitting control signal Emit. Among two adjacent signal traces 60, one signal trace 60 is electrically connected to the first cascading circuit and the pixel circuit, and the other signal trace 60 is electrically connected to the second cascading circuit and the pixel circuit.

[0144] As an example, the cascading circuit includes a plurality of cascaded shift registers, and two adjacent signal traces 60 can be electrically connected to different shift registers.

[0145] Of course, in other examples, the signal trace 60 can include traces electrically connected to the cascading circuit and the driving chip.

[0146] If there is not enough space to increase the spacing between signal traces in the same film layer, at least part of the line segments of the signal traces with a smaller spacing can also be subjected to line - changing processing.

[0147] Figures 14 to 16As shown in the figure, the display panel includes a first trace 61 and a second trace 62 that are adjacent and have parallel extending directions. The first trace 61 includes a first segment 611 and a second segment 612 that are connected to each other. The second trace 62 includes a third segment 623 and a fourth segment 624 that are connected to each other. The first segment 611 and the third segment 623 are adjacent, and the second segment 612 and the fourth segment 624 are adjacent. In the direction parallel to the light-emitting surface of the display panel, the distance between the first segment 611 and the third segment 623 is greater than the distance between the second segment 612 and the fourth segment 624. The first segment 611 and the third segment 623 are located in the same film layer, and at least the fourth segment 624 and the third segment 623 are located in different film layers.

[0148] In this embodiment, it is equivalent to performing a wire replacement process on the fourth segment 624 by the third segment 623, which is equivalent to increasing the distance between the second segment 612 and the fourth segment 624 to reduce the possibility of short circuit between the second segment 612 and the fourth segment 624 during cutting.

[0149] It should be noted that Figures 14 to 16 in the figure, traces with the same filling pattern represent traces located in the same film layer, and traces with different filling patterns represent traces located in different film layers. Segments of the same trace located in different film layers can be connected through vias.

[0150] The first trace 61 is electrically connected to the pixel circuit and the cascading circuit, and the second trace 62 is electrically connected to the pixel circuit and the cascading circuit. The first trace 61 and the second trace 62 can be used to transmit different signals.

[0151] As an example, the cascading circuit includes a first cascading circuit for outputting a scan signal scan and a second cascading circuit for outputting a light-emitting control signal Emit. The first trace 61 can be electrically connected to the first cascading circuit and the pixel circuit, and the second trace 62 can be electrically connected to the second cascading circuit and the pixel circuit.

[0152] As an example, the cascading circuit includes a plurality of cascaded shift registers, and the first trace 61 and the second trace 62 can be electrically connected to different shift registers.

[0153] Of course, in other examples, the first trace 61 and / or the second trace 62 may include traces electrically connected to the cascading circuit and the driving chip.

[0154] Exemplarily, the first segment 611 and the third segment 623 are located in the same film layer.

[0155] As an example, as Figure 14 shown in the figure, the second segment 612 and the fourth segment 624 are located in the same film layer.

[0156] As another example, as Figure 15 or Figure 16As shown, the second segment 612 and the fourth segment 624 are located in different film layers.

[0157] As an example, as Figure 15 shown, the second segment 612 and the first segment 611 are located in the same film layer.

[0158] As another example, as Figure 14 or Figure 16 shown, the second segment 612 and the first segment 611 are located in different film layers.

[0159] In some embodiments, as Figure 14 shown, at least one of the second segment 612 and the fourth segment 624 is located in the semiconductor layer B of the display panel. For example, both the second segment 612 and the fourth segment 624 are located in the semiconductor layer B.

[0160] The material of the trace located in the semiconductor layer B includes semiconductor materials, and the semiconductor materials include but are not limited to polysilicon (poly).

[0161] The semiconductor material has poor ductility. Therefore, even if the distance between the second segment 612 and the fourth segment 624 is small, the risk of short - circuit between the second segment 612 and the fourth segment 624 will be reduced.

[0162] In some embodiments, as Figure 15 shown, the first segment 611, the second segment 612, and the third segment 623 are located in the first metal layer M1, and the fourth segment 624 is located in the second metal layer M2. In this embodiment, the fourth segment 624 is rewired using other metal layers to increase the distance between the second segment 612 and the fourth segment 624. In addition, the first segment 611 and the second segment 612 are located in the same metal layer, so that the first trace 61 does not need to be rewired, reducing the process complexity.

[0163] The display panel further includes overlapping signal traces. The signal traces in the overlapping area are prone to cause the risk of short - circuit between the upper and lower traces during cutting. Special designs can be made for the signal traces in the overlapping area to reduce the risk of short - circuit of the signal traces in the overlapping area.

[0164] In some embodiments, as Figures 17 to 19 shown, the display panel includes a third trace 63 and a fourth trace 64 whose extension directions intersect. The third trace 63 includes a fifth segment 635 and a sixth segment 636 connected to each other, and the fourth trace 64 includes a seventh segment 647 and an eighth segment 648 connected to each other. In the thickness direction of the display panel, the sixth segment 636 and the eighth segment 648 at least partially overlap; the sixth segment 636 and the eighth segment 648 are located in different film layers, and the sixth segment 636 and the fifth segment 635 are located in different film layers, and / or the eighth segment 648 and the seventh segment 647 are located in different film layers.

[0165] It should be noted that Figures 17 to 19 In Figures 17 to 19 , the traces with the same filling pattern represent the traces located in the same film layer, and the traces with different filling patterns represent the traces located in different film layers. The line segments of the same trace located in different film layers can be connected through vias.

[0166] The third trace 63 is electrically connected to the pixel circuit and the cascading circuit, and the fourth trace 64 is electrically connected to the pixel circuit and the cascading circuit. The third trace 63 and the fourth trace 64 can be used to transmit different signals.

[0167] As an example, the cascading circuit includes a first cascading circuit for outputting a scan signal scan and a second cascading circuit for outputting a light emission control signal Emit. The third trace 63 can be electrically connected to the first cascading circuit and the pixel circuit, and the fourth trace 64 can be electrically connected to the second cascading circuit and the pixel circuit.

[0168] As an example, the cascading circuit includes a plurality of cascaded shift registers. The third trace 63 and the fourth trace 64 can be electrically connected to different shift registers.

[0169] Of course, in other examples, the third trace 63 and / or the fourth trace 64 may include traces electrically connected to the cascading circuit and the driving chip.

[0170] As an example, as Figure 17 shown, the sixth segment 636 and the eighth segment 648 are located in different film layers, the sixth segment 636 and the fifth segment 635 are located in different film layers, and the eighth segment 648 and the seventh segment 647 are located in the same film layer. In this example, it is equivalent to performing a wire replacement process on the sixth segment 636.

[0171] As another example, as Figure 18 shown, the sixth segment 636 and the eighth segment 648 are located in different film layers, the sixth segment 636 and the fifth segment 635 are located in different film layers, and the eighth segment 648 and the seventh segment 647 are located in different film layers, and the fifth segment 635 and the seventh segment 647 are located in different film layers. In this example, it is equivalent to performing a wire replacement process on both the sixth segment 636 and the eighth segment 648.

[0172] As yet another example, as Figure 19 shown, the sixth segment 636 and the eighth segment 648 are located in different film layers, the sixth segment 636 and the fifth segment 635 are located in the same film layer, and the eighth segment 648 and the seventh segment 647 are located in different film layers. In this example, it is equivalent to performing a wire replacement process on the eighth segment 648.

[0173] In the above embodiments, by performing wire replacement on the sixth segment 636 and / or the eighth segment 648 of the overlapping region, the distance between the sixth segment 636 and the eighth segment 648 in the thickness direction can be increased to reduce the risk of short circuit between the overlapping sixth segment 636 and eighth segment 648 during cutting.

[0174] In the embodiments of the present application, "being in the same film layer" for two structures means that the two structures can be formed simultaneously in the same process step. "Being in different film layers" for two structures means that the two structures cannot be formed simultaneously in the same process step.

[0175] In some embodiments, the ductility of the sixth segment 636 is lower than that of the fifth segment 635, and / or the ductility of the eighth segment 648 is lower than that of the seventh segment 647.

[0176] For example, the sixth segment 636 and / or the eighth segment 648 adopt materials with low ductility (such as poly, Mo, etc.) to reduce the risk of short circuit between the overlapping sixth segment 636 and eighth segment 648 during cutting.

[0177] In some embodiments, at least one conductive layer is provided between the sixth segment 636 and the eighth segment 648 in the thickness direction of the display panel. In this embodiment, replacing the wires of the sixth segment 636 and the eighth segment 648 in the overlapping region with wires having a greater distance can further increase the distance between the sixth segment 636 and the eighth segment 648 in the thickness direction to reduce the risk of short circuit between the overlapping sixth segment 636 and eighth segment 648 during cutting.

[0178] The above examples introduce that by performing wire replacement on the wires in the overlapping region, the distance between the wires in the overlapping region in the thickness direction of the display panel is increased to reduce the risk of short circuit between the overlapping wires during cutting.

[0179] In other embodiments, as Figure 20 shown, the display panel includes a fifth wire 65 and a sixth wire 66 whose extending directions intersect. The fifth wire 65 includes a ninth segment 659, and the sixth wire 66 includes a tenth segment 6610. In the thickness direction of the display panel, the ninth segment 659 and the tenth segment 6610 at least partially overlap. The fifth wire 65 and the sixth wire 66 are in different film layers. The ninth segment 659 and the tenth segment 6610 are in different film layers, and at least one of the ninth segment 659 and the tenth segment 6610 includes an opening K.

[0180] For example, the ninth segment 659 includes an opening K and the tenth segment 6610 does not include an opening.

[0181] For another example, the ninth segment 659 does not include an opening and the tenth segment 6610 includes an opening K.

[0182] For another example, the ninth segment 659 includes an opening K, and the tenth segment 6610 includes an opening K.

[0183] In this embodiment, the routing in the overlapping region is designed with a hollow-out, which can reduce the risk of short circuit of the routing in the overlapping region after cutting.

[0184] It should be noted that the present application does not limit the opening pattern.

[0185] In some embodiments, as Figure 21 shown, the display panel 100 includes an irregular edge s3. The irregular edge s3 can be a straight edge or a curved edge.

[0186] Figure 21 In (a), (b), (c), and (d) represent four different shapes of the display panel 100. For example, the display panel with the structure shown in any one of the Figures 1 to 7 、 Figures 9 to 12 drawings can be cut to obtain the display panel 100 with any one of the shapes in (a), (b), (c), and (d) in Figure 21 .

[0187] According to Figures 1 to 7 、 Figures 9 to 12 the display panel with the structure shown in any one of the drawings, it breaks the conventional design concept, no longer confines the cascade circuit 1 to the edge region of the display panel, but sets the cascade circuit 1 close to or even at the center of the display panel. In this way, when the display panel is cut to obtain other sizes or shapes of display panels, it is not easy to cut the cascade circuit 1, so as to protect the cascade circuit 1 from the risk of short circuit or open circuit, and thus avoid the abnormality of the cascade circuit 1 of the display panel shown in Figure 21 .

[0188] It can be understood that Figures 1 to 7 、 Figures 9 to 12 the display panel with the structure shown in any one of the drawings can be used as a common display panel, and the common display panel can be cut in various ways to obtain display panels of different sizes and shapes to a certain extent. Thus, while ensuring the performance of the display panel, it can flexibly meet different requirements; and there is no need to prepare a variety of different photomasks, which can reduce the product development cost and development cycle.

[0189] In some embodiments, as Figure 21 shown, the extending direction of the irregular edge s3 intersects both the first direction X and the second direction Y.

[0190] In some embodiments, as Figure 22As shown, the display panel includes m pixel circuit rows arranged along the second direction Y, where m is an integer greater than 1, and are labeled as the 1st pixel circuit row 2a_1 to the mth pixel circuit row 2a_m in sequence. The mth pixel circuit row 2a_m is closest to the bonding area BA of the display panel.

[0191] In the direction from the 1st pixel circuit row 2a_1 to the mth pixel circuit row 2a_m, the width of the display panel along the first direction X gradually increases.

[0192] Figure 22 Also shown are a plurality of sub-pixel areas Q3. Here, a small rectangular box represents a sub-pixel area Q3, and one pixel circuit is provided within one sub-pixel area Q3. One row of sub-pixel areas Q3 corresponds to one pixel circuit row.

[0193] Exemplarily, the display panel can be cut along the cutting lines L11 and L12 in Figure 2 to obtain a display panel with the shape shown in Figure 22 Since the cascading circuit 1 is located in the central area Q0, it is not easy to cut the cascading circuit 1, thereby being able to protect the cascading circuit 1 from the risk of short circuit or open circuit, and thus avoiding abnormalities in the cascading circuit 1 of the display panel shown in Figure 22 after cutting.

[0194] The shape and size of the display panel cannot be cut arbitrarily, but there are certain limiting conditions to ensure that the functions of the display panel after cutting are not damaged.

[0195] For example, to ensure that the functions of the display panel after cutting are not damaged, it is necessary to include the cascading circuit 1 extending along the second direction Y, the power supply signal line PVDD, the first type of signal line 3, and the common signal line PVEE.

[0196] In some embodiments, as shown in Figure 7 or Figure 9 or Figure 10 In the first direction X, the area between two common signal lines PVEE is a non-cuttable area.

[0197] In some embodiments, as shown in Figure 6 the display panel includes m pixel circuit rows 2a arranged along the second direction Y, where m is an integer greater than 1, and are labeled as the 1st pixel circuit row 2a_1 to the mth pixel circuit row 2a_m in sequence. The mth pixel circuit row 2a_m is closest to the bonding area BA of the display panel. Each pixel circuit 2 in the mth pixel circuit row 2a_m is a complete pixel circuit. That is to say, the mth pixel circuit row 2a_m is not cut.

[0198] For example, in the second direction Y, the position where the bonding area BA is located is below the display panel. Since the signals are output from bottom to top, if the lower end is cut off, the upper end corresponding thereto cannot be displayed either. In this embodiment, the m-th pixel circuit row 2a_m is not cut, that is to say, the bonding area BA is not cut, so as to ensure that all the signals required for the cut display panel can still be provided, thereby ensuring that the functions of the cut display panel are not damaged.

[0199] The present application also provides a display device, including the display panel provided by the present application. Please refer to Figure 23 , Figure 23 which is a schematic structural diagram of a display device provided by an embodiment of the present application. Figure 23 The provided display device 1000 includes the display panel 100 provided by any one of the above embodiments of the present application. Figure 23 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided by the embodiments of the present application can be other display devices with a display function such as wearable products, computers, TVs, in-vehicle display devices, etc. The present application does not make specific limitations thereto. The display device provided by the embodiments of the present application has the beneficial effects of the display panel provided by the embodiments of the present application. For the specific description of the display panel, reference can be made to the above embodiments, and details are not repeated herein.

[0200] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: The device comprises a central area, a first area and a second area, wherein the central area is located between the first area and the second area in a first direction, and the central area comprises a cascade circuit; And / or, the display panel includes a first type of signal line extending along a second direction, the cascade circuit of the display panel includes a plurality of shift registers arranged and cascaded along the second direction, the first type of signal line is electrically connected to the shift register, in the first direction, the distance between the shift register and the edge of the display panel is smaller than the distance between the first type of signal line and the edge of the display panel, and the first direction and the second direction intersect.

2. The display panel according to claim 1, characterized in that: The cascade circuit includes n shift registers arranged and cascaded along the second direction, where n is an integer greater than 1. In the second direction, the nth shift register among the n shift registers is closest to the binding area of ​​the display panel, and the nth shift register is connected to the binding area via a trigger signal line.

3. The display panel according to claim 1, characterized in that: The display panel further includes a first cutting mark. In the first direction, the first cutting mark is located on a side of the shift register close to an edge of the display panel.

4. The display panel according to claim 1 or 3, characterized in that: The display panel further includes a first cutting mark, and in the second direction, the first cutting mark is located between adjacent shift registers.

5. The display panel according to claim 4, characterized in that: In the second direction, the first cutting mark is spaced equidistant from two adjacent shift registers.

6. The display panel according to claim 1, characterized in that: The cascade circuit is used to output a scanning signal; The display panel includes a plurality of pixel circuit rows arranged along the second direction, and the plurality of pixel circuit rows are connected to the same light emitting control signal terminal.

7. The display panel according to claim 1, characterized in that: The display panel includes a plurality of pixel circuit rows arranged along the second direction, and the shift register is located between adjacent pixel circuit rows in the second direction.

8. The display panel according to claim 7, characterized in that: The display panel includes m pixel circuit rows arranged along the second direction, where m is an integer greater than 1, the binding area of ​​the mth pixel circuit row closest to the display panel is in the second direction, and the shift register is located on the side of the first pixel circuit row facing the binding area.

9. The display panel according to claim 1, characterized in that: The display panel includes a common signal line, and in the first direction, the first type of signal line is located between the common signal line and the cascade circuit.

10. The display panel according to claim 9, characterized in that: The display panel includes a plurality of pixel circuit columns arranged along the first direction. In the first direction, at least one pixel circuit column is disposed between the common signal line and an edge of the display panel.

11. The display panel according to claim 1, characterized in that: The first type of signal lines include high-level signal lines and low-level signal lines. The high-level signal lines are located at a first side of the cascade circuit in the first direction, and the low-level signal lines are located at a second side of the cascade circuit in the first direction.

12. The display panel according to claim 1, characterized in that: The display panel comprises a power signal line, and the cascade circuit is provided with the power signal line on both sides in the first direction; And / or, the display panel further includes a reset signal line, and the reset signal line is provided on both sides of the cascade circuit in the first direction.

13. The display panel according to claim 1, characterized in that: The first type of signal lines includes clock signal lines and other signal lines. In the first direction, the clock signal line is located between the other signal lines and the cascade circuit.

14. The display panel according to claim 1, characterized in that: The display panel comprises m pixel circuit rows arranged along the second direction, where m is an integer greater than 1, and the mth pixel circuit row is closest to the binding area of ​​the display panel; The display panel further includes an electrostatic discharge circuit, and the electrostatic discharge circuit is located between the mth pixel circuit row and the binding area.

15. The display panel according to claim 1, characterized in that: The display panel further includes a second cutting mark, and in the second direction, the second cutting mark is located on a side of the electrostatic discharge circuit facing the binding area of ​​the display panel.

16. The display panel according to claim 1, characterized in that: The spacing between at least some of the adjacent signal traces in the same film layer of the display panel and with parallel extension directions is greater than a first threshold.

17. The display panel according to claim 1, characterized in that: The display panel includes a first routing line and a second routing line that are adjacent and extend in parallel directions, the first routing line includes a first segment and a second segment that are connected to each other, the second routing line includes a third segment and a fourth segment that are connected to each other, the first segment and the third segment are adjacent, the second segment and the fourth segment are adjacent, in a direction parallel to the light emitting surface of the display panel, a spacing between the first segment and the third segment is greater than a spacing between the second segment and the fourth segment, the first segment and the third segment are located in the same film layer, and at least the fourth segment and the third segment are located in different film layers.

18. The display panel according to claim 17, characterized in that: At least one of the second segment and the fourth segment is located in a semiconductor layer of the display panel.

19. The display panel according to claim 17, characterized in that: The first segment, the second segment and the third segment are located in a first metal layer, and the fourth segment is located in a second metal layer.

20. The display panel according to claim 1, characterized in that: The display panel comprises a third routing line and a fourth routing line whose extension directions intersect each other, the third routing line comprises a fifth segment and a sixth segment connected to each other, the fourth routing line comprises a seventh segment and an eighth segment connected to each other, and in the thickness direction of the display panel, the sixth segment and the eighth segment at least partially overlap; The sixth section and the eighth section are located in different film layers, and the sixth section and the fifth section are located in different film layers, and / or the eighth section and the seventh section are located in different film layers.

21. The display panel according to claim 20, characterized in that: The ductility of the sixth segment is lower than the ductility of the fifth segment, and / or the ductility of the eighth segment is lower than the ductility of the seventh segment.

22. The display panel according to claim 20, characterized in that: At least one conductive layer is disposed between the sixth segment and the eighth segment in the thickness direction of the display panel.

23. The display panel according to claim 20, characterized in that: The display panel includes a fifth routing line and a sixth routing line whose extension directions intersect each other, the fifth routing line includes a ninth segment, the sixth routing line includes a tenth segment, and in the thickness direction of the display panel, the ninth segment and the tenth segment at least partially overlap; The ninth segment and the tenth segment are located in different film layers, and at least one of the ninth segment and the tenth segment includes an opening.

24. The display panel according to claim 1, characterized in that: The display panel includes a profiled edge.

25. The display panel according to claim 24, characterized in that: An extension direction of the special-shaped edge intersects both the first direction and the second direction.

26. The display panel according to claim 1, characterized in that: The display panel comprises m pixel circuit rows arranged along the second direction, where m is an integer greater than 1, and the mth pixel circuit row is closest to the binding area of ​​the display panel; In a direction from the first pixel circuit row to the mth pixel circuit row, the width of the display panel along the first direction gradually increases.

27. The display panel according to claim 9, characterized in that: In the first direction, the area between the two common voltage signal lines is an uncuttable area.

28. The display panel according to claim 1, characterized in that: The display panel comprises m pixel circuit rows arranged along the second direction, where m is an integer greater than 1, and the mth pixel circuit row is closest to the binding area of ​​the display panel; Each pixel circuit in the mth pixel circuit row is a complete pixel circuit.

29. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1-28.

Images