Pixel circuit, driving method thereof and display device

Abstract

The invention provides a pixel circuit, a driving method thereof and a display device. According to the pixel circuit, at least one control signal of the pixel circuit and at least one control signal of the (n + k) th row of pixel circuits located in the same column of the pixel circuit adopt an output signal of the same shifting register corresponding to the control signal. In this way, it can be understood that the corresponding control signals in the pixel circuits located in the same column in the k rows at intervals adopt the output signals of the same shifting register, and therefore the number of GOAs in the frame area of the display panel can be reduced, the occupied frame is reduced, and the narrow frame can be achieved conveniently.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device. Background Art

[0002] In a related display panel, a plurality of sub-pixel circuits and a pixel driving circuit for driving the sub-pixel circuits and disposed in a border area are provided. A single sub-pixel circuit requires a plurality of driving signals, and each driving signal is provided by a separate pixel driving circuit. However, this design method will occupy a relatively large border, which is not conducive to realizing a narrow border. Summary of the Invention

[0003] In view of this, an object of the present application is to provide a pixel circuit, a driving method thereof, and a display device to solve or partially solve the above problems.

[0004] Based on the above object, the present application provides a pixel circuit, including: a driving circuit, a data writing circuit, a first control circuit, a first storage circuit, a second storage circuit, a second control circuit, a third control circuit, a first reset circuit, a second reset circuit, and a light-emitting element;

[0005] The driving circuit includes a control terminal, a first terminal, and a second terminal, which are electrically connected to a first node, a third control circuit, and a second node respectively, and are configured to control a driving current flowing through the first terminal and the second terminal for driving the light-emitting element to emit light;

[0006] The first reset circuit is electrically connected to a first reset signal terminal, a first reset control signal terminal, and the second node or a first pole of the light-emitting element respectively, and is configured to apply a first reset voltage applied to the first reset signal terminal to the second node or the first pole of the light-emitting element under the control of a first reset control signal applied to the first reset control signal terminal;

[0007] The second reset circuit is electrically connected to a second reset signal terminal, a third node, and a second reset control signal terminal respectively, and is configured to apply a second reset voltage applied to the second reset signal terminal to the third node under the control of a second reset control signal applied to the second reset control signal terminal;

[0008] The first control circuit is electrically connected to a first signal terminal, the first node, and a first control signal terminal respectively, and is configured to apply a first signal applied to the first signal terminal to the first node under the control of a first control signal applied to the first control signal terminal;

[0009] The second control circuit is electrically connected to the first pole of the light-emitting element, the second node, and the second control signal terminal respectively, and is configured to connect or disconnect the first pole of the light-emitting element from the second node under the control of a second control signal applied to the second control signal terminal;

[0010] The first storage circuit is electrically connected to the first node and the second node respectively, and is configured to store the potential difference between the first node and the second node;

[0011] The second storage circuit is electrically connected to the second node and the third node respectively, and is configured to store the potential difference between the second node and the third node;

[0012] The third control circuit is electrically connected to the second signal terminal, the first end of the driving circuit, and the third control signal terminal respectively, and is configured to apply a second signal applied to the second signal terminal to the first end of the driving circuit under the control of a third control signal applied to the third control signal terminal to write the threshold voltage of the driving circuit to the second end of the driving circuit;

[0013] The data writing circuit is electrically connected to the data signal terminal, the third node, and the fourth control signal terminal respectively, and is configured to write a data signal applied to the data signal terminal to the second end of the driving circuit through the second storage circuit under the control of a fourth control signal applied to the fourth control signal terminal;

[0014] The second control circuit and the third control circuit are further configured to control the driving circuit to generate the driving current under the control of the second control signal and the third control signal respectively;

[0015] Wherein, the pixel circuit is located in the nth row of the display panel. The display panel includes N rows and M columns of pixel circuits and a gate driving circuit corresponding to the N rows of pixel circuits. The gate driving circuit includes a plurality of shift registers. At least one control signal of the pixel circuit and the pixel circuit in the (n + k)th row in the same column as the pixel circuit is an output signal of the same shift register corresponding to the control signal. The at least one control signal includes a first reset control signal, a second reset control signal, a first control signal, a second control signal, a third control signal, and / or a fourth control signal.

[0016] Optionally, k is 1, and the output level of the at least one control signal of the pixel circuit in the nth row has a displacement of at least one unit time from the output level of the at least one control signal of the pixel circuit in the (n + 1)th row in the same column.

[0017] Optionally, the first control signal terminal of the first control circuit and the second control signal terminal of the second control circuit receive the output signal of the same shift register, wherein the conduction level of the first control circuit is different from the conduction level of the second control circuit.

[0018] Optionally, the output level of the second reset control signal accessed by the second reset circuit has a shift of at least one unit time relative to the output level of the third control signal accessed by the third control circuit; and / or

[0019] The output level of the first control signal accessed by the first control circuit has a shift of at least one unit time relative to the output level of the third control signal accessed by the third control circuit, and the output level of the first control signal accessed by the first control circuit has a shift of at least one unit time relative to the output level of the second control signal accessed by the second control circuit.

[0020] Optionally, the output level of the second reset control signal accessed by the second reset circuit has a shift of at least one unit time relative to the output level of the third control signal accessed by the third control circuit;

[0021] The output level of the second control signal accessed by the second control circuit has a shift of at least one unit time relative to the output level of the first reset control signal accessed by the first reset circuit.

[0022] Optionally, the output level of the second reset control signal accessed by the second reset circuit has a shift of at least one unit time relative to the output level of the third control signal accessed by the third control circuit;

[0023] When k is 1, the output level of the data write control signal accessed by the data write circuit of the pixel circuit in the nth row has a shift of at least one unit time relative to the output level of the third control signal accessed by the third control circuit of the pixel circuit in the (n + 1)th row in the same column.

[0024] Optionally, the output level of the first control signal accessed by the first control circuit has a shift of at least one unit time from the output level of the third control signal accessed by the third control circuit; the output level of the first control signal accessed by the first control circuit has a shift of at least one unit time from the output level of the second control signal accessed by the second control circuit;

[0025] When k is 1, the output level of the data write signal accessed by the data write circuit in the (n + 1)th row has a shift of at least one unit time relative to the output level of the third control signal accessed by the third control circuit of the pixel circuit in the nth row in the same column.

[0026] Optionally, the polarities of the first transistor and the sixth transistor are different.

[0027] Based on the same inventive concept, the present application further provides a driving method, which is applied to the pixel circuit described in any one of the above. The method includes:

[0028] In the reset stage, making the output level of the first reset control signal have a shift of at least one unit time compared with the output level of the third control signal;

[0029] In the compensation stage, making the output level of the first control signal have a shift of at least one unit time compared with the output level of the fourth control signal; the output level of the first control signal has a shift of at least one unit time compared with the output level of the third control signal;

[0030] In the signal writing stage, the output level of the first reset control signal has a shift of at least one unit time compared with the output level of the first control signal; the output level of the first control signal has a shift of at least one unit time compared with the output level of the third control signal; the output level of the second control signal has a shift of at least one unit time compared with the output level of the first reset control signal.

[0031] Based on the same inventive concept, the present application further provides a display device, including the pixel circuit described in any one of the above.

[0032] As can be seen from the above, a pixel circuit, a driving method thereof, and a display device provided by the present application. The pixel circuit includes: the pixel circuit is located in the nth row of the display panel. The display panel includes N rows and M columns of pixel circuits and a gate driving circuit corresponding to the N rows of pixel circuits. The gate driving circuit includes a plurality of shift registers. At least one control signal of the pixel circuit and the pixel circuit in the (n + k)th row in the same column is an output signal of the same shift register corresponding to the control signal. The at least one control signal includes a first reset control signal, a second reset control signal, a first control signal, a second control signal, a third control signal, and / or a fourth control signal. By using the output signal of the same shift register corresponding to the control signal for at least one control signal of the pixel circuit and the pixel circuit in the (n + k)th row in the same column. It can be understood that the corresponding control signals in the pixel circuits in the same column separated by k rows use the output signals of the same shift register. In this way, the number of GOAs in the border area of the display panel can be saved, thereby reducing the occupied border and facilitating the realization of a narrow border. Description of the Drawings

[0033] To more clearly illustrate the technical solutions in the present application or related technologies, the following will briefly introduce the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings in the following description are only embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0034] Figure 1A Shows a schematic diagram of an exemplary pixel circuit.

[0035] Figure 1B Shows another schematic diagram of an exemplary pixel circuit.

[0036] Figure 2A Shows a schematic structural diagram of the exemplary pixel circuit provided by the present application.

[0037] Figure 2B Shows a connection block diagram of an N-row and M-column pixel circuit and a gate driving circuit according to the present application.

[0038] Figure 2C Shows a schematic diagram of the exemplary pixel circuit provided by the present application.

[0039] Figure 2D Shows a schematic diagram of the driving timing of the exemplary pixel circuit provided by the present application.

[0040] Figures 3A - 3B Shows a schematic diagram of the driving timing of an exemplary N-row and same-column pixel circuit sharing a shift register provided by the present application.

[0041] Figures 3C - 3D Shows a schematic diagram of the driving timing of another exemplary N-row and same-column pixel circuit sharing a shift register provided by the present application.

[0042] Figures 3E - 3F Shows a schematic diagram of the driving timing of another exemplary N-row and same-column pixel circuit sharing a shift register provided by the present application.

[0043] Figures 3G - 3H Shows a schematic diagram of the driving timing of another exemplary N-row and same-column pixel circuit sharing a shift register provided by the present application.

[0044] Figures 3I - 3J Shows a schematic diagram of the driving timing of another exemplary N-row and same-column pixel circuit sharing a shift register provided by the present application.

[0045] Figures 3K - 3L Shows a schematic diagram of the driving timing of another exemplary N-row and same-column pixel circuit sharing a shift register provided by the present application.

[0046] Figure 4A Shows a schematic structural diagram of another exemplary pixel circuit provided by the present application.

[0047] Figure 4B Shows a schematic diagram of another exemplary pixel circuit provided by the present application.

[0048] Figure 4C Shows the Figure 4B schematic diagram of the driving timing of the exemplary pixel circuit in

[0049] Figure 5A Shows a schematic diagram of another exemplary pixel circuit provided by the present application.

[0050] Figure 5B Shows Figure 5A the schematic diagram of the driving timing of the exemplary pixel circuit in

[0051] Figure 6A Shows a schematic diagram of another exemplary pixel circuit provided by the present application.

[0052] Figure 6B Shows in Figure 6A the schematic diagram of the driving timing of the exemplary pixel circuit in

[0053] Figure 6C Shows a schematic diagram of another exemplary pixel circuit provided by the present application.

[0054] Figure 6D Shows in Figure 6C the schematic diagram of the driving timing of the exemplary pixel circuit in

[0055] Figure 6E Shows a schematic diagram of another exemplary pixel circuit provided by the present application.

[0056] Figure 6F Shows in Figure 6E the schematic diagram of the driving timing of the exemplary pixel circuit in

[0057] Figure 6G Shows a schematic diagram of another exemplary pixel circuit provided by the present application.

[0058] Figure 6H Shows in Figure 6G the schematic diagram of the driving timing of the exemplary pixel circuit in Detailed implementation manners

[0059] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0060] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the ordinary meanings understood by those of ordinary skill in the art to which the present application belongs. The "first", "second" and similar terms used in the embodiments of the present application do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0061] Figure 1A shows a schematic diagram of an exemplary pixel circuit. Figure 1B shows another schematic diagram of an exemplary pixel circuit. Exemplarily, Figure 1A and Figure 1B The pixel circuits in are both 7T2C circuits. That is, the above pixel circuit is composed of 7 transistors and 2 capacitors. Among them, T1 is a compensation transistor, T2 is a reset transistor, T3 is a data writing transistor, T4 is a driving transistor, T5 and T6 are light-emitting control transistors, T7 is an anode reset transistor, and C1 and C2 are both storage capacitors. In this example, the compensation transistor, reset transistor, data writing transistor, light-emitting control transistor, and anode reset transistor in the 7T2C circuit each require a control signal to control their gates, so this pixel circuit requires six control signals. Correspondingly, six GOA (Gate On Array) circuits are required to generate these six control signals respectively. Since the GOA circuits are arranged in the border area of the display panel, and there are multiple rows of pixel circuits in the display panel, in this way, each row of pixel circuits requires at least six GOA circuits, which results in a large number of GOA circuits, occupying a large border, and is not conducive to realizing a narrow border.

[0062] Based on the above description, the embodiments of the present application provide a pixel circuit 10, by using the output signal of the same shift register for at least one control signal of the pixel circuit 10 and the pixel circuit 10 of the (n + k)-th row in the same column as the pixel circuit 10. It can be understood that the corresponding control signals in the pixel circuits 10 in the same column separated by k rows use the output signal of the same shift register. In this way, the number of GOAs in the border area of the display panel can be saved, thereby reducing the occupied border and facilitating the realization of a narrow border.

[0063] The transistors used in all embodiments of the present application can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. In the embodiments of the present application, to distinguish the two poles of the transistor other than the gate (which can also be referred to as the control terminal), one pole is referred to as the first pole and the other pole is referred to as the second pole.

[0064] Optionally, when the transistor is a thin-film transistor or a field-effect transistor, the first pole can be the drain and the second pole can be the source; or, the first pole can be the source and the second pole can be the drain.

[0065] Figure 2A The structural schematic diagram of the exemplary pixel circuit 10 provided by the present application is shown.

[0066] As Figure 2A shown, the embodiments of the present application provide a pixel circuit 10, including: a driving circuit 101, a data writing circuit 102, a first control circuit 103, a first storage circuit 104, a second storage circuit 105, a second control circuit 106, a third control circuit 107, a first reset circuit 108, a second reset circuit 109, and a light-emitting element 110 (OLED);

[0067] The driving circuit 101 includes a control terminal, a first terminal, and a second terminal, which are respectively electrically connected to the first node N1, the third control circuit 107, and the second node N2, and is used to control the driving current flowing through the first terminal and the second terminal for driving the light-emitting element 110 (OLED) to emit light.

[0068] Exemplarily, the control terminal of the driving circuit 101 is electrically connected to the first node N1, the first terminal of the driving circuit 101 is electrically connected to the second node N2, and the second terminal of the driving circuit 101 is electrically connected to the third node N3. The driving circuit 101 is used to control the driving current flowing through the first terminal and the second terminal for driving the light-emitting element 110 (OLED) to emit light under the control of the potential of the first node N1.

[0069] The first reset circuit 108 is respectively electrically connected to the first reset signal terminal Vint, the first reset control signal terminal GI(n), and the second node N2 or the first pole of the light-emitting element 110 (OLED), and is used to apply the first reset voltage accessed by the first reset signal terminal Vint to the first pole of the light-emitting element 110 (OLED) under the control of the first reset control signal accessed by the first reset control signal terminal GI(n).

[0070] Exemplarily, the first reset circuit 108 includes a control terminal, a first pole, and a second pole. The control terminal of the first reset circuit 108 is electrically connected to the first reset control signal terminal GI(n), the first pole of the first reset circuit 108 is electrically connected to the first reset signal terminal Vint, and the second pole of the first reset circuit 108 is electrically connected to the first pole of the light-emitting element 110 (OLED). That is, the first reset circuit 108 is configured to apply the first reset voltage applied to the first pole of the first reset circuit 108 to the first pole of the light-emitting element 110 (OLED) under the control of the first reset control signal applied to the control terminal.

[0071] Optionally, the first reset circuit 108 is respectively electrically connected to the first reset signal terminal Vint, the first reset control signal terminal GI(n), and the second node N2, and is configured to apply the first reset voltage applied to the first reset signal terminal Vint to the second node N2 under the control of the first reset control signal applied to the first reset control signal terminal GI(n).

[0072] Exemplarily, the first reset circuit 108 includes a control terminal, a first pole, and a second pole. The control terminal of the first reset circuit 108 is electrically connected to the first reset control signal terminal GI(n), the first pole of the first reset circuit 108 is electrically connected to the first reset signal terminal Vint, and the second pole of the first reset circuit 108 is electrically connected to the second node N2. That is, the first reset circuit 108 is configured to apply the first reset voltage applied to the first pole of the first reset circuit 108 to the second node N2 under the control of the first reset control signal applied to the control terminal.

[0073] The second reset circuit 109 is respectively electrically connected to the second reset signal terminal Vref, the third node N3, and the second reset control signal terminal GR1(n), and is configured to apply the second reset voltage applied to the second reset signal terminal Vref to the third node N3 under the control of the second reset control signal applied to the second reset control signal terminal GR1(n).

[0074] Exemplarily, the second reset circuit 109 includes a control terminal, a first pole, and a second pole. The control terminal of the second reset circuit 109 is electrically connected to the second reset control signal terminal GR1(n), the first pole of the second reset circuit 109 is electrically connected to the second reset signal terminal Vref, and the second pole of the second reset circuit 109 is electrically connected to the third node N3. That is, the second reset circuit 109 is configured to apply the second reset voltage applied to the first pole of the second reset circuit 109 to the third node N3 under the control of the second reset control signal applied to the control terminal.

[0075] The first control circuit 103 is electrically connected to the first signal terminal Vref, the first node N1, and the first control signal terminal GR2(n) respectively, and is configured to apply the first signal applied to the first signal terminal Vref to the first node N1 under the control of the first control signal applied to the first control signal terminal GR2(n).

[0076] Exemplarily, the first control circuit 103 includes a control terminal, a first pole, and a second pole. The control terminal of the first control circuit 103 is electrically connected to the first control signal terminal GR2(n), the first pole of the first control circuit 103 is electrically connected to the first signal terminal Vref, and the second pole of the first control circuit 103 is electrically connected to the first node N1. That is, the first control circuit 103 is configured to apply the first signal applied to the first pole to the first node N1 under the first control signal applied to the first control signal terminal GR2(n).

[0077] Preferably, the second reset signal terminal Vref and the first signal terminal Vref are the same signal terminal (such as Figure 2A Vref in). In this way, it is possible to avoid connecting two external signals, thereby reducing the wiring, and further reducing the signal crosstalk between the lines.

[0078] The second control circuit 106 is electrically connected to the first pole of the light-emitting element 110 (OLED), the second node N2, and the second control signal terminal EM2(n) respectively, and is configured to connect or disconnect the first pole of the light-emitting element 110 (OLED) from the second node N2 under the control of the second control signal applied to the second control signal terminal EM2(n).

[0079] Exemplarily, the second control circuit 106 includes a control terminal, a first pole, and a second pole. The control terminal of the second control circuit 106 is electrically connected to the second control signal terminal EM2(n), the first pole of the second control circuit 106 is electrically connected to the second node N2, and the second pole of the second control circuit 106 is electrically connected to the first pole of the light-emitting element 110 (OLED). Under the control of the second control signal applied to the control terminal of the second control circuit 106, the first pole of the light-emitting element 110 (OLED) is connected or disconnected from the second node N2.

[0080] The third control circuit 107 is electrically connected to the second signal terminal ELVDD, the first end of the driving circuit 101, and the third control signal terminal EM1(n) respectively, and is configured to apply the second signal applied to the second signal terminal ELVDD to the first end of the driving circuit 101 under the control of the third control signal applied to the third control signal terminal EM1(n) to write the threshold voltage of the driving circuit 101 to the second end of the driving circuit 101.

[0081] Exemplarily, the third control circuit 107 includes a control terminal, a first pole, and a second pole. The control terminal of the third control circuit 107 is electrically connected to the third control signal terminal EM1(n). The first pole of the third control circuit 107 is electrically connected to the second signal terminal ELVDD. The second pole of the third control circuit 107 is electrically connected to the first end of the drive circuit 101. In this way, under the third control signal applied to the control terminal of the third control circuit 107, the second signal applied to the first pole is applied to the first end of the drive circuit 101 to write the threshold voltage of the drive circuit 101 to the second end of the drive circuit 101.

[0082] Optionally, the second control circuit 106 and the third control circuit 107 are further configured to control the drive circuit 101 to generate the drive current under the control of the second control signal and the third control signal, respectively.

[0083] Exemplarily, the third control circuit 107 applies the second signal to the first end of the drive circuit 101 under the control of the third control signal to write the threshold voltage of the drive circuit 101 to the second end of the drive circuit 101; the second control circuit 106 writes the threshold voltage (i.e., the drive current) at the second end of the drive circuit 101 to the first pole of the light-emitting element 110 (OLED) under the control of the second control signal to realize the light emission of the light-emitting element 110 (OLED).

[0084] The first storage circuit 104 is electrically connected to the first node N1 and the second node N2 respectively, and is configured to store the potential difference between the first node N1 and the second node N2.

[0085] Exemplarily, the first storage circuit 104 includes a first pole and a second pole. The first pole of the first storage circuit 104 is electrically connected to the first node N1, and the second pole of the first storage circuit 104 is electrically connected to the second node N2. The first storage circuit 104 stores the potential difference between the first node N1 and the second node N2.

[0086] The second storage circuit 105 is electrically connected to the second node N2 and the third node N3 respectively, and is configured to store the potential difference between the second node N2 and the third node N3.

[0087] Exemplarily, the second storage circuit 105 includes a first pole and a second pole. The first pole of the second storage circuit 105 is electrically connected to the second node N2, and the second pole of the second storage circuit 105 is electrically connected to the third node N3. The second storage circuit 105 stores the potential difference between the second node N2 and the third node N3.

[0088] The data writing circuit 102 is electrically connected to the data signal terminal Vdata, the third node N3, and the fourth control signal terminal GW(n) respectively, and is configured to write the data signal accessed by the data signal terminal Vdata into the second terminal of the driving circuit 101 through the second storage circuit 105 under the control of the fourth control signal accessed by the fourth control signal terminal GW(n).

[0089] Exemplarily, the data writing circuit 102 includes a control terminal, a first pole, and a second pole. The control terminal of the data writing circuit 102 is electrically connected to the fourth control signal terminal GW(n), the first pole of the data writing circuit 102 is electrically connected to the data signal terminal Vdata, and the second pole of the data writing circuit 102 is electrically connected to the third node. That is, the data writing circuit 102 writes the data signal of the data signal terminal Vdata into the second node N2 under the control of the fourth control signal of the fourth control signal terminal GW(n), that is, writes it into the second terminal of the driving circuit 101 through the second storage circuit 105.

[0090] Optionally, the fourth control signal is generated by a gate driving circuit 11 (optionally, a gate on array (GOA) circuit on the array substrate).

[0091] Figure 2B A connection structure block diagram of an N-row and M-column pixel circuit 10 and a gate driving circuit 11 according to the present application is shown.

[0092] As Figure 2B shown, the pixel circuit 10 is located in the nth row of the display panel 1. The display panel 1 includes an N-row and M-column pixel circuit 10 and a gate driving circuit 11 corresponding to the N rows of the pixel circuits 10. The gate driving circuit 11 includes a plurality of shift registers. At least one control signal of the pixel circuit 10 and the pixel circuit 10 in the (n + k)th row located in the same column as the pixel circuit 10 is an output signal of the same shift register corresponding to the control signal. The at least one control signal includes a first reset control signal, a second reset control signal, a first control signal, a second control signal, a third control signal, and / or a fourth control signal.

[0093] Exemplarily, the display panel 1 includes 4 rows and 3 columns of pixel circuits 10 and a gate driving circuit 11 corresponding to the 4 rows and 3 columns of pixel circuits 10. Each pixel circuit 10 requires 6 shift registers to provide control signals for it. Then, the gate driving circuit 11 includes 216 shift registers corresponding to the 4 rows and 3 columns of pixel circuits 10. For example, at least one control signal of the first row of pixel circuits 10 and the second row of pixel circuits 10 in the same column as the first row of pixel circuits 10 is provided by the same shift register. Among them, the control signals include a first reset control signal, a second reset control signal, a first control signal, a second control signal, a third control signal, and a fourth control signal. Exemplarily, the first control signal of the first row of pixel circuits 10 and the second row of pixel circuits 10 in the same column as the first row of pixel circuits 10 is provided by the same shift register, the second reset control signal of the first row of pixel circuits 10 and the second row of pixel circuits 10 in the same column as the first row of pixel circuits 10 is provided by the same shift register, the third control signal of the first row of pixel circuits 10 and the second row of pixel circuits 10 in the same column as the first row of pixel circuits 10 is provided by the same shift register, and / or the second reset control signal of the first row of pixel circuits 10 and the second row of pixel circuits 10 in the same column as the first row of pixel circuits 10 is provided by the same shift register. It can be seen from this that two pixel circuits 10 actually require 12 GOA circuits to provide control signals for them. However, in this application, for pixel circuits 10 in the same column separated by k rows (where k rows can be multiple rows separated or adjacent rows), the corresponding control signals use the output signals of the same shift register. That is, through the above technical solution, two pixel circuits 10 save 4 GOA circuits. In this way, the number of GOAs in the pixel circuit 10 is saved, and further the occupied border is reduced, which is convenient for realizing a narrow border.

[0094] Figure 2C FIG. shows a schematic diagram of an exemplary pixel circuit 10 provided by the present application.

[0095] It should be noted that each exemplary pixel circuit 10 shown in the present application Figure 2A gives an example description of the circuit composition of each circuit module in Figure 2B , but this is not limited to each circuit module must adopt a structure exactly the same as that described in Figure 2B . For example, the driving circuit 101 adopts the circuit composition shown in Figure 2B , and the data writing circuit 102 can adopt a circuit composition different from that shown in

[0096] For example, it may include more transistors, etc., as long as it can apply the data voltage to the second node N2 under the control of the scan signal. This understanding also applies to other exemplary circuit structures of the present disclosure. Figure 2CAs shown, by way of example, the first control circuit 103 includes a first transistor T1; the control electrode of the first transistor T1 is electrically connected to the first control signal terminal GR2(n) and is used to receive the first control signal, the first electrode of the first transistor T1 is electrically connected to the first signal terminal Vref and is used to receive the first signal, and the second electrode of the first transistor T1 is electrically connected to the first node N1 and is used to apply the first signal to the first node N1 under the control of the received first control signal.

[0097] Specifically, the GOA circuit in the gate driving circuit 11 that outputs the first control signal writes the first control signal to the control terminal of the first transistor T1, causing the first transistor T1 to conduct, and the first transistor T1 applies the received first signal to the first node N1.

[0098] The first storage circuit 104 includes a first storage capacitor C1. The first electrode of the first storage capacitor C1 is electrically connected to the first node N1, and the second electrode of the first storage capacitor C1 is electrically connected to the second node N2.

[0099] Specifically, the first storage capacitor C1 is used to store the potential difference between the first node N1 and the second node N2.

[0100] The second storage circuit 105 includes a second storage capacitor C2. The first electrode of the second storage capacitor C2 is electrically connected to the third node N3, and the second electrode of the second storage capacitor C2 is electrically connected to the second node N2.

[0101] Specifically, the second storage capacitor C2 is used to store the potential difference between the second node N2 and the third node N3.

[0102] Optionally, the first storage capacitor C1 and the second storage capacitor C2 are connected in series. They can not only store the voltage signals of the corresponding nodes, but also play a role in voltage division to ensure that a preset voltage signal is input to the corresponding nodes.

[0103] The second reset circuit 109 includes a second transistor T2. The control electrode of the second transistor T2 is electrically connected to the second reset control signal terminal GR1(n) to receive the second reset control signal, the first electrode of the second transistor T2 is electrically connected to the second reset signal terminal Vref to receive the second reset voltage, and the second electrode of the second transistor T2 is electrically connected to the third node N3.

[0104] Specifically, the GOA circuit in the gate driving circuit 11 for outputting the second reset control signal writes the second reset control signal to the control terminal of the second transistor T2, and the second transistor T2 writes the second reset voltage to the third node N3 under the action of the second reset control signal.

[0105] The data writing circuit 102 includes a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the fourth control signal terminal GW(n) for receiving the fourth control signal. The first electrode of the third transistor T3 is electrically connected to the data signal terminal Vdata for receiving the data signal. The second electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 serves as the third node N3.

[0106] Specifically, the GOA circuit in the gate driving circuit 11 for outputting the fourth control signal writes the fourth control signal to the control terminal of the third transistor T3, and the third transistor T3 writes the data signal to the third node N3 under the control of the fourth control signal.

[0107] The driving circuit 101 includes a fourth transistor T4. The control electrode of the fourth transistor T4 serves as the control terminal of the driving circuit 101 and is electrically connected to the first node N1. The first electrode of the fourth transistor T4 serves as the first end of the driving circuit 101 and is electrically connected to the third control circuit 107. The second electrode of the fourth transistor T4 serves as the second end of the driving circuit 101 and is electrically connected to the second node N2.

[0108] Specifically, the fourth transistor T4 generates a driving current based on the voltage received by the third control circuit 107 received by the fourth transistor T4 under the action of the voltage at the first node N1 and writes it to the second node N2.

[0109] The third control circuit 107 includes a fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected to the third control signal terminal EM1(n) for receiving the third control signal. The first electrode of the fifth transistor T5 is electrically connected to the second signal terminal ELVDD for receiving the second signal. The second electrode of the fifth transistor T5 is electrically connected to the first electrode of the driving transistor.

[0110] Specifically, the GOA circuit in the gate driving circuit 11 for outputting the third control signal writes the third control signal to the control terminal of the fifth transistor T5, and the fifth transistor T5 writes the second signal to the first electrode of the driving transistor under the control of the third control signal.

[0111] The second control circuit 106 includes a sixth transistor T6. The control electrode of the sixth transistor T6 is electrically connected to the second control signal terminal EM2(n) for receiving the second control signal. The first electrode of the sixth transistor T6 is electrically connected to the second node N2. The second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element 110 (OLED).

[0112] Specifically, the GOA circuit in the gate driving circuit 11 for outputting the second control signal writes the second control signal to the control terminal of the sixth transistor T6. The sixth transistor T6 writes a driving current to the light-emitting element 110 (OLED) under the control of the second control signal, driving the light-emitting element 110 (OLED) to emit light.

[0113] The first reset circuit 108 includes a seventh transistor T7. The control electrode of the seventh transistor T7 is electrically connected to the first reset control signal terminal GI(n) for receiving the first reset control signal. The first electrode of the seventh transistor T7 is electrically connected to the first reset signal terminal Vint for receiving the first reset voltage. The second electrode of the first transistor T1 is electrically connected to the first electrode of the light-emitting element 110 (OLED).

[0114] Specifically, the GOA circuit in the gate driving circuit 11 for outputting the first reset signal writes the first reset control signal to the control terminal of the seventh transistor T7. The seventh transistor T7 writes the first reset voltage to the first electrode of the light-emitting element 110 (OLED) (that is, writes to the anode of the light-emitting element 110 (OLED) to reset the anode of the light-emitting element 110 (OLED)) under the control of the first reset signal.

[0115] Figure 2D The driving timing diagram of the exemplary pixel circuit 10 provided by the present application is shown.

[0116] Combined with Figure 2C and Figure 2DAs shown, the specific driving process is as follows: In the initialization (or reset) phase: The control signals of the second control signal terminal EM2(n), the second reset control signal terminal GR1(n), the first control signal terminal GR2(n), and the first reset control signal terminal GI(n) are all at high level, and the sixth transistor T6, the second transistor T2, the first transistor T1, and the bottom transistor are all turned on. Among them, the seventh transistor T7 is turned on, and the first reset signal of the first reset signal terminal VintVinit is written into the anode of the light-emitting device to initialize the anode potential of the light-emitting element 110 (OLED); the sixth transistor T6 is turned on, so as to initialize the potential of the second node N2 by using the first reset signal of the first reset signal terminal VintVinit; the first transistor T1 and the second transistor T2 are turned on, and the first signal is written into the first node N1, and the second reset signal is written into the third node N3, so as to initialize the potentials of the first node N1 and the third node N3. In this way, the initialization of the pixel circuit 10 is realized, that is, reset, that is: the potentials of each key node in the pixel circuit 10 are initialized (or reset) to the initial state.

[0117] In the compensation phase: The control signals of the third control signal terminal EM1(n), the second reset control signal, the first control signal, and the first reset control signal are all at high level, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are all turned on. The states of the first transistor T1, the second transistor T2, and the seventh transistor T7 remain unchanged, and the anode potential of the light-emitting element 110 (OLED), the potentials of the first node N1 and the third node N3 remain unchanged. At this time, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, so that the first end of the driving transistor (i.e., the fourth transistor T4) is set to the second signal of the second signal terminal ELVDD, so that the threshold voltage of the driving transistor is written into the second node N2, and the compensation of the threshold voltage of the driving transistor (the fourth transistor T4) is completed.

[0118] In the signal writing phase: The control signals of the fourth signal control terminal, the first control signal terminal GR2(n), and the first reset control signal terminal GI(n) are all at high level, and the first transistor T1, the third transistor T3, and the seventh transistor T7 are all turned on. The states of the first transistor T1 and the seventh transistor T7 remain unchanged, and the anode potential of the light-emitting element 110 (OLED) and the potential of the first node N1 remain unchanged. The third transistor T3 is turned on, and the data signal of the data signal terminal VdataVdata is written into the third node N3, and then the potential of the second node N2 jumps through the second storage capacitor C2, so that the data signal of the data signal terminal VdataVdata is written into the second node N2.

[0119] In the light-emitting stage: The control signals of the third control signal terminal EM1(n) and the second control signal terminal EM2(n) are both at high level, controlling the fifth transistor T5 and the sixth transistor T6 to turn on, so that the driving transistor (the fourth transistor T4) generates a current for driving the light-emitting device. Since the threshold voltage compensation has been performed on the driving transistor and the data voltage has been written, the generated driving current corresponds to the gray level of the pixel (not affected by the threshold voltage), and the light emission is completed.

[0120] Figures 3A - 3B Fig. shows an exemplary schematic diagram of a shift register shared by pixel circuits 10 in the same column of N rows provided by the present application and driving timing.

[0121] As Figure 3A shown, on the basis of the above embodiment, the second reset control signal terminal GR1(n) of the pixel circuit 10 in the nth row and mth column is electrically connected to the same shift register as the second reset control signal terminal GR1(n) of the pixel circuit 10 in the (n + 1)th row and mth column, that is, the second reset control signal terminal GR1(n) of the pixel circuit 10 in the nth row and mth column shares a GOA circuit with the second reset control signal terminal GR1(n) of the pixel circuit 10 in the (n + 1)th row and mth column.

[0122] In this embodiment, k is 1, and the output level of at least one control signal of the pixel circuit 10 in the nth row has a displacement of at least one unit time from the output level of at least one control signal of the pixel circuit 10 in the (n + 1)th row in the same column.

[0123] As Figure 3B shown, different from the driving process of the above embodiment: the second reset control signal terminal GR1(n) of the pixel circuit 10 in the nth row shares a shift register with the second reset control signal terminal GR1(n) of the pixel circuit 10 in the (n + 1)th row in the same column. Then the output levels of the first reset control signal terminal GI(n), the first control signal terminal GR2(n), the second control signal terminal EM2(n), the third control signal terminal EM1(n) and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the nth row are displaced by at least one unit time compared with the output levels of the first reset control signal terminal GI(n), the first control signal terminal GR2(n), the second control signal terminal EM2(n), the third control signal terminal EM1(n) and / or the fourth control signal terminal GW(n) in the pixel circuit 10 in the (n + 1)th row in the same column. That is, the output levels of the control signals in the pixel circuit 10 in the (n + 1)th row are delayed by at least one unit time compared with the output levels of the corresponding control signal terminals in the pixel circuit 10 in the nth row. The displacement of at least one unit time can be as Figure 3B1H in this way. In this way, the output level of the control signal of the next row in adjacent rows (the adjacent rows can also be k rows apart) is later than the output level of the control signal of the previous row by 1H, which can ensure the output stability of the control signal and further improve the driving stability of the pixel circuit 10.

[0124] As Figure 3B shown, the output level of the second reset signal connected to the second reset circuit 109 has a shift of at least one unit time from the output circuit of the third control signal connected to the third control circuit 107. Exemplarily, the falling edge of the waveform of GR1(n) is at least 1H later than the falling edge of the waveform of EM1(n) (1H is the time for writing the signal of one row of pixels, that is, the time when the third transistor T3 is turned on). In this way, it can be ensured that the falling edge of the waveform of GR1(n) is not later than the waveform of EM1(n + 1). Because during the high-level period of EM1(n + 1), the fifth transistor T5 is turned on, and the Vth of the fourth transistor T4 is gradually compensated, and the voltage of the second node N2 is constantly changing. Although it will finally tend to be stable, if the second transistor T2 is turned off earlier than the fifth transistor T5, it will cause a change in the third node N3, so that before the data write signal of the data write signal terminal Vdata is written, the second node N2 cannot be completely maintained at a known constant voltage (taking Vref in the figure as an example, but not limited to this), which will cause inaccurate signal writing.

[0125] Figures 3C - 3D shows another schematic diagram of a shift register shared by N rows of pixel circuits 10 in the same column and the driving timing provided by the present application.

[0126] As Figure 3C shown, on the basis of the above embodiment, the first control signal terminal GR2(n) of the pixel circuit 10 in the nth row and mth column is electrically connected to the same shift register as the first control signal terminal GR2(n) of the pixel circuit 10 in the (n + 1)th row and mth column, that is, the first control signal terminal GR2(n) of the pixel circuit 10 in the nth row and mth column shares a GOA circuit with the first control signal terminal GR2(n) of the pixel circuit 10 in the (n + 1)th row and mth column.

[0127] In this embodiment, k is 1, and the output level of at least one control signal of the pixel circuit 10 in the nth row has a displacement of at least one unit time from the output level of at least one control signal of the pixel circuit 10 in the (n + 1)th row in the same column.

[0128] As Figure 3DAs shown, different from the driving process of the above embodiment: the first control signal terminal GR2(n) of the pixel circuit 10 in the n-th row shares a shift register with the first control signal terminal GR2(n) of the pixel circuit 10 in the (n + 1)-th row in the same column. Then, the output levels of the first reset control signal terminal GI(n), the second reset control signal terminal GR1(n), the second control signal terminal EM2(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the n-th row have a displacement of up to one unit time compared to the output levels of the first reset control signal terminal GI(n), the second reset control signal terminal GR1(n), the second control signal terminal EM2(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) in the pixel circuit 10 in the (n + 1)-th row in the same column. That is, the output levels of the control signals in the pixel circuit 10 in the (n + 1)-th row are at least one unit time later than the output levels of the corresponding control signal terminals in the pixel circuit 10 in the n-th row. The displacement of at least one unit time can be, for example, Figure 3D 1H in

[0129] Continue to refer to Figure 3D , the output level of the first control signal connected to the first control circuit 103 has a displacement of at least one unit time compared to the output level of the third control signal connected to the third control circuit 107, and the output level of the first control signal connected to the first control circuit 103 has a displacement of at least one unit time compared to the output level of the second control signal connected to the second control circuit 106. Exemplarily, on the basis that the first control signal terminal GR2(n) of the pixel circuit 10 in the n-th row shares a shift register with the first control signal terminal GR2(n) of the pixel circuit 10 in the (n + 1)-th row in the same column, it is required that the falling edge of the GR2(n) waveform is at least 1H later than that of GW(n), so as to ensure that when the signal of the pixel in the (n + 1)-th row is written, the first transistor T1 is in the on state and the first node N1 is connected to a stable level (such as Vref). And the falling edge of the GR2(n) waveform is at least 1H later than the falling edge of the EM1(n) waveform in the compensation stage, so as to ensure that after the first transistor T1 in the (n + 1)-th row of pixels is turned off, the fifth transistor T5 is also in the off state, so that the Vth compensation of the driving transistor ends.

[0130] Figures 3E - 3F shows another exemplary schematic diagram of the shift register shared by N rows of pixel circuits 10 in the same column and the driving timing in the present application.

[0131] As Figure 3E shown, based on the above embodiments, the second reset control signal terminal GR1(n) and the first control signal terminal GR2(n) of the pixel circuit 10 in the n-th row and m-th column are electrically connected to the same shift register as those of the pixel circuit 10 in the (n + 1)-th row and m-th column. That is, the second reset control signal terminal GR1(n) and the first control signal terminal GR2(n) of the pixel circuit 10 in the n-th row and m-th column share a GOA circuit with those of the pixel circuit 10 in the (n + 1)-th row and m-th column.

[0132] In this embodiment, k is 1, and the output level of at least one control signal of the pixel circuit 10 in the n-th row has a displacement of at least one unit time compared with the output level of at least one control signal of the pixel circuit 10 in the (n + 1)-th row in the same column.

[0133] As Figure 3F shown, different from the driving process of the above embodiments: the second reset control signal terminal GR1(n) and the first control signal terminal GR2(n) of the pixel circuit 10 in the n-th row share a shift register with those of the pixel circuit 10 in the (n + 1)-th row in the same column. Then, the output levels of the first reset control signal terminal GI(n), the second control signal terminal EM2(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the n-th row have a displacement of at least one unit time compared with the output levels of the first reset control signal terminal GI(n), the second control signal terminal EM2(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the (n + 1)-th row in the same column. That is, the output levels of the control signals in the pixel circuit 10 in the (n + 1)-th row are delayed by at least one unit time compared with the output levels of the corresponding control signal terminals in the pixel circuit 10 in the n-th row. The displacement of at least one unit time can be 1H as in Figure 3F . In this way, the output level of the control signal of the next row in adjacent rows (adjacent rows can also be k rows apart) is delayed by 1H compared with the output level of the control signal of the previous row, which can ensure the output stability of the control signal and thus improve the driving stability of the pixel circuit 10.

[0134] Continue to refer to Figure 3F, in this embodiment, the output level of the second reset control signal connected to the second reset circuit 109 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107; and / or the output level of the first control signal connected to the first control circuit 103 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107, and the output level of the first control signal connected to the first control circuit 103 has a shift of at least one unit time relative to the output level of the second control signal connected to the second control circuit 106. Exemplarily, the falling edge of the waveform of GR1(n) is at least 1H later than the falling edge of the waveform of EM1(n) (1H is the time for writing the signal of one row of pixels, that is, the time when the third transistor T3 is turned on). This can ensure that the falling edge of the waveform of GR1(n) is not later than the waveform of EM1(n + 1). Because during the high-level period of EM1(n + 1), the fifth transistor T5 is turned on, and the Vth of the fourth transistor T4 is gradually compensated, and the voltage of the second node N2 is constantly changing. Although it will finally tend to be stable, if the turn-off time of the second transistor T2 is earlier than that of the fifth transistor T5, it will cause a change in the third node N3, so that before the data write signal of the data write signal terminal Vdata is written, the second node N2 cannot be completely maintained at a known constant voltage (taking Vref in the figure as an example, but not limited to this), which will cause inaccurate signal writing. The falling edge of the GR2(n) waveform is at least 1H later than that of GW(n). Only in this way can it be ensured that when the signal of the (n + 1)-th row of pixels is written, the first transistor T1 is in the on state, and the first node N1 is connected to a stable level (such as Vref). And the falling edge of the GR2(n) waveform is at least 1H later than the falling edge of the waveform of EM1(n) during the compensation stage. Only in this way can it be ensured that after the first transistor T1 of the (n + 1)-th row of pixels is turned off, the fifth transistor T5 is also in the off state, so that the Vth compensation of the driving transistor ends.

[0135] Figures 3G - 3H FIG. shows another exemplary schematic diagram of a shift register shared by pixel circuits 10 in the same column of N rows and the driving timing provided by the present application.

[0136] As Figure 3G shown, on the basis of the above embodiment, the second reset control signal terminal GR1(n) and the second control signal terminal EM2(n) of the pixel circuit 10 in the n-th row and m-th column are electrically connected to the same shift register as those of the pixel circuit 10 in the (n + 1)-th row and m-th column, that is, the second reset control signal terminal GR1(n) and the second control signal terminal EM2(n) of the pixel circuit 10 in the n-th row and m-th column share a GOA circuit with those of the pixel circuit 10 in the (n + 1)-th row and m-th column.

[0137] In this embodiment, k is 1. The output level of at least one control signal of the pixel circuit 10 in the n-th row has a displacement of at least one unit time from the output level of at least one control signal of the pixel circuit 10 in the (n + 1)-th row in the same column.

[0138] As Figure 3H shown, different from the driving process of the above embodiment: the second reset control signal terminal GR1(n) and the second control signal terminal EM2(n) of the pixel circuit 10 in the n-th row share a shift register with the second reset control signal terminal GR1(n) and the second control signal terminal EM2(n) of the pixel circuit 10 in the (n + 1)-th row in the same column. Then, the output levels of the first reset control signal terminal GI(n), the first control signal terminal GR2(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the n-th row have a displacement of at least one unit time compared to the output levels of the first reset control signal terminal GI(n), the first control signal terminal GR2(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the (n + 1)-th row in the same column. That is, the output levels of the control signals in the pixel circuit 10 in the (n + 1)-th row are later than the output levels of the corresponding control signal terminals in the pixel circuit 10 in the n-th row by at least one unit time. The displacement of at least one unit time can be, for example, Figure 3H 1H in

[0139] Continuing to refer to Figure 3H, the output level of the second reset control signal connected to the second reset circuit 109 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107; the output level of the second control signal connected to the second control circuit 106 has a shift of at least one unit time relative to the output level of the first reset control signal connected to the first reset circuit 108. Exemplarily, the falling edge time of the waveform of GR1(n) is at least 1H later than the falling edge time of the waveform of EM1(n) (1H is the time for writing the signal of one row of pixels, that is, the time when the third transistor T3 is turned on). This can ensure that the falling edge time of the waveform of GR1(n) is not later than the waveform of EM1(n + 1). Because during the high-level period of EM1(n + 1), the fifth transistor T5 is turned on, and the Vth of the fourth transistor T4 is gradually compensated. The voltage of the second node N2 is constantly changing. Although it will finally tend to be stable, if the turn-off time of the second transistor T2 is earlier than that of the fifth transistor T5, it will cause a change in the third node N3, resulting in the situation that before the data write signal of the data write signal terminal Vdata is written, the second node N2 cannot be completely maintained at a known constant voltage (taking Vref in the figure as an example, but not limited to this), which will cause inaccurate signal writing. The rising edge time of the waveform of EM2(n) from low level to high level is at least one 1H later than the falling edge time of the waveform of GI(n), so as to ensure that the sixth transistor T6 is in the off state when the signal of the (n + 1)-th row is written.

[0140] Figures 3I - 3J FIG. shows another exemplary schematic diagram of a shift register shared by pixel circuits 10 in the same column of N rows and the driving timing provided by the present application.

[0141] As Figure 3I shown, on the basis of the above embodiment, the second reset control signal terminal GR1(n) and the third control signal terminal EM1(n) of the pixel circuit 10 in the n-th row and m-th column are electrically connected to the same shift register as those of the pixel circuit 10 in the (n + 1)-th row and m-th column. That is, the second reset control signal terminal GR1(n) and the third control signal terminal EM1(n) of the pixel circuit 10 in the n-th row and m-th column share a GOA circuit with those of the pixel circuit 10 in the (n + 1)-th row and m-th column.

[0142] In this embodiment, k is 1, and the output levels of the at least one control signal of the pixel circuit 10 in the n-th row have a displacement of at least one unit time from the output levels of the at least one control signal of the pixel circuit 10 in the (n + 1)-th row located in the same column.

[0143] As Figure 3JAs shown, different from the driving process of the above embodiments: the second reset control signal terminal GR1(n) and the third control signal terminal EM1(n) of the pixel circuit 10 in the n-th row share a shift register with the second reset control signal terminal GR1(n) and the third control signal terminal EM1(n) of the pixel circuit 10 in the (n + 1)-th row in the same column. Then, the output levels of the first reset control signal terminal GI(n), the first control signal terminal GR2(n), the second control signal terminal EM2(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the n-th row have a displacement of at least one unit time compared to the output levels of the first reset control signal terminal GI(n), the first control signal terminal GR2(n), the second control signal terminal EM2(n), and / or the fourth control signal terminal GW(n) in the pixel circuit 10 in the (n + 1)-th row in the same column. That is, the output levels of the control signals in the pixel circuit 10 in the (n + 1)-th row are later than the output levels of the corresponding control signal terminals in the pixel circuit 10 in the n-th row by at least one unit time. The displacement of at least one unit time can be, for example, Figure 3J 1H in

[0144] Continue to refer to Figure 3J, the output level of the second reset control signal connected to the second reset circuit 109 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107; when k is 1, the output level of the data write control signal connected to the data write circuit 102 of the pixel circuit 10 in the nth row has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107 of the pixel circuit 10 in the (n + 1)th row in the same column. Exemplarily, the falling edge of the waveform of GR1(n) is at least 1H later than the falling edge of the waveform of EM1(n) (1H is the time for writing signals of one row of pixels, that is, the time when the third transistor T3 is turned on). In this way, it can be ensured that the falling edge of the waveform of GR1(n) is not later than the waveform of EM1(n + 1). Because during the high-level period of EM1(n + 1), the fifth transistor T5 is turned on, and the Vth of the fourth transistor T4 is gradually compensated, and the voltage of the second node N2 is constantly changing. Although it will finally tend to be stable, if the second transistor T2 is turned off earlier than the fifth transistor T5, it will cause a change in the third node N3, so that before the data write signal of the data write signal terminal Vdata is written, the second node N2 cannot be completely maintained as a known constant voltage (taking Vref in the figure as an example, but not limited to this), which will cause inaccurate signal writing. After the waveform of GW(n + 1) drops, the waveform of EM1 becomes high, and the falling edge of the waveform of GR1(n) of the second transistor T2 is at least 1H later than the falling edge of the waveform of EM1(n). In this way, it can be ensured that the second signal terminal ELVDD is applied to the first end of the driving circuit 101 to write the threshold voltage of the driving circuit 101 to the second end of the driving circuit 101.

[0145] Figures 3K - 3L FIG. shows another exemplary schematic diagram of a shift register shared by pixel circuits 10 in the same column of N rows and a driving timing in the present application.

[0146] As Figure 3K shown, on the basis of the above embodiment, the first control signal terminal GR2(n) and the third control signal terminal EM1(n) of the pixel circuit 10 in the nth row and mth column are electrically connected to the same shift register as those of the pixel circuit 10 in the (n + 1)th row and mth column, that is, the first control signal terminal GR2(n) and the third control signal terminal EM1(n) of the pixel circuit 10 in the nth row and mth column share a GOA circuit.

[0147] In this embodiment, when k is 1, the output levels of the at least one control signal of the pixel circuit 10 in the nth row have a displacement of at least one unit time from the output levels of the at least one control signal of the pixel circuit 10 in the (n + 1)th row in the same column.

[0148] As Figure 3L shown, different from the driving process of the above embodiment: the first control signal terminal GR2(n) and the third control signal terminal EM1(n) of the pixel circuit 10 in the nth row share a shift register with the first control signal terminal GR2(n) and the third control signal terminal EM1(n) of the pixel circuit 10 in the (n + 1)th row in the same column. Then, the output levels of the first reset control signal terminal GI(n), the second reset control signal terminal GR1(n), the second control signal terminal EM2(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the nth row have a displacement of up to one unit time compared to the output levels of the first reset control signal terminal GI(n), the second reset control signal terminal GR1(n), the second control signal terminal EM2(n), and / or the fourth control signal terminal GW(n) in the pixel circuit 10 in the (n + 1)th row in the same column. That is, the output levels of the control signals in the pixel circuit 10 in the (n + 1)th row are later than the output levels of the corresponding control signal terminals in the pixel circuit 10 in the nth row by at least one unit time. The displacement of at least one unit time can be, for example Figure 3L 1H in

[0149] Continue to refer to Figure 3L, the output level of the first control signal received by the first control circuit 103 and the output level of the third control signal received by the third control circuit 107 have a shift of at least one unit time; the output level of the first control signal received by the first control circuit 103 and the output level of the second control signal received by the second control circuit 106 have a shift of at least one unit time; when k is 1, the output level of the data write signal received by the data write circuit 102 in the (n + 1)-th row has a shift of at least one unit time relative to the output level of the third control signal received by the third control circuit 107 of the pixel circuit 10 in the n-th row in the same column. Exemplarily, on the basis that the first control signal terminal GR2(n) of the pixel circuit 10 in the n-th row and the first control signal terminal GR2(n) of the pixel circuit 10 in the (n + 1)-th row in the same column share a shift register, it is required that the falling edge of the GR2(n) waveform is at least 1H later than that of the GW(n) waveform, so as to ensure that when the signal of the pixel in the (n + 1)-th row is written, the first transistor T1 is in the on state and the level connected to the first node N1 is stable (such as Vref). And the falling edge of the GR2(n) waveform is at least 1H later than the falling edge of the waveform of EM1(n) in the compensation stage, so as to ensure that after the first transistor T1 of the pixel in the (n + 1)-th row is turned off, the fifth transistor T5 is also in the off state, so that the Vth compensation of the driving transistor ends. After the waveform of GW(n + 1) falls, the waveform of EM1 becomes high, and the falling edge of the waveform of GR1(n) of the second transistor T2 is at least 1H later than the falling edge of the waveform of EM1(n). In this way, it can be ensured that the second signal terminal ELVDD is applied to the first end of the driving circuit 101 to write the threshold voltage of the driving circuit 101 to the second end of the driving circuit 101.

[0150] The above-mentioned first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6 and seventh transistor T7 all adopt N-type transistors. The charging and discharging speeds of N-type transistors are relatively fast, which helps to improve the working efficiency and response speed of the circuit and can ensure the driving speed of the driving circuit 101.

[0151] Figure 4A The structural schematic diagram of another exemplary pixel circuit 10 provided by the present application is shown.

[0152] As Figure 4AAs shown, what is different from the above embodiment in this embodiment is that the first reset circuit 108 is electrically connected to the first reset signal terminal Vint, the first reset control signal terminal GI(n), and the second node N2 respectively, and is used to apply the first reset voltage connected to the first reset signal terminal Vint to the second node N2 under the control of the first reset control signal connected to the first reset control signal terminal GI(n).

[0153] Exemplarily, the first reset circuit 108 includes a control terminal, a first pole, and a second pole. The control terminal of the first reset circuit 108 is electrically connected to the first reset control signal terminal GI(n), the first pole of the first reset circuit 108 is electrically connected to the first reset signal terminal Vint, and the second pole of the first reset circuit 108 is electrically connected to the second node N2. That is, the first reset circuit 108 is used to apply the first reset voltage connected to the first pole of the first reset circuit 108 to the second node N2 under the control of the first reset control signal connected to the control terminal.

[0154] Figure 4B Fig. shows a schematic diagram of another exemplary pixel circuit 10 provided by the present application.

[0155] As Figure 4B shown, the first reset circuit 108 includes a seventh transistor T7. The control electrode of the seventh transistor T7 is electrically connected to the first reset control signal terminal GI(n) for receiving the first reset control signal. The first pole of the seventh transistor T7 is electrically connected to the first reset signal terminal Vint for receiving the first reset voltage. The second pole of the first transistor T1 is electrically connected to the second node N2.

[0156] Exemplarily, the GOA circuit in the gate driving circuit 11 for outputting the first reset signal writes the first reset control signal to the control terminal of the seventh transistor T7. The seventh transistor T7 writes the first reset voltage to the second node N2 under the control of the first reset signal to reset the second node N2.

[0157] Figure 4C Fig. shows the Figure 4B driving timing schematic diagram of the exemplary pixel circuit 10 provided by the present application.

[0158] As Figure 4CAs shown, the specific driving process is as follows: In the initialization (or reset) stage: The control signals of the second control signal terminal EM2(n), the second reset control signal terminal GR1(n), the first control signal terminal GR2(n), and the first reset control signal terminal GI(n) are all high levels, and the sixth transistor T6, the second transistor T2, the first transistor T1, and the bottom transistor are all turned on. Among them, the seventh transistor T7 is turned on, and the first reset signal of the first reset signal terminal VintVinit is written into the second node N2 to initialize the potential of the second node N2; the first transistor T1 and the second transistor T2 are turned on, the first signal is written into the first node N1, and the second reset signal is written into the third node N3, thereby initializing the potentials of the first node N1 and the third node N3. In this way, the initialization of the pixel circuit 10 is achieved, that is, reset, namely: the potential of each key node in the pixel circuit 10 is initialized (or reset) to the initial state.

[0159] In the compensation stage: The control signals of the third control signal terminal EM1(n), the second reset control signal, the first control signal, and the first reset control signal are all high levels, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are all turned on. The states of the first transistor T1, the second transistor T2, and the seventh transistor T7 remain unchanged, and the anode potential of the light-emitting element 110 (OLED), the potentials of the first node N1 and the third node N3 remain unchanged. At this time, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, so that the first end of the driving transistor (i.e., the fourth transistor T4) is set to the second signal of the second signal terminal ELVDD, thereby writing the threshold voltage of the driving transistor into the second node N2 to complete the compensation of the threshold voltage of the driving transistor (the fourth transistor T4).

[0160] In the signal writing stage: The control signals of the fourth signal control terminal, the first control signal terminal GR2(n), and the first reset control signal terminal GI(n) are all high levels, and the first transistor T1, the third transistor T3, and the seventh transistor T7 are all turned on. The states of the first transistor T1 and the seventh transistor T7 remain unchanged, and the anode potential of the light-emitting element 110 (OLED) and the potential of the first node N1 remain unchanged. The third transistor T3 is turned on, and the data signal of the data signal terminal VdataVdata is written into the third node N3, and then the potential of the second node N2 jumps through the second storage capacitor C2, thereby writing the data signal of the data signal terminal VdataVdata into the second node N2.

[0161] In the light-emitting stage: The control signals of the third control signal terminal EM1(n) and the second control signal terminal EM2(n) are both at high level, controlling the fifth transistor T5 and the sixth transistor T6 to turn on, so that the driving transistor (the fourth transistor T4) generates a current for driving the light-emitting device. Since the threshold voltage of the driving transistor has been compensated and the data voltage has been written, the generated driving current corresponds to the gray level of the pixel (not affected by the threshold voltage anymore), and the light emission is completed.

[0162] Figure 5A FIG. shows a schematic diagram of another exemplary pixel circuit 10 provided by the present application.

[0163] As Figure 5A shown, different from the above embodiment: The first control signal terminal GR2(n) of the first control circuit 103 and the second control signal terminal EM2(n) of the second control circuit 106 receive the output signals of the same shift register, wherein the conduction levels of the first control circuit 103 and the second control circuit 106 are different. That is, it can be understood that when the first control circuit 103 is turned on by a high level, the second control circuit 106 is turned on by a low level. On the contrary, when the first control circuit 103 is turned on by a low level, the second control circuit 106 is turned on by a high level.

[0164] Optionally, the first control circuit 103 includes a first transistor T1, and the second control circuit 106 includes a sixth transistor T6, and the polarities of the first transistor T1 and the sixth transistor T6 are different.

[0165] Exemplarily, the different polarities may refer to different types of the first transistor T1 and the sixth transistor T6. For example, when the first transistor T1 is an N transistor, the sixth transistor T6 is an N-type transistor. When the first transistor T1 is an N-type transistor, the sixth transistor T6 is a P-type transistor.

[0166] In this embodiment, the above-mentioned first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5 and seventh transistor T7 all adopt N-type transistors, and the sixth transistor T6 adopts a P-type transistor. This helps to improve the working efficiency and response speed of the circuit and can ensure the driving speed of the driving circuit 101.

[0167] Figure 5B FIG. shows Figure 5A the driving timing diagram of the exemplary pixel circuit 10 in

[0168] As Figure 5BAs shown, in the initialization stage: Initializing the upper half: The signals of the second reset control signal terminal GR1(n) and the first reset control signal terminal GI(n) are both at high level. The seventh transistor T7 is turned on to reset the second node N2, and the voltage of the second node N2 is Vint. The sixth transistor T6 remains in the previous on state. The seventh transistor T7 simultaneously resets the anode of the light-emitting device OLED, and the anode voltage of the light-emitting device is Vint. The second transistor T2 is turned on to reset the third node N3. The first transistor T1, the third transistor T3, and the fifth transistor T5 are in the off state.

[0169] Initializing the lower half: The signals of the third control signal terminal EM1(n), the second reset control signal terminal GR1(n), and the first reset control signal terminal GI(n) are all at high level. The first transistor T1, the third transistor T3, and the seventh transistor T7 are turned on. The first transistor T1 resets the first node N1. The second transistor T2, the fifth transistor T5, and the sixth transistor T6 are in the off state.

[0170] In the compensation stage: The third control signal terminal EM1(n), the second control signal terminal EM2(n), and the second reset control signal terminal GR1(n) are all at high level. During this period, the first transistor T1 continues to be in the on state. The second transistor T2 / the sixth transistor T6 / the seventh transistor T7 remain in the off state. After the fifth transistor T5 is turned on, it charges the second node N2, and the voltage of the second node N2 gradually increases until it reaches Vref - Vth (ideally). At this time, the fourth transistor T4 is turned off, completing the compensation for the threshold voltage of the fourth transistor T4. The threshold voltage of the fourth transistor T4 is stored across the first storage capacitor C1. During the threshold voltage compensation period, Vgd of the fourth transistor T4 = Vref - ELVDD during the threshold voltage compensation period needs to satisfy < Vth, so that the drain of the fourth transistor T4 is in the pinch-off region.

[0171] In the signal writing stage: EM2(n) and GR1(n) are both at high level. During this period, T3, T5, T6, and T7 are turned off, T1 remains in the on state, and T2 is turned on. The signal voltage is directly written to the N3 node. Due to capacitive voltage division, the voltage of the N2 node becomes Vref - Vth + C2×(Vdata - Vref) / (C1 + C2) ideally (without considering the coupling voltage loss). Without considering the coupling voltage loss, N1 is at Vref at this time.

[0172] In the light-emitting stage: EM1(n) is at a high level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the rest of the transistors TFT are turned off. The voltage of the second node N2 gradually becomes Voled (i.e., the anode voltage when the OLED emits light stably. Ideally, the second node N2 and the third node N3 become the same voltage after the sixth transistor T6 is turned on). The first node N1 (in a floating state), due to the coupling of the first storage capacitor C1, has the same voltage change as the second node N2, changing from Vref to Voled + Vth - C2*(Vdata - Vref) / (C1 + C2).

[0173] The drive current Id can be expressed by the equation: Id = u×Cox×W / 2L×(Vgs - Vth)2 = u×Cox×W / 2L×(Voled + Vth - C2*(Vdata - Vref) / (C1 + C2) - Voled - Vth)2 = u×Cox×W / 2L×(C1*(Vdata - Vref) / (C1 + C2))2;

[0174] Therefore: Id = k(Vref - Vdata)2;

[0175] In the above equation, 'μ' and 'Cox' can be constants, 'W' can be the channel width of the fourth transistor T4, 'L' can be the channel length of the fourth transistor T4, and 'Vgs' can refer to the differential voltage between the gate and source of the fourth transistor T4.

[0176] The drive current Id flowing through the light-emitting device OLED during the emission period can be independent of the threshold voltage (Vth) of the fourth transistor T4, and the brightness of the image output from the display panel 1 in the DP can be uniformly maintained, regardless of the characteristics (Vth) of the fourth transistor T4.

[0177] During the above driving process, the voltage source connected to the first transistor T1 can be ELVDD. The voltage source connected to the second transistor T2 is not limited to Vref. It can be an additionally set voltage source Vref or any stable DC voltage source, such as ELVSS / VINT / ELVDD. When in the low-frequency holding frame (1 - 119 Hz (relative to 240 Hz) or 1 - 59 Hz (relative to 120, 240, 360 Hz)), the cathode can be reset at a high frequency (120 Hz or 60 Hz) to reduce the occurrence of flicker. The seventh transistor T7 is turned on, and at least one of the fifth transistor T5 and the sixth transistor T6, i.e., the TFT, is turned off, and the rest of the TFTs are all turned off. A holding frame means that the signal is not written into the frame. The TFT can be an LTPS TFT, a metal oxide TFT, a PMOS, or an NMOS. When in the holding frame, the fifth transistor T5 is turned off, the sixth transistor T6 remains on, and the seventh transistor T7 is turned on to reset the anode to prevent flicker.

[0178] Figure 6A FIG. shows a schematic diagram of another exemplary pixel circuit 10 provided by the present application.

[0179] As Figure 6A shown, what is different from the embodiment in Figure 3E is that the first control signal terminal GR2(n) of the first control circuit 103 and the second control signal terminal EM2(n) of the second control circuit 106 receive the output signal of the same shift register, and / or, the fifth control signal terminal of the first control circuit 103 (such as Figure 6A the fifth control signal terminal GW(n) connected to the control electrode of the ninth transistor in

[0180] and the data write control signal terminal in the data write circuit 102 receive the output signal of the same shift register. Figure 6A Optionally, as shown in

[0181] Figure 6B in Figure 6A the first control circuit 103 includes an eighth transistor and a ninth transistor. The control terminal of the eighth transistor is electrically connected to the first control signal terminal GR2(n), the control terminal of the ninth transistor is electrically connected to the fifth control signal terminal, the first poles of the eighth transistor and the ninth transistor are both electrically connected to the first signal terminal Vref, and the second poles of the eighth transistor and the ninth transistor are both electrically connected to the first node N1.

[0182] As Figure 6BIn the above embodiment, on the basis of the above embodiment, the first control signal terminal GR2(n) and the second reset control signal terminal GR1(n) of the pixel circuit 10 in the n-th row and m-th column are electrically connected to the same shift register as those of the pixel circuit 10 in the (n + 1)-th row and m-th column. That is, the first control signal terminal GR2(n) and the second reset control signal terminal GR1(n) of the pixel circuit 10 in the n-th row and m-th column share a GOA circuit with those of the pixel circuit 10 in the (n + 1)-th row and m-th column.

[0183] In this embodiment, k is 1, and the output level of at least one control signal of the pixel circuit 10 in the n-th row has a displacement of at least one unit time from the output level of at least one control signal of the pixel circuit 10 in the (n + 1)-th row in the same column.

[0184] As Figure 6B shown, different from the driving process of the above embodiment: the first control signal terminal GR2(n) and the second reset control signal terminal GR1(n) of the pixel circuit 10 in the n-th row share a shift register with the first control signal terminal GR2(n) and the second reset control signal terminal GR1(n) of the pixel circuit 10 in the (n + 1)-th row in the same column. Then, the output levels of the first reset control signal terminal GI(n), the second control signal terminal EM2(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the n-th row have a displacement of at least one unit time compared with the output levels of the first reset control signal terminal GI(n), the second control signal terminal EM2(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the (n + 1)-th row in the same column. That is, the output levels of the control signals in the pixel circuit 10 in the (n + 1)-th row are delayed by at least one unit time compared with the output levels of the corresponding control signal terminals in the pixel circuit 10 in the n-th row. The displacement of at least one unit time can be 1H as Figure 6B shown. In this way, the output levels of the control signals in the next row of adjacent rows (the adjacent rows can also be k rows apart) are delayed by 1H compared with the output levels of the control signals in the previous row, which can ensure the output stability of the control signals and thus improve the driving stability of the pixel circuit 10.

[0185] Continue to refer to Figure 6B, in this embodiment, the output level of the second reset control signal connected to the second reset circuit 109 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107; and / or the output level of the first control signal connected to the first control circuit 103 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107, and the output level of the first control signal connected to the first control circuit 103 has a shift of at least one unit time relative to the output level of the second control signal connected to the second control circuit 106. Exemplarily, the falling edge of the waveform of GR1(n) is at least 1H later than the falling edge of the waveform of EM1(n) (1H is the time for writing the signal of one row of pixels, that is, the time when the third transistor T3 is turned on). This can ensure that the falling edge of the waveform of GR1(n) is not later than the waveform of EM1(n + 1). Because during the high-level period of EM1(n + 1), the fifth transistor T5 is turned on, and the Vth of the fourth transistor T4 is gradually compensated, and the voltage of the second node N2 is constantly changing. Although it will finally tend to be stable, if the turning-off time of the second transistor T2 is earlier than that of the fifth transistor T5, it will cause a change in the third node N3, so that before the data write signal of the data write signal terminal Vdata is written, the second node N2 cannot be completely maintained at a known constant voltage (taking Vref in the figure as an example, but not limited to this), which will cause inaccurate signal writing. The falling edge of the waveform of GR2(n) is at least 1H later than that of GW(n). Only in this way can it be ensured that when the signal of the (n + 1)-th row of pixels is written, the first transistor T1 is in the on state, and the first node N1 is connected to a stable level (such as Vref). And the falling edge of the waveform of GR2(n) is at least 1H later than the falling edge of the waveform of EM1(n) during the compensation stage. Only in this way can it be ensured that after the first transistor T1 of the (n + 1)-th row of pixels is turned off, the fifth transistor T5 is also in the off state, so that the Vth compensation of the driving transistor ends.

[0186] Figure 6C FIG. 10 shows a schematic diagram of another exemplary pixel circuit 10 provided by the present application.

[0187] As Figure 6C shown, what is different from the embodiment in Figure 6A in this embodiment is that as Figure 6C in Figure 6ABased on the embodiments, the first control signal terminal GR2(n), the second control signal terminal EM2(n), and the second reset control signal terminal GR1(n) of the pixel circuit 10 in the n-th row and m-th column are electrically connected to the same shift register as those of the pixel circuit 10 in the (n + 1)-th row and m-th column. That is, the first control signal terminal GR2(n), the second control signal terminal EM2(n), and the second reset control signal terminal GR1(n) of the pixel circuit 10 in the n-th row and m-th column share a GOA circuit with those of the pixel circuit 10 in the (n + 1)-th row and m-th column.

[0188] Figure 6D As shown in Figure 6C the driving timing diagram of the exemplary pixel circuit 10 in

[0189] In this embodiment, k is 1, and the output level of at least one control signal of the pixel circuit 10 in the n-th row has a displacement of at least one unit time from the output level of at least one control signal of the pixel circuit 10 in the (n + 1)-th row in the same column.

[0190] As Figure 6D shown, different from the driving process of the above embodiments: the first control signal terminal GR2(n), the second control signal terminal EM2(n), and the second reset control signal terminal GR1(n) of the pixel circuit 10 in the n-th row share a shift register with the first control signal terminal GR2(n), the second control signal terminal EM2(n), and the second reset control signal terminal GR1(n) of the pixel circuit 10 in the (n + 1)-th row in the same column. Then, the output levels of the first reset control signal terminal GI(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the n-th row have a displacement of at least one unit time compared to the output levels of the first reset control signal terminal GI(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the (n + 1)-th row in the same column. That is, the output levels of the control signals in the pixel circuit 10 in the (n + 1)-th row are delayed by at least one unit time compared to the output levels of the corresponding control signal terminals in the pixel circuit 10 in the n-th row. The displacement of at least one unit time can be, for example, Figure 6D 1H in

[0191] Continuing to refer to Figure 6D, in this embodiment, the output level of the second reset control signal connected to the second reset circuit 109 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107; and / or the output level of the first control signal connected to the first control circuit 103 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107; the output level of the first control signal connected to the first control circuit 103 has a shift of at least one unit time relative to the output level of the second control signal connected to the second control circuit 106. The output level of the second control signal connected to the second control circuit 106 has a shift of at least one unit time relative to the output level of the first reset control signal connected to the first reset circuit 108. Exemplarily, the falling edge of the waveform of GR1(n) is at least 1H later than the falling edge of the waveform of EM1(n) (1H is the time for writing the signal of one row of pixels, that is, the time when the third transistor T3 is turned on). This can ensure that the falling edge of the waveform of GR1(n) is not later than the waveform of EM1(n + 1). Because during the high-level period of EM1(n + 1), the fifth transistor T5 is turned on, and the Vth of the fourth transistor T4 is gradually compensated. The voltage of the second node N2 is constantly changing. Although it will finally tend to be stable, if the turn-off time of the second transistor T2 is earlier than that of the fifth transistor T5, it will cause a change in the third node N3, so that before the data write signal of the data write signal terminal Vdata is written, the second node N2 cannot be completely maintained at a known constant voltage (taking Vref in the figure as an example, but not limited to this), which will cause inaccurate signal writing. The falling edge of the waveform of GR2(n) is at least 1H later than that of GW(n). Only in this way can it be ensured that when the signal of the (n + 1)-th row of pixels is written, the first transistor T1 is in the on state, and the first node N1 is connected to a stable level (such as Vref). And the falling edge of the waveform of GR2(n) is at least 1H later than the falling edge of the waveform of EM1(n) during the compensation stage. Only in this way can it be ensured that after the first transistor T1 of the (n + 1)-th row of pixels is turned off, the fifth transistor T5 is also in the off state, so that the Vth compensation of the driving transistor ends. The moment when the waveform of EM2(n) changes from low level to high level is at least 1H later than the falling edge of the waveform of GI(n). Only in this way can it be ensured that the sixth transistor T6 is in the off state when the (n + 1)-th row of signals is written.

[0192] Figure 6E FIG. 10 shows a schematic diagram of another exemplary pixel circuit 10 provided by the present application.

[0193] As Figure 6E shown, what is different from the embodiment in Figure 6A in this embodiment is that, as Figure 6E in Figure 6ABased on the medium embodiment, the first control signal terminal GR2(n), the second control signal terminal EM2(n), and the second reset control signal terminal GR1(n) of the pixel circuit 10 at the n-th row and m-th column are electrically connected to the same shift register as those of the pixel circuit 10 at the (n + 1)-th row and m-th column. That is, the first control signal terminal GR2(n), the second control signal terminal EM2(n), and the second reset control signal terminal GR1(n) of the pixel circuit 10 at the n-th row and m-th column share a GOA circuit with those of the pixel circuit 10 at the (n + 1)-th row and m-th column.

[0194] Figure 6F is shown in Figure 6E the driving timing schematic diagram of the exemplary pixel circuit 10 in

[0195] In this embodiment, k is 1, and the output level of at least one control signal of the pixel circuit 10 at the n-th row has a displacement of at least one unit time from the output level of at least one control signal of the pixel circuit 10 at the (n + 1)-th row in the same column.

[0196] As Figure 6F shown, different from the driving process of the above embodiment: the first control signal terminal GR2(n), the second control signal terminal EM2(n), and the second reset control signal terminal GR1(n) of the pixel circuit 10 at the n-th row share a shift register with the first control signal terminal GR2(n), the second control signal terminal EM2(n), and the second reset control signal terminal GR1(n) of the pixel circuit 10 at the (n + 1)-th row in the same column. Then, the output levels of the first reset control signal terminal GI(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 at the n-th row have a displacement of at least one unit time compared to the output levels of the first reset control signal terminal GI(n), the third control signal terminal EM1(n), and / or the fourth control signal terminal GW(n) of the pixel circuit 10 at the (n + 1)-th row in the same column. That is, the output levels of the control signals in the pixel circuit 10 at the (n + 1)-th row are later than the output levels of the corresponding control signal terminals in the pixel circuit 10 at the n-th row by at least one unit time. The displacement of at least one unit time can be, for example, Figure 6F 1H in

[0197] Continuing to refer to Figure 6F, in this embodiment, the output level of the second reset control signal connected to the second reset circuit 109 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107; and / or, the output level of the first control signal connected to the first control circuit 103 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107; k is 1, and the output level of the data write control signal connected to the data write circuit 102 of the pixel circuit 10 in the nth row has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107 of the pixel circuit 10 in the (n + 1)th row in the same column. The output level of the second control signal connected to the second control circuit 106 has a shift of at least one unit time relative to the output level of the first reset control signal connected to the first reset circuit 108. Exemplarily, the falling edge of the waveform of GR1(n) is at least 1H later than the falling edge of the waveform of EM1(n) (1H is the time for writing the signal of one row of pixels, that is, the time when the third transistor T3 is turned on). This can ensure that the falling edge of the waveform of GR1(n) is not later than the waveform of EM1(n + 1). Because during the high-level period of EM1(n + 1), the fifth transistor T5 is turned on, and the Vth of the fourth transistor T4 is gradually compensated, and the voltage of the second node N2 is constantly changing. Although it will finally tend to be stable, if the second transistor T2 is turned off earlier than the fifth transistor T5, it will cause a change in the third node N3, so that before the data write signal of the data write signal terminal Vdata is written, the second node N2 cannot be completely maintained as a known constant voltage (taking Vref in the figure as an example, but not limited to this), which will cause inaccurate signal writing. The falling edge of the waveform of GR2(n) is at least 1H later than the waveform of GW(n). Only in this way can it be ensured that when the signal of the (n + 1)th row of pixels is written, the first transistor T1 is in the on state, and the first node N1 is connected to a stable level (such as Vref). And the falling edge of the waveform of GR2(n) is at least 1H later than the falling edge of the waveform of EM1(n) during the compensation stage. Only in this way can it be ensured that after the first transistor T1 of the (n + 1)th row of pixels is turned off, the fifth transistor T5 is also in the off state, so that the Vth compensation of the driving transistor ends. After the waveform of GW(n + 1) falls, the waveform of EM1 becomes high. The falling edge of the waveform of GR1(n) of the second transistor T2 is at least 1H later than the falling edge of the waveform of EM1(n). In this way, it can be ensured that the second signal terminal ELVDD is applied to the first end of the driving circuit 101 to write the threshold voltage of the driving circuit 101 to the second end of the driving circuit 101.

[0198] Figure 6G FIG. shows a schematic diagram of another exemplary pixel circuit 10 provided by the present application.

[0199] As Figure 6G shown, the difference between this embodiment and the Figure 6A embodiment in Figure 6G is that, on the basis of the embodiment in Figure 6A , the first control signal terminal GR2(n), the second control signal terminal EM2(n), the third control signal terminal EM1(n), and the second reset control signal terminal GR1(n) of the pixel circuit 10 in the n-th row and m-th column are electrically connected to the same shift register as those of the pixel circuit 10 in the (n + 1)-th row and m-th column. That is, the first control signal terminal GR2(n), the second control signal terminal EM2(n), the third control signal terminal EM1(n), and the second reset control signal terminal GR1(n) of the pixel circuit 10 in the n-th row and m-th column share a GOA circuit with those of the pixel circuit 10 in the (n + 1)-th row and m-th column.

[0200] Figure 6H shows Figure 6G the driving timing schematic diagram of the exemplary pixel circuit 10 in

[0201] In this embodiment, k is 1, and the output level of at least one control signal of the pixel circuit 10 in the n-th row has a displacement of at least one unit time from the output level of at least one control signal of the pixel circuit 10 in the (n + 1)-th row in the same column.

[0202] As Figure 6H shown, the difference from the driving process of the above embodiment is that: the first control signal terminal GR2(n), the second control signal terminal EM2(n), the third control signal terminal EM1(n), and the second reset control signal terminal GR1(n) of the pixel circuit 10 in the n-th row share a shift register with those of the pixel circuit 10 in the (n + 1)-th row in the same column. Then, the output level of each of the first reset control signal terminal GI(n) and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the n-th row has a displacement of at least one unit time compared with the output level of each of the first reset control signal terminal GI(n) and / or the fourth control signal terminal GW(n) of the pixel circuit 10 in the (n + 1)-th row in the same column. That is, the output level of each control signal in the pixel circuit 10 in the (n + 1)-th row is at least one unit time later than the output level of the corresponding control signal terminal in the pixel circuit 10 in the n-th row. The displacement of at least one unit time can be 1H as in Figure 6H . In this way, making the output level of the control signal in the next row of adjacent rows (the adjacent rows can also be k rows apart) be at least 1H later than the output level of the control signal in the previous row can ensure the output stability of the control signal, thereby improving the driving stability of the pixel circuit 10.

[0203] Continue to refer to Figure 6H, in this embodiment, the output level of the second reset control signal connected to the second reset circuit 109 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107; and / or, the output level of the first control signal connected to the first control circuit 103 has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107; the output level of the first control signal connected to the first control circuit 103 has a shift of at least one unit time relative to the output level of the second control signal connected to the second control circuit 106; k is 1, and the output level of the data write control signal connected to the data write circuit 102 of the pixel circuit 10 in the nth row has a shift of at least one unit time relative to the output level of the third control signal connected to the third control circuit 107 of the pixel circuit 10 in the (n + 1)th row in the same column. The output level of the second control signal connected to the second control circuit 106 has a shift of at least one unit time relative to the output level of the first reset control signal connected to the first reset circuit 108. Exemplarily, the falling edge of the waveform of GR1(n) is at least 1H later than the falling edge of the waveform of EM1(n) (1H is the time for writing the signals of one row of pixels, that is, the time when the third transistor T3 is turned on). In this way, it can be ensured that the falling edge of the waveform of GR1(n) is not later than the waveform of EM1(n + 1). Because during the high-level period of EM1(n + 1), the fifth transistor T5 is turned on, and the Vth of the fourth transistor T4 is gradually compensated, and the voltage of the second node N2 is constantly changing. Although it will finally tend to be stable, if the turning-off time of the second transistor T2 is earlier than that of the fifth transistor T5, it will cause a change in the third node N3, and when the data input signal of the data input signal terminal Vdata is written before the data input signal is written, the second node N2 cannot be completely maintained as a known constant voltage (taking Vref in the figure as an example, but not limited thereto), which will cause inaccurate signal writing. The falling edge of the waveform of GR2(n) is at least 1H later than that of GW(n). In this way, it can be ensured that when the signals of the pixels in the (n + 1)th row are written, the first transistor T1 is in the on state, and the first node N1 is connected to a stable level (such as Vref). And the falling edge of the waveform of GR2(n) is at least 1H later than the falling edge of the waveform of EM1(n) during the compensation stage. In this way, it can be ensured that after the first transistor T1 of the pixels in the (n + 1)th row is turned off, the fifth transistor T5 is also in the off state, so that the Vth compensation of the driving transistor ends. After the waveform of GW(n + 1) falls, the waveform of EM1 becomes high. The falling edge of the waveform of GR1(n) of the second transistor T2 is at least 1H later than the falling edge of the waveform of EM1(n). In this way, it can be ensured that the second signal terminal ELVDD is applied to the first end of the driving circuit 101 to write the threshold voltage of the driving circuit 101 to the second end of the driving circuit 101.The moment when the EM2(n) waveform changes from low level to high level is at least one 1H later than the falling moment of the GI(n) waveform, so as to ensure that the sixth transistor T6 is in the off state when the signal of the (n + 1)-th row is written.

[0204] Based on the same inventive concept, the present application further provides a driving method, and the driving method includes:

[0205] In the reset stage, making the output level of the first reset control signal have a shift of at least one unit time compared with the output level of the third control signal;

[0206] In the compensation stage, making the output level of the first control signal have a shift of at least one unit time compared with the output level of the fourth control signal; the output level of the first control signal has a shift of at least one unit time compared with the output level of the third control signal;

[0207] In the signal writing stage, the output level of the first reset control signal has a shift of at least one unit time compared with the output level of the first control signal; the output level of the first control signal has a shift of at least one unit time compared with the output level of the third control signal; the output level of the second control signal has a shift of at least one unit time compared with the output level of the first reset control signal.

[0208] Specifically, by using at least one control signal of the pixel circuit and the pixel circuit of the (n + k)-th row pixel circuit in the same column as the output signal of the same shift register corresponding to the control signal. That is to say, it can be understood that the control signals corresponding to the pixel circuits in the same column in rows separated by k rows (exemplarily, rows separated by k rows can be adjacent rows) adopt the output signals of the same shift register. In this way, the number of GOAs in the pixel circuit can be saved, thereby reducing the occupied border and facilitating the realization of a narrow border. And this driving method makes the output level of the first reset control signal have a shift of at least one unit time compared with the output level of the third control signal in the reset stage; in the compensation stage, making the output level of the first control signal have a shift of at least one unit time compared with the output level of the fourth control signal; the output level of the first control signal has a shift of at least one unit time compared with the output level of the third control signal; in the signal writing stage, the output level of the first reset control signal has a shift of at least one unit time compared with the output level of the first control signal; the output level of the first control signal has a shift of at least one unit time compared with the output level of the third control signal; the output level of the second control signal has a shift of at least one unit time compared with the output level of the first reset control signal; in this way, the control of the pixel circuit is made more stable and the afterimage of the product is reduced.

[0209] It should be noted that the method of the embodiment of the present application can be executed by a single device, such as a computer or a server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In this case of a distributed scenario, one of the multiple devices can only execute one or more steps of the method of the embodiment of the present application, and these multiple devices will interact with each other to complete the described method.

[0210] It should be noted that some embodiments of the present application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order from that in the above embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0211] Based on the same inventive concept, the present application also provides a display device, including the pixel circuit provided above.

[0212] Specifically, the pixel circuit is located in the nth row of the display panel. The display panel includes N rows and M columns of pixel circuits and a gate driving circuit corresponding to the N rows of pixel circuits. The gate driving circuit includes a plurality of shift registers. At least one control signal of the pixel circuit and the pixel circuit in the (n + k)th row in the same column as the pixel circuit is an output signal of the same shift register corresponding to the control signal. The at least one control signal includes a first reset control signal, a second reset control signal, a first control signal, a second control signal, a third control signal, and / or a fourth control signal. By making at least one control signal of the pixel circuit and the pixel circuit in the (n + k)th row in the same column as the pixel circuit be the output signal of the same shift register corresponding to the control signal. It can be understood that the corresponding control signals in the pixel circuits in the same column separated by k rows use the output signals of the same shift register. In this way, the number of GOAs in the pixel circuit can be saved, and thus the occupied border can be reduced, facilitating the realization of a narrow border.

[0213] The display device provided in this embodiment can be applied to any product or component with a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0214] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; within the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

[0215] In addition, for the sake of simplicity of explanation and discussion, and in order not to make the embodiments of the present application difficult to understand, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the accompanying drawings. Furthermore, the devices may be shown in block diagram form in order to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (i.e., these details should be entirely within the understanding of those skilled in the art). In cases where specific details (such as circuits) are set forth to describe exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application may be implemented without these specific details or with variations of these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0216] Although the present application has been described in connection with specific embodiments of the present application, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (such as dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0217] The embodiments of the present application are intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application shall be included within the protection scope of the present application.

Claims

1. A pixel circuit, characterized in that: include: A driving circuit, a data writing circuit, a first control circuit, a first storage circuit, a second storage circuit, a second control circuit, a third control circuit, a first reset circuit, a second reset circuit and a light emitting element; The driving circuit comprises a control end, a first end and a second end, which are electrically connected to the first node, the third control circuit and the second node respectively, and are used to control a driving current flowing through the first end and the second end for driving the light emitting element to emit light; The first reset circuit is electrically connected to the first reset signal terminal, the first reset control signal terminal and the second node or the first electrode of the light-emitting element, respectively, and is used to apply the first reset voltage connected to the first reset signal terminal to the second node or the first electrode of the light-emitting element under the control of the first reset control signal connected to the first reset control signal terminal; The second reset circuit is electrically connected to the second reset signal terminal, the third node and the second reset control signal terminal respectively, and is used to apply the second reset voltage connected to the second reset signal terminal to the third node under the control of the second reset control signal connected to the second reset control signal terminal; The first control circuit is electrically connected to the first signal terminal, the first node and the first control signal terminal respectively, and is used to apply the first signal connected to the first signal terminal to the first node under the control of the first control signal connected to the first control signal terminal; The second control circuit is electrically connected to the first electrode of the light-emitting element, the second node and the second control signal terminal respectively, and is used to connect or disconnect the first electrode of the light-emitting element with the second node under the control of the second control signal connected to the second control signal terminal; The first storage circuit is electrically connected to the first node and the second node respectively, and is used to store the potential difference between the first node and the second node; The second storage circuit is electrically connected to the second node and the third node respectively, and is used to store the potential difference between the second node and the third node; The third control circuit is electrically connected to the second signal terminal, the first terminal of the driving circuit and the third control signal terminal respectively, and is used to apply the second signal connected to the second signal terminal to the first terminal of the driving circuit under the control of the third control signal connected to the third control signal terminal so as to write the threshold voltage of the driving circuit to the second terminal of the driving circuit; The data writing circuit is electrically connected to the data signal terminal, the third node and the fourth control signal terminal respectively, and is used to write the data signal connected to the data signal terminal into the second terminal of the driving circuit through the second storage circuit under the control of the fourth control signal connected to the fourth control signal terminal; The second control circuit and the third control circuit are further used to control the driving circuit to generate the driving current under the control of the second control signal and the third control signal respectively; In which, the pixel circuit is located in the nth row of the display panel, the display panel includes N rows and M columns of pixel circuits and a gate driving circuit corresponding to the N rows of pixel circuits, the gate driving circuit includes multiple shift registers, and at least one control signal of the pixel circuit and the n+kth row of pixel circuits located in the same column as the pixel circuit is an output signal of the same shift register corresponding to the control signal, and the at least one control signal includes a first reset control signal, a second reset control signal, a first control signal, a second control signal, a third control signal and / or a fourth control signal.

2. The pixel circuit according to claim 1, characterized in that: k is 1, and the output level of the at least one control signal of the pixel circuit in the nth row and the output level of the at least one control signal of the pixel circuit in the (n+1)th row in the same column are shifted by at least one unit time.

3. The pixel circuit according to claim 1, characterized in that: A first control signal terminal of the first control circuit and a second control signal terminal of the second control circuit receive an output signal of the same shift register, wherein a conduction level of the first control circuit is different from a conduction level of the second control circuit.

4. The pixel circuit according to claim 1, characterized in that: An output level of a second reset control signal connected to the second reset circuit is shifted by at least one unit time relative to an output level of a third control signal connected to the third control circuit; and / or An output level of a first control signal connected to the first control circuit has a shift of at least one unit time relative to an output level of a third control signal connected to the third control circuit, and an output level of the first control signal connected to the first control circuit has a shift of at least one unit time relative to an output level of a second control signal connected to the second control circuit.

5. The pixel circuit according to claim 1, characterized in that: The output level of the second reset control signal connected to the second reset circuit is shifted by at least one unit time relative to the output level of the third control signal connected to the third control circuit; An output level of a second control signal connected to the second control circuit is shifted by at least one unit time relative to an output level of a first reset control signal connected to the first reset circuit.

6. The pixel circuit according to claim 1, characterized in that: An output level of the second reset control signal connected to the second reset circuit is shifted by at least one unit time relative to an output level of the third control signal connected to the third control circuit; k is 1, and the output level of the data write control signal connected to the data write circuit of the pixel circuit in the nth row is shifted by at least one unit time relative to the output level of the third control signal connected to the third control circuit of the pixel circuit in the n+1th row in the same column.

7. The pixel circuit according to claim 1, characterized in that: The output level of the first control signal connected to the first control circuit and the output level of the third control signal connected to the third control circuit have a shift of at least one unit time; the output level of the first control signal connected to the first control circuit and the output level of the second control signal connected to the second control circuit have a shift of at least one unit time; k is 1, and the output level of the data write signal connected to the data write circuit in the n+1th row is shifted by at least one unit time relative to the output level of the third control signal connected to the third control circuit of the pixel circuit in the nth row in the same column.

8. The pixel circuit according to claim 3, characterized in that: The first control circuit includes a first transistor; The control electrode of the first transistor is electrically connected to the first control signal terminal and is used to receive the first control signal, the first electrode of the first transistor is electrically connected to the first signal terminal and is used to receive the first signal, and the second electrode of the first transistor is electrically connected to the first node and is used to apply the first signal to the first node under the control of the received first control signal; and / or The first storage circuit comprises a first storage capacitor, a first electrode of the first storage capacitor is electrically connected to the first node, and a second electrode of the first storage capacitor is electrically connected to the second node; and / or The second reset circuit includes a second transistor, a control electrode of the second transistor is electrically connected to the second reset control signal terminal for receiving the second reset control signal, a first electrode of the second transistor is electrically connected to the second reset signal terminal for receiving the second reset voltage, and a second electrode of the second transistor is electrically connected to the third node; and / or The data writing circuit comprises a third transistor, a control electrode of the third transistor is electrically connected to the fourth control signal terminal for receiving the fourth control signal, a first electrode of the third transistor is electrically connected to the data signal terminal for receiving the data signal, a second electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor serves as the third node; and / or The second storage circuit comprises a second storage capacitor, a first electrode of the second storage capacitor is electrically connected to the third node, and a second electrode of the second storage capacitor is electrically connected to the second node; and / or The driving circuit comprises a fourth transistor, the control electrode of the fourth transistor being electrically connected to the first node as the control end of the driving circuit, the first electrode of the fourth transistor being electrically connected to the third control circuit as the first end of the driving circuit, and the second electrode of the fourth transistor being electrically connected to the second node as the second end of the driving circuit; and / or The third control circuit includes a fifth transistor, a control electrode of the fifth transistor is electrically connected to the third control signal terminal for receiving the third control signal, a first electrode of the fifth transistor is electrically connected to the second signal terminal for receiving the second signal, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; and / or The second control circuit includes a sixth transistor, a control electrode of the sixth transistor is electrically connected to the second control signal terminal for receiving the second control signal, a first electrode of the sixth transistor is electrically connected to the second node, and a second electrode of the sixth transistor is connected to the first electrode of the light-emitting element; and / or The first reset circuit includes a seventh transistor, a control electrode of the seventh transistor is electrically connected to the first reset control signal terminal for receiving the first reset control signal, a first electrode of the seventh transistor is electrically connected to the first reset signal terminal for receiving the first reset voltage, and a second electrode of the first transistor is electrically connected to the first electrode of the light-emitting element.

9. The pixel circuit according to claim 8, characterized in that: The first reset circuit includes a seventh transistor, a control electrode of the seventh transistor is electrically connected to the first reset control signal terminal for receiving the first reset control signal, a first electrode of the seventh transistor is electrically connected to the first reset signal terminal for receiving the first reset voltage, and a second electrode of the first transistor is electrically connected to the second node.

10. The pixel circuit according to claim 8 or 9, characterized in that: The first transistor and the sixth transistor have different polarities.

11. A driving method, applied to the pixel circuit according to any one of claims 1 to 10, characterized in that: The method comprises: In the reset phase, the output level of the first reset control signal is shifted by at least one unit time compared with the output level of the third control signal; In the compensation stage, the output level of the first control signal is shifted by at least one unit time compared with the output level of the fourth control signal; the output level of the first control signal is shifted by at least one unit time compared with the output level of the third control signal; In the signal writing stage, the output level of the first reset control signal has a shift of at least one unit time compared with the output level of the first control signal; the output level of the first control signal has a shift of at least one unit time compared with the output level of the third control signal; the output level of the second control signal has a shift of at least one unit time compared with the output level of the first reset control signal.

12. A display device, characterized in that: The method comprises the pixel circuit as claimed in any one of claims 1 to 10.

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