Method for determining input pin of driving chip and driving chip

Abstract

The invention discloses a method for determining an input pin of a driving chip and the driving chip, the driving chip receives a power supply voltage and a detection signal input by a first input / output pin, the detection signal comprises a first level signal and a logic data signal, after the power supply voltage is determined to be valid, an enable signal is switched from an invalid state to a valid state, and the first input / output pin receives the first level signal and the logic data signal; and when the enable signal is in a valid state, comparing the logic data signal with a target logic data signal, and determining the first input / output pin as an input pin according to a comparison result. Since the first input and output pin is determined as the input pin based on the power supply signal and the logic data signal, compared with determination only according to the level signal, the problems that the whole link is abnormal and data receiving cannot be completed due to the fact that the high level signal in a period of time is abnormal in the transmission process can be avoided; therefore, the accuracy and reliability of input pin determination are improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a method for determining an input pin of a driving chip and a driving chip. Background Art

[0002] In Mini-LED backlight driving, in order to reduce costs, the lamp board generally adopts a single-layer layout. To increase the flexibility of the design, the driving chip is usually designed to support the function of data I / O (input / output) interchange, that is, an input / output pin of the driving chip can be used as a data input pin or a data output pin.

[0003] In Mini-LED backlight driving, the driving chips are connected in series. When defining the transmission direction of the data signal in the serially connected driving chips, that is, when defining the input pins and output pins of the serially connected driving chips, a high-level signal with a certain duration is usually input to an input / output pin of the driving chip. If it is detected that the duration of the high-level signal input from an input / output pin of the driving chip reaches a preset duration, it is determined that this input / output pin is an input pin, and it is determined that the other input / output pin of the driving chip is an output pin. Then, a high-level signal with a certain duration input from the input pin of this driving chip is output to an input / output pin of the next-level driving chip through the output pin of this driving chip, and the input pins and output pins of the next-level driving chip are defined in the same way.

[0004] However, in the above method, if an abnormality occurs during the transmission of a high-level signal with a certain duration, the entire link will be abnormal and data reception cannot be completed. Summary of the Invention

[0005] The present invention provides a method for determining an input pin of a driving chip and a driving chip, so as to solve the problem in the prior art that when defining the input pins and output pins of serially connected driving chips, if an abnormality occurs during the transmission of a high-level signal with a certain duration, the entire link will be abnormal and data reception cannot be completed.

[0006] In a first aspect, the present application provides a method for determining an input pin of a driving chip, and the method includes:

[0007] Receiving a power supply voltage and a detection signal, where the detection signal includes a first-level signal and a logic data signal, and the detection signal is input from a first input / output pin of the driving chip;

[0008] After determining that the power supply voltage is valid, switching the state of the enable signal from an invalid state to a valid state;

[0009] When the state of the enabling signal is a valid state, compare the received logic data signal with a preset target logic data signal. If the comparison result is the same, determine that the first input / output pin is determined as the input pin of the driving chip.

[0010] In a possible implementation, after determining that the power supply voltage is valid, switching the state of the enabling signal from an invalid state to a valid state includes:

[0011] Determine that the power supply voltage is valid and determine that the first level signal lasts for a first preset duration, and switch the state of the enabling signal from the invalid state to the valid state.

[0012] In a possible implementation, the method further includes:

[0013] After determining that the power supply voltage is valid, switch the state of the input / output judgment signal from an invalid state to a valid state;

[0014] When determining that the state of the input / output judgment signal is a valid state, receive the detection signal through the first input / output pin.

[0015] In a possible implementation, determining that the first input / output pin is the input pin of the driving chip includes:

[0016] Switch the state of the input / output judgment signal from a valid state to an invalid state;

[0017] After determining that the state of the input / output judgment signal is switched from a valid state to an invalid state, determine that the first input / output pin is the input pin of the driving chip.

[0018] In a possible implementation, the method further includes:

[0019] After determining that the comparison result is different, switch the state of the reset signal from an invalid state to a valid state;

[0020] After determining that the state of the reset signal is a valid state, switch the state of the enabling signal from a valid state to an invalid state.

[0021] In a possible implementation, after determining that the power supply voltage is valid, the method further includes:

[0022] When determining that the state of the input / output judgment signal is a valid state and the duration for which the input / output judgment signal lasts is greater than or equal to a second preset duration, determine that the second input / output pin of the driving chip is the output pin of the driving chip.

[0023] In a possible implementation, after determining that the first input / output pin is an input pin of the drive chip, it further includes:

[0024] Determine a second input / output pin in the drive chip that is in an idle state as an output pin of the drive chip.

[0025] In a second aspect, the present application further provides a drive chip, including:

[0026] A power input pin for inputting a power supply voltage;

[0027] A first input / output pin for receiving a detection signal, where the detection signal includes a first level signal and a logic data signal;

[0028] An enable judgment module for receiving the power supply voltage and the detection signal, and after determining that the power supply voltage is valid, switching the state of the output enable signal from an invalid state to a valid state;

[0029] A logic judgment module for receiving the detection signal and the enable signal, and in the case where the state of the enable signal is a valid state, comparing the logic data signal with a preset target logic data signal, and if the comparison result is the same, determining that the first input / output pin is an input pin.

[0030] In a possible implementation, the enable judgment module is specifically configured to:

[0031] Determine that the power supply voltage is valid and determine that the first level signal lasts for a first preset duration, and switch the state of the enable signal from the invalid state to the valid state.

[0032] In a possible implementation, it further includes an input / output port;

[0033] The logic judgment module is further configured to switch the state of the input / output judgment signal from an invalid state to a valid state after determining that the power supply voltage is valid;

[0034] The input / output port is used to input the input / output judgment signal, and in the case where the state of the input / output judgment signal is a valid state, conduct the path between the first input / output pin and the enable judgment module, and conduct the path between the first input / output pin and the logic judgment module.

[0035] In a possible implementation, the drive chip further includes a data processing module, and the logic judgment module is specifically configured to:

[0036] In the case where the comparison result is the same, switch the state of the input / output judgment signal from a valid state to an invalid state;

[0037] The input / output port is used to set the signal transmission direction of the input / output port to be from the first input / output pin to the data processing module after determining that the state of the input / output judgment signal switches from the valid state to the invalid state.

[0038] In a possible implementation manner, the logic judgment module is specifically configured to:

[0039] After determining that the comparison result is different, switch the state of the reset signal from the invalid state to the valid state;

[0040] The enable judgment module is further configured to receive the reset signal, and switch the state of the enable signal from the valid state to the invalid state when the state of the reset signal is the valid state.

[0041] In a possible implementation manner, the driving chip further includes a second input / output pin;

[0042] The logic judgment module is further configured to determine that the second input / output pin is the output pin of the driving chip when it is determined that the power supply voltage is valid, the state of the input / output judgment signal is the valid state, and the duration for which the input / output judgment signal lasts is greater than or equal to a second preset duration.

[0043] In a possible implementation manner, the driving chip further includes a second input / output pin;

[0044] The logic judgment module is further configured to determine the second input / output pin in the idle state in the driving chip as the output pin of the driving chip after determining that the first input / output pin is an input pin.

[0045] In a possible implementation manner, the driving chip further includes a data processing module, and the logic judgment module is specifically configured to:

[0046] Set the signal transmission direction of the input / output port corresponding to the second input / output pin to be from the data processing module to the second input / output pin.

[0047] The beneficial effects of the present invention are as follows:

[0048] A method and a driving chip for determining an input pin of a driving chip provided by this application. The driving chip receives a power supply voltage and a detection signal. Among them, the detection signal includes a first-level signal and a logical data signal. The detection signal is input through a first input / output pin of the driving chip. After the driving chip determines that the power supply voltage is valid, it switches the state of the enable signal from an invalid state to a valid state. In the case where the state of the enable signal is a valid state, the received logical data signal is compared with a preset target logical data signal. If the comparison result is the same, it is determined that the first input / output pin is the input pin of the driving chip. Since the determination of the input pin of the driving chip is based on the power signal and the logical data signal, and the logical data signal is compared with the preset target logical data signal, compared with only judging according to the level signal, it can avoid the problem that the entire link goes wrong and data reception cannot be completed due to an abnormality in a high-level signal during a certain period of time in the transmission process, thereby improving the accuracy and reliability of the determination of the input pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0050] Figure 1 A schematic diagram of a series connection of driving chips provided by an embodiment of this application;

[0051] Figure 2 A schematic flow chart of a method for determining an input pin of a driving chip provided by an embodiment of this application;

[0052] Figure 3 A complete schematic flow chart of a method for determining an input pin of a driving chip provided by an embodiment of this application;

[0053] Figure 4 A schematic diagram of the structure of a driving chip provided by an embodiment of this application;

[0054] Figure 5 Another schematic diagram of the structure of a driving chip provided by an embodiment of this application;

[0055] Figure 6 Another schematic diagram of the structure of a driving chip provided by an embodiment of this application;

[0056] Figure 7 Another schematic diagram of the structure of a driving chip provided by an embodiment of this application;

[0057] Figure 8A timing diagram for determining the input pins of a driving chip provided by an embodiment of the present application;

[0058] Figure 9 Another timing diagram for determining the input pins of a driving chip provided by an embodiment of the present application;

[0059] Figure 10 A timing diagram for determining the output pins of a driving chip provided by an embodiment of the present application. Detailed implementation manners

[0060] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0061] In Mini-LED backlight driving, the same pin of a driving chip can be defined as an input pin of the driving chip, that is, a data input pin, or can be defined as an output pin of the driving chip, that is, a data output pin. As Figure 1 shown, three driving chips are connected in series, namely IC1, IC2, and IC3. Among them, Pin1 of IC1 is defined as the input pin of IC1, Pin2 of IC1 is defined as the output pin of IC1, Pin2 of IC2 is defined as the input pin of IC2, Pin1 of IC2 is defined as the output pin of IC2, Pin1 of IC3 is defined as the input pin of IC3, and Pin2 of IC3 is defined as the output pin of IC3.

[0062] A method and a driving chip for determining an input pin of a driving chip provided by an embodiment of the present application are applied to driving chips connected in series. The method includes, for any one of the driving chips connected in series, the driving chip receives a power supply voltage and a detection signal, where the detection signal includes a first level signal and a logic data signal, and the detection signal is input through a first input / output pin of the driving chip. After determining that the power supply voltage is valid, the driving chip switches the state of the enable signal from an invalid state to a valid state. When the state of the enable signal is in a valid state, the received logic data signal is compared with a preset target logic data signal. If the comparison result is the same, it is determined that the first input / output pin is the input pin of the driving chip. Since determining that the first input / output pin is the input pin of the driving chip is based on the power signal and the logic data signal, and the logic data signal is compared with the preset target logic data signal, compared with only defining according to the level signal, it can avoid the problem that the entire link fails due to an abnormality in the transmission of a high-level signal for a period of time, resulting in the inability to complete data reception, thereby improving the accuracy and reliability of determining the input pin of the driving chip.

[0063] The following will describe in detail a method and a driving chip for determining an input pin of a driving chip provided by an embodiment of the present application with reference to the accompanying drawings.

[0064] As Figure 2 shown, a schematic flowchart of a method for determining an input pin of a driving chip provided by an embodiment of the present application specifically includes the following steps:

[0065] S201. Receive a power supply voltage and a detection signal, where the detection signal includes a first level signal and a logic data signal, and the detection signal is input through a first input / output pin of the driving chip;

[0066] S202. After determining that the power supply voltage is valid, switch the state of the enable signal from an invalid state to a valid state;

[0067] S203. When the state of the enable signal is in a valid state, compare the received logic data signal with a preset target logic data signal. If the comparison result is the same, determine that the first input / output pin is the input pin of the driving chip.

[0068] The execution subject of the embodiment of the present application may be a driving chip. The first level signal in the embodiment of the present application may be a high-level signal or a low-level signal.

[0069] In a specific implementation, the driving chip can input a power supply voltage through a power supply input pin and input a detection signal through an input / output pin of the driving chip, that is, the first input / output pin of the driving chip. Usually, the driving chip includes two input / output pins, and the two input / output pins, one is defined as an input pin and the other is defined as an output pin.

[0070] After the power supply voltage input through the power supply input pin of the driving chip, the driving chip is powered on, that is, the power supply voltage is valid. After the driving chip determines that the power supply voltage is valid, it switches the state of the input / output judgment signal from an invalid state to a valid state. Among them, the input / output judgment signal is in an invalid state when it is a low-level signal, and the input / output judgment signal is in a valid state when it is a high-level signal.

[0071] When the state of the input / output judgment signal is in a valid state, a detection signal is input to the first input / output pin of the driving chip. The detection signal includes a first level signal and a logic data signal. Among them, the first level signal can be a high-level signal, and the logic data signal can be any combination of 0 and 1. For example, 1010 or 0101.

[0072] In a specific implementation, the first level signal in the detection signal is before the logic data signal, and there can be a time period between the first level signal and the logic data signal, and the start time of the first level signal is later than the start time of the valid power supply voltage.

[0073] In one embodiment, after the driving chip determines that the power supply voltage is valid, it switches the state of the enable signal from an invalid state to a valid state. After the driving chip determines that the state of the enable signal is in a valid state, it compares the received logic data signal with a preset target logic signal, and determines the first input / output pin as the input pin of the driving chip according to the comparison result. Specifically, when the comparison result is the same, the first input / output pin is determined as the input pin of the driving chip.

[0074] In another embodiment, after the driving chip determines that the power supply voltage is valid and determines that the duration of the first level signal in the detection signal is greater than a first preset duration, it switches the state of the enable signal from an invalid state to a valid state. After the driving chip determines that the state of the enable signal is in a valid state, it compares the received logic data signal with a preset target logic signal, and determines the first input / output pin as the input pin of the driving chip according to the comparison result. Specifically, when the comparison result is the same, the first input / output pin is determined as the input pin of the driving chip.

[0075] For example, if the preset target logic data signal is 0101 and the received logic data signal is also 0101, then the first input / output pin is determined as the input pin of the driving chip.

[0076] If the comparison result is different, it is determined that the received logical data signal is abnormal. At this time, the state of the reset signal is switched from the invalid state to the valid state. After the driving chip determines that the state of the reset signal is the valid state, the state of the enable signal is switched from the valid state to the invalid state, thereby realizing the reset of the enable judgment module, waiting to receive the next detection signal, and restarting to determine the input pin of the driving chip. In the embodiment of the present application, when the detection signal is abnormal, it is not necessary for the driving chip to be powered on again to determine the input pin again, reducing the complexity of determining the input pin.

[0077] In one embodiment, after determining that the first input / output pin is the input pin of the driving chip, the second input / output pin of the driving chip in the idle state is determined as the output pin of the driving chip.

[0078] The driving chip usually includes two input / output pins and one pin for inputting the power supply voltage. After determining that one input / output pin of the driving chip is the input pin, the other input / output pin is determined as the output pin.

[0079] In a specific implementation, after the driving chip determines that the first input / output pin is the input pin of the driving chip, the state of the input / output judgment signal is switched from the valid state to the invalid state, and the state of the input / output signal is switched to the invalid state.

[0080] In one embodiment, after the driving chip determines that the power supply voltage is valid, if the duration of the state of the input / output judgment signal being in the valid state is greater than or equal to the second preset duration, the second input / output pin of the driving chip is determined as the output pin of the driving chip.

[0081] Wherein, the second preset duration is greater than the first preset duration.

[0082] In the embodiment of the present application, when determining the input pin of the driving chip, the front end only inputs a detection signal to one input / output pin of the driving chip and does not input a detection signal to the other input / output pin. A set of judgment logics can be configured for each input / output pin of the driving chip, that is, the judgment logic of the input / output pin receiving the detection signal determines that the input / output pin is the input pin of the driving chip, and the judgment logic of the input / output pin not receiving the detection signal determines that the input / output pin is the output pin of the driving chip.

[0083] As Figure 3 shown, it is a schematic diagram of the complete method flow for determining the input pin of a driving chip provided by the embodiment of the present application, which specifically includes the following steps:

[0084] S301. The drive chip receives a power supply voltage and a detection signal. The detection signal includes a first-level signal and a logic data signal, and the detection signal is input through the first input / output pin of the drive chip.

[0085] S302. After the drive chip determines that the power supply voltage is valid, it switches the input / output judgment signal from the invalid state to the valid state.

[0086] Among them, the invalid state of the input / output judgment signal is a low-level signal, and the valid state of the input / output judgment signal is a high-level signal.

[0087] S303. After the drive chip determines that the input / output judgment signal is in the valid state, it receives the detection signal.

[0088] S304. After the drive chip determines that the first-level signal in the detection signal lasts for a first preset duration, it switches the state of the enable signal from the invalid state to the valid state.

[0089] After the input / output judgment signal is in the valid state, the detection signal will be input to the drive chip through this pin. The detection signal includes a first-level signal and a logic data signal. The first-level signal can be a high-level signal, and the duration is greater than or equal to the first preset duration, and the first-level signal is before the logic data signal.

[0090] The invalid state of the enable signal can be a low-level signal, and the valid state of the enable signal can be a high-level signal.

[0091] S305. After the drive chip determines that the state of the enable signal is the valid state, it compares the logic data signal in the detection signal with a preset target logic signal.

[0092] S306. Determine whether the comparison results are the same. If so, execute S307; otherwise, execute S309.

[0093] S307. The drive chip determines that the pin for inputting the detection signal is the input pin of the drive chip.

[0094] S308. The drive chip switches the state of the input / output judgment signal from the valid state to the invalid state.

[0095] S309. The drive chip switches the state of the reset signal from the invalid state to the valid state.

[0096] The invalid state of the reset signal can be a low-level signal, and the valid state of the reset signal can be a high-level signal.

[0097] S310. After the drive chip determines that the reset signal is in the valid state, it switches the state of the enable signal from the valid state to the invalid state.

[0098] After the driving chip determines that the duration for which the input / output judgment signal is in the valid state is greater than or equal to the second preset duration, it determines that the second input / output pin is the output pin of the driving chip.

[0099] Based on the same inventive concept, an embodiment of the present application further provides a driving chip. The principle for the driving chip to solve the technical problem is similar to the principle for any of the above methods for determining the input pin of the driving chip. The implementation of the driving chip can refer to the implementation of the method, and the repeated parts will not be elaborated.

[0100] As Figure 4 shown, a driving chip provided by an embodiment of the present application includes:

[0101] A power input pin 41 for inputting a power supply voltage VDD;

[0102] A first input / output pin 42 for inputting a detection signal, where the detection signal includes a first level signal and a logic data signal;

[0103] An enable judgment module 43 for receiving the power supply voltage VDD and the detection signal, and after determining that the power supply voltage VDD is valid, switching the state of the output enable signal from an invalid state to a valid state;

[0104] A logic judgment module 44 for receiving the detection signal and the enable signal, and in the case where the state of the enable signal is a valid state, comparing the logic data signal with a preset target logic data signal. If the comparison result is the same, it determines that the first input / output pin is an input pin.

[0105] For the driving chip provided by the embodiment of the present application, the power supply voltage VDD is input through the power input pin 41, and the detection signal is input through the first input / output pin 42. After the enable judgment module 42 receives the power supply voltage VDD, that is, after determining that the power supply voltage VDD is valid, it inputs an enable signal in a valid state to the logic judgment module 43. After the logic judgment module 43 receives the power supply voltage VDD and the enable signal in a valid state, it compares the logic data signal in the detection signal with the preset target logic signal, and determines the first input / output pin as the input pin of the driving chip according to the comparison result. Specifically, if the comparison result is the same, it determines that the first input / output pin is the input pin of the driving chip. Since determining the first input / output pin for receiving the detection signal as an input pin is based on the power signal and the logic data signal, and the logic data signal is compared with the preset target logic data signal, compared with only determining based on the level signal, it can avoid the problem that the entire link is abnormal and data reception cannot be completed due to an abnormality in a high-level signal during a certain period of time in the transmission process, thereby improving the accuracy and reliability of determining the input pin.

[0106] In the embodiment of the present application, the power input pin 41 and the first input / output pin 42 are both external pins of the drive chip, and the enable judgment module 42 and the logic judgment module 43 are both modules inside the drive chip.

[0107] In one embodiment, after the enable judgment module 42 receives the power supply voltage VDD and determines that the duration of the first level signal in the detection signal is greater than the first preset duration, it inputs an enable signal in an effective state to the logic judgment module 43. After the logic judgment module 43 receives the power supply voltage VDD and the enable signal in an effective state, it compares the logic data signal in the detection signal with a preset target logic signal. If the comparison result is the same, it determines that the first input / output pin is the input pin of the drive chip.

[0108] In one embodiment, as Figure 5 shown, the drive chip provided by the embodiment of the present application may further include an input / output port 44 and a data processing module 46;

[0109] After the logic judgment module 42 determines that the power supply voltage VDD is effective, it switches the state of the output input / output judgment signal from an invalid state to an effective state;

[0110] The input / output port 44 inputs the input / output judgment signal. When the input / output judgment signal is in an effective state, it conducts the path between the target pin 42 and the enable judgment module 43, and conducts the path between the target pin 42 and the logic judgment module 44;

[0111] After the logic judgment module 44 determines that the first input / output pin 42 is the input pin of the drive chip, it sets the signal transmission direction of the input / output port 45 to the direction of transmitting from the first input / output pin 42 to the data processing module 46.

[0112] In the embodiment of the present application, after the power supply voltage is input through the power input pin 41, the logic judgment module 44 outputs an input / output judgment signal in an effective state to the input / output port 45. After the input / output port receives the input / output judgment signal in an effective state, the input / output port 45 conducts the path between the first input / output pin 42 and the logic judgment module 44, and conducts the path between the first input / output pin 42 and the enable judgment module 43. If a detection signal is input to the first input / output pin 42, after the detection signal is input from the first input / output pin 42, it is output to the enable judgment module 43 and the logic judgment module 44 through the input / output port 45.

[0113] It should be noted that in the embodiments of the present application, when the input / output port 45 receives an input / output judgment signal in an effective state, the transmission direction of the signal can be set to unidirectional, that is, transmitted from the first input / output pin 42 to the enable judgment module 43 and from the first input / output pin 42 to the logic judgment module 44. It can also be set to bidirectional, that is, it can be transmitted from the first input / output pin 42 to the enable judgment module 43 and from the first input / output pin 42 to the logic judgment module 44, and can also be transmitted from the enable judgment module 43 to the first input / output pin 42 and from the logic judgment module 44 to the first input / output pin. The embodiments of the present application do not limit this.

[0114] After determining that the power supply voltage is effective and determining that the first level signal in the detection signal lasts for the first preset duration, the enable judgment module 43 switches the output enable signal from an invalid state to an effective state;

[0115] After determining that the received enable signal is in an effective state, the logic judgment module 44 compares the logic data signal in the received detection signal with a preset target logic data signal. If the comparison result is the same, it is determined that the first input / output pin 42 is the input pin of the driving chip.

[0116] If the logic judgment module 44 determines that the comparison result of the logic data signal and the preset target logic data signal is different, it indicates that the logic data signal is abnormal, and the state of the reset signal input from the logic judgment module 44 to the enable judgment module 43 is switched from an invalid state to an effective state;

[0117] After receiving the reset signal in an effective state, the enable judgment module 43 switches the state of the enable signal from an effective state to an invalid state, thereby realizing the reset of the enable signal.

[0118] After determining that the first input / output pin 42 is the input pin of the driving chip, the logic judgment module 44 switches the input / output judgment signal from an effective state to an invalid state. After the input / output port 45 determines that the input / output judgment signal is switched from an effective state to an invalid state, it disconnects the path between the first input / output pin 42 and the enable judgment module 43 and disconnects the path between the first input / output pin and the logic judgment module 44, that is, exits the logic of determining the input pin of the driving chip, and conducts the path between the first input / output pin 42 and the data processing module 46, and sets the transmission direction of the signal to the direction transmitted from the first input / output pin 42 to the data processing module 46.

[0119] In the embodiment of the present application, after the input / output port 45 in the driving chip conducts the path between the first input / output pin 42 and the data processing module 46, and sets the signal transmission direction to be from the first input / output pin 42 to the data processing module 46, the definition of the input pin of the driving chip is completed.

[0120] After the driving chip completes the definition of the input / output pin, another input / output pin is determined as the output pin of the driving chip.

[0121] Specifically, as Figure 6 shown, the driving chip further includes an input / output port 47 and an input / output pin 48. After the driving chip defines the input / output pin 42 as an input pin, the logic judgment module 44 in the driving chip sends a control signal to the input / output port 47 to control the signal transmission direction of the input / output port 47 to be from the data processing module 46 to the input / output pin 48, so as to define the input / output pin 48 as the output pin of the driving chip.

[0122] In the above embodiment, after the logic judgment module 44 in the driving chip defines the input / output pin 42 as an input pin and the input / output pin 48 as an output pin, after the driving works normally, the display data is input from the input pin to the data processing module 46, and after being processed by the data processing module 46, it is output through the output pin.

[0123] In one embodiment, as Figure 7 shown, the driving chip further includes an enable judgment module 49 and a logic judgment module 50. The power input pin 41 inputs the power supply voltage VDD. After the logic judgment module 50 receives the power supply voltage VDD, it switches the state of the output input / output judgment signal from the invalid state to the valid state. Since the detection signal is input from the input / output pin 42, the input / output pin 48 will not input the detection signal, and the state of the input / output judgment signal output by the logic judgment module 50 always remains in the valid state, that is, the input / output judgment signal is a high-level signal. After the logic judgment module 50 determines that the duration of the output input / output judgment signal is greater than or equal to the second preset duration, it determines the input / output pin as the output pin, that is, the logic judgment module 50 sends a control signal to the input / output port 47 to control the signal transmission direction of the input / output port 47 to be from the data processing module 46 to the input / output pin 48.

[0124] As Figure 8 shown, it is a timing diagram for determining the input pin of the driving chip provided by the embodiment of the present application. Next, in combination with Figure 7 and Figure 8 , the embodiment of the present application will be described in detail.

[0125] Referring to Figure 8, after the power supply voltage VDD is input, the driving chip enters the working mode. After the logic judgment module 44 receives the high-level power supply voltage VDD, it switches the output input / output judgment signal from low level to high level;

[0126] After the input / output port 45 receives the high-level input / output judgment signal, it conducts the path between the input / output pin 42 and the enable judgment module 43, and conducts the path between the input / output pin 42 and the logic judgment module 44;

[0127] The input / output pin 42 inputs a high-level signal for a period of time, that is, the first-level signal in the detection signal. At this time, the enable signal received by the logic judgment module 44 is a low-level signal. Therefore, the logic judgment module 44 does not perform logic judgment work. The high-level signal input by the input / output pin 42 for a period of time is input to the enable judgment module 43. The enable judgment module 43 performs enable judgment according to the power supply voltage VDD and the high-level signal for a period of time. If the power supply voltage is in the high-level stage and the duration of the high-level signal input by the input / output pin 42 is greater than or equal to the first preset duration T1, the enable judgment module 43 will raise the output enable signal, that is, switch the enable signal from a low-level signal to a high-level signal;

[0128] After the logic judgment module 44 receives the high-level enable signal, it starts logic judgment work. After the input / output pin 42 outputs a high-level signal for a period of time, it starts to output a logic judgment signal, that is, the logic judgment signal in the detection signal. This logic judgment signal can be any combination of binary numbers. For example, 1010, or 0101. The logic judgment module 44 compares the received logic judgment signal with the preset target logic judgment signal. If the comparison result is the same, it will pull down the output input / output judgment signal, that is, switch the input / output judgment signal from a high-level signal to a low-level signal;

[0129] After the input / output port 45 determines that the input input / output judgment signal is switched from a high-level signal to a low-level signal, it sets the signal transmission direction to be transmitted from the input / output pin 42 to the data processing module 46.

[0130] As Figure 9 shown, it is another timing diagram for determining the input pin of the driving chip provided by the embodiment of the present application. The following combines Figure 7 and Figure 9 , and details the embodiment of the present application.

[0131] Referring to Figure 9 , after the power supply voltage VDD is input, the driving chip enters the working mode. After the logic judgment module 44 receives the high-level power supply voltage VDD, it switches the output input / output judgment signal from a low-level signal to a high-level signal;

[0132] The input / output pin 42 inputs a high-level signal for a period of time, that is, the first-level signal in the detection signal. At this time, the enable signal received by the logic judgment module 44 is a low-level signal. Therefore, the logic judgment module 44 does not perform logic judgment work. The high-level signal for a period of time input by the input / output pin 42 is input to the enable judgment module 43. The enable judgment module 43 performs an enable judgment based on the power supply voltage VDD and the high-level signal for a period of time. If the power supply voltage VDD is in the high-level stage and the duration of the high-level signal input through the input / output pin 42 is greater than or equal to the first preset duration T1, the enable judgment module 43 will raise the output enable signal, that is, switch the enable signal from a low-level signal to a high-level signal.

[0133] After the logic judgment module 44 receives the high-level enable signal, it starts the logic judgment work. After the input / output pin 42 outputs the high-level signal for a period of time, it starts to output the logic judgment signal. If the logic judgment signal is abnormal and the logic judgment module 42 compares the logic judgment signal with the target logic judgment signal and the comparison result is different, the logic judgment module 42 will raise the output reset signal, that is, switch the reset signal from a low-level signal to a high-level signal.

[0134] After the enable judgment module 43 receives the high-level reset signal, it will pull down the enable signal to complete the reset of the enable judgment module 43.

[0135] As Figure 10 shown, it is a timing diagram for determining the output pin of the drive chip provided by the embodiment of the present application. The following will be combined with Figure 8 and Figure 10 , and the embodiments of the present application will be described in detail.

[0136] When the input / output pin 48 of the drive chip does not input a detection signal and the power input pin 41 inputs the power supply voltage VDD, after the logic judgment module 50 receives the power supply voltage VDD input by the power input pin 41, it will switch the state of the output input / output judgment signal from an invalid state to a valid state. Since the input / output pin 48 does not input a detection signal, the enable judgment module 49 will not raise the enable signal, and the enable signal is always in a low-level state. After the logic judgment module 50 raises the output input / output judgment signal, it will not perform logic judgment either. The input / output judgment signal output by the logic judgment module 50 will be in a continuous high-level state. When the logic judgment module 50 determines that the duration of the continuous high-level input / output judgment signal is greater than or equal to the second preset duration T2, it will define the input / output pin as the output pin of the drive chip, that is, set the transmission direction of the input / output port 47 to be from the data processing module 46 to the input / output pin 48.

[0137] The method and driving chip for determining the input pins of a driving chip provided by the embodiments of the present application. After the driving chip is normally powered on, the first input / output pin of the driving chip receives a detection signal. The logic judgment module outputs an input / output judgment signal with a high level according to the input power supply voltage, that is, the power supply voltage is a high-level signal, and the state of the input / output judgment signal output by the logic judgment module is high level;

[0138] When the state of the input / output judgment signal is a high-level signal, the path between the first input / output pin and the enable judgment module is conducted, and the path between the first input / output pin and the logic judgment module is conducted;

[0139] The enable judgment module makes a judgment according to the input power supply voltage and the first-level signal in the detection signal. If the power supply voltage VDD is high level and the first-level signal lasts for the first preset duration T1, the enable judgment module outputs an enable signal in an effective state, that is, an enable signal with a high level, and the logic judgment module starts the logic judgment work;

[0140] The logic judgment module makes a judgment according to the logic judgment signal in the detection signal and the preset target logic judgment signal. After judging that the logic judgment signal is the same as the target logic judgment signal, the output input / output judgment signal is switched from high level to low level. After the input / output port determines that the received input / output judgment signal is switched from high level to low level, the signal transmission direction is set to be transmitted from the first input / output pin to the data processing module, and the definition of the input pin of the driving chip is completed;

[0141] If the logic judgment module judges that the logic judgment signal is different from the target logic judgment signal, the logic judgment module outputs a reset signal with a high level. After the enable judgment module receives the reset signal with a high level, it pulls down the output enable signal to complete the reset of the enable judgment module. The enable judgment module continues to wait for the input of the next detection signal and starts to determine the input pin of the driving chip again.

[0142] The determination of the output pins of the driving chip in the embodiments of the present application includes two methods. Method 1: After determining that one input / output pin of the driving chip is an input pin, the other input / output pin is defined as the output pin of the driving chip. Method 2: After determining that the duration of the input / output judgment signal exceeds the second preset duration, the corresponding input / output pin of the driving chip is determined as the output pin of the driving chip. The two methods for determining the output pins can improve the flexibility of determining the output pins of the driving chip.

[0143] Those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these changes and modifications.

Claims

1. A method for determining an input pin of a driver chip, characterized in that: The method includes: Receiving a power supply voltage and a detection signal, wherein the detection signal includes a first level signal and a logic data signal, and the detection signal is input through a first input / output pin of the driving chip; After determining that the power supply voltage is valid, switching the state of the enable signal from an invalid state to a valid state; When the state of the enable signal is a valid state, the received logic data signal is compared with a preset target logic data signal, and if the comparison result is the same, the first input-output pin is determined to be an input pin of the driver chip.

2. The method according to claim 1, characterized in that After determining that the power supply voltage is valid, switching the state of the enable signal from an invalid state to a valid state includes: It is determined that the power supply voltage is valid, and it is determined that the first level signal lasts for a first preset time period, and the state of the enable signal is switched from the invalid state to the valid state.

3. The method according to claim 2, characterized in that The method further comprises: After determining that the power supply voltage is valid, switching the state of the input / output determination signal from an invalid state to a valid state; When it is determined that the state of the input / output determination signal is a valid state, the detection signal is received through the first input / output pin.

4. The method according to claim 2, characterized in that: The step of determining that the first input-output pin is an input pin of the driver chip includes: Switching the state of the input / output determination signal from a valid state to an invalid state; After determining that the state of the input / output determination signal is switched from a valid state to an invalid state, the first input / output pin is determined as an input pin of the driving chip.

5. The method according to claim 2, characterized in that: The method further comprises: After determining that the comparison result is different, switching the state of the reset signal from an invalid state to a valid state; After determining that the state of the reset signal is a valid state, the state of the enable signal is switched from a valid state to an invalid state.

6. The method according to claim 3, characterized in that After determining that the power supply voltage is valid, the method further includes: When it is determined that the state of the input / output determination signal is a valid state and the duration of the input / output determination signal is greater than or equal to a second preset duration, the second input / output pin of the driver chip is determined to be the output pin of the driver chip.

7. The method according to any one of claims 1 to 4, characterized in that: After determining that the first input-output pin is the input pin of the driver chip, the method further includes: A second input-output pin in the driver chip that is in an idle state is determined as an output pin of the driver chip.

8. A driver chip, characterized in that: include: Power input pin, used to input power supply voltage; A first input / output pin, used to receive a detection signal, wherein the detection signal includes a first level signal and a logic data signal; An enable judgment module, used for receiving the power supply voltage and the detection signal, and switching the output enable signal from an invalid state to a valid state after determining that the power supply voltage is valid; The logic judgment module is used to receive the detection signal and the enable signal, and when the state of the enable signal is valid, compare the logic data signal with a preset target logic data signal, and if the comparison result is the same, determine that the first input-output pin is an input pin.

9. The driver chip according to claim 8, characterized in that: The enabling judgment module is specifically used for: It is determined that the power supply voltage is valid, and it is determined that the first level signal lasts for a first preset time period, and the state of the enable signal is switched from the invalid state to the valid state.

10. The driver chip according to claim 9, characterized in that: Also includes input and output ports; The logic judgment module is also used to switch the state of the input / output judgment signal from an invalid state to a valid state after determining that the power supply voltage is valid; The input / output port is used to input the input / output judgment signal, and when the state of the input / output judgment signal is a valid state, the path between the first input / output pin and the enable judgment module is connected, and the path between the first input / output pin and the logic judgment module is connected.

11. The driver chip according to claim 10, characterized in that: The driver chip further includes a data processing module, and the logic judgment module is specifically used for: When the comparison results are the same, switching the state of the input / output judgment signal from a valid state to an invalid state; The input / output port is used to set the signal transmission direction of the input / output port to be transmitted from the first input / output pin to the data processing module after determining that the state of the input / output judgment signal is switched from a valid state to an invalid state.

12. The driver chip according to claim 9, characterized in that: The logic judgment module is specifically used for: After determining that the comparison result is different, switching the state of the reset signal from an invalid state to a valid state; The enable judgment module is further used to receive the reset signal, and when the state of the reset signal is a valid state, switch the state of the enable signal from a valid state to an invalid state.

13. The driving chip according to claim 9, characterized in that: The driver chip also includes a second input and output pin; The logic judgment module is also used to determine that the second input-output pin is the output pin of the driving chip when it is determined that the power supply voltage is valid, the state of the input-output judgment signal is a valid state, and the duration of the input-output judgment signal is greater than or equal to a second preset duration.

14. The driver chip according to claim 9, characterized in that: The driver chip also includes a second input and output pin; The logic judgment module is further used to determine the second input-output pin in the driver chip that is in an idle state as an output pin of the driver chip after determining that the first input-output pin is an input pin.

15. The driver chip according to claim 13 or 14, characterized in that: The driver chip further includes a data processing module, and the logic judgment module is specifically used for: The signal transmission direction of the input / output port corresponding to the second input / output pin is set to be transmitted from the data processing module to the second input / output pin.

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