System and method suitable for service function access of stability control device

Abstract

The invention discloses a system and method suitable for service function access of a stability control device, and the system comprises a main CPU board which is used for the operation of a real-time operation system, strategy calculation and global data processing; the OPT board is used for connecting each cascade device through an optical port to realize multi-type data access, and each cascade device comprises a cascade sub-machine, a cascade host and a cascade communication interface device; the backboard gigabit bus is used for connecting the main CPU board and the OPT board and is divided into a plurality of virtual channels, and each channel has an independent QoS strategy; the configuration file is used for defining communication attribute configuration of each optical port of the OPT board, and the communication attribute configuration comprises port type, data interaction format and protocol stack configuration; according to the invention, the flexible configuration of the device-level access type and number is realized, the service function access flexibility of the stability control device is provided, and the real-time access and efficient processing of large-capacity data are effectively supported.

Description

Technical Field

[0001] The present invention belongs to the technical field of secondary power equipment, and particularly relates to a method and system for accessing the service functions of a stability control device. Background Art

[0002] The power grid security and stability control device (stability control device) is an important guarantee for the safe operation of the power system. As the second line of defense, when a large disturbance occurs in the power grid, it can prevent the system from becoming unstable by quickly executing control measures such as generator tripping and load shedding. With the continuous expansion of the power grid scale and the high proportion of new energy access, the operation mode of the power grid has become increasingly complex, posing higher requirements for the real-time performance, reliability, and flexibility of the stability control system. Modern stability control systems need to process massive amounts of data and quickly coordinate multi-region control strategies, and the limitations of traditional system architectures are gradually emerging when dealing with these challenges.

[0003] Currently, the flexible configuration of the stability control system mainly relies on the combination of hardware boards or software modular design. In terms of hardware, some technologies adopt the plug-and-play combination of functional boards (such as communication interface boards, sampling boards, etc.), and adapt to different application scenarios by increasing or decreasing the number or type of boards. In terms of software, existing technologies dynamically load protection logics or data sampling strategies through configuration files to achieve the on-demand combination of functional modules.

[0004] However, in the existing technologies, the flexibility of hardware configuration is limited to the board level, and it is impossible to independently define the functions of multiple communication ports on a single board, resulting in low utilization rate of port resources and difficulty in adapting to diverse access requirements. Although the modular design at the software level can improve the logical configurability, it does not optimize the data transmission mechanism for the high real-time requirements of the stability control system, resulting in communication delays. Ultimately, the overall flexibility of the system is insufficient and the real-time performance is limited, making it difficult to meet the stringent requirements of modern power grids for high performance and high reliability of the stability control system. Summary of the Invention

[0005] Object of the Invention: The object of the present invention is to provide a system for accessing the service functions of a stability control device that can be flexibly configured and realizes the flexible access and high real-time processing of large-capacity data. On the other hand, a method for accessing the service functions of a stability control device is provided.

[0006] Technical Solution: The system described in the present invention includes:

[0007] A main CPU board, which is used to run a real-time operating system, perform policy calculation, and process global data, ensuring the accuracy and timeliness of the core decisions of the system;

[0008] OPT board, which is used to connect cascading devices through optical ports to achieve access of multiple types of data. The cascading devices include cascading slave machines, cascading master machines, and cascading communication interface devices, realizing high-speed data throughput and stable transmission, and at the same time having excellent anti-interference ability to adapt to harsh industrial environments;

[0009] Backplane gigabit bus, which is used to connect the main CPU board and the OPT board, is divided into multiple virtual channels, and each channel has an independent QoS policy to provide differentiated service quality guarantees for different service data, ensuring the absolute priority transmission of key control instructions;

[0010] Configuration file, which is used to define the communication attribute configurations of each optical port of the OPT board, including port type, data interaction format, and protocol stack configuration, enabling the system to quickly be compatible with multiple communication protocols.

[0011] The entire system realizes rapid deployment, seamless switching, and intelligent operation and maintenance through deep cooperation of each component, significantly improving the operation efficiency and reliability of traditional cascading systems.

[0012] Preferably, the OPT board includes:

[0013] A number of SFP optical ports, whose function types are dynamically defined through the configuration file, support the cascading slave machine, cascading master machine, or cascading communication interface device mode, greatly improving the utilization rate of hardware resources and the flexibility of networking;

[0014] MCU, which is used to initialize each optical port according to the configuration parameters sent by the main CPU board, allocate DMA buffers, and load the corresponding protocol parsing engine, not only ensuring the business continuity during multi-mode switching, but also significantly improving the protocol processing efficiency in complex industrial environments.

[0015] This architecture effectively solves the pain points commonly found in traditional cascading systems, such as poor protocol compatibility, time-consuming mode switching, and low resource utilization rate, while ensuring nanosecond-level transmission latency, providing a high-reliability and low-latency deterministic network guarantee for the power grid through two core technologies: hardware resource virtualization and protocol processing acceleration.

[0016] Preferably, the main CPU board includes:

[0017] DSP1 core, as an application core, executes user programs and processes user data and variable interaction data;

[0018] DSP2 core, as a communication core, manages data reception and transmission and platform management data, and realizes data synchronization with the DSP1 core through a ping-pong buffer.

[0019] This architecture realizes the physical isolation and parallel processing of computing and communication functions, which not only avoids the reduction of real-time performance caused by resource competition, but also ensures the integrity and timeliness of data interaction between the dual cores through a hardware-level data synchronization mechanism. Compared with the traditional single-core solution, this design significantly improves the multi-task processing ability of the system in complex industrial scenarios, enabling key services such as control instruction processing, protocol stack operation, and data acquisition to be truly executed in parallel, providing a deterministic computing performance guarantee for industrial automation applications with high real-time requirements.

[0020] Preferably, the data interaction between the main CPU board and the OPT board is realized through the frame-by-frame transmission technology. The backplane gigabit bus is divided into several virtual hundred-megabit channels, and each channel transmits independent data packets. The data packet types include application data, variable interaction data, and platform management data.

[0021] While maintaining the bandwidth advantage of the gigabit-level bus, this design realizes the transmission reliability similar to physical isolation, enabling different service flows such as control instructions, status monitoring, and system management to not interfere with each other, providing a data transmission solution with strict timing guarantee for industrial-level communication, and significantly improving the real-time response ability and communication stability of the system under complex working conditions.

[0022] The method of the present invention includes the following steps:

[0023] (1) The main CPU board loads and parses the configuration file, and distributes the communication attribute configuration of each optical port of the OPT board to the MCU of the OPT board through the backplane gigabit bus.

[0024] (2) The MCU of the OPT board initializes each optical port according to the parameters in the communication attribute configuration, allocates DMA buffers, and loads the protocol parsing engine.

[0025] (3) Establish a data interaction channel between the main CPU board and the OPT board, including the upstream channel of the data path of the cascading device - OPT board - main CPU board and the downstream channel of the data path of the main CPU board - OPT board - cascading device.

[0026] This process enables the system to have the plug-and-play ability through the software-defined hardware method, and can adapt to different cascading devices without manual intervention. Through the resource pre-allocation and protocol pre-loading mechanisms, it ensures the end-to-end low-latency characteristics of the data transmission path. At the same time, the standardized configuration process effectively avoids manual operation errors, significantly improves the industrial field deployment efficiency and communication reliability, and provides an out-of-the-box solution for multi-device cascading scenarios.

[0027] Preferably, the data processing of the OPT board includes:

[0028] Schedule the corresponding software modules according to the configuration information to achieve differential message parsing for cascaded slave machines, cascaded master machines, and cascaded communication interface devices, and be able to dynamically call different software modules to accurately parse the heterogeneous messages of various cascaded devices;

[0029] Filter the upstream data of the cascaded slave machines, cascaded master machines, and cascaded communication interface devices by type and then forward them to the DSP1 core and DSP2 core of the main CPU board respectively to achieve the optimal allocation of computing resources;

[0030] Packetize the downstream data of the main CPU board according to the preset device-level communication frame format and send it to the cascaded slave machines, cascaded master machines, and cascaded communication interface devices through the corresponding optical ports to ensure that the downstream data strictly follows the protocol specifications of the target devices.

[0031] This design significantly improves the data processing ability of the system in complex industrial environments, not only ensuring the real-time response of key services, but also optimizing the overall performance of the system through hardware-level data routing, providing an efficient and reliable data processing solution for multi-device cascading scenarios.

[0032] Preferably, the data processing of the main CPU board includes:

[0033] In the receiving process, the FPGA on the main CPU board receives the communication data transmitted by the backplane gigabit bus through the PCIe interface and stores it in the shared interaction space; establish a receiving ping-pong buffer in the on-chip OCM of the main CPU board. The DSP2 core first compares the historical counter lastcnt values of the two cores at the end of the preset interrupt cycle. If they are inconsistent, synchronize and trigger an alarm. Then, check the new data in the PCIe space and store it in the receiving ping-pong buffer, and update the real-time counter thiscnt value; at the head of the interrupt, the DSP1 and DSP2 cores compare their respective lastcnt and thiscnt values. If they are not equal, set the local data available flag bit, and update their respective lastcnt to thiscnt. The application layers of DSP1 and DSP2 make application-layer logical judgments based on the judgment of the local data available flag bit and take the data in their respective corresponding buffers, and clear the local data available flag at the end of the interrupt.

[0034] In the sending process, the main CPU board sends 10 data packets to the OPT board in each preset interrupt cycle, including 8 packets of application data maintained by the DSP1 core, 1 packet of variable interaction data jointly maintained by the two cores, and 1 packet of platform management data maintained by the DSP2 core. A sending ping-pong buffer is established in the on-chip OCM of the main CPU board. The DSP1 and DSP2 cores buffer the data to be sent by writing it into the sending ping-pong buffer and update their respective thiscnt values. At the head of the interrupt cycle, the DSP2 core first determines whether the thiscnt values of the two cores are the same. After confirmation, it compares the thiscnt with the lastcnt value. If they are not equal, it takes out the data from the sending ping-pong buffer and writes it into the PCIe space, and updates the lastcnt to thiscnt. Finally, after a preset time offset, the application FPGA of the main CPU board sends the data from the PCIe space to the OPT board through the backplane gigabit bus.

[0035] Through the innovative dual-core cooperation mechanism and ping-pong buffer architecture, this design realizes the high reliability and determinacy of industrial-level data communication. In the receiving process, the counter comparison synchronization technology is adopted to ensure the data consistency of the two cores, combined with the interrupt-driven flag management mechanism, effectively avoiding data loss or duplicate processing. The sending process realizes strict timing control of multi-service data, and cooperates with the dual-core verification mechanism to ensure the complete synchronization of key data. It gives full play to the low-latency characteristics of FPGA hardware acceleration and on-chip memory OCM, achieving a microsecond-level data processing cycle in complex industrial scenarios, meeting the real-time requirements of the control system, and improving the communication reliability to the industrial-level standard through multiple verification mechanisms, providing a deterministic data communication solution for high-precision industrial automation systems.

[0036] Preferably, the data interaction between the OPT board and the cascaded slave machines includes:

[0037] In the sending process, within the preset interrupt cycle, the OPT board obtains and parses the message sent by the main CPU through the gigabit high-speed interface. When it is determined to be in the cascaded slave machine mode, according to the optical port number and CMD channel data, the message is encapsulated and sent according to the SV 9-2 protocol. Each optical port only sends 1 frame of data in each interrupt cycle, with a maximum length of 1500 bytes. The CMD field is filled according to the instruction type, the broadcast instruction is filled with 0xFF, and no instruction is filled with zero, ensuring the accuracy and timeliness of instruction distribution.

[0038] In the receiving process, the OPT board polls each optical port within the preset interrupt cycle, performs format verification and parsing on the received slave machine message. If the reply messages of the CMD broadcast frame are received by 8 optical ports at the same time, the CMD reply message is stored in the secondary buffer corresponding to the optical port, and the parsed slave machine message is framed according to the inter-board communication protocol and then uploaded to the main CPU.

[0039] This solution effectively suppresses the peak communication pressure through a hierarchical buffering design (optical port buffer + secondary buffer). Combined with an adaptive protocol conversion mechanism, it perfectly solves common problems such as instruction conflicts and data congestion in multi-submachine systems while ensuring industrial-level communication real-time performance, providing a highly reliable distributed communication infrastructure for scenarios such as intelligent manufacturing.

[0040] Preferably, the data interaction between the OPT board and the cascaded host includes:

[0041] In the sending process, the OPT board queries and parses the messages sent by the main CPU within a preset interrupt cycle. When it is determined to be in the cascaded host mode, it frames the data according to the network message frame format between cascaded hosts and sends the framed message to the cascaded host through the hardware network interface driver chip.

[0042] In the receiving process, within a preset interrupt cycle, the OPT board polls the network message reception status of each optical port, performs format verification and parsing processing on the received host messages, repackages the host messages according to the message protocol format specified between the CPU board, and sends the repackaged host messages to the main CPU board through the gigabit high-speed interface.

[0043] This solution uses a timed polling mechanism to ensure communication real-time performance and improves the transmission efficiency through the hardware network interface driver. It not only maintains the communication characteristics of the cascaded host but also realizes stable docking with the main control system, providing reliable cross-system communication support for industrial networks.

[0044] Preferably, the data interaction between the OPT board and the cascaded communication interface device includes:

[0045] In the sending process, within a preset interrupt cycle, the OPT board queries and parses the messages sent by the main CPU through the gigabit high-speed interface. When it is determined to be in the cascaded communication interface device mode, it frames the 1500-byte data transmitted by the main CPU according to the network message frame format of the cascaded communication chassis and transmits the framed message to the communication interface device through the corresponding channel. Among them, the 1500-byte data contains at most 63 2M channel data.

[0046] In the receiving process, within a preset interrupt cycle, the OPT board polls the network message reception status of each optical port, performs format verification and parsing processing on the received communication interface device messages, repackages the communication interface device messages according to the message protocol format specified between the main CPU board, and sends the data to the main CPU board through the backplane gigabit high-speed interface.

[0047] This solution realizes the efficient aggregation and distribution of large-scale channel data while ensuring communication real-time performance through standardized interrupt cycle control, significantly improving the data transmission efficiency between the communication interface device and the main control system.

[0048] Beneficial effects: Compared with the prior art, the present invention has the following remarkable advantages: 1. It realizes the flexible configuration of the access types and numbers at the device level, provides the flexibility for the access of the stability control device service functions, and effectively supports the real-time access and efficient processing of large-capacity data; 2. It ensures that the stability control system can respond in a timely manner to the changes in the grid operating conditions, improves the timeliness of data processing and the overall stability of the system; 3. It standardizes the design of the stability control logic program, reduces the need for customized development, and lowers the complexity of code maintenance; 4. It has good scalability and can flexibly meet the development needs of future power systems. Brief Description of the Drawings

[0049] Figure 1 It is a schematic diagram of the system structure of the present invention;

[0050] Figure 2 It is a backplane diagram of the stability control device chassis of the present invention;

[0051] Figure 3 It is a flowchart of the initialization of the communication system of the stability control device of the present invention;

[0052] Figure 4 It is the communication message format between the CPU and the OPT of the present invention;

[0053] Figure 5 It is a flowchart of the CPU sending data to the OPT of the present invention;

[0054] Figure 6 It is a flowchart of the CPU receiving data from the OPT of the present invention;

[0055] Figure 7 It is a flowchart of the OPT receiving data from the CPU of the present invention;

[0056] Figure 8 It is a flowchart of the OPT sending data to the cascaded slave machine of the present invention;

[0057] Figure 9 It is a flowchart of the OPT receiving data from the cascaded slave machine of the present invention;

[0058] Figure 10 It is a flowchart of the OPT sending data to the cascaded master machine of the present invention;

[0059] Figure 11 It is a flowchart of the OPT receiving data from the cascaded master machine of the present invention;

[0060] Figure 12 It is a flowchart of the OPT sending data to the communication interface device of the present invention;

[0061] Figure 13 It is a flowchart of the OPT receiving data from the communication interface device of the present invention. Detailed implementation mode

[0062] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings.

[0063] As Figure 1 shown, the system described in the present invention includes:

[0064] A main CPU board for running a real-time operating system, policy calculation, and global data processing; an OPT board for connecting cascading devices through optical ports to achieve multi-type data access. The cascading devices include cascading sub-units, cascading hosts, and cascading communication interface devices; a backplane gigabit bus for connecting the main CPU board and the OPT board, divided into multiple virtual channels, and each channel has an independent QoS policy; a configuration file for defining the communication attribute configuration of each optical port of the OPT board, including port type, data interaction format, and protocol stack configuration.

[0065] As Figure 2 shown, the main CPU board is connected to the OPT board through a gigabit high-speed bus, responsible for policy logic operation and global data processing; the OPT board is connected to the cascading sub-unit, cascading host, and cascading communication interface device through optical ports to achieve multi-type data access; the backplane adopts a gigabit Ethernet architecture, divided into 10 virtual channels (fragmentation technology), and each channel has an independent QoS policy. Among them, the main CPU board is embedded with an ARM multi-core processor, runs a real-time operating system, and performs stability control policy calculation and status monitoring. The DSP1 core of the CPU board serves as the application core, undertakes the task of executing user programs, prepares data and processes the received data, covering user data and variable interaction data. The DSP2 core of the CPU board: serves as the communication core, is responsible for sending the data prepared by DSP1 and receiving data for DSP1 to use. The OPT board is configured with 8 SFP optical ports, and the hardware acceleration of message encapsulation / parsing is performed through DPAA (Data Path Acceleration Architecture). The functional types of each optical port (cascading sub-unit / cascading host / cascading communication interface device) are dynamically defined by the configuration file.

[0066] The method described in the present invention includes:

[0067] Step 1: Configuration file writing and parsing

[0068] Write a device-level configuration description file, and define the number of effective optical ports actually used on the communication expansion board (OPT), the external communication functions of each optical port (cascading sub-unit, cascading host, cascading communication interface device), and the number of sampling intervals, the number of I / O ports, etc. included in the data interaction under different communication attributes of each optical port in the configuration description file according to the access requirements under different working conditions. This device configuration description file is downloaded and saved in the file storage directory of the device operating system.

[0069] During the power-on initialization phase of the device, when the host CPU board starts, it loads the device configuration description file stored in the file system, parses out the above communication attribute configuration information of each optical port of the communication expansion board (OPT), and transmits it to the MCU on the communication expansion board through the CAN bus channel on the device backplane.

[0070] Step 2: Initialization of each optical port of the communication expansion board

[0071] The MCU of the OPT board reconstructs the configuration attributes of each optical port on the OPT board according to the communication attribute configuration of each optical port issued by the main CPU board (such as parameters like Port1 being in the cascaded slave mode, etc.): initializes each enabled and effective optical port according to the configuration parameters, allocates the corresponding DMA buffer storage area space, and loads and initializes the corresponding optical port protocol parsing engine software (packet disassembling and assembling software modules; communication protocol stack).

[0072] Step 3: Data receiving and transmitting processing of the host OPT board

[0073] Step 3-1: Device-level access and output data processing

[0074] According to the application requirements, different frame formats for data interaction and communication between the host OPT board and the cascaded host, cascaded slave, and cascaded communication interface devices are designed, as shown in Tables 1 to 4. The OPT board software schedules the corresponding software modules to receive and process different types of application messages of each optical port according to the initialized configuration information during the operation of the device, realizing the flexible access and data parsing of different device types. At the same time, the external transmission messages at the device level also call the corresponding software modules at each optical port on the OPT board to packetize according to the defined device-level communication transmission frame format and send them to the peer device through the corresponding optical port.

[0075] Step 3-2: Real-time data receiving and transmitting processing of the OPT board for communication with the CPU board

[0076] After summarizing the data accessed at the external device level, the host OPT board needs to promptly transmit it to the host CPU board for logical decision-making. Based on the backplane gigabit bus frame transmission technology, according to the function requirements of the data types accessed by the stability control host, the backplane gigabit bus is framed into 10 frames of 100M Ethernet messages for transmission, and a specific data interaction message frame format between the OPT board and the CPU board is designed. After the host OPT board collects the network message information of the cascaded devices at each optical port, according to the designed inter-board data interaction frame format, it filters and forwards the external access uplink data information by type to the DSP board and the CPU board management core of the host; at the same time, it parses the external downlink data information of the host CPU board and sends it to the cascaded devices through each optical port, realizing the real-time receiving and transmitting processing of large-capacity data through the device backplane.

[0077] Step 4: Data receiving and transmitting processing of each core of the host CPU board

[0078] There are 2 DSP cores designed on the CPU board. DSP1 is the application core, which is responsible for running upper-layer application programs, preparing data to be sent, and processing received data, including user data and variable interaction data. DSP2 is the communication core, which is responsible for sending the data prepared by DSP1, receiving data and providing it for DSP1 to use. At the same time, DSP2 core also directly receives and processes platform management data without the participation of DSP1.

[0079] Step 4-1: Receiving process

[0080] The FPGA on the host CPU board receives communication data (application data, variable interaction data, and platform management data) transmitted through the backplane gigabit bus, and parses the message according to the specific data interaction message frame format defined in Step 4 above. The parsed data is transmitted to the CPU board PCIe data sharing and interaction space by type and channel through the PCIe interface.

[0081] By establishing a receiving ping-pong buffer in the OCM on the CPU board, DSP2 judges whether the two cores are synchronized (whether the lastcnt of the two cores is the same value) at the end of this interrupt. If they are not synchronized, the two cores are configured to be synchronized, and an alarm signal is given to the application. Subsequently, DSP2 checks whether there is new data in the PCIe space of the FPGA. If there is, the data is received into the ping-pong buffer, and the receiving counter value (thiscnt) is updated.

[0082] Both DSP1 and DSP2 judge whether thiscnt is the same as their respective lastcnt at the head of each interrupt. If they are different, it means there is new data, and the local data available flag is set, and their respective lastcnt is updated to thiscnt. The application layers of DSP1 and DSP2 make logical judgments at the application layer according to the judged local data available flag and take the data in the corresponding buffer of ((thiscnt - 1) & 0x1) of each of them (the variable exchange buffer data is composed of the data of the two cores), and clear the local data available flag at the end of the interrupt.

[0083] Step 4-2: Sending process

[0084] The CPU board sends 10 data packets to a single OPT board in each interrupt: 8 packets of application data, 1 packet of platform management data, and 1 packet of variable exchange data. Among them, the user data is maintained by the DSP1 core, the variable interaction data is jointly maintained by the two cores (formed by packing the variable data of the two DSP cores), and the platform management data is maintained by DSP2.

[0085] By establishing a sending ping-pong buffer in the on-chip OCM, DSP1 and DSP2 buffer the sending data to the buffer (thiscnt & 0x1) of their respective OCMs at the end of this interrupt. Among them, the variable exchange buffer is composed of the data of the two cores, and their respective thiscnt is updated.

[0086] DSP2 judges whether the thiscnt of the two cores is the same at the interrupt header. If they are the same, it further judges the thiscnt number and the lastcnt. If they are different, it means there is new data. DSP2 fetches the data in the buffer area of (lastcnt & 0x1) in the ping-pong buffer, writes the data to be sent into the PCIe space, and updates the lastcnt to thiscnt. After a period of offset (calculated from the interrupt header and can be configured by software), the CPU board uses the FPGA to send the data from the PCIe space to the OPT board through the backplane gigabit bus.

[0087] As Figure 3 shown, the initialization process of the stable control device communication system includes:

[0088] Step 1 Configuration file parsing: When the main CPU starts, it loads the configuration file and parses the communication attributes (port type, MAC address whitelist, message framing rules, etc.) of each optical port of the OPT board. The main CPU sends the configuration parameters to the OPT board MCU through the CAN bus.

[0089] Step 2 Optical port dynamic initialization: The OPT board MCU reconstructs the optical port driver layer according to the configuration parameters sent by the main CPU (such as Port1 is in the cascaded sub-unit mode): allocates DMA buffer space, such as allocating a 2MB circular buffer for the cascaded sub-unit optical port. Loads the corresponding protocol parsing engine (such as the SV 9-2ASDU parsing module, communication stack).

[0090] The communication message frame format of the 10 100Mbps Ethernet virtualized by the gigabit bus between the OPT and the main CPU is as Figure 4 shown (the maximum application data is 1498Bytes, and 2Bytes of crc and checksum are added at the end of the frame):

[0091] Among them, CH: 0x00~0x07, representing the 1st to 8th optical port numbers, and 1500 bytes is the application message content sent by the main CPU to the cascaded device; TYPE: represents the message type (needs to cooperate with the value of CH, as shown in Table 1 below):

[0092] Table 1 TYPE represents the message type

[0093]

[0094] CNT: represents the interrupt sequence number to ensure that the 10 frames of data received come from the same interrupt on the CPU side;

[0095] LEN_H, LEN_L: represent the effective message length in the subsequent 1498 bytes; CRC: represents the INT16 sum check from the frame header to before the CRC of this frame.

[0096] The OPT board periodically sends up to 10 frames of data to the main CPU, and sends the data of the slave machine received in the previous interrupt at the head of this interrupt.

[0097] The data flow from the CPU to the OPT is as Figure 5 shown:

[0098] Step 1 Preparation stage: The interrupt of the CPU board is started to initiate the data sending process. Subsequently, DSP1 and DSP2 respectively write the data they need to send into the transmit buffer established on the chip.

[0099] Step 2 Check and preparation: DSP2 checks the data counts of itself and DSP1. If they are inconsistent, error handling is performed and the data sending is stopped; if they are consistent, DSP2 retrieves the data from the buffer, formats the frame header, and then writes the data into the PCIE space.

[0100] Step 3 Sending and ending: The FPGA retrieves the data from the PCIE space and sends the data to the OPT board via the gigabit high-speed bus. After the data sending is completed, the process ends.

[0101] The data flow for the CPU to receive OPT data is as Figure 6 shown:

[0102] Step 1 Start and synchronization check: The interrupt of the CPU board is started to initiate the data receiving process. Then, DSP2 checks the synchronization status of the dual cores. If the synchronization is abnormal, the process directly ends; if the synchronization is normal, it proceeds to the next step.

[0103] Step 2 Data reception judgment: DSP2 checks whether there is new data in the PCIE space. If there is new data, it receives the data into the receive buffer on the chip; if there is no new data, the process ends.

[0104] Step 3 Data processing and ending: DSP1 and DSP2 check whether there is newly received data. If there is, they retrieve the data from the corresponding buffer and unpack it; if there is no, the process ends. After completing the data processing, the entire receiving process ends.

[0105] The data flow for the OPT to receive CPU data is as Figure 7 shown:

[0106] Step 1 Data detection and verification: During the operation of the OPT board, a periodic interrupt mechanism is triggered every 833 microseconds. In this interrupt handler, the OPT board checks whether there is new data from the CPU. Once new data is detected, the system starts the CRC verification process for the received message. If the verification process determines that it fails, the message is directly discarded, and the error counter is incremented accordingly to record the verification failure; if the verification is successful, it proceeds to the next step.

[0107] Step 2 Frame Type Processing: For frames that pass the CRC check, the OPT board will judge their frame types. For frames of the types of cascaded slave machines, cascaded master machines, and cascaded communication interface chassis, the OPT board will encapsulate them and then send the encapsulated frames to the corresponding target locations; for frames of the variable interaction type, the OPT board will store them in a specific storage area. Moreover, the OPT board will call a dedicated function to update real-time variables and, at the same time, send digital input / output variable interaction data and CMD command data according to the established timing rules. When the OPT board receives a CMD command frame, it will parse it to obtain the channel number information. Meanwhile, the data in the CMD command frame will be temporarily stored for subsequent sending. The OPT board has predefined the number of variables that cover the variables of the slave machines corresponding to the optical ports, and through the physical connection method of pulling wires, it realizes the data interaction function with the main CPU to ensure the integrity of the entire data transmission and processing process.

[0108] The data sending process from OPT to the cascaded slave machine is as Figure 8 shown:

[0109] Step 1 Timing Interrupt and Data Query: During the operation of the system, the hardware timer is set to trigger a timing interrupt every 0.833 milliseconds. When the interrupt occurs, the interrupt service program is immediately started. In this program, the OPT board queries the data sent by the main CPU through a specific gigabit high-speed interface to obtain possible new data packets.

[0110] Step 2 Mode Judgment and Frame Assembly and Sending: After obtaining the data packet, the OPT board parses and judges the packet according to the pre-set packet format to determine whether it is in the cascaded slave machine mode. If the judgment result is the cascaded slave machine mode, according to the optical port number and CMD channel data, encapsulate and organize the packet in the SV 9-2 format. In each interrupt cycle, each network interface only supports the sending of one variable-length frame packet, and the maximum packet sending length is 1500 bytes. During the encapsulation and sending process, if the CMD command is a broadcast frame sent by the original host, fill it with 0XFF; if the CMD command frame has no data, fill it with zeros.

[0111] The data receiving process of OPT from the cascaded slave machine is as Figure 9 shown:

[0112] Step 1 Timing Interrupt and Packet Query: During the operation of the system, the hardware timer is set to trigger a timing interrupt every 0.833 milliseconds. After the interrupt is triggered, the corresponding interrupt service program is immediately started. In this program, the OPT board conducts a query operation on each network port one by one to judge whether there is a new network packet to be received, so as to obtain the corresponding packet data in a timely manner.

[0113] Step 2 Message Parsing and Sending: Once the OPT board receives a message during the query process of each external interactive network port, it performs corresponding message format verification and parsing on the message according to the frame format specification for communication and interaction with the cascaded slave machine. After the parsing is completed, if reply messages of the CMD broadcast frame sent by the original host are received by 8 optical ports simultaneously, the CMD reply messages will be stored in the CMD message secondary buffer configured for each optical port (the maximum number of cached CMD messages is 2 frames). After disassembling and unpacking the cascaded slave machine messages received by each optical port, the OPT board performs framing according to the specified message protocol format between the OPT board and the CPU board, and sends up to 10 frames of message data to the main CPU in the same interrupt.

[0114] The data sending process from the OPT to the cascaded host is as Figure 10 shown:

[0115] Step 1 Timing Interrupt and Data Query: During the system operation, the hardware timer is set to trigger a timing interrupt every 0.833 milliseconds. When the interrupt occurs, the interrupt service program is immediately started. In this program, the OPT board queries the data sent by the main CPU through a specific gigabit high-speed interface to obtain possible new data messages.

[0116] Step 2 Mode Judgment and Framing and Sending: After obtaining the data message, the OPT board parses and judges the message according to the pre-set message format to determine whether it is in the cascaded host mode. If the judgment result is the cascaded host mode, the OPT board performs framing on the message content according to the relevant specifications of the network message frame format between the cascaded hosts. After framing, the OPT board calls the hardware network port driver chip to send the framed network message to the cascaded host to achieve accurate data transmission.

[0117] The data receiving process of the OPT from the cascaded host is as Figure 11 shown:

[0118] Step 1 Timing Interrupt and Message Query: During the system operation, the hardware timer is set to trigger a timing interrupt every 0.833 milliseconds. After the interrupt is triggered, the corresponding interrupt service program is immediately started. In this program, the OPT board performs a query operation on each network port one by one to determine whether there is a new network message to be received, so as to obtain the corresponding message data in time.

[0119] Step 2 Message Encapsulation and Sending: Once the OPT board receives a message during the query process of the external interactive network port, it performs corresponding message format verification and parsing on the message according to the frame format specification for communication and interaction with the cascaded host. After the parsing is completed, it performs encapsulation according to the specified message protocol format between the OPT board and the CPU board, and sends the encapsulated message to the main CPU through the hardware gigabit high-speed interface.

[0120] The data sending process from OPT to the communication interface device is as follows Figure 12 as shown below:

[0121] Step 1: Timing interrupt and data query: During the operation of the system, the hardware timer is set to trigger a timing interrupt every 0.833 milliseconds. When the interrupt occurs, the interrupt service program is immediately started. In this program, the OPT board queries the data sent by the main CPU through a specific gigabit high-speed interface to obtain possible new data packets.

[0122] Step 2: Mode judgment and frame assembly and sending: After obtaining the data packet, the OPT board parses and judges the packet according to the pre-set packet format to determine whether it is in the cascaded communication interface device mode. If the judgment result is the cascaded communication interface device mode, the OPT board assembles the 1500-byte data transmitted by the main CPU into a frame according to the cascaded communication chassis network packet frame format and directly transmits it to the communication interface device through the corresponding channel. Among the 1500-byte data transmitted, there can be at most 63 2M channel data.

[0123] The data receiving process of OPT from the communication interface device is as follows Figure 13 as shown below:

[0124] Step 1: Timing interrupt and packet query: During the operation of the system, the hardware timer is set to trigger a timing interrupt every 0.833 milliseconds. After the interrupt is triggered, the corresponding interrupt service program is immediately started. In this program, the OPT board queries each network interface one by one to determine whether there is a new network packet to be received, so as to obtain the corresponding packet data in time.

[0125] Step 2: Packet sending: Once the OPT board receives a packet during the query of the external interaction network interface, it checks and parses the packet format according to the interaction frame format with the communication interface device. After the parsing and processing are completed, it is encapsulated according to the specified packet protocol format with the main CPU board and sent to the main CPU board through the backplane gigabit high-speed interface.

Claims

1. A system suitable for accessing the service function of a stabilization control device, characterized in that: include: Main CPU board, used to run real-time operating system, strategy calculation and global data processing; The OPT board is used to connect various cascade devices through optical ports to achieve multi-type data access. The cascade devices include cascade slaves, cascade hosts and cascade communication interface devices; The backplane Gigabit bus is used to connect the main CPU board and the OPT board. It is divided into multiple virtual channels, and each channel has an independent QoS policy. Configuration file, used to define the communication attribute configuration of each optical port of the OPT board, including port type, data exchange format and protocol stack configuration.

2. The system according to claim 1, characterized in that The OPT board includes: Several SFP optical ports, whose function types are dynamically defined through configuration files, support cascaded slave, cascaded host or cascaded communication interface device modes; MCU is used to initialize each optical port according to the configuration parameters sent by the main CPU board, allocate DMA buffers, and load the corresponding protocol analysis engine.

3. The system according to claim 1, characterized in that The main CPU board comprises: DSP1 core, as the application core, executes user programs and processes user data and variable interaction data; DSP2 core, as a communication core, manages data transmission and reception and platform management data, and synchronizes data with DSP1 core through ping-pong buffer.

4. The system according to claim 3, characterized in that The data interaction between the main CPU board and the OPT board is achieved through frame transmission technology, which divides the backplane Gigabit bus into several virtual 100M channels, each channel transmits independent data packets, and the data packet types include application data, variable interaction data and platform management data.

5. A method for flexible access to service functions of a stabilization control device, characterized in that: The following steps are involved: (1) The main CPU board loads and parses the configuration file, and sends the communication attribute configuration of each optical port of the OPT board to the MCU of the OPT board through the backplane Gigabit bus; (2) The MCU of the OPT board initializes each optical port according to the parameters in the communication attribute configuration, allocates DMA buffers, and loads the protocol parsing engine; (3) Establishing a data exchange channel between the main CPU board and the OPT board, including an uplink channel of the cascade device-OPT board-main CPU board data path and a downlink channel of the main CPU board-OPT board-cascade device data path.

6. The method according to claim 5, characterized in that The data processing of the OPT board includes: Dispatching corresponding software modules according to configuration information to implement differentiated message parsing of cascaded slaves, cascaded hosts and cascaded communication interface devices; The uplink data of the cascaded slaves, cascaded hosts and cascaded communication interface devices are filtered by type and forwarded to the DSP1 core and DSP2 core of the main CPU board respectively; The downlink data of the main CPU board is packaged according to the preset device-level communication frame format and sent to the cascade slave machine, cascade host machine and cascade communication interface device through the corresponding optical port.

7. The method according to claim 5, characterized in that The data processing of the main CPU board includes: In the receiving process, the main CPU board uses FPGA to receive the communication data transmitted by the backplane gigabit bus through the PCIe interface and stores it in the shared interactive space; a receiving ping-pong buffer is established in the OCM on the main CPU board, and the DSP2 core first compares the lastcnt values ​​of the historical counters of the two cores at the end of the preset interrupt cycle. If they are inconsistent, synchronization is performed and an alarm is triggered. Then, the new data in the PCIe space is checked and stored in the receiving ping-pong buffer, and the real-time counter thiscnt value is updated; the DSP1 and DSP2 cores compare their respective lastcnt and thiscnt values ​​at the interrupt header. If they are not equal, the local data flag is set and their respective lastcnt is updated to thiscnt. The application layer of DSP1 and DSP2 judges the local data flag and takes the data in their corresponding buffers for application layer logic judgment, and clears the local data flag at the end of the interrupt. In the sending process, the main CPU board sends 10 data packets to the OPT board in each preset interrupt cycle, including 8 packets of application data maintained by the DSP1 core, 1 packet of variable interaction data maintained by the dual cores, and 1 packet of platform management data maintained by the DSP2 core; a sending ping-pong buffer is established in the OCM on the main CPU board, and the DSP1 and DSP2 cores write the data to be sent into the sending ping-pong buffer and update their respective thiscnt values; the DSP2 core first determines whether the thiscnt values ​​of the dual cores are consistent at the head of the interrupt cycle, and then compares thiscnt with the lastcnt value after confirming that they are consistent. If they are not equal, the data is taken out from the sending ping-pong buffer and written into the PCIe space, and lastcnt is updated to thiscnt; finally, the main CPU board uses FPGA to send the data from the PCIe space to the OPT board through the backplane gigabit bus after a preset time offset.

8. The method according to claim 5, characterized in that The data interaction between the OPT board and the cascaded sub-machine includes: In the sending process, within the preset interrupt cycle, the OPT board obtains and parses the message sent by the main CPU through the Gigabit high-speed interface. When it is determined to be the cascaded slave mode, it encapsulates and sends the message according to the SV 9-2 protocol based on the optical port number and CMD channel data. Each optical port only sends 1 frame of data in each interrupt cycle, with a maximum length of 1500 bytes. The CMD field is filled according to the instruction type, 0xFF for broadcast instructions, and zero for no instructions. In the receiving process, the OPT board polls each optical port within the preset interrupt cycle, performs format check and analysis on the received slave machine message. If 8 optical ports receive the reply message of the CMD broadcast frame at the same time, the CMD reply message will be stored in the secondary buffer corresponding to the optical port, and the parsed slave machine message will be framed according to the inter-board communication protocol and uploaded to the main CPU.

9. The method according to claim 5, characterized in that The data interaction between the OPT board and the cascade host includes: In the sending process, the OPT board queries and parses the message sent by the main CPU within the preset interrupt cycle. When it is determined to be the cascade host mode, it frames the data according to the network message frame format between the cascade hosts, and sends the framed message to the cascade host through the hardware network port driver chip; In the receiving process, within the preset interrupt cycle, the OPT board polls the network message reception status of each optical port, performs format verification and parsing on the received host message, re-encapsulates the host message according to the message protocol format specified between the CPU board, and sends the encapsulated host message to the main CPU board through the Gigabit high-speed interface.

10. The method according to claim 5, characterized in that The data interaction between the OPT board and the cascade communication interface device includes: In the sending process, within the preset interruption cycle, the OPT board queries and parses the message sent by the main CPU through the gigabit high-speed interface. When it is determined to be the cascade communication interface device mode, the 1500-byte data transmitted by the main CPU is framed according to the cascade communication chassis network message frame format, and the framed message is transmitted to the communication interface device through the corresponding channel, where the 1500-byte data contains data of up to 63 2M channels; In the receiving process, within the preset interrupt cycle, the OPT board polls the network message reception status of each optical port, performs format check and parsing on the received communication interface device message, re-encapsulates the communication interface device message according to the message protocol format specified between the main CPU board, and sends the data to the main CPU board through the backplane Gigabit high-speed interface.

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