An interface conversion method, device, product, and computer-readable storage medium

Abstract

The present invention discloses an interface conversion method, device, product, and computer-readable storage medium, relating to the field of communication technologies. It includes, based on the information corresponding to the start symbol and end symbol in the data to be converted received through a segmented interface, real-time positioning of the start and end boundaries of each data packet, accurately tracking the valid range of the data segment through a state machine, avoiding boundary misalignment or truncation caused by the compressed data stream format of the segmented interface, thereby solving the problem of data loss. According to the current state and the next-hop transition state of the state machine, dynamically allocate the data processing operations executed by the first channel and the second channel to output converted data that meets the transmission requirements of the streaming interface, solving the technical problem of the structural contradiction between the dynamic characteristics of the segmented interface and the continuity requirements of the streaming interface, and achieving the technical effect of line-speed parsing of the data stream.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to an interface conversion method, device, product, and computer-readable storage medium. Background Art

[0002] With the development of high-speed network communication technologies, the 400G / 200G Ethernet protocol has become the core transmission standard for data centers due to its ultra-high bandwidth characteristics. It adopts a compressed data stream format with fixed segments, while high-speed interconnect protocols such as PCIe (Peripheral Component Interconnect Express) usually implement data transmission based on the AXI4-Stream (Advanced eXtensible Interface 4-Stream) streaming interface. However, in the prior art, there is a lack of an efficient conversion solution for segmented interfaces and streaming interfaces, especially in the direction of converting segmented data to streaming data (Segmented_to_AXIS). Due to the structural contradiction between the dynamic characteristics of the segmented interface and the continuity requirements of the streaming interface, there are risks of data loss, throughput limitation, and protocol compatibility in high-throughput scenarios, affecting the performance of heterogeneous protocol interconnection.

[0003] Therefore, how to provide a solution to the above technical problems is an issue that those skilled in the art need to solve currently. Summary of the Invention

[0004] The present invention provides an interface conversion method, device, product, and computer-readable storage medium to at least solve the technical problem of the structural contradiction between the dynamic characteristics of the segmented interface and the continuity requirements of the streaming interface in the related art.

[0005] The present invention provides an interface conversion method, including: determining information corresponding to a start symbol and an end symbol in data to be converted received by a segmented interface of an interface conversion device within a current clock cycle; determining a next transition state of a state machine based on the information and the current state of the state machine; and controlling a first channel and / or a second channel of the interface conversion device to perform corresponding data processing operations according to the next transition state, so as to output converted data through the first channel and / or the second channel, and the converted data meets the transmission requirements of the streaming interface of the interface conversion device.

[0006] The present invention also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of the above interface conversion method when executing the computer program.

[0007] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above interface conversion method.

[0008] The present invention also provides a computer program product including a computer program, which, when executed by a processor, implements the steps of the above interface conversion method.

[0009] Through the present invention, based on the information corresponding to the start symbol and end symbol in the data to be converted received through the segmented interface, the start and end boundaries of each data packet are located in real time, and the effective range of the data segment is accurately tracked through a state machine, avoiding boundary misalignment or truncation caused by the compressed data stream format of the segmented interface, thereby solving the problem of data loss. According to the current state and the next-hop state of the state machine, the data processing operations executed by the first channel and the second channel are dynamically allocated to output converted data that meets the transmission requirements of the streaming interface, solving the technical problem that there is a structural contradiction between the dynamic characteristics of the segmented interface and the continuity requirements of the streaming interface, and achieving the technical effect of line-speed parsing of the data stream. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To more clearly illustrate the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 It is a flowchart of an interface conversion method provided by an embodiment of the present invention.

[0012] Figure 2 It is a schematic diagram of an interface conversion provided by an embodiment of the present invention.

[0013] Figure 3 It is a schematic diagram of packet splicing of a segmented interface provided by an embodiment of the present invention.

[0014] Figure 4 It is a schematic diagram of header interruption provided by an embodiment of the present invention.

[0015] Figure 5 It is a schematic diagram of middle-packet interruption provided by an embodiment of the present invention.

[0016] Figure 6 It is a schematic diagram of tail-packet interruption provided by an embodiment of the present invention.

[0017] Figure 7 It is a schematic diagram of small-packet transmission interruption provided by an embodiment of the present invention.

[0018] Figure 8A schematic diagram of idle state jump provided by an embodiment of the present invention.

[0019] Figure 9 The first schematic diagram of non-idle state jump provided by an embodiment of the present invention.

[0020] Figure 10 The second schematic diagram of non-idle state jump provided by an embodiment of the present invention. Detailed implementation manners

[0021] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0022] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0023] In order to enable those skilled in the art of the present technology to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0024] An embodiment of the present invention provides an interface conversion method. Referring to Figure 1 , in combination with the execution process of the interface conversion method, the method will be described in detail.

[0025] The interface conversion method provided by the embodiment of the present invention includes:

[0026] S101: Determine the information corresponding to the start symbol and the end symbol in the data to be converted received by the segmented interface of the interface conversion device within the current clock cycle.

[0027] In this embodiment, the interface conversion is specifically the conversion from a segmented interface (Segment) to a streaming interface (AXIS). The conversion schematic diagram is shown in Figure 2 as follows, Figure 2It shows the conversion of a single-channel original 400G / 200G MAC Segment data interface into a dual-channel standard AXIS data interface. Among them, RX_MAC_VALID is a data valid flag, used to indicate whether the received data is valid; RX_MAC_DATA is the data, that is, the content of the transmitted data, with a bit width of 1024 / 512 bits, and each 64 bits is a Segmented; RX_MAC_INFRAME is a Segment valid flag (data segment valid flag), where each 1 bit corresponds to a Segmented, and can indicate the sop (start symbol) and eop (end symbol). RX_EOP_EMPTY indicates the number of remaining bytes of the last Segmented when the frame ends, and the rest are indication signals (errors and statuses, such as Figure 2 RX_MAC_FCS_ERROR (FCS check error flag in Figure 2 , used to indicate the frame check sequence (FCS) error of this Segment), RX_MAC_FCS_ERROR (receive error flag, used to indicate error type information), RX_MAC_STATUS (status information, used to provide status information related to reception)). The AXIS interface is a VALID-READY handshake. AXIS_TX_TVALID is a send data valid flag, used to indicate that the current output AXIS data is valid (VALID-READY handshake signal); AXIS_TX_TREADY is a send ready flag, which is set high when the downstream module is ready to receive data (VALID-READY handshake signal); AXIS_TX_TLAST is a frame end flag, used to indicate that the current transmission is the last data packet of the frame; AXIS_TX_TDATA

[1024] is the send data, representing the data signal of the AXIS interface, with a bit width of 1024 bits, and AXIS_TX_TKEEP[1024 / 8] is the data byte valid mask, where each 1 bit corresponds to one byte (8 bits) of TDATA, indicating whether the byte is valid. The user sideband signal is used to carry additional information related to the data (such as error flags, status information), and every 64 bits corresponds to 2 bits of user signal.

[0028] Taking the segmented interface of 400G MAC as an example, its bit width is 1024 bits, and it can be divided into 16 segments (data segments) in total. Each segment is 64 bits (8 bytes), inframe is 16 bits, and each bit corresponds to the valid flag of each segment, and valid corresponds to the valid flag of the global segment. The sop (start symbol) and eop (end symbol) of the data packet may fall into any one of the 16 segments, as shown in Figure 3 shown.

[0029] Considering that the minimum packet length of the data packet is 64 bytes and the minimum frame interval is 12 bytes, so 16 segments can contain at most two SOPs and two EOPs, and at least no SOPs and EOPs. Generally, there are roughly the following seven cases. In the first case, there are no SOPs and EOPs (the current is the middle data part of the data packet, and inframe is FFFF); in the second case, there is only one SOP (which may appear at the beginning, in the middle, or at the end); in the third case, there is only one EOP (which may appear at the beginning, in the middle, or at the end); in the fourth case, there is one SOP and one EOP (the SOP to the EOP is regarded as a whole and appears at the beginning, in the middle, or at the end); in the fifth case, there are two SOPs and one EOP; in the sixth case, there are two EOPs and one SOP; in the seventh case, there are two SOPs and two EOPs.

[0030] Since the EOP and SOP can be used to indicate the start and end boundaries of the data packet, in order to facilitate subsequent processing such as direct output, cross-segment splicing, and interruption recovery of the data, in this embodiment, first, the information corresponding to the start symbol and the end symbol in the data to be converted received by the segmentation interface of the interface conversion device within the current clock cycle is determined. The information corresponding to the start symbol and the end symbol includes at least the number of start symbols and the number of end symbols in the data to be converted received within the current clock cycle.

[0031] In an alternative embodiment, when the interface conversion method in this embodiment is applied in the intelligent network card scenario, it can be understood that the intelligent network card needs to efficiently process 400G data from the network, identify the data packet boundary for fast offloading (such as encryption / decryption). In this application scenario, the data packet length is variable, and there may be dense small packets (such as ARP requests / responses, ICMP packets) or large packets (video streams or storage data), and the frame interval is compact. Assume that in the data to be converted received within the current clock cycle (Ethernet frame, a MAC layer data frame compliant with the IEEE 802.3 standard), assume , each segment has a width of 64 bits (8 bytes). To determine the positions of sop and eop, it is only necessary to rely on the INFRAM signal. Looking from right to left, the rightmost bit is bit0, and the leftmost bit is bit15. When it is detected that adjacent bits change from 0 to 1 (looking from right to left), this segment is considered as sop. When it is detected that adjacent bits change from 1 to 0, this segment is considered as eop. In this embodiment, the first sop is bit4 (segment4), the second sop is bit14 (segment14), the first eop position is bit10 (segment10), and eop_empty only indicates how many bytes are still needed for the segment corresponding to eop to make up a complete segment (8 bytes). If at this time , it means that the valid byte count of segment10 is 8 - 3 = 5 bytes, and three bytes are invalid.

[0032] In another alternative embodiment, the interface conversion method in this embodiment is applied in a network offloading scenario. The network offloading engine needs to handle TCP segment reassembly to ensure the integrity of data packets for offloading protocol parsing (such as HTTP header extraction). It can be understood that long data stream fragmentation (such as TCP stream fragmentation) may span multiple clock cycles. Assume that the data to be converted received within the current clock cycle (which can be based on the network layer (IP packet) and transport layer (TCP segment) data fragmentation of the TCP / IP protocol stack), . Traverse RX_MAC_INFRAME. In this embodiment, the first sop is bit10 (segment10), the first eop is bit4 (segment4), and the second eop is bit14 (segment14).

[0033] In addition, when determining sop and eop, it is also necessary to compare the inframes of the previous and next frames. For example, if the inframe of the first frame is 16'b0011_1111_1111_1111, and the inframe of the second frame is 16'b1111_1111_1111_1111, the bit0 of the second frame has a transition relative to the bit15 of the previous frame. Therefore, bit0 of the second frame is also a sop.

[0034] It can be understood that the minimum packet length of a network packet is 64 bytes. Therefore, at least 8 consecutive segments are considered as one packet, and there is at least a distance of two segments between two packets. The RX_MAC_INFRAME of the two frames provided in the above embodiments is only an example for identifying eop and sop, and it can be specifically set according to actual engineering requirements. This embodiment does not make specific limitations here.

[0035] S102: Determine the next transition state of the state machine based on the current state of the information and the state machine.

[0036] In this embodiment, a state machine is established in advance based on the states corresponding to the number of eop and sop that can be included in the data segments in the data that can be received by the segmented interface within one clock cycle. It includes IDLE (idle state), SOP2_EOP1 (including two sops and one eop), SOP1_EOP1 (including one sop and one eop and the eop position is ahead of the sop), EOP1_SOP1 (including one sop and one eop and the eop position lags behind the sop), EOP1 (only including one eop), SOP1 (only including one sop), NO_SOP_EOP (not including sop and eop), SOP2_EOP1 (including two sops and one eop), SOP1_EOP2 (including one sop and two eops). The specific state machine transitions and state controls are shown in Table 1.

[0037] Table 1 Schematic table of state machine transitions and state controls

[0038]

[0039] According to the current state, as well as the number and relative positions of eop and sop, the next transition state can be determined. Exemplarily, assuming the current state is IDLE, the next state may be SOP2_EOP1, may also be EOP1_SOP1, may also be SOP1. If there is only one sop currently, the next state of the current state IDLE is SOP1, and so on.

[0040] S103: Control the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next transition state, so as to output the converted data through the first channel and / or the second channel, and the converted data meets the transmission requirements of the streaming interface of the interface conversion device. In this embodiment, data processing operations to be performed by the first channel and the second channel in the interface conversion device are pre-configured for each state in the state machine, including but not limited to outputting data, caching data, etc., so as to realize combining the segmented data into the converted data that meets the transmission requirements of the streaming interface. Among them, the bidirectional one-hot code converts sop and eop, and the combinational logic controls the output valid tkeep.

[0041] Taking the above two application scenarios as examples again, in the smart network card application scenario, it is detected that the data to be converted in the current clock cycle includes 2 SOPs and 1 EOP. According to the jump rule in Table 1, assuming the current state is the idle state IDLE, it is necessary to jump to the SOP2_EOP1 state, that is, SOP2_EOP1 is the next jump state. At this time, the first channel outputs the current packet data (segment4 - segment10), and caches the next packet data (the starting position is segment14, starting to cache) to the next cycle, waiting for the subsequent EOP to arrive.

[0042] In the network offloading application scenario, assuming it is detected that the data to be converted in the current clock cycle includes 2 EOPs and 1 SOP. According to the rule in Table 1, if the current state is the SOP2_EOP1 state, it jumps to the SOP1_EOP2 state, that is, SOP1_EOP2 is the next jump state in this embodiment. At this time, there are two possible output actions. The first output action: The first channel outputs the current packet data (including the data after the second SOP in the SOP2_EOP1 state and the data before the first EOP in the current clock cycle), and the second channel outputs the next packet data (that is, the data between the first SOP and the second EOP in the current clock cycle). The second output action: The first channel outputs the current packet data, caches the remaining data of the current packet, and the second channel outputs the next packet data. For other jumps and output actions, similarly, they are not specifically limited in this embodiment. As an optional embodiment, the interface conversion device can be built based on programmable logic devices, including but not limited to FPGA (Field - Programmable Gate Array), CPLD (Complex Programmable Logic Device), ASIC (Application - Specific Integrated Circuit), SoC (System on Chip), etc. It can be implemented using RTL (Register - Transfer Level), which is convenient for system maintenance and function expansion, and at least includes a segmented interface for receiving the data to be converted, a processor, and a streaming interface including two channels for implementing the conversion and output of the data to be converted into the converted data that meets the transmission requirements of the streaming interface.

[0043] Through this embodiment, based on the information corresponding to the start character and the end character in the data to be converted received by the segmented interface, the start and end boundaries of each data packet are located in real time, and the effective range of the data segment is accurately tracked through the state machine to avoid boundary dislocation or truncation caused by the compressed data stream format of the segmented interface, thereby solving the problem of data loss. According to the current state and the next jump state of the state machine, the data processing operations performed by the first channel and the second channel are dynamically allocated to output the converted data that meets the transmission requirements of the streaming interface, thereby solving the technical problem of the structural contradiction between the dynamic characteristics of the segmented interface and the continuity requirements of the streaming interface, and achieving the technical effect of data stream line speed analysis.

[0044] Based on the above embodiment:

[0045] In an exemplary embodiment, the information includes the number of start characters and the number of end characters; the process of determining the information corresponding to the start characters and the end characters in the data to be converted received by the segmented interface of the interface conversion device in the current clock cycle includes: parsing the data segment validity identifier carried in the data to be converted received by the segmented interface of the interface conversion device in the current clock cycle; determining the number of start characters and the number of end characters based on the data segment validity identifier.

[0046] In this embodiment, each bit in the data segment validity identifier RX_MAC_INFRAME corresponds to a segment in the data to be converted, indicating whether the segment is valid and whether it contains sop or eop, thereby accurately identifying the starting and ending positions of the data packet, thereby avoiding the ambiguity of the data packet boundary. Accurate boundary management reduces errors that may occur when splicing or splitting data packets, such as data loss, duplication or mismatch.

[0047] In an exemplary embodiment, the data segment valid identifier includes a start vector identifier and an end vector identifier; the process of determining the number of start characters and the number of end characters based on the data segment valid identifier includes: determining the number of start characters and the number of end characters based on the start vector identifier and the end vector identifier.

[0048] The process of determining the number of start characters and the number of end characters based on the start vector identifier and the end vector identifier includes: performing a bitwise OR operation on the start vector identifier and the end vector identifier respectively to obtain the number of start characters and the number of end characters.

[0049] In this embodiment, because the minimum packet (64B) occupies at least 8 segments, the lower 8 bits and upper 8 bits of the start vector identifier i_rx_mac_sop and the end vector identifier i_rx_mac_eop can each be 1 at most once. Therefore, it is only necessary to perform a bitwise OR operation on each of them to calculate the number of sops and eops at the current moment, and then know the next jump status.

[0050] In an exemplary embodiment, the information further includes the positional relationship between the start symbol and the end symbol. The process of determining the positional relationship between the start symbol and the end symbol according to the valid identifier of the data segment includes: determining the positions of the start symbol and the end symbol according to the valid identifier of the data segment; when the position of the start symbol is greater than the position of the end symbol, the positional relationship is that the position of the end symbol is ahead of the position of the start symbol; when the position of the start symbol is less than the position of the end symbol, the positional relationship is that the position of the end symbol lags behind the position of the start symbol.

[0051] In this embodiment, considering that there is a moment when one sop and one eop are included, it is necessary to further clarify the relative positions of the sop and the eop at this time. If the position of the sop is greater than the position of the eop, the state SOP1_EOP1 is entered; otherwise, the state EOP1_SOP1 is entered.

[0052] In an exemplary embodiment, the process of determining the next transition state of the state machine based on the information and the current state of the state machine includes: when the global valid identifier carried in the data to be converted corresponds to a valid state, determining the next transition state of the state machine based on the information and the current state of the state machine.

[0053] Considering that there is an interruption phenomenon in the process of sending the valid in the data packet, it may occur at the packet header (refer to Figure 4 ), in the middle of the packet (refer to Figure 5 ), or at the packet tail (refer to Figure 6 ), and there may be an interruption of 1 to N clk. In addition, there is also an intermittent phenomenon in the process of sending small packets (refer to Figure 7 , Figure 7 where dt0 represents data0 and dt1 represents data1, respectively representing two small packets).

[0054] In this embodiment, the next transition state is determined only when the global valid identifier carried in the data to be converted corresponds to a valid state. If the global valid identifier carried in the data to be converted corresponds to an invalid state, the data at this moment is not processed temporarily.

[0055] In an exemplary embodiment, the process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next transition state includes: if the current state is the idle state, controlling the first channel of the interface conversion device to perform corresponding data processing operations according to the next transition state; the data processing operations are to output the current packet data, cache the current packet data, or cache the next packet data.

[0056] In this embodiment, in combination with Figure 8As shown in Table 1, if the current state is the idle state, the next transition state may be SOP1, EOP1_SOP1, or SOP2_EOP1. If the current T is the initial value 01, the default output is on the first channel AXIS1. If the current sop_one (including only one sop), further calculate the position of the sop. If it is 0, control the first channel AXIS1 to directly output the current packet data. If it is not 0, control the first channel AXIS1 to shift and cache the current packet data. If the current eop1_sop1 (including one eop and one sop, and the sop is ahead of the eop), then control the first channel AXIS1 to directly shift and output the current packet data. If SOP2_EOP1 (including one eop and two sops), then control the first channel AXIS1 to directly shift and output the current packet data, and cache the next packet data.

[0057] In this embodiment, according to the current state and the characteristics of the data packet, it is possible to select to directly output the current packet data or cache the data to adapt to different data transmission requirements. By calculating the position of the SOP, the output and caching operations of the data can be accurately controlled to ensure the correct start and end boundaries of the data packet.

[0058] In an exemplary embodiment, the process of determining the current channel activation mode includes: determining the offset corresponding to the current packet data; determining the output mode of the current packet data according to the offset and the end symbol position of the next packet data; determining the current channel activation mode based on the output mode.

[0059] In this embodiment, if it is necessary to output the data of packet A twice at a certain moment (usually at the end of packet A), then the data of packet B at this time is output by AXIS2. When it is necessary to output the data of packet B twice at a certain moment (usually at the end of packet B), the next packet A immediately switches back to output on AXIS1, as follows Figure 9 shown. Therefore, it is necessary to add a judgment on the relative relationship between the current offset offset and the eop_pos (the end symbol position of the next packet data): when or the output mode is single output of the current packet combination; when or the output mode is double output of the current packet combination. Based on this, set a 2-bit T variable (used to represent the current channel activation mode), and each bit represents the corresponding AXIS channel: when the channel activation mode is that neither channel outputs; when the channel activation mode is to output only from AXIS1; the channel activation mode is to output only from AXIS2; the channel activation mode is to output from AXIS1 and AXI2 simultaneously.

[0060] In an exemplary embodiment, the process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next jump state includes: if the current state is a non-idle state and the next jump state is a second target jump state corresponding to including at least one start symbol and / or at least one end symbol, control the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next jump state and the current channel activation mode.

[0061] In addition, if the current state is a non-idle state and the next jump state is a first target jump state corresponding to not including a start symbol and an end symbol, control the first channel of the interface conversion device to output the current packet data and cache the next packet data.

[0062] In this embodiment, if the current state is any state in the SOP2_EOP1 / SOP1_EOP1 / SOP1 / NO_SOP_EOP / SOP2_EOP2 state: when i_rx_mac_valid is valid, the next state may be EOP1, SOP1_EOP1, SOP1_EOP2, SOP2_EOP2 or NO_SOP_EOP, and the output channel selection depends on the current T value. If the current is eop1, further judge the T type, if , then the main channel shifts and outputs the current packet data, otherwise the main channel shifts and outputs the current packet data, and shifts and caches the remaining data; if the current is sop1_eop1, further judge the T type, if , then the main channel shifts and outputs the current data and caches the next packet data; otherwise the main channel outputs the current packet data, caches the remaining data of the current packet, and the auxiliary channel caches the next packet data; if the current is sop_eop2, further judge the T type, if , then the main channel shifts and outputs the current data, and the auxiliary channel outputs the next packet data; otherwise the main channel outputs the current packet data, caches the remaining data of the current packet, and the auxiliary channel outputs the next packet data; if the current is sop2_eop2, further judge the T type, if , then the main channel shifts and outputs the current data and caches and outputs the next packet data; otherwise the main channel outputs the current packet data, caches the remaining data of the current packet, the auxiliary channel outputs the next packet data, and caches the next packet data of the next packet data; if it is no_sop_eop, the main channel outputs the current packet data and caches the next packet data, as shown in Figure 10 shown.

[0063] In an exemplary embodiment, if the current state is a non-idle state, the process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next jump state and the current channel activation mode includes: if the current state is a first-type non-idle state, controlling the first channel of the interface conversion device to perform a corresponding third data processing operation and / or controlling the second channel of the interface conversion device to perform a corresponding fourth data processing operation according to the next jump state and the current channel activation mode; the third data processing operation includes outputting the next packet of data, or caching the next packet of data, or outputting the end data of the previous packet, or outputting the previous packet of data, or outputting the next packet of data and caching the next packet of data of the next packet of data; the fourth data processing operation includes outputting the next packet of data, or caching the next packet of data, or outputting the next packet of data and caching the next packet of data of the next packet of data.

[0064] If the current state is any of EOP1 / EOP1_SOP1 / SOP1_EOP2: When i_rx_mac_valid is valid, the next state may be SOP1, EOP1_SOP1, SOP2_EOP1, and the output channel selection depends on the current T value. If the next jump state is SOP1, if , the first channel outputs or caches the next packet of data, otherwise, the first channel outputs the end data of the previous packet, and the second channel outputs or caches the next packet of data. If the next jump state is EOP1_SOP1, if , the first channel outputs or caches the next packet of data, otherwise, the first channel outputs the previous packet of data, and the second channel outputs the next packet of data. If the next jump state is SOP2_EOP1, if , the first channel outputs the next packet of data and caches the next packet of data of the next packet of data. Otherwise, the first channel outputs the previous packet of data, and the second channel outputs the next packet of data and caches the downloaded packet data.

[0065] In summary, the present invention implements a method for converting a Segmented interface to an AXIS interface based on a programmable logic device (FPGA). This method addresses the Segmented interface provided by the existing Intel FPGA 400G / 200G MAC and proposes a synchronous conversion method based on state machine control, dual-channel pipeline output, and dual buffering. This method effectively bridges the MAC interface and the PCIe user interface, opening up the system data flow architecture. It is easy to use, flexible, and adaptable to multiple application scenarios.

[0066] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0067] An embodiment of the present invention further provides an interface conversion system, including: a first determination module, configured to determine information corresponding to a start symbol and an end symbol in the data to be converted received by the segmented interface of the interface conversion device in the current clock cycle; a second determination module, configured to determine the next jump state of the state machine based on the information and the current state of the state machine; and a processing module, configured to control the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next jump state, so as to output the converted data through the first channel and / or the second channel, and the converted data meets the transmission requirements of the streaming interface of the interface conversion device.

[0068] In an exemplary embodiment, the information includes the number of start symbols and the number of end symbols; the process of determining the information corresponding to the start symbol and the end symbol in the data to be converted received by the segmented interface of the interface conversion device in the current clock cycle includes: parsing the data segment valid flag carried in the data to be converted received by the segmented interface of the interface conversion device in the current clock cycle; and determining the number of start symbols and the number of end symbols according to the data segment valid flag.

[0069] In an exemplary embodiment, the data segment valid flag includes a start vector flag and an end vector flag; the process of determining the number of start symbols and the number of end symbols according to the data segment valid flag includes: determining the number of start symbols and the number of end symbols based on the start vector flag and the end vector flag.

[0070] In an exemplary embodiment, the process of determining the number of start symbols and the number of end symbols based on the start vector flag and the end vector flag includes: performing a bitwise OR operation on the start vector flag and the end vector flag respectively to obtain the number of start symbols and the number of end symbols.

[0071] In an exemplary embodiment, the information further includes the positional relationship between the start symbol and the end symbol; the process of determining the positional relationship between the start symbol and the end symbol according to the data segment valid flag includes: determining the start symbol position and the end symbol position according to the data segment valid flag; when the start symbol position is greater than the end symbol position, the positional relationship is that the end symbol position is ahead of the start symbol position; when the start symbol position is less than the end symbol position, the positional relationship is that the end symbol position lags behind the start symbol position.

[0072] In an exemplary embodiment, the process of determining the next jump state of the state machine based on the information and the current state of the state machine includes: when the global valid flag carried in the data to be converted corresponds to a valid state, determining the next jump state of the state machine based on the information and the current state of the state machine.

[0073] In an exemplary embodiment, the process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next-hop state includes: if the current state is the idle state, controlling the first channel of the interface conversion device to perform the corresponding data processing operation; the data processing operation is to output the current packet data, cache the current packet data, or cache the next packet data.

[0074] In an exemplary embodiment, the process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next-hop state includes: if the current state is a non-idle state and the next-hop state is a first target jump state corresponding to not including a start symbol and an end symbol, controlling the first channel of the interface conversion device to output the current packet data and cache the next packet data.

[0075] In an exemplary embodiment, the process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next-hop state includes: if the current state is a non-idle state and the next-hop state is a second target jump state corresponding to including at least one start symbol and / or at least one end symbol, controlling the first channel and / or the second channel of the interface conversion device to perform the corresponding data processing operation according to the next-hop state and the current channel activation mode.

[0076] In an exemplary embodiment, the process of determining the current channel activation mode includes: determining the offset corresponding to the current packet data; determining the output mode of the current packet data according to the offset and the end symbol position of the next packet data; determining the current channel activation mode based on the output mode.

[0077] In an exemplary embodiment, if the current state is a non-idle state, the process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next-hop state and the current channel activation mode includes: if the current state is a first type of non-idle state, controlling the first channel of the interface conversion device to perform the corresponding first data processing operation according to the next-hop state and the current channel activation mode and / or controlling the second channel of the interface conversion device to perform the corresponding second data processing operation; the first data processing operation includes outputting the current packet data, or outputting the current packet data and caching the remaining data of the current packet, or outputting the current packet data and caching the next packet data; the second data processing operation includes caching the next packet data, or outputting the next packet data, or outputting the next packet data and caching the next packet of the next packet data.

[0078] In an exemplary embodiment, when the current state is a non-idle state, the process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next transition state and the current channel activation mode includes: when the current state is a first type of non-idle state, controlling the first channel of the interface conversion device to perform a corresponding third data processing operation and / or controlling the second channel of the interface conversion device to perform a corresponding fourth data processing operation according to the next transition state and the current channel activation mode; the third data processing operation includes outputting the next packet of data, or caching the next packet of data, or outputting the end data of the previous packet, or outputting the previous packet of data, or outputting the next packet of data and caching the next packet of the next packet of data; the fourth data processing operation includes outputting the next packet of data, or caching the next packet of data, or outputting the next packet of data and caching the next packet of the next packet of data.

[0079] An embodiment of the present invention also provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above embodiments of the interface conversion method.

[0080] An embodiment of the present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above embodiments of the interface conversion method when running.

[0081] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs, etc., various media that can store computer programs.

[0082] An embodiment of the present invention also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments of the interface conversion method are implemented.

[0083] An embodiment of the present invention also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments of the interface conversion method are implemented.

[0084] For the descriptions of the features in the corresponding embodiments of the interface conversion system, computer program product, electronic device, and computer-readable storage medium, reference may be made to the relevant descriptions of the corresponding embodiments of the interface conversion method, which will not be elaborated here one by one.

[0085] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present invention.

[0086] The above has introduced in detail an interface conversion method, device, product, and computer-readable storage medium provided by the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. An interface conversion method, characterized in that, including: determining information corresponding to a start symbol and an end symbol in data to be converted received by a segmented interface of an interface conversion device during a current clock cycle; the information includes the number of start symbols, the number of end symbols, and the positional relationship between the start symbol and the end symbol; determining a next transition state of the state machine based on the information and the current state of the state machine; controlling a first channel and / or a second channel of the interface conversion device to perform corresponding data processing operations according to the next transition state, so as to output converted data through the first channel and / or the second channel, and the converted data meets the transmission requirements of the streaming interface of the interface conversion device; The process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next transition state includes: if the current state is an idle state, controlling the first channel of the interface conversion device to perform corresponding data processing operations according to the next transition state; the data processing operation is to output current packet data, cache current packet data, or cache next packet data; if the current state is a non-idle state and the next transition state is a first target transition state corresponding to not including a start symbol and an end symbol, controlling the first channel of the interface conversion device to output current packet data and cache next packet data.

2. The interface conversion method according to claim 1, characterized in that The process of determining information corresponding to a start symbol and an end symbol in data to be converted received by a segmented interface of an interface conversion device during a current clock cycle includes: parsing a data segment valid flag carried in the data to be converted received by the segmented interface of the interface conversion device during the current clock cycle; determining the number of start symbols and the number of end symbols according to the data segment valid flag.

3. The interface conversion method according to claim 2, wherein The data segment valid flag includes a start vector flag and an end vector flag; The process of determining the number of start symbols and the number of end symbols according to the data segment valid flag includes: determining the number of start symbols and the number of end symbols based on the start vector flag and the end vector flag.

4. The interface conversion method according to claim 3, characterized in that The process of determining the number of start symbols and the number of end symbols based on the start vector flag and the end vector flag includes: performing a bitwise OR operation on the start vector flag and the end vector flag respectively to obtain the number of start symbols and the number of end symbols.

5. The interface conversion method according to claim 2, wherein The process of determining the positional relationship between the start symbol and the end symbol according to the data segment valid flag includes: determining a start symbol position and an end symbol position according to the data segment valid flag; when the start symbol position is greater than the end symbol position, the positional relationship is that the end symbol position is ahead of the start symbol position; when the start symbol position is less than the end symbol position, the positional relationship is that the end symbol position lags behind the start symbol position.

6. The interface conversion method according to claim 1, wherein The process of determining a next transition state of the state machine based on the information and the current state of the state machine includes: when the global valid flag carried in the data to be converted corresponds to a valid state, determining a next transition state of the state machine based on the information and the current state of the state machine.

7. The interface conversion method according to any one of claims 1-6, characterized in that The process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next-hop transition state includes: If the current state is a non-idle state, and the next-hop transition state is a second target transition state corresponding to at least one start symbol and / or at least one end symbol, control the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next-hop transition state and the current channel activation mode.

8. The interface conversion method according to claim 7, wherein The process of determining the current channel activation mode includes: Determine the offset corresponding to the current packet data; Determine the output mode of the current packet data according to the offset and the end symbol position of the next packet of data; Determine the current channel activation mode based on the output mode.

9. The interface conversion method according to claim 7, characterized in that, If the current state is a non-idle state, the process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next-hop transition state and the current channel activation mode includes: If the current state is a first type of non-idle state, control the first channel of the interface conversion device to perform a corresponding first data processing operation and / or control the second channel of the interface conversion device to perform a corresponding second data processing operation according to the next-hop transition state and the current channel activation mode; the first data processing operation includes outputting the current packet data, or outputting the current packet data and caching the remaining data of the current packet, or outputting the current packet data and caching the next packet of data; the second data processing operation includes caching the next packet of data, or outputting the next packet of data, or outputting the next packet of data and caching the next packet of data after the next packet of data.

10. The interface conversion method according to claim 7, characterized in that If the current state is a non-idle state, the process of controlling the first channel and / or the second channel of the interface conversion device to perform corresponding data processing operations according to the next-hop transition state and the current channel activation mode includes: If the current state is a first type of non-idle state, control the first channel of the interface conversion device to perform a corresponding third data processing operation and / or control the second channel of the interface conversion device to perform a corresponding fourth data processing operation according to the next-hop transition state and the current channel activation mode; the third data processing operation includes outputting the next packet of data, or caching the next packet of data, or outputting the end data of the previous packet, or outputting the previous packet of data, or outputting the next packet of data and caching the next packet of data after the next packet of data; the fourth data processing operation includes outputting the next packet of data, or caching the next packet of data, or outputting the next packet of data and caching the next packet of data after the next packet of data.

11. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by a processor, the steps of the interface conversion method according to any one of claims 1 to 10 are implemented.

12. An electronic device, characterized in that, Including: A memory for storing a computer program; A processor for implementing the steps of the interface conversion method according to any one of claims 1 to 10 when executing the computer program.

13. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the interface conversion method according to any one of claims 1 to 10 are implemented.

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