Display device

Abstract

A display device is provided. The display device includes: a substrate on which a pixel electrode is disposed; a light emitting element on the pixel electrode; and a connection electrode layer including a plurality of connection electrodes between the pixel electrode and the light emitting element, the plurality of connection electrodes being spaced apart from each other.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0187307, filed with the Korean Intellectual Property Office on December 20, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] This disclosure relates to a display device. Background art

[0004] With the development of multimedia, the importance of display devices is increasing. For this reason, various types of display devices such as organic light - emitting diode (OLED) displays and liquid crystal displays (LCDs) are being used.

[0005] A display device for displaying an image includes a display panel, such as an organic light - emitting display panel or a liquid crystal display panel. Among them, a light - emitting display panel may include light - emitting elements, such as light - emitting diodes (LEDs), organic light - emitting diodes (OLEDs) using organic materials as light - emitting materials, inorganic light - emitting diodes using inorganic materials as light - emitting materials, etc.

[0006] Aspects and features of embodiments of the present disclosure will provide a display device having an improved bonding yield between a light - emitting element and a pixel electrode.

[0007] However, the aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art from the present disclosure. Summary of the invention

[0008] According to one or more embodiments, a display device includes: a substrate on which a pixel electrode is disposed; a light - emitting element on the pixel electrode; and a plurality of connection electrodes between the pixel electrode and the light - emitting element, the plurality of connection electrodes being spaced apart from each other.

[0009] In one or more embodiments, each of the plurality of connection electrodes contacts the light - emitting element at different points.

[0010] In one or more embodiments, the light - emitting element includes a protective layer having a plurality of through - holes on at least one side of the light - emitting element, wherein the plurality of connection electrodes contact the light - emitting element through the plurality of through - holes.

[0011] In one or more embodiments, the width of one of the plurality of through - holes is less than or equal to the width of one of the plurality of connection electrodes.

[0012] In one or more embodiments, the plurality of connection electrodes are spaced apart from the edge of the light - emitting element.

[0013] In one or more embodiments, the plurality of connection electrodes have a circular or polygonal cross-section.

[0014] In one or more embodiments, the plurality of connection electrodes include a first connection electrode, a second connection electrode, a third connection electrode, and a fourth connection electrode, wherein the first connection electrode, the second connection electrode, the third connection electrode, and the fourth connection electrode are arranged radially symmetrically with respect to each other.

[0015] In one or more embodiments, the plurality of connection electrodes further include a fifth connection electrode, wherein the first connection electrode, the second connection electrode, the third connection electrode, and the fourth connection electrode are arranged along a circumference centered on the fifth connection electrode.

[0016] In one or more embodiments, each of the plurality of connection electrodes includes a reflective portion in contact with the light-emitting element and a connection portion on one surface of the reflective portion, wherein the reflective portion includes a metal having a higher reflectivity than the reflectivity of the connection portion.

[0017] In one or more embodiments, the light-emitting element includes a current diffusion layer, a first semiconductor layer, an active layer, and a second semiconductor layer, wherein the current diffusion layer, the first semiconductor layer, the active layer, and the second semiconductor layer are sequentially stacked, and the current diffusion layer is closer to one of the plurality of connection electrodes than the first semiconductor layer.

[0018] In one or more embodiments, the display device further includes a common electrode on the light-emitting element.

[0019] According to one or more embodiments, a display device includes: a substrate on which a pixel electrode is provided; a light-emitting element on the pixel electrode; and a connection electrode between the pixel electrode and the light-emitting element, the connection electrode having a main body portion at the center and a plurality of branch portions extending outward from the main body portion.

[0020] In one or more embodiments, the main body portion and the plurality of branch portions are integral.

[0021] In one or more embodiments, the light-emitting element includes a protective layer having a through hole on at least one side of the light-emitting element, wherein the connection electrode contacts the light-emitting element through the through hole.

[0022] In one or more embodiments, the width of the through hole is less than or equal to the width of the connection electrode.

[0023] In one or more embodiments, the plurality of branch portions are spaced apart from the edge of the light-emitting element.

[0024] In one or more embodiments, the plurality of branch portions include a first branch portion, a second branch portion, a third branch portion, and a fourth branch portion, and the plurality of branch portions extend in four directions.

[0025] In one or more embodiments, the connection electrode includes a reflective portion in contact with the light-emitting element and a connection portion on one surface of the reflective portion, wherein the reflective portion includes a metal having a reflectivity higher than that of the connection portion.

[0026] In one or more embodiments, the light-emitting element includes a current diffusion layer, a first semiconductor layer, an active layer, and a second semiconductor layer, wherein the current diffusion layer, the first semiconductor layer, the active layer, and the second semiconductor layer are sequentially stacked, and the current diffusion layer is closer to the connection electrode than the first semiconductor layer.

[0027] In one or more embodiments, the display device further includes a common electrode on the light-emitting element.

[0028] Aspects and features of embodiments of the present disclosure will provide a display device having improved color purity and brightness.

[0029] The display device according to one or more embodiments forms a plurality of connection electrodes on the bottom surface of the light-emitting element, so that the light-emitting element can be stably connected to the pixel electrode without falling down during the bonding process. Therefore, the bonding yield of the light-emitting element can be improved, and the color purity and brightness can be improved.

[0030] In addition, by distributing a plurality of connection electrodes on one surface of the light-emitting element, current diffusion can be improved by dispersing the contact between the connection electrode and the light-emitting element.

[0031] However, the effects of the present disclosure are not limited to the foregoing effects, and various other effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0033] Figure 2 is a layout view showing a display device according to one or more embodiments.

[0034] Figure 3 is a block diagram showing a display device according to one or more embodiments.

[0035] Figure 4 is an equivalent circuit diagram showing a sub-pixel according to one or more embodiments.

[0036] Figure 5It is an equivalent circuit diagram showing sub-pixels according to one or more embodiments.

[0037] Figure 6 It is a layout diagram showing a plurality of pixels in a display area according to one or more embodiments.

[0038] Figure 7 It is shown along Figure 6 A cross-sectional view of the display device taken along line I1-I1'.

[0039] Figure 8 It is a perspective view of a light-emitting element according to one or more embodiments.

[0040] Figure 9 It is Figure 7 An enlarged view of region A of Figure 8 A cross-sectional view of the display device taken along line II-II'.

[0041] Figure 10 It is according to one or more embodiments of Figure 7 An enlarged view of region A.

[0042] Figure 11 It is a plan view of a light-emitting element and a connection electrode according to one or more embodiments.

[0043] Figure 12 It is Figure 11 A perspective view of the light-emitting element and the connection electrode of

[0044] Figure 13 It is a plan view of a light-emitting element and a connection electrode according to one or more embodiments.

[0045] Figure 14 It is Figure 13 A perspective view of the light-emitting element and the connection electrode of

[0046] Figure 15 It is a perspective view of a light-emitting element and a connection electrode, illustrating defects that occur when a single connection electrode is provided on the light-emitting element.

[0047] Figure 16 It is a perspective view showing the bonding defect of light-emitting elements bonded by one connection electrode.

[0048] Figures 17 to 29 It is a diagram showing a method of manufacturing a display device according to one or more embodiments.

[0049] Figure 30 It is an exemplary diagram schematically showing a virtual reality device including a display device according to one or more embodiments.

[0050] Figure 31It is an exemplary diagram schematically showing an intelligent device including a display device according to one or more embodiments.

[0051] Figure 32 It is a diagram schematically showing an example of a vehicle including a display device according to one or more embodiments.

[0052] Figure 33 It is a diagram schematically showing an example of a transparent display device including a display device according to one or more embodiments. Detailed embodiments

[0053] Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limited. Throughout the present disclosure, the same reference numerals indicate the same components. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

[0054] To describe the embodiments of the present disclosure, parts irrelevant to the description may not be provided.

[0055] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it may be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, no intervening element may be present.

[0056] In addition, the phrase “in a plan view” means when observing an object part from above, and the phrase “in a schematic cross-sectional view” means when observing a schematic cross-section taken by vertically cutting the object part from the side. The term “overlap” or “overlapped” means that a first object may be above or below a second object, or on one side of the second object, and vice versa. Additionally, the term “overlap” may include laminating, stacking, facing or facing towards, extending over, covering or partially covering, or any other suitable term as understood and appreciated by those of ordinary skill in the art. The expression “not overlapping with...” may include meanings such as “spaced apart from...”, “separated from...”, or “set beside...” or “offset from...” or any other suitable equivalent as understood and appreciated by those of ordinary skill in the art. The terms “facing” and “facing towards” may mean that a first object may be directly or indirectly opposite a second object. In the case where a third object is interposed between the first object and the second object, the first object and the second object may be understood as being indirectly opposite each other but still facing each other.

[0057] For ease of description, in this document, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device during use or operation. For example, in the case where the device shown in the figure is flipped, a device located "below" or "beneath" another device may be positioned "above" the other device. Thus, the illustrative term "below" can include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatial relative terms may be interpreted differently depending on the orientation.

[0058] When an element is referred to as being "connected" or "coupled" to another element, the element may be "directly connected" or "directly coupled" to the other element, or "electrically connected" or "electrically coupled" to the other element, and one or more intermediate elements may be interposed therebetween. It will be further understood that when the terms "comprise", "comprises", "has", "have", "having", "include" and / or "includes" are used, they may specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components and / or any combination thereof.

[0059] It will be understood that although terms such as "first", "second", "third", etc. may be used in this document to describe various elements, these elements should not be limited by these terms. For convenience of description and interpretation, these terms are used to distinguish one element from another. For example, when discussing a "first element" in the specification, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner without departing from the teachings herein.

[0060] In view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation range of a particular value determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0061] In this disclosure and the claims, for purposes of their meaning and interpretation, the term "and / or" is intended to encompass any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in the sense of a conjunctive or disjunctive connective and can be understood as being equivalent to "and / or". In the specification and claims, for purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0062] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless clearly defined herein.

[0063] Taking the present disclosure as a whole, one of ordinary skill in the art will understand that each suitable feature of the various embodiments of the present disclosure can be partially or fully combined or combined with each other, and can interact technically and operate in various suitable ways, and each embodiment can be implemented independently of each other or in combination with each other in any suitable manner, unless otherwise stated or implied.

[0064] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0065] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0066] Reference Figure 1 , the display device 10 is a device for displaying video or still images such as a mobile phone, a smart phone, a tablet personal computer, and a portable electronic device (such as a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigator, and an ultra-mobile PC (UMPC)), and a display screen for various products such as a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IOT) device.

[0067] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes (OLEDs), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a miniaturized light-emitting display device using micro or nano light-emitting diodes (micro LED or nano LED). Hereinafter, the description focuses on the fact that the display device 10 is a micro light-emitting display device, but the present disclosure is not limited thereto. On the other hand, the micro light-emitting diodes are hereinafter referred to as light-emitting diodes for ease of explanation.

[0068] The display device 10 includes a display panel 100, a display driving circuit 250, a circuit board 300, and a power supply circuit 500.

[0069] The display panel 100 may be formed as a planar rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 meet may not be rounded to have an appropriate curvature (e.g., a predetermined curvature), or may be formed as right angles. The planar shape of the display panel 100 is not limited to rectangular, and may be formed as other polygons, circular, or elliptical shapes. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may include curved portions having a constant or varying curvature formed at the left and right ends of the display panel 100. Additionally, the display panel 100 may be formed to be flexible so as to be bendable, curvable, foldable, and / or rollable.

[0070] The display panel 100 (e.g., Figure 7 the substrate SUB) may include a main region MA and a sub-region SBA.

[0071] The main region MA may include a display region DA for displaying an image and a non-display region NDA, which is a peripheral region of the display region DA and surrounds the display region DA along the edge or periphery of the display region DA (e.g., around the display region DA). The display region DA may include a plurality of pixels for displaying an image. For example, a pixel may include a first sub-pixel emitting a first light, a second sub-pixel emitting a second light, and a third sub-pixel emitting a third light.

[0072] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. Although Figure 1The expanded sub-region SBA is shown, but the sub-region SBA can be bent, and in this case, the sub-region SBA can be disposed on the bottom surface of the display panel 100. When the sub-region SBA is bent, it can overlap with the main region MA in a third direction DR3, which is the thickness direction of the display panel 100. The display driving circuit 250 can be disposed in the sub-region SBA.

[0073] The display driving circuit 250 can generate signals and voltages for driving the display panel 100. The display driving circuit 250 can be formed as an integrated circuit (IC) and attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 250 can be attached to the circuit board 300 using a chip on film (COF) method.

[0074] The circuit board 300 can be attached to one end of the sub-region SBA of the display panel 100. In this way, the circuit board 300 can be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 can receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 can be a flexible printed circuit board (FPCB), a rigid printed circuit board (RPCB), or a flexible film such as a chip on film (COF).

[0075] The power supply circuit 500 (e.g., a power supply unit) can generate and / or provide multiple panel driving voltages according to an external power supply voltage. The power supply circuit 500 can be formed as an integrated circuit (IC) and attached to the circuit board 300 using the COF method.

[0076] Figure 2 is a layout diagram showing a display device according to one or more embodiments. Figure 2 The sub-region SBA is shown unfolded without being bent.

[0077] Reference Figure 2 , the display panel 100 can include a main region MA and a sub-region SBA.

[0078] The main region MA can include a display region DA for displaying an image and a non-display region NDA that is a peripheral region of the display region DA. The display region DA can occupy most of the main region MA. The display region DA can be placed at the center of the main region MA.

[0079] The display region DA can include a plurality of pixels PX for displaying an image, and each of the plurality of pixels PX can include a plurality of sub-pixels SPX. A pixel PX can be defined as a group of sub-pixels that is the smallest unit capable of presenting a white gray level.

[0080] The non-display area NDA may not be placed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be arranged around the display area DA (e.g., arranged to surround the display area DA). The non-display area NDA may be an edge area of the display panel 100.

[0081] The first scan driving unit (or first scan driving part) SDC1 and the second scan driving unit (or second scan driving part) SDC2 may be provided in the non-display area NDA. The first scan driving unit SDC1 is provided on one side (e.g., the left side) of the display panel 100, and the second scan driving unit SDC2 is provided on the other side (e.g., the right side) of the display panel 100. However, the present disclosure is not limited thereto. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may be electrically connected to the display driving circuit 250 through a scan fan-out line. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may receive a scan control signal from the display driving circuit 250, generate a scan signal according to the scan control signal, and output the scan signal to the scan line.

[0082] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 is less than the length of the main region MA in the first direction DR1, or may be substantially equal to the length of the main region MA in the first direction DR1. The sub-region SBA may be curved and may be provided at the lower part of the display panel 100. In this case, the sub-region SBA may overlap the main region MA in the third direction DR3.

[0083] The sub-region SBA may include a connection region CA, a pad region PA, and a bending region BA.

[0084] The connection region CA is a region that protrudes from one side of the main region MA in the second direction DR2. One side of the connection region CA may be in contact with the non-display area NDA of the main region MA, and the other side of the connection region CA may be in contact with the bending region BA.

[0085] The pad region PA is a region where the pad PD and the display driving circuit 250 are provided. The display driving circuit 250 may be attached to the driving pad of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pad PD of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad region PA may be in contact with the bending region BA.

[0086] The bent area BA is the area to be bent. When the bent area BA is bent, the pad area PA can be disposed below the connection area CA and below the main area MA (e.g., disposed below the connection area CA and below the main area MA in the thickness direction (e.g., the third direction DR3)). The bent area BA can be disposed between the connection area CA and the pad area PA. One side of the bent area BA can be in contact with the connection area CA, and the other side of the bent area BA can be in contact with the pad area PA.

[0087] The non-display power supply line NVSL can be disposed in the non-display area NDA, the connection area CA, the bent area BA, and the pad area PA.

[0088] The non-display power supply line NVSL can be disposed on four sides of the display area DA in the non-display area NDA. The non-display power supply line NVSL can be arranged around at least three sides of the display area DA (e.g., arranged to surround at least three sides of the display area DA). For example, the non-display power supply line NVSL can be around the left side, the top side, and the right side of the display area DA (e.g., can surround the left side, the top side, and the right side of the display area DA), and can be disposed on at least a part of the lower side. In addition, the non-display power supply line NVSL can be disposed outside the first scan driving unit SDC1 and outside the second scan driving unit SDC2. For example, the non-display power supply line NVSL can be disposed on the left side of the first scan driving unit SDC1 and on the right side of the second scan driving unit SDC2. The non-display power supply line NVSL can be disposed between the first scan driving unit SDC1 and the edge of the substrate SUB (e.g., see Figure 7 ), and can be disposed between the second scan driving unit SDC2 and the edge of the substrate SUB. Optionally, the non-display power supply line NVSL can overlap with the first scan driving unit SDC1 and the second scan driving unit SDC2.

[0089] The non-display power supply line NVSL can be disposed at the left and right edges of the connection area CA and the bent area BA. The non-display power supply line NVSL can be connected in the pad area PA to the pads PD adjacent to one side edge and the pads PD adjacent to the other side edge among the pads PD. The second driving voltage ( Figure 1 of 300) on the circuit board Figure 1 of 500) can be supplied to the non-display power supply line NVSL. Figure 3 of VSS).

[0090] Figure 3 is a block diagram showing a display device according to one or more embodiments.

[0091] Refer to Figure 3, the display area DA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL. According to one or more embodiments, each of the plurality of pixels PX includes a plurality of sub-pixels SPX.

[0092] The plurality of pixels PX may be arranged in a matrix form in a first direction DR1 and a second direction DR2. For example, the plurality of pixels PX may be arranged in rows and columns along the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL may extend in the first direction DR1 and may be arranged along the second direction DR2. The plurality of data lines DL may extend in the second direction DR2 and may be arranged along the first direction DR1. The plurality of scan lines SL may include a plurality of write scan lines GWL, a plurality of control scan lines GCL, a plurality of initialization scan lines GIL, and a plurality of bias scan lines GBL.

[0093] Each of the plurality of sub-pixels SPX may be connected to one write scan line GWL among the plurality of write scan lines GWL, one control scan line GCL among the plurality of control scan lines GCL, one initialization scan line GIL among the plurality of initialization scan lines GIL, one bias scan line GBL among the plurality of bias scan lines GBL, one emission control line EL among the plurality of emission control lines EL, and one data line DL among the plurality of data lines DL. A data voltage of the data line DL may be provided to each of the plurality of sub-pixels SPX according to a write scan signal of the write scan line GWL, and light may be emitted through a light-emitting element according to the data voltage.

[0094] The non-display area NDA includes a first scan driving unit SDC1, a second scan driving unit SDC2, and a display driving circuit 250.

[0095] Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may include a write scan signal output unit 611, a control scan signal output unit 612, an initialization scan signal output unit 613, a bias scan signal output unit 614, and a light emission signal output unit 615. Each of the write scan signal output unit 611, the control scan signal output unit 612, the initialization scan signal output unit 613, the bias scan signal output unit 614, and the light emission signal output unit 615 may receive a scan timing control signal SCS from the timing control circuit 251. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 251 and sequentially output it to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS and sequentially output it to the control scan line GCL. The initialization scan signal output unit 613 may generate an initialization scan signal according to the scan timing control signal SCS and sequentially output it to the initialization scan line GIL. The bias scan signal output unit 614 may generate a bias scan signal according to the scan timing control signal SCS and sequentially output it to the bias scan line GBL. The light emission signal output unit 615 may generate a light emission control signal according to the scan timing control signal SCS and sequentially output it to the emission control line EL.

[0096] The display driving circuit 250 includes a timing control circuit 251 and a data driving circuit 252.

[0097] The data driving circuit 252 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 251. The data driving circuit 252 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs them to the data line DL. In this case, the sub-pixel SPX is selected by the write scan signals of the first scan driving unit SDC1 and the second scan driving unit SDC2, and the data voltage may be provided to the selected sub-pixel SPX.

[0098] The timing control circuit 251 may receive digital video data DATA and a timing signal from an external source. The timing control circuit 251 may generate a scan timing control signal SCS and a data timing control signal DCS according to the timing signal to control the display panel 100. The timing control circuit 251 may output the scan timing control signal SCS to the first scan driving unit SDC1 and the second scan driving unit SDC2. The timing control circuit 251 may output the digital video data DATA and the data timing control signal DCS to the data driving circuit 252.

[0099] The data driving circuit 252 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 251.

[0100] The data driving circuit 252 may provide corresponding data signals (e.g., analog data voltages) to the sub-pixels SPX. For example, the data driving circuit 252 may convert the digital video data DATA into analog data voltages according to the data timing control signal DCS and output them to the data lines DL. The sub-pixels SPX may be selected by the write scan signals of the first scan driving unit SDC1 and the second scan driving unit SDC2, and the data signals may be provided to the selected sub-pixels SPX.

[0101] The power supply circuit 500 may generate a plurality of panel driving voltages according to an external power supply voltage. For example, the power supply circuit 500 may generate a first driving voltage VDD, a second driving voltage VSS, and a third driving voltage VINT, and may provide the first driving voltage VDD, the second driving voltage VSS, and the third driving voltage VINT to the display panel 100.

[0102] Figure 4 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments.

[0103] Reference Figure 4 , the sub-pixel SPX according to one or more embodiments may be connected to scan lines GWL, GIL, GCL, and GBL, an emission control line EL, and a data line DL. For example, the sub-pixel SPX may be connected to a write scan line GWL, an initialization scan line GIL, a control scan line GCL, a bias scan line GBL, an emission control line EL, and a data line DL.

[0104] The sub-pixel SPX according to one or more embodiments includes a driving transistor DT, a switching element, a capacitor C1, and a light-emitting element LE. The switching element includes a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6. The driving transistor DT, the switching element, and the capacitor C1 may be referred to as a pixel circuit. The pixel circuit may include a driving transistor DT, at least one switching transistor (e.g., ST1, ST2, ST3, ST4, ST5, and ST6), and a capacitor C1. In one or more embodiments, the pixel circuit may include the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 as switching transistors. The configuration of the pixel circuit is not limited to Figure 4 and Figure 5 the embodiments of, and may be changed in various ways.

[0105] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls the drain-source current (e.g., hereinafter referred to as "driving current Ids") flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode.

[0106] The light-emitting element LE may be a micro light-emitting diode.

[0107] The light-emitting element LE emits light according to the driving current Ids. The amount of light emitted from the light-emitting element LE may be proportional to the driving current Ids. The anode electrode of the light-emitting element LE is connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode may be connected to the second power supply line VSL to which the second power supply voltage is applied. A parasitic capacitance Cel may be formed between the anode electrode and the cathode electrode of the light-emitting element LE.

[0108] A capacitor C1 is formed between the gate electrode of the driving transistor DT and the first power supply line VDL to which the first power supply voltage is applied. The first power supply voltage may be at a level higher than the second power supply voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode may be connected to the first power supply line VDL.

[0109] As Figure 4 shown, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6, as well as the driving transistor DT, may all be formed as P-type metal oxide semiconductor field effect transistors (P-type MOSFETs). In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT may be formed of polysilicon.

[0110] The gate electrode of the second transistor ST2 may be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 may be connected to the control scan line GCL. The gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. The gate electrodes of the fifth transistor ST5 and the sixth transistor ST6 may be connected to the emission control line EL. Since the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as P-type MOSFETs, they can be turned on when a scan signal with a low gate voltage and an emission signal (e.g., an emission signal with a low voltage) are respectively applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emission control line EL. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL.

[0111] For example, the first transistor ST1 may be connected between the second electrode and the gate electrode of the driving transistor DT. The second transistor ST2 may be connected between the data line DL and the first electrode of the driving transistor DT. The third transistor ST3 may be connected between the initialization voltage line VIL and the gate electrode of the driving transistor DT. The fourth transistor ST4 may be connected between the initialization voltage line VIL and the light-emitting element LE. The fifth transistor ST5 may be connected between the first power supply line VDL and the first electrode of the driving transistor DT. The sixth transistor ST6 may be connected between the second electrode of the driving transistor DT and the light-emitting element LE.

[0112] Figure 5 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments.

[0113] Reference Figure 5 , the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of P-type MOSFETs, and the first transistor ST1 and the third transistor ST3 may be formed as N-type MOSFETs. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as P-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as N-type MOSFETs may be formed of an oxide semiconductor. In this case, the transistors formed of polysilicon and the transistors formed of the oxide semiconductor may be arranged in different layers.

[0114] Since the first transistor ST1 and the third transistor ST3 are formed as N-type MOSFETs, the first transistor ST1 can be turned on when a control scan signal with a high gate voltage is applied to the control scan line GCL, and the third transistor ST3 can be turned on when an initialization scan signal is applied to the initialization scan line GIL. In comparison, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as P-type MOSFETs, so they can be turned on when scan signals and emission signals with low gate voltages (e.g., emission signals with low voltages) are respectively applied to the write scan line GWL, the bias scan line GBL, and the emission control line EL.

[0115] Optionally, Figure 4 the fourth transistor ST4 in [[ ]] can be formed of an N-type MOSFET. In this case, the active layer of each of the fourth transistors ST4 can be formed of an oxide semiconductor. When the fourth transistor ST4 is formed of an N-type MOSFET, it can be turned on when a bias scan signal with a high gate voltage is applied to the bias scan line GBL.

[0116] In one or more embodiments, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT can all be formed as N-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT can be formed of an oxide semiconductor.

[0117] Figure 6 is a layout diagram showing a plurality of pixels in a display area according to one or more embodiments.

[0118] Referring to [[ ]] Figure 6 , each of the plurality of pixels PX in the display area DA can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0119] The plurality of pixels PX can be arranged in a matrix form. In each of the plurality of pixels PX, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be arranged along a first direction DR1.

[0120] The first subpixel SPX1 may emit light of a first color, the second subpixel SPX2 may emit light of a second color, and the third subpixel SPX3 may emit light of a third color. Here, the light of the first color may be light in a red wavelength band, the light of the second color may be light in a green wavelength band, and the light of the third color may be light in a blue wavelength band. For example, the blue wavelength band may indicate that the main peak wavelength of the light is contained in a wavelength band of about 370nm to 460nm, the green wavelength band may indicate that the main peak wavelength of the light is contained in a wavelength band of about 480nm to 560nm, and the red wavelength band may indicate that the main peak wavelength of the light is contained in a wavelength band of about 600nm to 750nm.

[0121] Each of the first to third sub-pixels SPX1 to SPX3 may include a pixel electrode PXE and one or more light emitting elements LE.

[0122] Each of the first pixel electrode PXE1 , the second pixel electrode PXE2 , and the third pixel electrode PXE3 has a rectangular planar shape having short sides in the first direction DR1 and long sides in the second direction DR2 . However, the present disclosure is not limited thereto.

[0123] A plurality of light emitting elements LE may be arranged to overlap the pixel electrodes PXE1 , PXE2 , and PXE3 .

[0124] The first pixel electrode PXE1 may be electrically connected to the fourth transistor ( Figure 4 and Figure 5 ST4) of the first electrode and the sixth transistor ( Figure 4 and Figure 5 The second pixel electrode PXE2 may be electrically connected to the fourth transistor (ST6) of the second sub-pixel SPX2 through the second connection hole CT2. Figure 4 and Figure 5 ST4) of the first electrode and the sixth transistor ( Figure 4 and Figure 5 The third pixel electrode PXE3 may be electrically connected to the fourth transistor (ST6) of the third sub-pixel SPX3 through the third connection hole CT3. Figure 4 and Figure 5 ST4) of the first electrode and the sixth transistor ( Figure 4 and Figure 5 The second electrode of ST6).

[0125] A plurality of light-emitting elements LE may be disposed on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. The same number of light-emitting elements LE may be disposed on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. For example, two light-emitting elements LE may be disposed on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. The plurality of light-emitting elements LE may emit third light, i.e., light in a blue wavelength band, but is not limited thereto.

[0126] Figure 7 is a cross-sectional view of a display device taken along the line I1-I1'. Figure 6 is a cross-sectional view of a display device taken along the line I1-I1'. Figure 8 is a perspective view of a light-emitting element according to one or more embodiments. Figure 9 is Figure 7 an enlarged view of region A of Figure 8 and a cross-sectional view of a display device taken along the line II-II'. Figure 10 is an enlarged view of region A of Figure 7 according to one or more embodiments.

[0127] Refer to Figure 7 and Figure 8 , the substrate SUB may be made of an insulating material such as glass, polymer resin, etc. If the substrate SUB is made of a polymer resin, it may be a flexible substrate that can be stretched. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0128] The barrier film BR may be disposed on the substrate SUB. The barrier film BR is a film for protecting the transistors of the thin-film transistor layer TFTL and the light-emitting elements LE of the light-emitting element layer EML from moisture that penetrates through the substrate SUB (which is easily permeated by moisture). The barrier film BR may be composed of a plurality of inorganic films stacked alternately. For example, the barrier film BR may be formed as a multilayer of an alternating inorganic film of one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0129] The first thin-film transistor TFT1 may be disposed on the barrier film BR. The first thin-film transistor TFT1 may be Figure 5 the fourth transistor ST4 or the sixth transistor ST6 shown in

[0130] The first active layer ACT1 of the first thin-film transistor TFT1 may be disposed on the barrier film BR. The first active layer ACT1 of the first thin-film transistor TFT1 may include polysilicon, single-crystalline silicon, low-temperature polysilicon, and / or amorphous silicon.

[0131] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region overlapping with the first gate electrode G1 in a third direction DR3, and the third direction DR3 is the thickness direction of the substrate SUB. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions that do not overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 may be regions in which ions are doped into the silicon semiconductor to make it conductive.

[0132] The first gate insulating film 131 may be disposed on the first channel region CHA1, the first source region S1, and the first drain region D1 of the first thin film transistor TFT1, and on the barrier film BR. The first gate insulating film 131 may be formed of an inorganic film (for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0133] The first gate metal layer GTL1 may be disposed on the first gate insulating film 131. The first gate metal layer GTL1 may include the first gate electrode G1 and the first capacitor electrode CAE1 of the first thin film transistor TFT1. The first gate electrode G1 may overlap with the first active layer ACT1 in the third direction DR3. In Figure 7 it is shown that the first gate electrode G1 and the first capacitor electrode CAE1 are spaced apart from each other (for example, arranged to be separated from each other), but the first gate electrode G1 and the first capacitor electrode CAE1 may be connected to each other. The first gate metal layer GTL1 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys.

[0134] The second gate insulating film 132 may be disposed on the first gate electrode G1, the first capacitor electrode CAE1, and the first gate insulating film 131 of the first thin film transistor TFT1. The second gate insulating film 132 may be formed of an inorganic film (for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0135] The second gate metal layer GTL2 may be disposed on the second gate insulating film 132. The second gate metal layer GTL2 may include the second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap with the first capacitor electrode CAE1 in the third direction DR3. Because the second gate insulating film 132 has a suitable dielectric constant (for example, a predetermined dielectric constant), the capacitor (Figure 5 C1) in [the above] can be formed by a first capacitor electrode CAE1, a second capacitor electrode CAE2, and a second gate insulating film 132 disposed therebetween. The second gate metal layer GTL2 can be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or its alloy.

[0136] The first interlayer insulating film 141 can be disposed on the second capacitor electrode CAE2 and the second gate insulating film 132. The first interlayer insulating film 141 can be formed of an inorganic film (such as, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0137] The second thin film transistor TFT2 can be disposed on the first interlayer insulating film 141. The second thin film transistor TFT2 can be Figure 5 the first transistor ST1 or the third transistor ST3 shown [above]. The second thin film transistor TFT2 can include a second active layer ACT2 and a second gate electrode G2.

[0138] The second active layer ACT2 of the second thin film transistor TFT2 can be disposed on the first interlayer insulating film 141. The second active layer ACT2 can include an oxide semiconductor. For example, the second active layer ACT2 can include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), and / or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0139] The second active layer ACT2 can include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 can be a region overlapping with the second gate electrode G2 in the third direction DR3. The second source region S2 can be disposed on one side of the second channel region CHA2, and the second drain region D2 can be disposed on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 can be regions not overlapping with the second gate electrode G2 in the third direction DR3. The second source region S2 and the second drain region D2 can be regions where the oxide semiconductor is reduced to make it conductive.

[0140] The third gate insulating film 133 can be disposed on the second active layer ACT2 of the second thin film transistor TFT2 and the first interlayer insulating film 141. The third gate insulating film 133 can be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0141] The third gate metal layer GTL3 may be disposed on the third gate insulating film 133. The third gate metal layer GTL3 may include the second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may overlap with the second active layer ACT2 in the third direction DR3. The third gate metal layer GTL3 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or its alloys.

[0142] The second interlayer insulating film 142 may be disposed on the second gate electrode G2 of the second thin film transistor TFT2 and the third gate insulating film 133. The second interlayer insulating film 142 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0143] The first data metal layer DTL1 may be disposed on the second interlayer insulating film 142. The first data metal layer DTL1 may include a first source connection electrode SBE3, a second source connection electrode SBE1, and a third source connection electrode SBE2. The first source connection electrode SBE3 may be connected to the first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 that passes through the first gate insulating film 131, the second gate insulating film 132, the first interlayer insulating film 141, the third gate insulating film 133, and the second interlayer insulating film 142. The second source connection electrode SBE1 may be connected to the second source region S2 of the second active layer ACT2 through a second source connection contact hole BCT1 that passes through the second interlayer insulating film 142 and the third gate insulating film 133. The third source connection electrode SBE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third source connection contact hole BCT2 that passes through the second interlayer insulating film 142 and the third gate insulating film 133. The first data metal layer DTL1 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or its alloys. For example, the first data metal layer DTL1 may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0144] A first organic layer 160 may be disposed on the first source connection electrode SBE3, the second source connection electrode SBE1, the third source connection electrode SBE2, and on the second interlayer insulating film 142 to planarize the steps caused by the first thin film transistor TFT1 and the second thin film transistor TFT2. The first organic layer 160 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0145] The second data metal layer DTL2 may be disposed on the first organic layer 160. The second data metal layer DTL2 may include a fourth source connection electrode SBE4. The fourth source connection electrode SBE4 may be connected to the first source connection electrode SBE3 through a second pixel contact hole PCT2 passing through the first organic layer 160. The second data metal layer DTL2 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys. For example, the second data metal layer DTL2 may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0146] The second organic layer 180 may be disposed on the fourth source connection electrode SBE4 and the first organic layer 160. The second organic layer 180 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0147] The light-emitting element layer EML may be disposed on the second organic layer 180. The light-emitting element layer EML may include pixel electrodes PXE1, PXE2, and PXE3, a light-emitting element LE, a common electrode CE, and a connection electrode BE.

[0148] The pixel electrode layer PXL may be disposed on the second organic layer 180. The pixel electrode layer PXL may include a first pixel electrode PXE1, a second pixel electrode PXE2, and a third pixel electrode PXE3. In the first sub-pixel SPX1, the first pixel electrode PXE1 may be connected to the fourth source connection electrode SBE4 through a first connection hole ( Figure 6 CT1 in) passing through the second organic layer 180. In the second sub-pixel SPX2, the second pixel electrode PXE2 may be connected to the fourth source connection electrode SBE4 through a second connection hole ( Figure 6 CT2 in) passing through the second organic layer 180. In the third sub-pixel SPX3, the third pixel electrode PXE3 may be connected to the fourth source connection electrode SBE4 through a third connection hole ( Figure 6 CT3 in) passing through the second organic layer 180.

[0149] In the first sub-pixel SPX1, the first pixel electrode PXE1 may be connected to the first source region S1 or the first drain region D1 of the first thin-film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Therefore, the voltage controlled by the first thin-film transistor TFT1 in the first sub-pixel SPX1 may be applied to the first pixel electrode PXE1.

[0150] In addition, in the second sub-pixel SPX2, the second pixel electrode PXE2 can be connected to the first source region S1 or the first drain region D1 of the first thin-film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Therefore, the voltage controlled by the first thin-film transistor TFT1 in the second sub-pixel SPX2 can be applied to the second pixel electrode PXE2.

[0151] In addition, in the third sub-pixel SPX3, the third pixel electrode PXE3 can be connected to the first source region S1 or the first drain region D1 of the first thin-film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Therefore, the voltage controlled by the first thin-film transistor TFT1 in the third sub-pixel SPX3 can be applied to the third pixel electrode PXE3.

[0152] The pixel electrode layer PXL can be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys. For example, the pixel electrode layer PXL can be made of copper (Cu) with low surface resistance to reduce the resistance of each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3.

[0153] The bank layer BNL can be provided to cover the edges of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. The bank layer BNL can be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The bank layer BNL can include a light-blocking material to prevent the light from the light-emitting element LE of one sub-pixel from traveling to an adjacent sub-pixel. For example, the bank layer BNL can include an inorganic black pigment such as carbon black or an organic black pigment.

[0154] The light-emitting element LE can be provided on the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 that are exposed and not covered by the bank layer BNL. One or more light-emitting elements LE can be provided on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3.

[0155] As Figure 7As shown, the light-emitting element LE can be disposed in each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. The light-emitting element LE can be a vertical light-emitting diode element extending in the third direction DR3. That is, the length of the light-emitting element LE in the third direction DR3 can be greater than the length in the horizontal direction. The length in the horizontal direction indicates the length in the first direction DR1 and / or the length in the second direction DR2. For example, the length of the light-emitting element LE in the third direction DR3 can be about 1 μm to 5 μm. However, the present disclosure is not limited thereto, and the length of the light-emitting element LE in the third direction DR3 can be equal to or less than the length in the horizontal direction.

[0156] The light-emitting element LE can be a micro light-emitting diode element. Refer to Figure 8 and Figure 9 , the connection electrode layer BEL can be disposed between the light-emitting element LE and the pixel electrode layer PXL, and the light-emitting element LE can include a current spreading layer CSL, a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2 sequentially stacked in the thickness direction (i.e., the third direction DR3) of the substrate SUB. In one or more embodiments, an electron blocking layer can be disposed between the first semiconductor layer SEM1 and the active layer MQW. In addition, a superlattice layer can be disposed between the active layer MQW and the second semiconductor layer SEM2. In addition, the current spreading layer CSL can be omitted.

[0157] In addition, the light-emitting element LE can include a protective layer INS around at least a portion of the current spreading layer CSL, the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 (e.g., surrounding the at least a portion).

[0158] The light-emitting element LE can have a cylindrical shape, a disk shape, and / or a rod shape in which the height is longer than the width. However, it is not limited thereto, and the light-emitting element LE can be shaped like a rod, a wire, a tube, etc., and / or can have a polygonal column shape such as a cube, a cuboid, and / or a hexagonal column, or can have a shape extending in one direction but having a partially inclined outer surface (e.g., an outer perimeter or a circumferential surface).

[0159] The current spreading layer CSL is a layer for improving the light extraction efficiency, and can be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO) to transmit light.

[0160] The first semiconductor layer SEM1 may be disposed on the current spreading layer CSL. The length of the bottom surface of the first semiconductor layer SEM1 in the first direction DR1 or in the second direction DR2 may be less than the length of the connection electrode BE in the first direction DR1 and / or in the second direction DR2. The first semiconductor layer SEM1 may be made of GaN doped with a dopant of the first conductivity type (such as Mg, Zn, Ca, Ba, etc.).

[0161] The active layer MQW may be disposed on the first semiconductor layer SEM1. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0162] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN and / or AlGaN, but is not limited thereto. Optionally, the active layer MQW may have a structure in which a semiconductor material having a high bandgap and a semiconductor material having a low bandgap are alternately stacked, and may include other group III-V semiconductor materials according to the wavelength range of the emitted light.

[0163] When the active layer MQW includes InGaN, the color of the emitted light may vary according to the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer MQW may shift to the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer MQW may shift to the blue wavelength band. For example, the content of indium (In) in the active layer MQW of a light-emitting element LE that emits third light (for example, light in the blue wavelength band) may be about 10 wt% to 20 wt%.

[0164] The second semiconductor layer SEM2 may be disposed on the active layer MQW. The second semiconductor layer SEM2 may be doped with a dopant of the second conductivity type such as Si, Ge, Se, Sn, etc. For example, the second semiconductor layer SEM2 may be N-GaN doped with N-type Si.

[0165] An electron blocking layer may be disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer may be a layer that inhibits or prevents too many electrons from flowing into the active layer MQW. For example, the electron blocking layer may be AlGaN and / or P-AlGaN doped with P-type Mg. The electron blocking layer may be omitted.

[0166] The superlattice layer may be provided between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer may be a layer for reducing the stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer may be formed of InGaN and / or GaN. The superlattice layer may be omitted.

[0167] The protective layer INS may be provided on one side of the current diffusion layer CSL, one side of the first semiconductor layer SEM1, one side of the active layer MQW, and one side of the second semiconductor layer SEM2. The protective layer INS may be a film that protects the outer surface (e.g., the outer periphery or the circumferential surface) of the light-emitting element LE.

[0168] The protective layer INS may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0169] The connection electrode layer BEL is provided between the light-emitting element LE and the pixel electrode layer PXL. The connection electrode layer BEL may include a plurality of connection electrodes BE1, BE2, BE3, and BE4. For example, the connection electrode layer BEL may include a first connection electrode BE1, a second connection electrode BE2, a third connection electrode BE3, and a fourth connection electrode BE4, but is not limited thereto.

[0170] The plurality of connection electrodes BE1, BE2, BE3, and BE4 are connected to the pixel electrodes PXE1, PXE2, and PXE3 and the light-emitting element LE that overlap in the thickness direction.

[0171] The plurality of connection electrodes BE1, BE2, BE3, and BE4 may be provided on the corresponding pixel electrodes PXE1, PXE2, and PXE3. The plurality of connection electrodes BE1, BE2, BE3, and BE4 may be used as bonding metals for bonding the pixel electrodes PXE1, PXE2, and PXE3 to the light-emitting element LE during the manufacturing process.

[0172] The plurality of connection electrodes BE1, BE2, BE3, and BE4 may include a connection portion BE-1 and a reflective portion BE-2. The reflective portion BE-2 is disposed to be spaced apart (e.g., separated) from the pixel electrodes PXE1, PXE2, and PXE3 as compared to the connection portion BE-1, and the connection portion BE-1 is disposed on the pixel electrodes PXE1, PXE2, and PXE3 to bond the pixel electrodes PXE1, PXE2, PXE3, and the light-emitting element LE. The reflective portion BE-2 may be disposed closer to the first semiconductor layer SEM1 than the connection portion BE-1. The reflective portion BE-2 is configured to reflect light emitted from the light-emitting element LE in the lateral directions of up, down, left, and right and not traveling in the upward direction, thereby preventing or reducing the mixing of light emitted from the light-emitting element LE in the adjacent light-emitting regions EA1, EA2, and EA3. The reflective portion BE-2 may include a metal material having a higher reflectivity, such as Al, than the connection portion BE-1. The reflective portion BE-2 may include a metal having a reflectivity higher than that of the connection portion BE-1.

[0173] Each of the plurality of connection electrodes BE1, BE2, BE3, and BE4 may be in contact with the pixel electrodes PXE1, PXE2, and PXE3. Each of the plurality of connection electrodes BE1, BE2, BE3, and BE4 may be in direct contact with the current spreading layer CSL of the light-emitting element LE. Each of the plurality of connection electrodes BE1, BE2, BE3, and BE4 contacts the light-emitting element LE at different points. To this end, the protective layer INS may have a plurality of through-holes such that the plurality of connection electrodes BE1, BE2, BE3, and BE4 are in direct contact with the current spreading layer CSL. For example, the protective layer INS may include a plurality of through-holes H1, H2, H3, and H4 on a surface in contact with the plurality of connection electrodes BE1, BE2, BE3, and BE4. The current spreading layer CSL may be exposed through the plurality of through-holes H1, H2, H3, and H4.

[0174] The plurality of through-holes H1, H2, H3, and H4 may correspond one-to-one with the plurality of connection electrodes BE. For example, the protective layer INS may include a first through-hole H1, a second through-hole H2, a third through-hole H3, and a fourth through-hole H4. The first through-hole H1 overlaps with the first connection electrode BE1 in the thickness direction (e.g., the third direction DR3), and the width of the first through-hole H1 may be smaller than the width of the first connection electrode BE1. The second through-hole H2 overlaps with the second connection electrode BE2 in the thickness direction, and the width of the second through-hole H2 may be smaller than the width of the second connection electrode BE2. The third through-hole H3 overlaps with the third connection electrode BE3 in the thickness direction, and the width of the third through-hole H3 may be smaller than the width of the third connection electrode BE3. The fourth through-hole H4 overlaps with the fourth connection electrode BE4 in the thickness direction, and the width of the fourth through-hole H4 may be smaller than the width of the fourth connection electrode BE4. In one or more other embodiments, asFigure 10 As shown, the width of each of the plurality of through holes H1, H2, H3, and H4 may be the same as the width of the corresponding connection electrodes BE1, BE2, BE3, and BE4. For example, the width of the first through hole H1 may be equal to the width of the first connection electrode BE1. The width of the third through hole H3 may be equal to the width of the third connection electrode BE3. Similarly, in one or more embodiments, the width of the second through hole H2 may be equal to the width of the second connection electrode BE2, and the width of the fourth through hole H4 may be equal to the width of the fourth connection electrode BE4.

[0175] The plurality of through holes H1, H2, H3, and H4 may be spaced apart from each other in a plane (e.g., separated). The distance between the plurality of adjacent through holes H1, H2, H3, and H4 may be the same. The distance between each of the plurality of through holes H1, H2, H3, and H4 and the center of the light-emitting element LE may be the same, but is not limited thereto. Each of the plurality of through holes H1, H2, H3, and H4 may be circular in a plan view, but is not limited thereto. For example, the plurality of through holes H1, H2, H3, and H4 may be rectangular or triangular.

[0176] The sizes of the plurality of through holes H1, H2, H3, and H4 may be the same, but are not limited thereto. The plurality of through holes H1, H2, H3, and H4 may be arranged to be spaced apart from the edge of the light-emitting element LE (e.g., separated). The through holes H1, H2, H3, and H4 may be arranged to be spaced apart from the edge of the light-emitting element LE by the same distance from each other (e.g., separated). For example, the distance between the first through hole H1 and the edge of the light-emitting element LE may be the same as the distance between the second through hole H2 and the edge of the light-emitting element LE. The distance between the first through hole H1 and the edge of the light-emitting element LE may be the same as the distance between the third through hole H3 and the edge of the light-emitting element LE. In addition, the distance between the first through hole H1 and the edge of the light-emitting element LE may be the same as the distance between the fourth through hole H4 and the edge of the light-emitting element LE.

[0177] The plurality of connection electrodes BE1, BE2, BE3, and BE4 may be in direct contact through the through holes H1, H2, H3, and H4 in the protective layer INS. The width of the through holes H1, H2, H3, and H4 may be the same as or narrower than the width of the connection electrodes BE1, BE2, BE3, and BE4.

[0178] The first connection electrode BE1, the second connection electrode BE2, the third connection electrode BE3, and the fourth connection electrode BE4 may be spaced apart from each other in a plane (e.g., separated). The distance between the adjacent connection electrodes BE1, BE2, BE3, and BE4 may be the same.

[0179] The sizes of each of the connection electrodes BE1, BE2, BE3, and BE4 may be the same, but are not limited thereto. Each of the connection electrodes BE1, BE2, BE3, and BE4 may have any shape as long as it can support the light-emitting element LE. For example, the cross-section of each of the connection electrodes BE1, BE2, BE3, and BE4 may not only be circular, but also a polygon such as a square, pentagon, and / or hexagon. However, the heights of each of the connection electrodes BE1, BE2, BE3, and BE4 are all the same, so that the light-emitting element LE on the top can be supported, and thus the light-emitting element LE can be stably placed upright on the pixel electrodes PXE1, PXE2, and PXE3 without falling down.

[0180] According to one or more embodiments, when the light-emitting element LE is electrically connected to the pixel electrodes PXE1, PXE2, and PXE3 in the display panel 100, the plurality of connection electrodes BE1, BE2, BE3, and BE4 can reduce the resistance between the light-emitting element LE and the pixel electrodes PXE1, PXE2, and PXE3. The connection electrode BE (BE1, BE2, BE3, and BE4) may include a conductive metal. For example, the connection electrode BE may include gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and / or silver (Ag). For example, the connection electrode BE may include a 9:1 alloy, 8:2 alloy, and / or 7:3 alloy of gold and tin, or may include an alloy of copper, silver, and / or tin (SAC305).

[0181] The connection electrode BE and the pixel electrodes PXE1, PXE2, and PXE3 may be bonded by an eutectic process.

[0182] The third organic layer 191 may be provided to cover a part of the side surfaces of the bank layer BNL and the plurality of light-emitting elements LE. The third organic layer 191 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0183] The fourth organic layer 192 may be provided on the third organic layer 191. The fourth organic layer 192 may be provided to cover a part of the side surface of each of the plurality of light-emitting elements LE. The fourth organic layer 192 may be provided lower than the plurality of light-emitting elements LE to expose the tops of the light-emitting elements LE.

[0184] The fourth organic layer 192 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0185] The third organic layer 191 and the fourth organic layer 192 are layers for flattening the steps caused by the plurality of light-emitting elements LE. If the height of the third organic layer 191 is arranged such that the third organic layer 191 can cover most of the side surfaces of each of the plurality of light-emitting elements LE, the fourth organic layer 192 can be omitted.

[0186] The common electrode CE can be provided on the top surfaces of each of the plurality of light-emitting elements LE and on the top surface of the fourth organic layer 192. The common electrode CE can be a common layer formed commonly in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The common electrode CE can be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO) that can transmit light.

[0187] In one or more embodiments, the pixel electrode PXE (PXE1, PXE2, PXE3) can be referred to as an anode electrode or a first electrode, and the common electrode CE can be referred to as a cathode electrode or a second electrode.

[0188] The first capping layer CAP1 can be provided on the common electrode CE. The first capping layer CAP1 can be formed of an inorganic layer film (for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0189] The light-blocking layer BM, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL can be provided on the first capping layer CAP1. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL can be formed by separating the light-blocking layer BM. Thus, the first light conversion layer QDL1 is provided in the first sub-pixel SPX1 on the first capping layer CAP1, the second light conversion layer QDL2 is provided in the second sub-pixel SPX2 on the first capping layer CAP1, and the light-transmitting layer TPL can be provided in the third sub-pixel SPX3 on the first capping layer CAP1. The light-blocking layer BM can overlap the bank layer BNL in the third direction DR3 and can not overlap the plurality of light-emitting elements LE.

[0190] The first light conversion layer QDL1 can convert a part of the third light (e.g., light in the blue wavelength band) incident from the light-emitting element LE into the first light (e.g., light in the red wavelength band). The first light conversion layer QDL1 can include a first base resin BRS1 and first wavelength conversion particles WCP1. The first base resin BRS1 can include a light-transmissive organic material. For example, the first base resin BRS1 can include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, and / or an imide-based resin. The first wavelength conversion particles WCP1 can convert a part of the third light (e.g., light in the blue wavelength band) incident from the light-emitting element LE into the first light (e.g., light in the red wavelength band). The first wavelength conversion particles WCP1 can be quantum dots (QDs), quantum rods, fluorescent materials, and / or phosphorescent materials.

[0191] The second light conversion layer QDL2 can convert a part of the third light (e.g., light in the blue wavelength band) incident from the light-emitting element LE into the second light (e.g., light in the green wavelength band). It can include a second base resin BRS2 and second wavelength conversion particles WCP2. The second base resin BRS2 can include a light-transmissive organic material. For example, the second base resin BRS2 can include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, and / or an imide-based resin. The second wavelength conversion particles WCP2 can convert a part of the third light (e.g., light in the blue wavelength band) incident from the light-emitting element LE into the second light (e.g., light in the green wavelength band). The second wavelength conversion particles WCP2 can be quantum dots (QDs), quantum rods, fluorescent materials, and / or phosphorescent materials.

[0192] The light transmissive layer TPL can include a light-transmissive organic material. For example, the light transmissive layer TPL can include an epoxy resin, an acrylic resin, a cardo resin, and / or an imide resin.

[0193] The light blocking layer BM can include a first light blocking layer BM1 and a second light blocking layer BM2 stacked in sequence. The length of the first light blocking layer BM1 in the first direction DR1 or in the second direction DR2 can be wider than the length of the second light blocking layer BM2 in the first direction DR1 or in the second direction DR2. The first light blocking layer BM1 and the second light blocking layer BM2 can be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The first light blocking layer BM1 and the second light blocking layer BM2 can include a light blocking material to prevent the light from the light-emitting element LE of one sub-pixel from traveling to an adjacent sub-pixel. For example, the first light blocking layer BM1 and the second light blocking layer BM2 can include an inorganic black pigment such as carbon black and / or an organic black pigment.

[0194] The second capping layer CAP2 can be disposed on the first capping layer CAP1 and the light blocking layer BM. The second capping layer CAP2 can be disposed on the side surface and the top surface of the light blocking layer BM. That is to say, the second capping layer CAP2 can be disposed on one side of the first light blocking layer BM1 and on the side surface and the top surface of the second light blocking layer BM2.

[0195] The reflective layer RF can be disposed between the light blocking layer BM and the first light conversion layer QDL1, between the light blocking layer BM and the second light conversion layer QDL2, and between the light blocking layer BM and the light transmission layer TPL. The reflective layer RF can be disposed on the second capping layer CAP2 disposed on one side of the first light blocking layer BM1 and one side of the second light blocking layer BM2. The reflective layer RF is used to reflect the light traveling in the lateral direction from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL.

[0196] The reflective layer RF can include a highly reflective metal material such as aluminum (Al). The thickness of the reflective layer RF can be about 0.1 μm.

[0197] Optionally, the reflective layer RF can include M (where M is an integer greater than or equal to 2) pairs of a first layer and a second layer having different refractive indexes to be used as a distributed Bragg reflector (DBR). In this case, the M first layers and the M second layers can be alternately arranged. The first layer and the second layer can be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0198] The third capping layer CAP3 can be disposed on the second capping layer CAP2, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL. The third capping layer CAP3 can be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer). The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL can be encapsulated by the first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3.

[0199] The fifth organic layer 193 can be disposed on the third capping layer CAP3. The fifth organic layer 193 can be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0200] A plurality of color filters CF1, CF2, and CF3 can be disposed on the fifth organic layer 193. The plurality of color filters CF1, CF2, and CF3 can include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0201] The first color filter CF1 disposed in the first sub-pixel SPX1 can transmit first light (e.g., light in a red wavelength band) and absorb or block third light (e.g., light in a blue wavelength band). Accordingly, the first color filter CF1 can transmit the first light (e.g., light in a red wavelength band) converted by the first light conversion layer QDL1 among the third light (e.g., light in a blue wavelength band) emitted by the light-emitting element LE, and absorb or block the third light (e.g., light in a blue wavelength band) not converted by the first light conversion layer QDL1. Accordingly, the first sub-pixel SPX1 can emit first light (e.g., light in a red wavelength band).

[0202] The second color filter CF2 disposed in the second sub-pixel SPX2 can transmit second light (e.g., light in a green wavelength band) and absorb or block third light (e.g., light in a blue wavelength band). Accordingly, the second color filter CF2 can transmit the second light (e.g., light in a green wavelength band) converted by the second light conversion layer QDL2 among the third light (e.g., light in a blue wavelength band) emitted by the light-emitting element LE, and absorb or block the third light (e.g., light in a blue wavelength band) not converted by the second light conversion layer QDL2. Accordingly, the second sub-pixel SPX2 can emit second light (e.g., light in a green wavelength band).

[0203] The third color filter CF3 disposed in the third sub-pixel SPX3 can transmit third light (e.g., light in a blue wavelength band). Accordingly, the third color filter CF3 can transmit the third light (e.g., light in a blue wavelength band) emitted from the light-emitting element LE and passing through the light-transmitting layer TPL. Accordingly, the third sub-pixel SPX3 can emit third light (e.g., light in a blue wavelength band).

[0204] The first color filter CF1, the second color filter CF2, and the third color filter CF3 overlapping in the third direction DR3 can overlap the bank layer BNL and the light-blocking layer BM in the third direction DR3.

[0205] The sixth organic layer 194 for planarization can be disposed on the plurality of color filters CF1, CF2, and CF3. The sixth organic layer 194 can be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0206] According to one or more embodiments, a plurality of connection electrodes BE are formed on the bottom of the light-emitting element LE such that the light-emitting element LE can be stably connected to the pixel electrode PXE without falling down during the bonding process. Accordingly, the bonding yield of the light-emitting element LE can be improved, and color purity and luminance can be improved.

[0207] In addition, by distributing a plurality of connection electrodes BE on one surface of the light-emitting element LE, current diffusion can be improved by dispersing the contact between the connection electrodes BE and the light-emitting element LE.

[0208] Hereinafter, Figures 11 to 14 is a plan view or a perspective view of a light-emitting element according to one or more embodiments.

[0209] Figure 11 is a plan view of a light-emitting element and connection electrodes according to one or more embodiments. Figure 12 is Figure 11 a perspective view of the light-emitting element and connection electrodes.

[0210] Referring to Figure 11 and Figure 12 , the connection electrode layer BEL may include a first connection electrode BE1, a second connection electrode BE2, a third connection electrode BE3, a fourth connection electrode BE4, and a fifth connection electrode BE5. The first connection electrode BE1, the second connection electrode BE2, the third connection electrode BE3, the fourth connection electrode BE4, and the fifth connection electrode BE5 may be arranged to be spaced apart from each other (e.g., separated).

[0211] The fifth connection electrode BE5 may be provided at the center of the light-emitting element LE. The first connection electrode BE1, the second connection electrode BE2, the third connection electrode BE3, and the fourth connection electrode BE4 may be formed to surround the fifth connection electrode BE5 (e.g., around the fifth connection electrode BE5). The first connection electrode BE1, the second connection electrode BE2, the third connection electrode BE3, and the fourth connection electrode BE4 may be arranged along the same perimeter (e.g., circumference). The first connection electrode BE1, the second connection electrode BE2, the third connection electrode BE3, and the fourth connection electrode BE4 may be located within the edge of the light-emitting element LE.

[0212] The first connection electrode BE1, the second connection electrode BE2, the third connection electrode BE3, and the fourth connection electrode BE4 may be arranged to be spaced apart from each other at substantially equal or equal intervals (e.g., separated). The first connection electrode BE1, the second connection electrode BE2, the third connection electrode BE3, and the fourth connection electrode BE4 may be provided symmetrically with respect to each other radially. The first connection electrode BE1, the second connection electrode BE2, the third connection electrode BE3, and the fourth connection electrode BE4 may be coaxial with each other, for example, may be arranged along a circumference centered on the fifth connection electrode BE5, but is not limited thereto. The fifth connection electrode BE5 may be spherical or cylindrical in shape, but is not limited thereto. The cross-section of the fifth connection electrode BE5 may not only be circular, but also be a polygon such as a square, pentagon, or hexagon.

[0213] Figure 13is a plan view of a light-emitting element and a connection electrode according to one or more embodiments. Figure 14 is Figure 13 a perspective view of the light-emitting element and the connection electrode.

[0214] Referring Figure 13 and Figure 14 When viewed from above, the connection electrode BE may have a cross-shaped structure or a similar structure. The connection electrode BE may include a main body portion BD provided at the center, and a plurality of branch portions BR1, BR2, BR3, and BR4 extending outward in four directions around the main body portion BD, for example. For example, the main body portion BD may be provided at the center of the light-emitting element LE, and the first branch portion BR1, the second branch portion BR2, the third branch portion BR3, and the fourth branch portion BR4 may extend toward the edge of the light-emitting element LE. Each of the plurality of branch portions BR1, BR2, BR3, and BR4 may be provided at a substantially equal distance or an equal distance from the edge of the light-emitting element LE. The main body portion BD and the plurality of branch portions BR1, BR2, BR3, and BR4 may be integrally formed.

[0215] Figure 15 is a perspective view of the light-emitting element and the connection electrode, illustrating defects that occur when a single connection electrode is provided on the light-emitting element.

[0216] As Figure 15 shown, when one connection electrode BE is provided on the light-emitting element LE, the possibility that the light-emitting element LE does not fall on the pixel electrodes PXE1, PXE2, and PXE3 increases only when the connection electrode BE is provided at the center of one side of the light-emitting element LE.

[0217] In one or more embodiments, if the connection electrode BE is not aligned and not provided at the center of the light-emitting element LE, the possibility of falling on the pixel electrodes PXE1, PXE2, and PXE3 may increase.

[0218] Figure 16 is a perspective view showing the bonding defect of the light-emitting element bonded by one connection electrode.

[0219] As Figure 16 shown, the connection electrode BE has a curved top surface due to the nature of the process. Therefore, when one connection electrode BE is provided at the bottom of the light-emitting element LE, the light-emitting element LE may tip over on the pixel electrodes PXE1, PXE2, and PXE3. Alternatively, the light-emitting element LE may be tilted and bonded to the pixel electrodes PXE1, PXE2, and PXE3, thereby reducing the light-emitting efficiency.

[0220] In addition, if the connection electrode BE is as Figure 15 andFigure 16 shown to have a volume formed at the center, or if Figures 7 to 14 as in the embodiment of, a plurality of relatively small connection electrodes are formed, the total volume of the connection electrode BE can be reduced. Therefore, an effect of saving materials can be expected.

[0221] Hereinafter, a manufacturing process of the display device 10 according to one or more embodiments will be described with reference to other drawings.

[0222] Figures 17 to 29 is a diagram showing a method of manufacturing a display device according to one or more embodiments.

[0223] Figures 17 to 29 is shown in a cross-sectional view of the structure according to the formation order of each layer of the display device 10, and generally can correspond to Figure 7 a cross-sectional view of. In addition, Figures 6 to 10 the embodiment of is shown, and a display device of the embodiment of can be manufactured by partially changing the manufacturing process. In addition, hereinafter, the first light-emitting region EA1 of the display device 10 will be focused on. Figures 11 to 14 Reference

[0224] to Figures 17 to 20 a plurality of light-emitting elements LE and a connection electrode layer BEL are formed on a base substrate WAF.

[0225] Specifically, a base substrate WAF is prepared. The base substrate WAF may be a sapphire substrate (Al2O3) or a silicon wafer containing silicon. However, the present disclosure is not limited thereto, and one or more embodiments when the base substrate WAF is a sapphire substrate will be described by way of example.

[0226] A plurality of semiconductor material layers SEML2, MQWL, and SEML1, and a material layer CSLL for a current diffusion layer CSL are formed on the base substrate WAF. In Figures 18 to 28 the electron blocking layer and the superlattice layer are omitted. The plurality of semiconductor material layers grown by an epitaxial method can be formed by a growth seed crystal. Here, the method of forming the semiconductor material layer may be electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal organic chemical vapor deposition (MOCVD), etc., and the semiconductor material layer may preferably be formed by metal organic chemical vapor deposition (MOCVD). However, the present disclosure is not limited thereto.

[0227] Within the range that can be routinely selected to form the target material, there is no particular limitation on the precursor material for forming multiple semiconductor material layers. In one example, the precursor material can be a metal precursor containing an alkyl group such as a methyl group and / or an ethyl group. For example, it can be a compound such as trimethylgallium (Ga(CH3)3), trimethylaluminum (Al(CH3)3), and / or triethyl phosphate ((C2H5)3PO4), but is not limited thereto.

[0228] Specifically, a second semiconductor material layer SEML2 is formed on the base substrate WAF. The drawings show that the second semiconductor material layer SEML2 is further stacked, but is not limited thereto, and multiple layers can be formed.

[0229] The active material layer MQWL and the first semiconductor material layer SEML1 are sequentially formed on the second semiconductor material layer SEML2 using the method described above.

[0230] Next, a material layer CSLL for the current spreading layer CSL is formed on the first semiconductor material layer SEML1.

[0231] Next, referring to Figure 18 , the multiple semiconductor material layers SEML2, MQWL, and SEML1 and the material layer CSLL for the current spreading layer CSL are etched to form the stem portion of the light-emitting element LE.

[0232] The semiconductor material layers SEML2, MQWL, and SEML1 and the material layer for the current spreading layer CSL can be etched by a conventional method. For example, the process for etching the semiconductor material layers SEML2, MQWL, and SEML1 can be dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of the dry etching method, anisotropic etching is possible and can be suitable for vertical etching. When using the etching methods described above, the etchant can be Cl2 and / or O2. However, it is not limited thereto.

[0233] Through this process, the stem portions of multiple light-emitting elements LE can be obtained. Therefore, the stem portions of the multiple light-emitting elements LE are formed to include the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1, and the current spreading layer CSL.

[0234] Next, referring to Figure 19 , a protective layer INS is formed to cover the stem portion of the light-emitting element LE (for example, to cover the outer periphery or circumferential surface of the stem portion of the light-emitting element LE).

[0235] Next, referring to Figure 20, a plurality of through holes H1 and H3 are formed in a protective layer INS formed on one surface of a rod portion of a light-emitting element LE, and a plurality of connection electrodes BE1 and BE3 are formed.

[0236] The protective layer INS exposes a current diffusion layer CSL through the plurality of through holes H1 and H3. The connection electrodes BE1 and BE3 can be formed by stacking an electrode material layer on a base substrate WAF and then etching it by an etching process, thereby forming the plurality of connection electrodes BE1 and BE3 overlapping the plurality of through holes H1 and H3, but each of the connection electrodes BE1 and BE3 can be formed to be spaced apart from each other (for example, spaced apart).

[0237] Therefore, a plurality of connection electrodes BE1 and BE3 can be formed to cover the current diffusion layer CSL exposed by the plurality of through holes H1 and H3. The current diffusion layer CSL and the connection electrodes BE1 and BE3 can be in direct contact with each other through the plurality of through holes H1 and H3.

[0238] Next, referring to Figure 21 , a first support film SPL1 is attached to Figure 20 the plurality of light-emitting elements LE manufactured on a base substrate WAF. At this time, a first adhesive layer ADL1 can be interposed between the first support film SPL1 and the light-emitting element LE.

[0239] The first adhesive layer ADL1 can be aligned on the plurality of light-emitting elements LE and attached to the plurality of connection electrodes BE1 and BE3 of the plurality of light-emitting elements LE. The plurality of light-emitting elements LE are arranged in large numbers and can be attached to the first adhesive layer ADL1 without being separated from the base substrate WA.

[0240] The first support film SPL1 can be made of a material that is transparent and mechanically stable to allow light to pass through. For example, the first support film SPL1 can include a transparent polymer such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The first adhesive layer ADL1 can include an adhesive material for bonding the light-emitting element LE. For example, the adhesive material can include urethane acrylate, epoxy acrylate, polyester acrylate, etc. The adhesive material can be a material whose adhesiveness changes when ultraviolet (UV) light or heat is applied, thereby facilitating the separation of the adhesive layer from the light-emitting element LE.

[0241] Next, referring to Figure 21 and Figure 22 , a laser (first laser) is irradiated onto the base substrate WAF to separate the light-emitting element LE from the base substrate WAF. The base substrate WAF is separated from each second semiconductor layer SEM2 of the plurality of light-emitting elements LE.

[0242] The process for separating the base substrate WAF can be carried out by a laser lift-off (LLO) process. The laser lift-off process utilizes a laser, and a KrF excimer laser (248 nm wavelength) can be used as the source. The energy density of the excimer laser is in the range of about 550 mJ / cm 2 to 950 mJ / cm 2 and the incident area can be in the range of 50×50μm 2 to 1×1cm 2 but is not limited thereto. By irradiating the base substrate WAF with a laser, the base substrate WAF can be separated from the light-emitting element LE.

[0243] Next, referring to Figure 22 etch the first adhesive layer ADL1 in the area that does not overlap with the light-emitting element LE.

[0244] Next, referring to Figure 23 align the first support film SPL1 on the interposer substrate SPL2. The interposer substrate SPL2 can be composed of a second support layer and a second adhesive layer provided on the second support layer. The second support layer can be made of a material that is transparent and mechanically stable to allow light to pass through. The second support layer material can be an exemplary material used in the first support film SPL1. The second adhesive layer can include an adhesive material for bonding the light-emitting element LE. As the second adhesive layer material, an exemplary material used in the first adhesive layer ADL1 can be applied.

[0245] Thereafter, the desired light-emitting element LE can be selectively transferred to the interposer substrate SPL2 using a mask MASK and a laser. At this time, remove the first support film SPL1 and the first adhesive layer ADL1 on the plurality of connection electrodes BE1 and BE3.

[0246] Referring to Figure 24 the light-emitting element LE not covered by the mask MASK is transferred to the interposer substrate SPL2 by a laser.

[0247] By Figures 17 to 24 the process, the light-emitting element LE can be manufactured and transferred to the interposer substrate SPL2.

[0248] Next, referring to Figure 25 prepare a substrate SUB on which a bank layer BNL (not shown in Figures 25 to 29 ) and a pixel electrode PXE are provided, and attach the interposer substrate SPL2 to the substrate SUB such that the plurality of connection electrodes BE1 and BE3 connected to the plurality of light-emitting elements LE are in contact with the pixel electrode PXE.

[0249] Heat and pressure are applied or a laser is applied to melt the plurality of connection electrodes BE1 and BE3, thereby bonding the pixel electrode PXE and the plurality of light-emitting elements LE. Then, as Figure 26 shown, the intermediate layer substrate SPL2 is removed.

[0250] Referring to Figure 27 , organic layers 191 and 192 are formed to planarize the steps caused by the plurality of light-emitting elements LE, and a common electrode CE is formed on the organic layers 191 and 192 and the plurality of light-emitting elements LE.

[0251] Next, as Figure 28 shown, a first capping layer CAP1 is formed on the common electrode CE, and then a light-blocking layer BM, a second capping layer CAP2, a reflective layer RF, and a first light conversion layer QDL1 are continuously formed on the first capping layer CAP1. Then, a third capping layer CAP3 is formed on the light-blocking layer BM, the reflective layer RF, and the first light conversion layer QDL1.

[0252] Next, as Figure 29 shown, a fifth organic layer 193 is formed on the third capping layer CAP3, and a color filter (e.g., Figure 29 the first color filter CF1 in

[0253] Figure 30 is an example diagram of a virtual reality device including a display device according to one or more embodiments. Figure 30 shows a virtual reality device 1 in which a display device 10 according to one or more embodiments is used.

[0254] Referring to Figure 30 , the virtual reality device 1 according to one or more embodiments may be a device in the form of glasses. The virtual reality device 1 according to one or more embodiments may include a display device 10, a left lens 10a, a right lens 10b, a support frame 20, a left temple 30a and a right temple 30b, a reflective member 40, and a display device housing 50.

[0255] Figure 30 shows the virtual reality device 1 including two temples 30a and 30b. However, the present disclosure is not limited thereto. The virtual reality device 1 according to one or more embodiments may be used in a head-mounted display including a head-mounted strap that can be worn on the head instead of the temples 30a and 30b. For example, the virtual reality device 1 according to one or more embodiments may not be limited to Figure 30 the example shown in

[0256] The display device housing 50 can accommodate the display device 10 and the reflection member 40. The image displayed on the display device 10 can be reflected from the reflection member 40 and provided to the user's right eye through the right lens 10b. Accordingly, the user can view the virtual reality image displayed on the display device 10 through the right eye.

[0257] Figure 30 It is shown that the display device housing 50 is provided at the right end of the support frame 20. However, the present disclosure is not limited thereto. For example, the display device housing 50 may be provided at the left end of the support frame 20. In this case, the image displayed on the display device 10 can be reflected from the reflection member 40 and provided to the user's left eye via the left lens 10a. Accordingly, the user can view the virtual reality image displayed on the display device 10 via the left eye. As another example, the display device housing 50 may be provided at each of the left and right ends of the support frame 20. In this case, the user can view the virtual reality image displayed on the display device 10 via both the left and right eyes.

[0258] Figure 31 is an example diagram of a smart device including a display device according to one or more embodiments.

[0259] Reference Figure 31 , the display device 10 according to one or more embodiments can be applied to a smart watch 2 which is one of the smart devices.

[0260] Figure 32 is an example diagram of a vehicle including a display device according to one or more embodiments. Figure 32 It shows a vehicle in which a display device according to one or more embodiments is used.

[0261] Reference Figure 32 , the display devices 10_a, 10_b, and 10_c according to one or more embodiments can be applied to an instrument panel of a vehicle, applied to a center fascia of a vehicle, or applied to a center information display (CID) provided on the instrument panel of a vehicle. In addition, each of the display devices 10_d and 10_e according to one or more embodiments can be applied to each interior mirror display, which replaces each of the side mirrors of a vehicle.

[0262] Figure 33 is an example diagram of a transparent display device including a display device according to one or more embodiments.

[0263] Reference Figure 33, a display device according to one or more embodiments can be applied to a transparent display device. The transparent display device can transmit light therethrough while displaying an image IM thereon. Thus, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10, but also view an object RS or a background located behind the transparent display device. In the case where the display device 10 is applied to the transparent display device, Figure 7 the substrate SUB of the display device 10 shown in

[0264] may include a light-transmissive portion that allows light to pass therethrough, or may be made of a material that allows light to pass therethrough. At the end of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the embodiments without substantially departing from the principles and scope of the present disclosure. Therefore, the embodiments of the present disclosure are used only in an overview and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: a substrate on which a pixel electrode is disposed; A light emitting element, on the pixel electrode; as well as A plurality of connection electrodes are provided between the pixel electrode and the light emitting element, and the plurality of connection electrodes are spaced apart from each other.

2. The display device according to claim 1, wherein: Each of the plurality of connection electrodes contacts the light emitting element at a different point.

3. The display device according to claim 1, wherein: The light emitting element includes a protective layer having a plurality of through holes on at least one side of the light emitting element, The plurality of connection electrodes contact the light emitting elements through the plurality of through holes.

4. The display device according to claim 3, wherein: A width of a through hole among the plurality of through holes is less than or equal to a width of a connecting electrode among the plurality of connecting electrodes.

5. The display device according to claim 1, wherein: The plurality of connection electrodes are spaced apart from edges of the light emitting element.

6. The display device according to claim 1, wherein: The plurality of connection electrodes have a circular or polygonal cross section.

7. The display device according to claim 1, wherein: The plurality of connection electrodes include a first connection electrode, a second connection electrode, a third connection electrode and a fourth connection electrode, The first connection electrode, the second connection electrode, the third connection electrode and the fourth connection electrode are arranged to be radially symmetrical with each other.

8. The display device according to claim 7, wherein: The plurality of connection electrodes further include a fifth connection electrode, The first connection electrode, the second connection electrode, the third connection electrode and the fourth connection electrode are arranged along a circumference centered on the fifth connection electrode.

9. The display device according to claim 1, wherein: Each of the plurality of connection electrodes includes a reflection portion in contact with the light emitting element and a connection portion on one surface of the reflection portion, The reflective portion includes a metal having a reflectivity higher than that of the connecting portion.

10. The display device according to claim 1, wherein: The light emitting element comprises a current diffusion layer, a first semiconductor layer, an active layer and a second semiconductor layer. The current diffusion layer, the first semiconductor layer, the active layer and the second semiconductor layer are sequentially stacked, and the current diffusion layer is closer to a connection electrode among the plurality of connection electrodes than the first semiconductor layer. The display device according to claim 1 , further comprising a common electrode on the light emitting element.

12. A display device comprising: a substrate on which a pixel electrode is disposed; A light emitting element, on the pixel electrode; as well as A connection electrode is provided between the pixel electrode and the light emitting element, the connection electrode having a main body portion at the center and a plurality of branch portions extending outward from the main body portion.

13. The display device according to claim 12, wherein: The main body portion and the plurality of branch portions are integral.

14. The display device according to claim 12, wherein: The light emitting element includes a protective layer having a through hole on at least one side of the light emitting element, Wherein, the connecting electrode contacts the light emitting element through the through hole.

15. The display device according to claim 14, wherein: The width of the through hole is less than or equal to the width of the connecting electrode.

16. The display device according to claim 12, wherein: The plurality of branch portions are spaced apart from an edge of the light emitting element.

17. The display device according to claim 12, wherein: The plurality of branch portions include a first branch portion, a second branch portion, a third branch portion, and a fourth branch portion, and the plurality of branch portions extend in four directions.

18. The display device according to claim 12, wherein: The connection electrode includes a reflection portion in contact with the light emitting element and a connection portion on one surface of the reflection portion, The reflective portion includes a metal having a reflectivity higher than that of the connecting portion.

19. The display device according to claim 12, wherein: The light emitting element comprises a current diffusion layer, a first semiconductor layer, an active layer and a second semiconductor layer. The current diffusion layer, the first semiconductor layer, the active layer and the second semiconductor layer are sequentially stacked, and the current diffusion layer is closer to the connection electrode than the first semiconductor layer.

20. The display device according to claim 12, further comprising a common electrode on the light emitting element.

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