Method of manufacturing display device

Abstract

There is provided a method of manufacturing a display device, the display device including: a substrate; a first thin film transistor disposed over the substrate and including a first semiconductor layer and a first gate electrode; a second thin film transistor including a second semiconductor layer and a second gate electrode; a first insulating layer between the first semiconductor layer and the first gate electrode; a second insulating layer between the first gate electrode and the second semiconductor layer; a third insulating layer between the second semiconductor layer and the second gate electrode; a fourth insulating layer on the second gate electrode; a first hole over the first semiconductor layer and through the first insulating layer and the second insulating layer; and a second hole within the first hole and passing through the third insulating layer and the fourth insulating layer.

Description

[0001] Cross - reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2023 - 0187564, filed with the Korean Intellectual Property Office on December 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] One or more embodiments relate to a display device and a method of manufacturing the display device. Background art

[0004] A display device visually displays data. The display device is used as a display unit of a miniaturized product such as a mobile phone and is used as a display unit of a large - sized product such as a television.

[0005] The display device includes a plurality of sub - pixels that receive an electrical signal and emit light to display an image to the outside. Each sub - pixel includes a display element. As an example, an organic light - emitting display device includes an organic light - emitting diode as a display element. Generally, an organic light - emitting display device includes a transistor and an organic light - emitting diode on a substrate and operates while the organic light - emitting diode emits light spontaneously.

[0006] Recently, since the usage purposes of display devices have been diversified, various attempts have been made to design display devices with improved quality. Summary of the invention

[0007] One or more embodiments include a display device having improved characteristics of a transistor and a method of manufacturing the display device. However, such technical features are merely examples and the present disclosure is not limited thereto.

[0008] Additional aspects will be set forth in part in the following description, and in part will be apparent from the description, or may be learned by practice of the presented embodiments of the present disclosure.

[0009] According to one or more embodiments, a display device includes: a substrate; a first thin - film transistor disposed on the substrate and including a first semiconductor layer and a first gate electrode; a second thin - film transistor including a second semiconductor layer and a second gate electrode; a first insulating layer between the first semiconductor layer and the first gate electrode; a second insulating layer between the first gate electrode and the second semiconductor layer; a third insulating layer between the second semiconductor layer and the second gate electrode; a fourth insulating layer on the second gate electrode; a first hole above the first semiconductor layer and passing through the first insulating layer and the second insulating layer; and a second hole within the first hole and passing through the third insulating layer and the fourth insulating layer.

[0010] The width of the first hole can be greater than the width of the second hole.

[0011] The second thin film transistor may further include a third gate electrode disposed under and overlapping with the second semiconductor layer, and the second insulating layer may include a second-first insulating layer and a second-second insulating layer, wherein the second-first insulating layer is between the first gate electrode and the third gate electrode, and the second-second insulating layer is on the third gate electrode.

[0012] The display device may further include a fifth insulating layer between the second insulating layer and the second semiconductor layer, wherein the fifth insulating layer may fill at least a portion of the first hole.

[0013] The fifth insulating layer may include an inorganic insulating material.

[0014] The display device may further include an electrode disposed on the fourth insulating layer and overlapping with the first semiconductor layer, wherein the electrode may contact the first semiconductor layer through the second hole.

[0015] The electrode may contact the fifth insulating layer that fills at least a portion of the first hole.

[0016] The first semiconductor layer may include a silicon semiconductor material, and the second semiconductor layer may include an oxide semiconductor material.

[0017] The display device may further include an oxide layer disposed on the first semiconductor layer and disposed in the first hole.

[0018] The second hole may pass through the oxide layer.

[0019] According to one or more embodiments, a method of manufacturing a display device includes: forming a first semiconductor layer of a first thin film transistor over a substrate; forming a first insulating layer on the first semiconductor layer; forming a first gate electrode of the first thin film transistor on the first insulating layer; forming a second insulating layer on the first gate electrode; forming a first hole above the first semiconductor layer and passing through the first insulating layer and the second insulating layer; performing a heat treatment on the first semiconductor layer; forming a second semiconductor layer of a second thin film transistor on the second insulating layer; forming a third insulating layer on the second semiconductor layer; forming a second gate electrode of the second thin film transistor on the third insulating layer; forming a fourth insulating layer on the second gate electrode; and forming a second hole within the first hole and passing through the third insulating layer and the fourth insulating layer.

[0020] The width of the first hole can be greater than the width of the second hole.

[0021] The method may further include forming a third gate electrode of a second thin film transistor disposed under and overlapping with the second semiconductor layer, wherein forming the second insulating layer may include: forming a second-first insulating layer between the first gate electrode and the third gate electrode; and forming a second-second insulating layer on the third gate electrode.

[0022] The method may further include forming a fifth insulating layer between the second insulating layer and the second semiconductor layer, wherein the fifth insulating layer may fill at least a portion of the first hole.

[0023] The fifth insulating layer may include an inorganic insulating material.

[0024] The second hole may pass through the fifth insulating layer that fills at least a portion of the first hole.

[0025] The method may further include forming an electrode overlapping with the first semiconductor layer on the fourth insulating layer, wherein the electrode may be in contact with the first semiconductor layer through the second hole.

[0026] The electrode may be in contact with the fifth insulating layer that fills at least a portion of the first hole.

[0027] The method may further include forming an oxide layer on the first semiconductor layer and disposed in the first hole before forming the second semiconductor layer.

[0028] The second hole may pass through the oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings.

[0030] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0031] Figure 2 is a schematic equivalent circuit diagram of a light emitting diode of a display device according to an embodiment and a sub-pixel circuit electrically connected thereto.

[0032] Figure 3 is taken along line I-I' according to an embodiment Figure 1 of a schematic cross-sectional view of the display device.

[0033] Figure 4 is a plan view of a first hole and a first contact hole of a display device according to an embodiment.

[0034] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5Eis a cross-sectional view showing a process of manufacturing a display device according to an embodiment.

[0035] Figure 6 is a schematic cross-sectional view of a display device according to an embodiment.

[0036] Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D are cross-sectional views showing a process of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0037] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals always refer to like elements. At this point, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by referring to the accompanying drawings to explain aspects of the present specification. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variants thereof.

[0038] Since the present disclosure allows for various changes and multiple embodiments, specific embodiments will be shown in the drawings and described in the written description. The effects and features of the present disclosure and the methods for achieving them will be clarified with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in various forms.

[0039] Hereinafter, embodiments will be described with reference to the accompanying drawings, wherein like reference numerals always refer to like elements and repeated descriptions thereof are omitted.

[0040] Although terms such as "first" and "second" may be used to describe various components, such components should not be limited to the above terms. The above terms are used to distinguish one component from another.

[0041] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0042] It will be understood that as used herein, the terms "comprise", "comprising", "include" and / or "including" specify the presence of the stated features or components, but do not preclude the addition of one or more other features or components.

[0043] It will be further understood that when a layer, region, or element is referred to as being "on" another layer, region, or element, it can be directly or indirectly on the other layer, region, or element. That is, for example, there can be intervening layers, regions, or elements.

[0044] For ease of explanation, the dimensions of the elements in the drawings can be enlarged or reduced. As an example, for ease of description, the dimensions and thicknesses of each of the elements shown in the drawings are arbitrarily represented, and thus, the present disclosure is not necessarily limited thereto.

[0045] In cases where a specific implementation can be different, the specific process order can be performed in an order different from the described order. As an example, two consecutively described processes can be performed substantially simultaneously or in the reverse order.

[0046] In this specification, "A and / or B" means A or B or both A and B. In this specification, "at least one of A and B" means A or B or both A and B.

[0047] It will be understood that when a layer, region, or element is referred to as being "connected" to another layer, region, or element, it can be "directly connected" to the other layer, region, or element, or it can be "indirectly connected" to the other layer, region, or element with yet another layer, region, or element therebetween. For example, it will be understood that when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it can be "directly electrically connected" to the other layer, region, or element, or it can be "indirectly electrically connected" to the other layer, region, or element with yet another layer, region, or element interposed therebetween.

[0048] The x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different orientations that are not perpendicular to each other.

[0049] Figure 1 is a schematic plan view of a display device 10 according to an embodiment.

[0050] Reference Figure 1 , various elements constituting the display device 10 are provided on a substrate 100. The substrate 100 includes a display area DA and a peripheral area PA surrounding the display area DA. The display area DA can be covered by a packaging member for protecting against external air, moisture, etc.

[0051] Light-emitting diodes LED are arranged in the display area DA of the substrate 100. The display device 10 can be configured to display an image by using the light emitted from the light-emitting diodes LED. Each light-emitting diode LED can be configured to emit, for example, red light, green light, or blue light.

[0052] In an embodiment, a light-emitting diode (LED) may include an organic light-emitting diode, and the organic light-emitting diode includes an organic material as a light-emitting material. In an embodiment, the light-emitting diode (LED) may be an inorganic light-emitting diode including an inorganic material. The inorganic light-emitting diode may include a PN junction diode, and the PN junction diode includes a material based on an inorganic material semiconductor. When a forward voltage is applied to the PN junction diode, holes and electrons are injected, and the energy generated by the recombination of the holes and electrons is converted into light energy, and thus, light of a preset color can be emitted.

[0053] The size of the light-emitting diode (LED) may be in the micrometer or nanometer range. As an example, the light-emitting diode (LED) may be a micro light-emitting diode. In other embodiments, the light-emitting diode (LED) may be a nanorod light-emitting diode. The nanorod light-emitting diode may include gallium nitride (GaN).

[0054] In an embodiment, the light-emitting diode (LED) may be a quantum dot light-emitting diode. As described above, the emission layer of the light-emitting diode (LED) may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots. Hereinafter, for ease of description, the case where the light-emitting diode (LED) includes an organic light-emitting diode is described.

[0055] Each light-emitting diode (LED) may be electrically connected to a sub-pixel circuit (PC), and each sub-pixel circuit (PC) may include a transistor and a capacitor. The sub-pixel circuits (PC) may each be electrically connected to a peripheral circuit arranged in a peripheral area (PA). The peripheral circuit arranged in the peripheral area (PA) may include a scan driving circuit 20, a terminal portion (PAD), a driving power supply line 11, and a common power supply line 13.

[0056] The scan driving circuit 20 may be configured to provide a scan signal to each of the sub-pixel circuits (PC) through a scan line (SL), and provide an emission control signal to each of the sub-pixel circuits (PC) through an emission control line (EL). The scan driving circuit 20 may be arranged on two opposite sides around a display area (DA). The sub-pixel circuits (PC) arranged in the display area (DA) may be electrically connected to at least one of the scan driving circuits 20 provided on the left and right sides.

[0057] The terminal portion (PAD) may be arranged on one side of the substrate 100. The terminal portion (PAD) may be exposed without being covered by an insulating layer and connected to a display circuit board 30. A display driver 32 may be arranged on the display circuit board 30.

[0058] The display driver 32 can be configured to generate a control signal transmitted to the scan driver circuit 20. The display driver 32 can be configured to generate a data signal, and the generated data signal can be transmitted to the sub-pixel circuit PC through the fan-out wiring FW and the data line DL connected to the fan-out wiring FW.

[0059] The display driver 32 can be configured to supply the driving voltage ELVDD (see Figure 2 ) to the driving power line 11 and supply the common voltage ELVSS (see Figure 2 ) to the common power line 13. The driving voltage ELVDD can be applied to the sub-pixel circuit PC through the driving voltage line PL connected to the driving power line 11, and the common voltage ELVSS can be applied to the opposite electrode (e.g., the cathode) of the light-emitting diode LED through the common power line 13.

[0060] The driving power line 11 can extend in the x direction below the display area DA. The common power line 13 can have an annular shape with an open side to partially surround the display area DA.

[0061] Figure 1 The display device 10 is a device for displaying moving images or still images and can be used in portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile personal computers (UMPCs), etc. In other embodiments, the display device 10 can be used as a display screen for various products, including televisions, notebook computers, monitors, billboards, Internet of Things (IoT) devices, etc. In addition, according to an embodiment, the display device 10 can be used in wearable devices, including smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, in an embodiment, the display device 10 is applicable to a display screen in an instrument panel of an automobile, a central dashboard of an automobile, or a central information display (CID) arranged on the dashboard, an in-vehicle mirror display replacing the side mirror of an automobile, and a display of an entertainment system arranged on the back surface of the front seat of a rear seat passenger in an automobile.

[0062] In an embodiment, the display device 10 can be a foldable display device. As an example, the display device 10 can be folded around a folding axis extending in a first direction (e.g., the x direction) or a second direction (e.g., the y direction).

[0063] Figure 2 is a schematic equivalent circuit diagram of the light-emitting diode LED and the sub-pixel circuit PC electrically connected thereto of the display device 10 according to an embodiment.

[0064] Refer to Figure 1 andFigure 2 A light-emitting diode LED can be electrically connected to a sub-pixel circuit PC, where the sub-pixel circuit PC includes a plurality of transistors and capacitors. In an embodiment, the light-emitting diode LED can be an organic light-emitting diode OLED.

[0065] As an example, the sub-pixel circuit PC can include a plurality of thin-film transistors T1, T2, T3, T4, T5, T6, and T7, a first capacitor Cst, and a second capacitor Cbt. In an embodiment, the plurality of thin-film transistors T1, T2, T3, T4, T5, T6, and T7 can include a driving transistor T1, a switching transistor T2, a compensating transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6, and a second initialization transistor T7. In an embodiment, the first capacitor Cst can be a storage capacitor, and the second capacitor Cbt can be a boosting capacitor. However, the embodiments are not limited thereto. In an embodiment, the sub-pixel circuit PC may not include the second capacitor Cbt.

[0066] The organic light-emitting diode OLED can include a sub-pixel electrode and a counter electrode. The sub-pixel electrode of the organic light-emitting diode OLED can be connected to the driving transistor T1 through the emission control transistor T6 and can receive a driving current I d and the counter electrode can be configured to receive a common voltage ELVSS. The organic light-emitting diode OLED can be configured to generate light with a brightness corresponding to the driving current I d corresponding.

[0067] In an embodiment, some of the plurality of thin-film transistors T1, T2, T3, T4, T5, T6, and T7 can be n-channel metal-oxide-semiconductor (NMOS) field-effect transistors (n-channel MOSFETs), and the remaining transistors can be p-channel metal-oxide-semiconductor (PMOS) field-effect transistors (p-channel MOSFETs). As an example, as Figure 2 shown, among the plurality of thin-film transistors T1, T2, T3, T4, T5, T6, and T7, the compensating transistor T3 and the first initialization transistor T4 can be n-channel MOSFETs (NMOS), and the remaining transistors can be p-channel MOSFETs (PMOS).

[0068] The signal lines may include a first scan line GWL, a second scan line GCL, a third scan line GIL, an emission control line EML, a fourth scan line GBL, and a data line DL. The first scan line GWL is configured to transmit a first scan signal GW, the second scan line GCL is configured to transmit a second scan signal GC, the third scan line GIL is configured to transmit a third scan signal GI to a first initialization transistor T4, the emission control line EML is configured to transmit an emission control signal EM to an operation control transistor T5 and an emission control transistor T6, the fourth scan line GBL is configured to transmit a fourth scan signal GB to a second initialization transistor T7, and the data line DL is configured to transmit a data signal Dm.

[0069] The driving voltage line PL may be configured to transmit a driving voltage ELVDD to the driving transistor T1. The first initialization voltage line VIL1 may be configured to transmit a first initialization voltage Vint to the sub-pixel circuit PC, wherein the first initialization voltage Vint initializes the driving transistor T1. The second initialization voltage line VIL2 may be configured to transmit a second initialization voltage Vaint to the sub-pixel circuit PC, wherein the second initialization voltage Vaint initializes the organic light-emitting diode OLED. Specifically, the first initialization voltage line VIL1 may be configured to transmit the first initialization voltage Vint to the first initialization transistor T4, and the second initialization voltage line VIL2 may be configured to transmit the second initialization voltage Vaint to the second initialization transistor T7.

[0070] In an embodiment, the signal lines, the first initialization voltage line VIL1, the second initialization voltage line VIL2, the driving voltage line PL, and the common voltage line VSL may be shared by the sub-pixel circuit PC.

[0071] The gate electrode of the driving transistor T1 may be connected to a first capacitor Cst and a second capacitor Cbt via a second node N2. One of the source region and the drain region of the driving transistor T1 may be connected to the driving voltage line PL via a first node N1 through the operation control transistor T5, and the other of the source region and the drain region of the driving transistor T1 may be electrically connected to the sub-pixel electrode of the organic light-emitting diode OLED through the emission control transistor T6. The driving transistor T1 may be configured to receive the data signal Dm according to the switching operation of the switching transistor T2 and provide a driving current I d to the organic light-emitting diode OLED.

[0072] The gate electrode of the switching transistor T2 can be connected to the first scan line GWL configured to transmit the first scan signal GW and the second capacitor Cbt. One of the source region and the drain region of the switching transistor T2 can be connected to the data line DL, and the other of the source region and the drain region of the switching transistor T2 can be connected to the driving transistor T1 through the first node N1 and to the driving voltage line PL through the operation control transistor T5. The switching transistor T2 can perform a conduction switching operation according to the first scan signal GW transmitted through the first scan line GWL, and transmit the data signal Dm to the driving transistor T1 through the first node N1, and the data signal Dm is transmitted through the data line DL.

[0073] The gate electrode of the compensation transistor T3 is connected to the second scan line GCL. One of the source region and the drain region of the compensation transistor T3 can be connected to the sub-pixel electrode of the organic light emitting diode OLED through the emission control transistor T6. The other of the source region and the drain region of the compensation transistor T3 can be connected to the first capacitor Cst and to the gate electrode of the driving transistor T1 through the node connection line 166. The compensation transistor T3 can be turned on according to the second scan signal GC to compensate for the threshold voltage of the driving transistor T1 by diode-connecting the driving transistor T1, wherein the second scan signal GC is transmitted through the second scan line GCL.

[0074] The gate electrode of the first initialization transistor T4 can be connected to the third scan line GIL. One of the source region and the drain region of the first initialization transistor T4 can be connected to the first initialization voltage line VIL1. The other of the source region and the drain region of the first initialization transistor T4 can be connected to the first capacitor electrode CE1 of the first capacitor Cst and to the gate electrode of the driving transistor T1. The first initialization transistor T4 can be turned on according to the third scan signal GI received through the third scan line GIL, and can initialize the voltage of the gate voltage of the driving transistor T1 by transmitting the first initialization voltage Vint to the gate electrode of the driving transistor T1.

[0075] The gate electrode of the operation control transistor T5 can be connected to the emission control line EML. One of the source region and the drain region of the operation control transistor T5 can be connected to the driving voltage line PL, and the other of the source region and the drain region of the operation control transistor T5 can be connected to the driving transistor T1 and the switching transistor T2 through the first node N1.

[0076] The gate electrode of the emission control transistor T6 can be connected to the emission control line EML. One of the source region and the drain region of the emission control transistor T6 can be connected to the driving transistor T1 and the compensation transistor T3, and the other of the source region and the drain region of the emission control transistor T6 can be electrically connected to the sub-pixel electrode of the organic light emitting diode OLED.

[0077] The operation control transistor T5 and the emission control transistor T6 can be turned on simultaneously according to an emission control signal EML transmitted through an emission control line EML, and a current path can be formed such that a driving current I d flows in a direction from a driving voltage line PL to an organic light emitting diode OLED.

[0078] A gate electrode of a second initialization transistor T7 can be connected to a fourth scan line GBL, one of a source region and a drain region of the second initialization transistor T7 can be connected to a sub-pixel electrode of the organic light emitting diode OLED, and the other of the source region and the drain region of the second initialization transistor T7 can be electrically connected to a second initialization voltage line VIL2 to receive a second initialization voltage Vaint. The second initialization transistor T7 can be turned on according to a fourth scan signal GB transmitted through the fourth scan line GBL, and can initialize the sub-pixel electrode of the organic light emitting diode OLED.

[0079] In an embodiment, the fourth scan signal GB can be substantially synchronized with the first scan signal GW. In an embodiment, the fourth scan signal GB can be substantially synchronized with the first scan signal GW of a sub-pixel located in a next row. As an example, the fourth scan line GBL can be substantially the same as the first scan line GWL of a sub-pixel in a next row.

[0080] The first capacitor Cst can include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 can be connected to a gate electrode of the driving transistor T1, and the second capacitor electrode CE2 can be connected to the driving voltage line PL. The first capacitor Cst can hold a voltage applied to the gate electrode of the driving transistor T1 by storing and holding a voltage corresponding to a difference between voltages of two opposite ends of the gate electrode of the driving transistor T1 and the driving voltage line PL.

[0081] The second capacitor Cbt can include a third capacitor electrode CE3 and a fourth capacitor electrode CE4. The third capacitor electrode CE3 can be connected to the first scan line GWL and a gate electrode of the switching transistor T2. The fourth capacitor electrode CE4 can be connected to the gate electrode of the driving transistor T1 and the first capacitor electrode CE1 of the first capacitor Cst. The second capacitor Cbt serves as a boosting capacitor. When the first scan signal GW of the first scan line GWL is a voltage that turns off the switching transistor T2, the second capacitor Cbt can be configured to clearly present a black gray level by increasing a voltage of a second node N2.

[0082] In an embodiment, at least one of the plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 may include a semiconductor layer containing an oxide, and the remaining transistors may include a semiconductor layer containing amorphous silicon or polycrystalline silicon.

[0083] Specifically, the driving transistor T1 that directly affects the brightness of the display device 10 may be configured to include a semiconductor layer containing polycrystalline silicon having high reliability, and thus, a high-resolution display device may be achieved through such a configuration.

[0084] Because the oxide semiconductor has a high carrier mobility and a low leakage current, even if the driving time is long, the voltage drop may not be large. That is, because even when the display device 10 is driven at a low frequency, the color change of the image according to the voltage drop is not large, the display device 10 may be driven at a low frequency.

[0085] Because the oxide semiconductor has the advantage of a low leakage current, at least one of the compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T7 connected to the gate electrode of the driving transistor T1 may include an oxide semiconductor, and thus, the leakage current that may flow to the gate electrode of the driving transistor T1 can be prevented, and at the same time, the power consumption can be reduced.

[0086] In an embodiment, as Figure 2 shown, the compensation transistor T3 and the first initialization transistor T4 may include an oxide semiconductor, and thus, the power consumption of the display device 10 can be even further improved.

[0087] Figure 3 is a schematic cross-sectional view of the display device 10 taken along the Figure 1 line I-I' according to an embodiment. In addition, Figure 4 is a plan view of the first hole H1 and the first contact hole PCNT1 of the display device 10 according to an embodiment.

[0088] Referring to Figure 3 , the first thin film transistor TFT1, the second thin film transistor TFT2, and the first capacitor Cst may be arranged in the display area DA. The first thin film transistor TFT1 may correspond to Figure 2 the driving transistor T1, and the second thin film transistor TFT2 may correspond to Figure 2 the compensation transistor T3 and the first initialization transistor T4. In an embodiment, the first thin film transistor TFT1 may be set as a p-channel MOSFET, and the second thin film transistor TFT2 may be set as an n-channel MOSFET.

[0089] The first thin film transistor TFT1 may include a first semiconductor layer Act1 and a first gate electrode GE1 that at least partially overlaps with the first semiconductor layer Act1.

[0090] The second thin film transistor TFT2 may include a second semiconductor layer Act2 and a second gate electrode GE2 that at least partially overlaps with the second semiconductor layer Act2. The second gate electrode GE2 may include a second lower gate electrode GE2a and a second upper gate electrode GE2b.

[0091] In an embodiment, the first semiconductor layer Act1 of the first thin film transistor TFT1 and the second semiconductor layer Act2 of the second thin film transistor TFT2 may include different materials from each other. As an example, the first semiconductor layer Act1 may include a silicon semiconductor material, and the second semiconductor layer Act2 may include an oxide semiconductor material.

[0092] The first capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor Cst may overlap with the first thin film transistor TFT1.

[0093] The substrate 100 may include a glass material, a ceramic material, a metal, or a flexible or bendable material. In the case where the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin, and the polymer resin includes polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate.

[0094] The substrate 100 may have a single-layer structure or a multi-layer structure of the above materials, and may further include an inorganic layer in the case of a multi-layer structure. In an embodiment, the substrate 100 may have a structure of organic material / inorganic material / organic material.

[0095] A barrier layer (not shown) may be further provided between the substrate 100 and the buffer layer 110. The barrier layer may be configured to prevent or reduce impurities from below the substrate 100 from passing through the first semiconductor layer Act1 and the second semiconductor layer Act2. The barrier layer may include an inorganic material, an organic material, or an organic / inorganic composite material, and includes a single layer or multiple layers containing an inorganic material and an organic material, and the inorganic material includes an oxide or a nitride.

[0096] The bottom metal layer BML may be provided between the substrate 100 and the buffer layer 110. The bottom metal layer BML may include a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and includes a single layer or multiple layers containing the above materials.

[0097] The bottom metal layer BML can overlap with at least a part of the first semiconductor layer Act1. The bottom metal layer BML can protect the first semiconductor layer Act1. The bottom metal layer BML can be configured to receive an arbitrary (or preset) voltage. Due to the bottom metal layer BML applied with an arbitrary voltage, unnecessary charges can be prevented from accumulating on the first semiconductor layer Act1 while driving the sub-pixel circuit PC, where the sub-pixel circuit PC includes both an n-channel MOSFET and a p-channel MOSFET. Therefore, the characteristics of the first thin-film transistor TFT1 including the first semiconductor layer Act1 can be stably maintained.

[0098] The first semiconductor layer Act1 can be disposed on the buffer layer 110. The first semiconductor layer Act1 can include amorphous silicon or polycrystalline silicon. The first semiconductor layer Act1 can include a channel region, a drain region, and a source region, with the drain region and the source region on two opposite sides of the channel region. The source region and the drain region can each be a region doped with a dopant. The first semiconductor layer Act1 can include a single layer or multiple layers.

[0099] The first gate insulating layer 111 can be disposed on the first semiconductor layer Act1. The first gate insulating layer 111 can include an inorganic insulating layer, the inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and the first gate insulating layer 111 can include a single-layer or multi-layer structure including the above materials. In an embodiment, the first gate insulating layer 111 can be the first insulating layer.

[0100] The first gate electrode GE1 and the first capacitor electrode CE1 can be disposed on the first gate insulating layer 111. In an embodiment, the first gate electrode GE1 can be integrally formed with the first capacitor electrode CE1. The first gate electrode GE1 can perform the function of the first capacitor electrode CE1, or the first capacitor electrode CE1 can perform the function of the first gate electrode GE1.

[0101] The first gate electrode GE1 and the first capacitor electrode CE1 can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and include a single-layer or multi-layer including the above materials.

[0102] The first interlayer insulating layer 113 may be disposed on the first gate electrode GE1 and / or the first capacitor electrode CE1. The first interlayer insulating layer 113 may include an inorganic insulating layer, the inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and the first interlayer insulating layer 113 may include a single-layer or multi-layer structure including the above materials. In an embodiment, the first interlayer insulating layer 113 may be a second-first insulating layer.

[0103] The second capacitor electrode CE2 may be disposed on the first interlayer insulating layer 113. The second capacitor electrode CE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and include a single-layer or multi-layer including the above materials.

[0104] The second capacitor electrode CE2 may overlap with the first gate electrode GE1 and / or the first capacitor electrode CE1. In Figure 3 this case, the second capacitor electrode CE2 may overlap with the first capacitor electrode CE1, and the first interlayer insulating layer 113 is therebetween, and they form a capacitance. In this case, the first interlayer insulating layer 113 may be used as a dielectric layer.

[0105] The second interlayer insulating layer 117a may be disposed on the second capacitor electrode CE2. The second interlayer insulating layer 117a may include an inorganic insulating layer, the inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and the second interlayer insulating layer 117a may have a single-layer structure or a multi-layer structure including the above materials. As an example, the second interlayer insulating layer 117a may be a single-layer of silicon nitride. In an embodiment, the second interlayer insulating layer 117a may be a second-second insulating layer. The first interlayer insulating layer 113 and the second interlayer insulating layer 117a may be a second insulating layer.

[0106] The first hole H1 and the second hole H2 may be defined in the insulating layer between the first semiconductor layer Act1 and the second semiconductor layer Act2. As an example, the first hole H1 and the second hole H2 may be defined in the first gate insulating layer 111, the first interlayer insulating layer 113, and the second interlayer insulating layer 117a, and may pass through the first gate insulating layer 111, the first interlayer insulating layer 113, and the second interlayer insulating layer 117a. Each of the first hole H1 and the second hole H2 may overlap with a source region or a drain region of the first semiconductor layer Act1. As an example, the first hole H1 may overlap with one of the source region and the drain region of the first semiconductor layer Act1, and the second hole H2 may overlap with the other of the source region and the drain region of the first semiconductor layer Act1.

[0107] The third interlayer insulating layer 117b may be disposed on the second interlayer insulating layer 117a. The third interlayer insulating layer 117b may include an inorganic insulating layer, the inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and the third interlayer insulating layer 117b may have a single-layer structure or a multi-layer structure including the above materials. The third interlayer insulating layer 117b may be an inorganic insulating layer having a relatively small hydrogen content compared to other inorganic insulating layers of the display device 10. As an example, the third interlayer insulating layer 117b may be a single layer of silicon oxide. In an embodiment, the third interlayer insulating layer 117b may be the fifth insulating layer.

[0108] The third interlayer insulating layer 117b may fill at least a part of each of the first hole H1 and the second hole H2. In other words, a part of the third interlayer insulating layer 117b may fill at least a part of the first hole H1 and the second hole H2. The third interlayer insulating layer 117b may cover the inner surfaces of the insulating layers forming the first hole H1 and the second hole H2. The third interlayer insulating layer 117b may cover the inner surfaces of the first gate insulating layer 111, the first interlayer insulating layer 113, and the second interlayer insulating layer 117a that form the first hole H1 and the second hole H2.

[0109] The second semiconductor layer Act2 may be disposed on the third interlayer insulating layer 117b. The second semiconductor layer Act2 may include an oxide semiconductor material. The second semiconductor layer Act2 may include an oxide of at least one of, for example, indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). As an example, the second semiconductor layer Act2 may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, or the like.

[0110] The second semiconductor layer Act2 may include a channel region, a drain region, and a source region, the drain region and the source region being on two opposite sides of the channel region. The second semiconductor layer Act2 may include a single layer or multiple layers.

[0111] The second gate electrode GE2 may be disposed under and / or on the second semiconductor layer Act2. The second lower gate electrode GE2a may be disposed under the second semiconductor layer Act2. The second upper gate electrode GE2b may be disposed on the second semiconductor layer Act2. In an embodiment, the second upper gate electrode GE2b may be the second gate electrode, and the second lower gate electrode GE2a may be the third gate electrode.

[0112] The second lower gate electrode GE2a may include the same material as that of the second capacitor electrode CE2 and be disposed on the same layer (e.g., the first interlayer insulating layer 113). Since the second semiconductor layer Act2 including an oxide semiconductor material is susceptible to light, the second semiconductor layer Act2 may be protected by the second lower gate electrode GE2a. The second lower gate electrode GE2a may prevent photocurrent from being introduced into the second semiconductor layer Act2 due to external light incident from the direction of the substrate 100, and thus prevent the device characteristics of the second thin film transistor TFT2 including an oxide semiconductor material from changing.

[0113] The second upper gate electrode GE2b may be disposed on the second gate insulating layer 119. The second upper gate electrode GE2b may overlap with the second lower gate electrode GE2a, and the second gate insulating layer 119 is therebetween. The second upper gate electrode GE2b may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and include a single layer or multiple layers containing the above materials. In an embodiment, the second gate insulating layer 119 may be the third insulating layer.

[0114] Although the second gate insulating layer 119 is shown in Figure 3 to be disposed to cover the second semiconductor layer Act2 over the entire surface of the substrate 100, in an embodiment, the second gate insulating layer 119 may be patterned to overlap a part of the second semiconductor layer Act2. As an example, the second gate insulating layer 119 may be patterned to overlap the channel region of the second semiconductor layer Act2.

[0115] The fourth interlayer insulating layer 121 may be disposed on the second upper gate electrode GE2b. The fourth interlayer insulating layer 121 may include an inorganic insulating layer, the inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and the fourth interlayer insulating layer 121 may include a single layer or a multi-layer structure containing the above materials. In an embodiment, the fourth interlayer insulating layer 121 may be the fourth insulating layer.

[0116] The first connection electrode E1, the second connection electrode E2, the third connection electrode E3, and the fourth connection electrode E4 may be disposed on the fourth interlayer insulating layer 121. The first connection electrode E1 to the fourth connection electrode E4 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and include a single layer or multiple layers containing the above materials. As an example, the first connection electrode E1 to the fourth connection electrode E4 may have a three-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0117] The first contact hole PCNT1 and the second contact hole PCNT2 may be defined in the insulating layer between the first connection electrode E1 and the second connection electrode E2 and the first semiconductor layer Act1. Refer to Figure 3 and Figure 4 , the first contact hole PCNT1 may be within the first hole H1 and overlap with the first hole H1. The second contact hole PCNT2 may be within the second hole H2 and overlap with the second hole H2. The widths of the first contact hole PCNT1 and the second contact hole PCNT2 may be less than the widths of the first hole H1 and the second hole H2, respectively. That is, the widths of the first hole H1 and the second hole H2 may be greater than the widths of the first contact hole PCNT1 and the second contact hole PCNT2, respectively. As an example, as Figure 4 shown, the width W1 of the first hole H1 may be greater than the width W2 of the first contact hole PCNT1. In other words, the first contact hole PCNT1 may completely overlap with the first hole H1. The second contact hole PCNT2 may completely overlap with the second hole H2.

[0118] In an embodiment, the difference between the width W1 of the first hole H1 and the width W2 of the first contact hole PCNT1 may be about 0.8 μm to about 1.8 μm. In an embodiment, the width W1 of the first hole H1 may be about 2.6 μm to about 3.2 μm.

[0119] Since the first hole H1 and the second hole H2 have widths larger than the widths of the first contact hole PCNT1 and the second contact hole PCNT2, hydrogen emission from the first semiconductor layer Act1 through the first hole H1 and the second hole H2 can be rapidly performed in the heat treatment process described in the following reference Figure 5B .

[0120] The first contact hole PCNT1 and the second contact hole PCNT2 may be defined in the third interlayer insulating layer 117b, the second gate insulating layer 119, and the fourth interlayer insulating layer 121, and may penetrate through the third interlayer insulating layer 117b, the second gate insulating layer 119, and the fourth interlayer insulating layer 121. The first contact hole PCNT1 may penetrate through a part of the third interlayer insulating layer 117b filling the first hole H1. The second contact hole PCNT2 may penetrate through a part of the third interlayer insulating layer 117b filling the second hole H2. Each of the first contact hole PCNT1 and the second contact hole PCNT2 may overlap with a source region or a drain region of the first semiconductor layer Act1.

[0121] The first connection electrode E1 may be electrically connected to the first semiconductor layer Act1 through the first contact hole PCNT1. A part of the first connection electrode E1 may fill at least a part of the first contact hole PCNT1. A part of the first connection electrode E1 may be buried in the first contact hole PCNT1. The first connection electrode E1 may contact the first semiconductor layer Act1 through the first contact hole PCNT1. The part of the first connection electrode E1 filling the first contact hole PCNT1 may contact the third interlayer insulating layer 117b filling the first hole H1.

[0122] The second connection electrode E2 may be electrically connected to the first semiconductor layer Act1 through the second contact hole PCNT2. A part of the second connection electrode E2 may fill at least a part of the second contact hole PCNT2. A part of the second connection electrode E2 may be buried in the second contact hole PCNT2. The second connection electrode E2 may contact the first semiconductor layer Act1 through the second contact hole PCNT2. The part of the second connection electrode E2 filling the second contact hole PCNT2 may contact the third interlayer insulating layer 117b filling the second hole H2.

[0123] The third contact hole OCNT1 and the fourth contact hole OCNT2 may be defined in the insulating layer between the third connection electrode E3 and the fourth connection electrode E4 and the second semiconductor layer Act2.

[0124] The third contact hole OCNT1 and the fourth contact hole OCNT2 may be defined in the second gate insulating layer 119 and the fourth interlayer insulating layer 121, and may penetrate through the second gate insulating layer 119 and the fourth interlayer insulating layer 121. Each of the third contact hole OCNT1 and the fourth contact hole OCNT2 may overlap with a source region or a drain region of the second semiconductor layer Act2.

[0125] The third connection electrode E3 can be electrically connected to the second semiconductor layer Act2 through the third contact hole OCNT1. A part of the third connection electrode E3 can fill at least a part of the third contact hole OCNT1. A part of the third connection electrode E3 can be buried in the third contact hole OCNT1. The third connection electrode E3 can be in contact with the second semiconductor layer Act2 through the third contact hole OCNT1.

[0126] The fourth connection electrode E4 can be electrically connected to the second semiconductor layer Act2 through the fourth contact hole OCNT2. A part of the fourth connection electrode E4 can fill at least a part of the fourth contact hole OCNT2. A part of the fourth connection electrode E4 can be buried in the fourth contact hole OCNT2. The fourth connection electrode E4 can be in contact with the second semiconductor layer Act2 through the fourth contact hole OCNT2.

[0127] The planarization layer 123 can be disposed on the first connection electrode E1 to the fourth connection electrode E4. The planarization layer 123 can include a single layer or multiple layers containing an organic material and provide a flat upper surface. The planarization layer 123 can include a general polymer (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a parylene polymer, a vinyl alcohol-based polymer, and blends thereof.

[0128] The light-emitting diode LED can be disposed on the planarization layer 123. The light-emitting diode LED can be an organic light-emitting diode OLED. The organic light-emitting diode OLED can include a sub-pixel electrode 210, an intermediate layer 220, and a counter electrode 230, wherein the intermediate layer 220 includes an emission layer.

[0129] The sub-pixel electrode 210 can be a (semi) transparent electrode or a reflective electrode. In an embodiment, the sub-pixel electrode 210 can include a reflective layer and a transparent or semi-transparent electrode layer on the reflective layer, wherein the reflective layer includes at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof. The transparent or semi-transparent electrode layer can include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In an embodiment, the sub-pixel electrode 210 can include ITO / Ag / ITO.

[0130] The sub-pixel electrode 210 can be connected to the first connection electrode E1 through a contact hole formed in the planarization layer 123. The sub-pixel electrode 210 can be electrically connected to the first semiconductor layer Act1 through the first connection electrode E1.

[0131] The bank layer 127 can be disposed on the planarization layer 123. In addition, the bank layer 127 can prevent the occurrence of arcs or the like at the edge of the sub-pixel electrode 210 by increasing the distance between the edge of the sub-pixel electrode 210 and the counter electrode 230 above the sub-pixel electrode 210.

[0132] The bank layer 127 can include an organic insulating material such as polyimide, acrylic resin, benzocyclobutene, phenolic resin, etc., and is formed by using spin coating or the like. The bank layer 127 can include an organic insulating material. The bank layer 127 can include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In other embodiments, the bank layer 127 can include an organic insulating material and an inorganic insulating material. In an embodiment, the bank layer 127 can include a light-blocking material and be set to black. In the case where the bank layer 127 includes a light-blocking material, external light reflection caused by the metal structure disposed below the bank layer 127 can be reduced.

[0133] The intermediate layer 220 can be disposed in the opening of the bank layer 127. The intermediate layer 220 can include an emission layer. The emission layer can include an organic material, and the organic material includes a fluorescent material or a phosphorescent material that emits red light, green light, blue light, or white light. The emission layer can include a polymer organic material or a low molecular weight organic material. Functional layers can be selectively further disposed under and on the emission layer, and the functional layers include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL).

[0134] The intermediate layer 220 can be disposed corresponding to the plurality of sub-pixel electrodes 210. However, the embodiments are not limited thereto. The intermediate layer 220 can include a layer integrated over the plurality of sub-pixel electrodes 210. However, various modifications can be made.

[0135] The counter electrode 230 may be a transmissive electrode or a reflective electrode. In an embodiment, the counter electrode 230 may be a transparent or semi-transparent electrode and may include a metal thin film including Li, Ca, F, Al, Ag, Mg, or a compound thereof, or a material having a multi-layer structure such as LiF / Ca or LiF / Al, and having a small work function. In addition, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In2O3 may be further disposed on the metal thin film. The counter electrode 230 may be disposed to extend over the display area DA and be provided on the intermediate layer 220 and the bank layer 127. The counter electrode 230 may be integrally formed to extend over a plurality of organic light-emitting diodes OLEDs to correspond to the plurality of sub-pixel electrodes 210.

[0136] The organic light-emitting diode OLED may be covered by a packaging layer (not shown). The packaging layer may include at least one organic packaging layer and at least one inorganic packaging layer. The inorganic packaging layer may include an inorganic material including alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, silicon oxynitride, etc. The organic packaging layer may include a polymer-based material. The polymer-based material may include an acrylic-based resin (such as polymethyl methacrylate and polyacrylic acid), an epoxy-based resin, polyimide, and polyethylene. In an embodiment, the organic packaging layer may include an acrylic polymer.

[0137] Figures 5A to 5E is a cross-sectional view showing a process of manufacturing the display device 10 according to an embodiment. Through Figures 5A to 5E the process shown in, the Figure 3 display device 10 may be formed.

[0138] Referring to Figure 5A , a first thin-film transistor TFT1, a first capacitor Cst, and a second lower gate electrode GE2a may be formed on the substrate 100 in the display area DA.

[0139] A bottom metal layer BML may be formed on the substrate 100, and a buffer layer 110 may be formed. A first semiconductor layer Act1 of the first thin-film transistor TFT1 may be formed on the buffer layer 110. A first gate insulating layer 111 covering the first semiconductor layer Act1 may be formed, and a first gate electrode GE1 may be formed. The first gate electrode GE1 may be integrally formed with a first capacitor electrode CE1 of the first capacitor Cst. Thus, the first thin-film transistor TFT1 may be formed.

[0140] A first interlayer insulating layer 113 can be formed to cover the first gate electrode GE1 and / or the first capacitor electrode CE1. A second capacitor electrode CE2 and a second lower gate electrode GE2a can be formed on the first interlayer insulating layer 113. A second interlayer insulating layer 117a can be formed to cover the second capacitor electrode CE2 and the second lower gate electrode GE2a.

[0141] Reference Figure 5B , a first hole H1 and a second hole H2 can be formed. The first hole H1 and the second hole H2 can penetrate through the first gate insulating layer 111, the first interlayer insulating layer 113, and the second interlayer insulating layer 117a. Each of the first hole H1 and the second hole H2 can be above a source region or a drain region of the first semiconductor layer Act1 and overlap with the source region or the drain region of the first semiconductor layer Act1.

[0142] The first hole H1 and the second hole H2 are formed, and a heat treatment can be performed on the stacked structure. As an example, the first semiconductor layer Act1 can be heat treated. In the case of heat treating the first semiconductor layer Act1, hydrogen (H) bonded to silicon (Si) of the first semiconductor layer Act1 including a silicon semiconductor material can be released through the first hole H1 and the second hole H2. The device characteristics of the first thin film transistor TFT1 can be controlled by intentionally inducing defects in the first semiconductor layer Act1. Specifically, the device characteristics of the first thin film transistor TFT1 can be improved by ensuring the dynamic range of the first thin film transistor TFT1 and optimizing the sensitivity.

[0143] In an embodiment, the heat treatment process can be performed at 380 °C for about 15 minutes.

[0144] Reference Figure 5C , a third interlayer insulating layer 117b can be formed on the second interlayer insulating layer 117a. The third interlayer insulating layer 117b can fill at least a part of each of the first hole H1 and the second hole H2. A part of the third interlayer insulating layer 117b can fill at least a part of the first hole H1 and the second hole H2. The third interlayer insulating layer 117b can cover the inner surfaces of the first gate insulating layer 111, the first interlayer insulating layer 113, and the second interlayer insulating layer 117a that form the first hole H1 and the second hole H2.

[0145] A second semiconductor layer Act2 can be formed on the third interlayer insulating layer 117b. The second semiconductor layer Act2 can overlap with the second lower gate electrode GE2a. A second gate insulating layer 119 can be formed to cover the second semiconductor layer Act2. A second upper gate electrode GE2b can be formed on the second gate insulating layer 119. A second thin film transistor TFT2 can be formed. A fourth interlayer insulating layer 121 can be formed to cover the second upper gate electrode GE2b.

[0146] A first contact hole PCNT1 and a second contact hole PCNT2 can be formed. The first contact hole PCNT1 can be within the first hole H1 and overlap with the first hole H1. The second contact hole PCNT2 can be within the second hole H2 and overlap with the second hole H2. The widths of the first contact hole PCNT1 and the second contact hole PCNT2 can be smaller than the widths of the first hole H1 and the second hole H2, respectively.

[0147] The first contact hole PCNT1 and the second contact hole PCNT2 can penetrate through the third interlayer insulating layer 117b, the second gate insulating layer 119, and the fourth interlayer insulating layer 121. The first contact hole PCNT1 can penetrate through a part of the third interlayer insulating layer 117b that fills the first hole H1. The second contact hole PCNT2 can penetrate through a part of the third interlayer insulating layer 117b that fills the second hole H2. Each of the first contact hole PCNT1 and the second contact hole PCNT2 can overlap with a source region or a drain region of the first semiconductor layer Act1.

[0148] Reference Figure 5D , a third contact hole OCNT1 and a fourth contact hole OCNT2 can be formed. The third contact hole OCNT1 and the fourth contact hole OCNT2 can penetrate through the second gate insulating layer 119 and the fourth interlayer insulating layer 121. Each of the third contact hole OCNT1 and the fourth contact hole OCNT2 can overlap with a source region or a drain region of the second semiconductor layer Act2.

[0149] Reference Figure 5E , first connection electrodes E1 to fourth connection electrodes E4 can be formed on the fourth interlayer insulating layer 121.

[0150] The first connection electrode E1 can contact the first semiconductor layer Act1 through the first contact hole PCNT1. A part of the first connection electrode E1 that fills the first contact hole PCNT1 can contact the third interlayer insulating layer 117b that fills the first hole H1.

[0151] The second connection electrode E2 can contact the first semiconductor layer Act1 through the second contact hole PCNT2. A part of the second connection electrode E2 that fills the second contact hole PCNT2 can contact the third interlayer insulating layer 117b that fills the second hole H2.

[0152] The third connection electrode E3 can contact the second semiconductor layer Act2 through the third contact hole OCNT1. The fourth connection electrode E4 can contact the second semiconductor layer Act2 through the fourth contact hole OCNT2.

[0153] In the comparative example, both the first thin film transistor and the second thin film transistor are formed, a hole exposing the first semiconductor layer is formed, and a process of heat-treating the first semiconductor layer can be performed. In this case, the hole can be a contact hole for allowing the first connection electrode and the second connection electrode to contact the first semiconductor layer. In this case, during the process of heat-treating the stacked structure, the insulating layer around the second semiconductor layer can be heat-treated together with the first semiconductor layer. Hydrogen can be released from the first semiconductor layer through the hole, and at the same time, hydrogen can move from the adjacent insulating layer to the second semiconductor layer. When hydrogen is introduced into the second semiconductor layer including the oxide semiconductor material, the threshold voltage of the second thin film transistor decreases and a (-) shift phenomenon may occur. That is, the device characteristics of the second thin film transistor may deteriorate. Therefore, the device characteristics of the first thin film transistor are improved, but the device characteristics of the second thin film transistor may deteriorate.

[0154] However, according to an embodiment, after the first thin film transistor TFT1 is formed, before the second semiconductor layer Act2 of the second thin film transistor TFT2 is formed, a first hole H1 and a second hole H2 extending to the first semiconductor layer Act1 and exposing the first semiconductor layer Act1 can be formed, and a heat treatment can be performed. The second semiconductor layer Act2 and the second upper gate electrode GE2b of the second thin film transistor TFT2 can be formed, and a first contact hole PCNT1 and a second contact hole PCNT2 overlapping with the first hole H1 and the second hole H2 respectively can be formed. The first contact hole PCNT1 and the second contact hole PCNT2 can be holes for allowing the first connection electrode E1 and the second connection electrode E2 to contact the first semiconductor layer Act1 respectively. In this case, since the formation of the first hole H1 and the second hole H2 and the heat treatment process are performed before the second semiconductor layer Act2 is formed, the device characteristics of the second thin film transistor TFT2 can be prevented from being changed due to the movement of hydrogen from the adjacent insulating layer to the second semiconductor layer Act2 during the heat treatment. Therefore, the device characteristics of the first thin film transistor TFT1 can be improved, and at the same time, the device characteristics of the second thin film transistor TFT2 can be maintained.

[0155] Figure 6 is a schematic cross-sectional view of a display device according to an embodiment. Figure 6 is Figure 3 a modified embodiment. Hereinafter, the differences will be mainly described, and the repeated descriptions will be omitted.

[0156] Referring to Figure 6 , an oxide layer OFL can be provided on the first semiconductor layer Act1. The oxide layer OFL can be provided in the first hole H1 and the second hole H2.

[0157] The first contact hole PCNT1 can penetrate through the oxide layer OFL provided in the first hole H1. The second contact hole PCNT2 can penetrate through the oxide layer OFL provided in the second hole H2. The oxide layer OFL can be in contact with a part of the first connection electrode E1 filling the first contact hole PCNT1. The oxide layer OFL can be in contact with a part of the second connection electrode E2 filling the second contact hole PCNT2.

[0158] The oxide layer OFL can include an oxide. The oxide layer OFL can be configured to prevent hydrogen from being introduced into the first semiconductor layer Act1.

[0159] Figures 7A to 7D is a cross-sectional view showing a process of manufacturing a display device according to an embodiment. By Figures 7A to 7D the process shown in Figure 6 a display device can be formed. Figures 7A to 7D is Figures 5A to 5E a modified embodiment. Hereinafter, the differences will be mainly described, and the repeated descriptions will be omitted.

[0160] Referring to Figure 7A , a first thin film transistor TFT1, a first capacitor Cst, and a second lower gate electrode GE2a can be formed on the substrate 100 in the display area DA. In addition, a buffer layer 110, a first gate insulating layer 111, a first interlayer insulating layer 113, and a second interlayer insulating layer 117a can be formed.

[0161] The first hole H1 and the second hole H2 are formed, and the stacked structure can be heat-treated. As an example, the first semiconductor layer Act1 can be heat-treated. By allowing hydrogen (H) bonded to silicon (Si) of the first semiconductor layer Act1 to be released through the first hole H1 and the second hole H2, the device characteristics of the first thin film transistor TFT1 can be improved.

[0162] Referring to Figure 7B , an oxide layer OFL can be formed on the first semiconductor layer Act1. The oxide layer OFL can be formed in the first hole H1 and the second hole H2.

[0163] In an embodiment, the formation of the oxide layer OFL can be performed simultaneously with the heat treatment process. As an example, the oxide layer OFL can be formed by controlling the temperature of the heat treatment process to exceed 360 °C and / or controlling the heat treatment process time to exceed 15 minutes.

[0164] In an embodiment, the formation of the oxide layer OFL can be performed as a separate process after the heat treatment process. As an example, the oxide layer OFL can be formed by an O2 plasma process. However, the embodiment is not limited thereto. The formation of the oxide layer OFL can be performed by various known methods.

[0165] Reference Figure 7C A second thin film transistor TFT2 can be formed on the first thin film transistor TFT1. In addition, a third interlayer insulating layer 117b, a second gate insulating layer 119, and a fourth interlayer insulating layer 121 can be formed.

[0166] A first contact hole PCNT1 and a second contact hole PCNT2 can be formed. The first contact hole PCNT1 can be formed within and overlap with the first hole H1, and penetrate through the third interlayer insulating layer 117b, the second gate insulating layer 119, the fourth interlayer insulating layer 121, and the oxide layer OFL. The second contact hole PCNT2 can be formed within and overlap with the second hole H2, and penetrate through the third interlayer insulating layer 117b, the second gate insulating layer 119, the fourth interlayer insulating layer 121, and the oxide layer OFL.

[0167] Reference Figure 7D A third contact hole OCNT1 and a fourth contact hole OCNT2 can be formed. First to fourth connection electrodes E1 to E4 can be formed. The first connection electrode E1 and the second connection electrode E2 can contact the first semiconductor layer Act1 through the first contact hole PCNT1 and the second contact hole PCNT2. The third connection electrode E3 and the fourth connection electrode E4 can contact the second semiconductor layer Act2 through the third contact hole OCNT1 and the fourth contact hole OCNT2.

[0168] According to an embodiment, a display device having improved transistor characteristics and a method of manufacturing the display device can be achieved. However, the scope of the present disclosure is not limited by this effect.

[0169] It should be understood that the embodiments described herein should be considered merely illustrative and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail can be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A method for manufacturing a display device, the method comprising: forming a first semiconductor layer of a first thin film transistor on the substrate; forming a first insulating layer on the first semiconductor layer; forming a first gate electrode of the first thin film transistor on the first insulating layer; forming a second insulating layer on the first gate electrode; a first hole formed over the first semiconductor layer and passing through the first insulating layer and the second insulating layer; performing a heat treatment on the first semiconductor layer; forming a second semiconductor layer of a second thin film transistor on the second insulating layer; forming a third insulating layer on the second semiconductor layer; forming a second gate electrode of the second thin film transistor on the third insulating layer; forming a fourth insulating layer on the second gate electrode; as well as A second hole is formed in the first hole and passes through the third insulating layer and the fourth insulating layer.

2. The method according to claim 1, wherein: The width of the first hole is greater than the width of the second hole.

3. The method according to claim 1 , further comprising forming a third gate electrode of the second thin film transistor disposed under the second semiconductor layer and overlapping the second semiconductor layer, in, Forming the second insulating layer includes: forming a second-first insulating layer between the first gate electrode and the third gate electrode; and A second-second insulating layer is formed on the third gate electrode.

4. The method according to claim 1, further comprising forming a fifth insulating layer between the second insulating layer and the second semiconductor layer, in, The fifth insulating layer fills at least a portion of the first hole.

5. The method according to claim 4, wherein: The fifth insulating layer includes an inorganic insulating material.

6. The method according to claim 4, wherein: The second hole passes through the fifth insulating layer filling the at least a portion of the first hole.

7. The method according to claim 4, further comprising forming an electrode on the fourth insulating layer overlapping the first semiconductor layer, in, The electrode contacts the first semiconductor layer through the second hole.

8. The method according to claim 7, wherein: The electrode contacts the fifth insulating layer filling the at least a portion of the first hole.

9. The method according to claim 1, wherein: The method further includes forming an oxide layer on the first semiconductor layer and disposed in the first hole before forming the second semiconductor layer.

10. The method according to claim 9, wherein: The second hole passes through the oxide layer.

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