Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are disclosed. The display device includes a pixel electrode on a substrate; a pixel defining layer on the substrate and the pixel electrode, and defining a pixel opening exposing at least a portion of the pixel electrode; a first sidewall pattern on the pixel defining layer and including a conductive material; a second sidewall pattern on the first sidewall pattern and having a lower surface defining an undercut structure together with a side surface of the first sidewall pattern in a cross-sectional view; a cladding pattern covering at least a portion of a side surface of the first sidewall pattern and containing a conductive material; a light emitting layer on the pixel electrode in the pixel opening; and a common electrode on the light emitting layer and electrically connected to the cladding pattern.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. More particularly, the present disclosure relates to a display device that provides visual information and a method of manufacturing the display device. Background Art

[0002] As information technology develops, the importance of a display device as a connection medium between a user and information is becoming prominent. For example, the use of display devices such as liquid crystal display ("LCD") devices, organic light emitting display ("OLED") devices, plasma display devices, quantum dot display devices, etc. is increasing.

[0003] A display device includes a plurality of conductive patterns. In order for the display device to stably display an image, a low contact resistance between the conductive patterns is desirable. Summary of the Invention

[0004] Embodiments provide a display device having improved reliability.

[0005] Embodiments provide a method of manufacturing a display device.

[0006] A display device according to an embodiment includes: a pixel electrode on a substrate; a pixel defining layer on the substrate and the pixel electrode and defining a pixel opening exposing at least a part of the pixel electrode; a first sidewall pattern on the pixel defining layer and including a conductive material; a second sidewall pattern on the first sidewall pattern and having a lower surface that, in a cross-sectional view, together with a side surface of the first sidewall pattern defines an undercut structure; a coating pattern that covers at least a part of the side surface of the first sidewall pattern and includes a conductive material; a light emitting layer in the pixel opening on the pixel electrode; and a common electrode on the light emitting layer and electrically connected to the coating pattern.

[0007] In one embodiment, the coating pattern may contact the side surface of the first sidewall pattern and the lower surface of the second sidewall pattern.

[0008] In one embodiment, the coating pattern may cover the entire portion of the lower surface of the second sidewall pattern that protrudes from the upper surface of the first sidewall pattern.

[0009] In one embodiment, the coating pattern may continuously extend from the side surface of the first sidewall pattern to the lower surface of the second sidewall pattern.

[0010] In one embodiment, the coating pattern may be located within the undercut structure.

[0011] In one embodiment, the coating pattern may overlap with the second sidewall pattern in a plan view.

[0012] In one embodiment, the coating pattern and the first sidewall pattern may comprise different materials from each other.

[0013] In one embodiment, the coating pattern may comprise molybdenum (Mo).

[0014] In one embodiment, the display device may further include an auxiliary electrode on the common electrode and in contact with the coating pattern.

[0015] In one embodiment, the contact area between the coating pattern and the auxiliary electrode may be greater than the contact area between the coating pattern and the common electrode.

[0016] In one embodiment, the auxiliary electrode may comprise a conductive oxide.

[0017] In one embodiment, the display device may further include a capping pattern on the pixel electrode, at least partially covered by the pixel defining layer, and comprising a material different from that of the coating pattern.

[0018] In one embodiment, the capping pattern may comprise a conductive oxide.

[0019] In one embodiment, the display device may further include a dummy coating pattern in contact with the upper surface of the second sidewall pattern and comprising the same material as the coating pattern.

[0020] In one embodiment, the coating pattern may cover the entire side surface of the first sidewall pattern.

[0021] In one embodiment, the coating pattern may cover a part of the side surface of the first sidewall pattern, rather than the entire side surface.

[0022] In one embodiment, the display device may further include: a dummy light-emitting layer, which is disconnected from the light-emitting layer, comprises the same material as the light-emitting layer, and is disposed on the second sidewall pattern; and a dummy common electrode, which is disconnected from the common electrode, comprises the same material as the common electrode, and is disposed on the dummy light-emitting layer.

[0023] A method of manufacturing a display device according to an embodiment includes: forming a pixel electrode on a substrate; forming a capping film on the pixel electrode; forming a pixel defining layer on the substrate to cover at least a part of the pixel electrode and at least a part of the capping film; forming a first sidewall pattern including a conductive material on the pixel defining layer, and forming a second sidewall pattern including a material different from that of the first sidewall pattern on the first sidewall pattern; removing a part of the first sidewall pattern to form an undercut structure defined by a side surface of the first sidewall pattern and a lower surface of the second sidewall pattern in a cross-sectional view; forming a coating film including a conductive material on the capping film, the pixel defining layer, the first sidewall pattern, and the second sidewall pattern; forming a coating pattern covering at least a part of the side surface of the first sidewall pattern by removing a part of the coating film via a first etching process; and forming a capping pattern by removing a part of the capping film via a second etching process.

[0024] In one embodiment, an etching rate of the capping film for the first etching process may be lower than an etching rate of the coating film for the first etching process.

[0025] In one embodiment, an etching rate of each of the first sidewall pattern, the second sidewall pattern, and the coating pattern for the second etching process may be lower than an etching rate of the capping film for the second etching process.

[0026] In one embodiment, the first etching process may be a whole surface etching process.

[0027] In one embodiment, the first etching process may be an anisotropic dry etching process.

[0028] In one embodiment, in the forming of the coating pattern, the coating film may be etched such that the coating pattern is located within the undercut structure.

[0029] In one embodiment, in the forming of the coating pattern, the coating film may be etched such that the coating pattern overlaps with the second sidewall pattern in a plan view.

[0030] In one embodiment, the coating film may be formed to cover the entirety of the first sidewall pattern and the second sidewall pattern.

[0031] The display device according to an embodiment may include a sidewall pattern disposed on a pixel defining layer and having an undercut structure. Accordingly, an emission layer may be independently formed for each pixel region through the undercut structure of the sidewall pattern, and leakage current between adjacent pixel regions may be effectively reduced or prevented. Accordingly, a high-resolution display device may be implemented even in a case where it is difficult to form an emission layer using a fine metal mask (“FMM”) due to a small interval between pixel regions and / or a small size (e.g., area) of the pixel regions.

[0032] In addition, in the display device according to an embodiment of the present invention, the sidewall pattern may include a first sidewall pattern and a second sidewall pattern stacked in sequence, and a coating pattern covering at least a part of a side surface of the first sidewall pattern and including a conductive material may be disposed on the side surface of the first sidewall pattern. Accordingly, the side surface of the first sidewall pattern may be exposed to air with relatively little or no oxygen. Accordingly, the coating pattern may effectively reduce or prevent the formation of an oxide film on the side surface of the first sidewall pattern. In addition, even when combined with oxygen in the air, a material (e.g., molybdenum (Mo)) included in the coating pattern may not form an oxide film or may form only a water-soluble and easily removable oxide film. Accordingly, the coating pattern may have a low contact resistance when contacting a common electrode and / or an auxiliary electrode receiving a power supply voltage. Accordingly, the reliability of the display device may be effectively improved.

[0033] In addition, in a method of manufacturing a display device according to an embodiment of the present invention, a coating pattern may be formed through an etching process using the undercut structure of a sidewall pattern. For example, the coating pattern may be formed through an etch-back process using an anisotropic dry etching process. Accordingly, the coating pattern may be formed without a separate mask or a photoresist pattern. Accordingly, a display device may be easily formed, and the efficiency of a manufacturing process of the display device may be effectively improved.

[0034] It should be understood that the foregoing general description and the following detailed description are both exemplary and explanatory and are intended to provide further explanation of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Exemplary non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0036] Figure 1 is a plan view illustrating a display device according to an embodiment of the present invention.

[0037] Figure 2 is for illustrating Figure 1 a cross-sectional view of an example taken along line I-I’.

[0038] Figure 3 isFigure 2 An enlarged view of region A.

[0039] Figures 4 to 14 A diagram for explaining a method of manufacturing a display device according to an embodiment of the present invention.

[0040] Figure 15 For example, along Figure 1 Another example of a cross-sectional view taken along line I-I'.

[0041] Figure 16 For example, along Figure 1 Yet another example of a cross-sectional view taken along line I-I'. Detailed Description

[0042] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, "a," "the," and "at least one" do not denote a limitation of quantity and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, "an element" and "at least one element" have the same meaning unless the context clearly indicates otherwise. "At least one" should not be construed as limiting "a." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of the stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0043] It will be understood that when an element is referred to as being "on" another element or "connected to" another element, it can be directly on the other element or directly connected to the other element, or there may be intervening elements therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0044] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, without departing from the teachings herein, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0045] Hereinafter, a display device according to an embodiment will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0046] Figure 1 FIG. is a plan view illustrating a display device according to an embodiment of the present invention. As used herein, "plan view" means a view in the thickness direction (i.e., the third direction DR3) of the substrate SUB.

[0047] Refer to Figure 1 , a display device DD according to an embodiment of the present invention may include a display area DA and a peripheral area PA. The display area DA may be an area for generating light or displaying an image by adjusting the transmittance of light provided from an external light source. The peripheral area PA may be located around the display area DA. For example, the peripheral area PA may surround the entire display area DA. The peripheral area PA may be an area where no image is displayed. However, the present invention is not limited thereto, and in another embodiment, an image may be displayed in at least a part of the peripheral area PA.

[0048] The display area DA may include a plurality of pixel areas. The pixel areas may be arranged in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the pixel areas may include a first pixel area PXA1, a second pixel area PXA2, and a third pixel area PXA3. The third direction DR3 may be a normal direction of the plane defined by the first direction DR1 and the second direction DR2. That is, the third direction DR3 may be perpendicular to the first direction DR1 and the second direction DR2.

[0049] Each of the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3 may mean an area where light emitted from a light-emitting element is emitted to the outside of the display device DD. For example, first light may be emitted from the first pixel area PXA1, second light may be emitted from the second pixel area PXA2, and third light may be emitted from the third pixel area PXA3. In one embodiment, the first light may be red light, the second light may be green light, and the third light may be blue light. However, the present invention is not limited thereto. For another example, the first pixel area to the third pixel area PXA1, PXA2, and PXA3 may be combined to emit yellow light, cyan light, and magenta light.

[0050] Each of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may have a triangular planar shape, a square planar shape, a circular planar shape, an elliptical planar shape, etc. In one embodiment, each of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may have a rectangular planar shape. However, the present invention is not necessarily limited thereto, and in another embodiment, each of the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may have a planar shape other than the rectangular planar shape. As used herein, the "planar shape" of an object is the shape of the object in a plan view.

[0051] In addition, Figure 1 Illustratively, the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 all have the same size, but the present invention is not necessarily limited thereto. In another embodiment, the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 may have different sizes from each other.

[0052] The driver for driving the pixels in the pixel regions PXA1, PXA2, and PXA3 may be provided in the peripheral region PA. For example, the driver may include a gate driver, a data driver, a light-emitting driver, etc.

[0053] Figure 2 For illustration of Figure 1 a cross-sectional view of an example taken along line I-I'. As used herein, a "cross-sectional view" means a view cut by a plane including the thickness direction (i.e., the third direction DR3) of the substrate SUB.

[0054] Referring to Figure 1 and Figure 2 , the display device DD may include a substrate SUB, a circuit layer CEL, a pixel electrode PE, a capping pattern CPP, a pixel defining layer PDL, a sidewall pattern SW, a coating pattern CLP, a first light-emitting layer to a third light-emitting layer EL1, EL2, and EL3, a first dummy light-emitting layer to a third dummy light-emitting layer DEL1, DEL2, and DEL3, a common electrode CE, a dummy common electrode DCE, an auxiliary electrode AE, a dummy auxiliary electrode DAE, a packaging pattern ECP, a first packaging layer ECL1, and a second packaging layer ECL2.

[0055] The pixel electrode PE, the first light-emitting layer EL1, and the common electrode CE may form the first light-emitting element LED1. The first light-emitting element LED1 may correspond to the first pixel region PXA1. The pixel electrode PE, the second light-emitting layer EL2, and the common electrode CE may form the second light-emitting element LED2. The second light-emitting element LED2 may correspond to the second pixel region PXA2. The pixel electrode PE, the third light-emitting layer EL3, and the common electrode CE may form the third light-emitting element LED3. The third light-emitting element LED3 may correspond to the third pixel region PXA3.

[0056] The substrate SUB may include a transparent or opaque material. In one embodiment, examples of materials that can be used as the substrate SUB may include glass, quartz, plastic, silicon semiconductors, etc. These may be used alone or in combination with each other.

[0057] The circuit layer CEL may be disposed on the substrate SUB. The circuit layer CEL may include a plurality of transistors. Each of the transistors may include a control electrode, an input electrode, and an output electrode. For example, the circuit layer CEL may include transistors for driving the first to third light-emitting elements LED1, LED2, and LED3.

[0058] The circuit layer CEL may include a semiconductor pattern, a conductive pattern, and signal lines. The insulating layer, the semiconductor layer, and the conductive layer may be disposed on the substrate SUB by coating, deposition, etc., and the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned. Accordingly, the circuit layer CEL including the semiconductor pattern, the conductive pattern, and the signal lines may be disposed on the substrate SUB.

[0059] The pixel electrode PE may be disposed on the circuit layer CEL. The pixel electrode PE may be electrically connected to at least one of the transistors of the circuit layer CEL. The pixel electrode PE may include a metal, an alloy, a metal oxide, a transparent conductive material, etc.

[0060] The capping pattern CPP may be disposed on the pixel electrode PE. The capping pattern CPP may expose at least a part of the pixel electrode PE. In one embodiment, the thickness of the capping pattern CPP in the third direction DR3 may be less than the thickness of the pixel electrode PE in the second direction DR3.

[0061] The capping pattern CPP may include a conductive material. In one embodiment, for example, the capping pattern CPP may include a conductive oxide. Examples of conductive oxides that can be used as the capping pattern CPP may include indium tin oxide (“ITO”), indium zinc oxide (“IZO”), indium gallium oxide (“IGO”), indium zinc tin oxide (“IZTO”), indium gallium tin oxide (“IGTO”), indium gallium zinc oxide (“IGZO”), indium gallium zinc tin oxide (“IGZTO”), etc. These may be used alone or in combination with each other.

[0062] An air gap can be defined on the pixel electrode PE through the capping pattern CPP. That is, the air gap can be defined on the pixel electrode PE through the space between the capping patterns CPP. Through this air gap, the leakage current between adjacent pixel regions can be further reduced.

[0063] In Figure 2 , the ends of the capping pattern CPP are illustrated as protruding beyond the ends of the pixel defining layer PDL towards the pixel opening PO, but the present invention is not necessarily limited thereto. For another example, the ends of the capping pattern CPP may be recessed away from the pixel opening PO compared to the ends of the pixel defining layer PDL, thereby defining an undercut structure with the pixel defining layer PDL. In this way, the leakage current between adjacent pixel regions can be further reduced.

[0064] The pixel defining layer PDL can be disposed on the circuit layer CEL, the pixel electrode PE, and the capping pattern CPP.

[0065] The pixel defining layer PDL can cover at least a part of the pixel electrode PE. Additionally, the pixel defining layer PDL can cover at least a part of the capping pattern CPP. The pixel defining layer PDL can define a pixel opening PO that exposes at least a part of the pixel electrode PE. The pixel defining layer PDL can correspond to the non-pixel region NPXA. That is, the first to third pixel regions PXA1, PXA2, and PXA3 can be defined by the pixel opening PO of the pixel defining layer PDL.

[0066] In one embodiment, the pixel defining layer PDL can include an inorganic material. Examples of inorganic materials that can be used as the pixel defining layer PDL can include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (Si x N y O z ), magnesium fluoride (MgF x ), etc. These can be used alone or in combination with each other. The pixel defining layer PDL can have a single-layer structure or a multi-layer structure including multiple layers.

[0067] The sidewall pattern SW can be disposed on the pixel defining layer PDL. In one embodiment, for example, the sidewall pattern SW can be disposed between adjacent pixel regions. The sidewall pattern SW can have a multi-layer structure. In one embodiment, for example, the sidewall pattern SW can include a first sidewall pattern SW1 and a second sidewall pattern SW2 stacked in sequence.

[0068] The first sidewall pattern SW1 may be disposed on the pixel defining layer PDL. The first sidewall pattern SW1 may include a conductive material. Examples of the conductive material that can be used as the first sidewall pattern SW1 may include aluminum (Al), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), indium tin oxide (ITO), etc. These can be used alone or in combination with each other. Preferably, the first sidewall pattern SW1 may include aluminum (Al).

[0069] The second sidewall pattern SW2 may be disposed on the first sidewall pattern SW1. The second sidewall pattern SW2 may protect the first sidewall pattern SW1 from corrosion, oxidation, etc. In one embodiment, the second sidewall pattern SW2 may include a material different from that of the first sidewall pattern SW1. In one embodiment, for example, the first sidewall pattern SW1 may include a first conductive material, and the second sidewall pattern SW2 may include a second conductive material different from the first conductive material. In one embodiment, for example, the first conductive material may be aluminum (Al), and the second conductive material may be titanium (Ti). However, the material that can be used as the second sidewall pattern SW2 need not be limited as long as it is different from the material of the first sidewall pattern SW1. For another example, the second sidewall pattern SW2 may include an inorganic insulating material.

[0070] Figure 3 is Figure 2 an enlarged view of region A of.

[0071] Hereinafter, with further reference to Figure 3 the structure of the sidewall pattern SW and the structure around the sidewall pattern SW will be described in more detail.

[0072] Referring to Figure 2 and Figure 3 the sidewall pattern SW may have an undercut structure UC. In one embodiment, for example, the first sidewall pattern SW1 and the second sidewall pattern SW2 may define the undercut structure UC. Specifically, the side surface S1 of the first sidewall pattern SW1 and the lower surface S2 of the second sidewall pattern SW2 may define the undercut structure UC.

[0073] The width of the lower surface S2 of the second sidewall pattern SW2 in the first direction DR1 may be greater than the width of the upper surface S3 of the first sidewall pattern SW1 in the first direction DR1. Accordingly, the second sidewall pattern SW2 may protrude in the first direction DR1 or in a direction opposite to the first direction DR1 from the point where the side surface S1 of the first sidewall pattern SW1 intersects the upper surface S3 of the first sidewall pattern SW1. That is, the second sidewall pattern SW2 may define a terminal structure. In other words, the lower surface S2 of the second sidewall pattern SW2 may have a portion that protrudes from the upper surface S3 of the first sidewall pattern SW1 in the first direction DR1 or in a direction opposite to the first direction DR1. Accordingly, the undercut structure UC may be defined by the side surface S1 of the first sidewall pattern SW1 and the lower surface S2 of the second sidewall pattern SW2.

[0074] The coating pattern CLP may be disposed on the side surface S1 of the first sidewall pattern SW1. In one embodiment, for example, the coating pattern CLP may be in contact with the side surface S1 of the first sidewall pattern SW1. The coating pattern CLP may cover at least a portion of the side surface S1 of the first sidewall pattern SW1. In one embodiment, for example, the coating pattern CLP may cover the entire side surface S1 of the first sidewall pattern SW1. However, the present invention is not necessarily limited thereto. The coating pattern CLP may have a single-layer structure or a multi-layer structure including a plurality of layers.

[0075] The coating pattern CLP may be located within the undercut structure UC of the sidewall pattern SW. In one embodiment, for example, the coating pattern CLP may overlap the second sidewall pattern SW2 in a plan view.

[0076] In one embodiment, when a coating film (CLF, see Figure 9 ) covering the entire sidewall pattern SW is formed and a whole-surface etching process is performed on the coating film, the coating pattern CLP located within the undercut structure UC may be formed. In other words, when the whole-surface etching process is performed on the coating film, the portion of the coating film shielded by the terminal structure of the second sidewall pattern SW2 may not be etched and may remain as the coating pattern CLP. Accordingly, the coating pattern CLP may be located within the undercut structure UC of the sidewall pattern SW. This will be described in more detail with reference to Figure 9 and Figure 10 hereafter.

[0077] The coating pattern CLP may be in contact with the lower surface S2 of the second sidewall pattern SW2. In one embodiment, for example, the coating pattern CLP may cover at least a portion of the lower surface S2 of the second sidewall pattern SW2. Specifically, the coating pattern CLP may cover the portion of the lower surface S2 of the second sidewall pattern SW2 that protrudes from the upper surface S3 of the first sidewall pattern SW1 in the first direction DR1 or in the direction opposite to the first direction DR1. In one embodiment, for example, the coating pattern CLP may cover the entire portion of the lower surface S2 of the second sidewall pattern SW2 that protrudes from the upper surface S3 of the first sidewall pattern SW1 in the first direction DR1 or in the direction opposite to the first direction DR1.

[0078] As described above, the coating pattern CLP may be a part of the coating film, and this part is not etched due to the end structure of the second sidewall pattern SW2 when the entire surface etching process is performed on the coating film. Accordingly, the coating pattern CLP may cover the portion of the lower surface S2 of the second sidewall pattern SW2 that protrudes from the upper surface S3 of the first sidewall pattern SW1 in the first direction DR1 or in the direction opposite to the first direction DR1.

[0079] In one embodiment, the coating pattern CLP may continuously extend from the side surface S1 of the first sidewall pattern SW1 to the lower surface S2 of the second sidewall pattern SW2. In one embodiment, for example, when the coating pattern CLP covers the entire side surface S1 of the first sidewall pattern SW1, the coating pattern CLP may continuously extend from the upper surface of the pixel defining layer PDL along the side surface S1 of the first sidewall pattern SW1 to the lower surface S2 of the second sidewall pattern SW2.

[0080] The coating pattern CLP may include a conductive material and may be electrically connected to the common electrode CE. That is, even when the coating pattern CLP covers at least a portion of the side surface S1 of the first sidewall pattern SW1, the common electrode CE may be electrically connected to the first sidewall pattern SW1 through the coating pattern CLP. Accordingly, the power supply voltage applied to the first sidewall pattern SW1 may be transmitted to the common electrode CE.

[0081] In one embodiment, the coating pattern CLP may include molybdenum (Mo). In one embodiment, for example, the coating pattern CLP may be a single-layer structure including molybdenum (Mo). Again, for example, the coating pattern CLP may have a multi-layer structure including at least one layer containing molybdenum (Mo). In this case, the layer containing molybdenum (Mo) may be disposed in the outermost layer among several layers of the coating pattern CLP.

[0082] The encapsulation pattern CLP may include a material different from that of the first sidewall pattern SW1. In one embodiment, for example, the first sidewall pattern SW1 may include a first conductive material, and the encapsulation pattern CLP may include a third conductive material different from the first conductive material. In one embodiment, for example, the first conductive material may be aluminum (Al), and the third conductive material may be molybdenum (Mo).

[0083] The encapsulation pattern CLP may include a material different from that of the capping pattern CPP. In one embodiment, for example, the capping pattern CPP may include a conductive oxide, and the encapsulation pattern CLP may include a third conductive material different from the conductive oxide. In one embodiment, for example, the conductive oxide of the capping pattern CPP may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), etc., and the third conductive material may be molybdenum (Mo).

[0084] The encapsulation pattern CLP may effectively reduce or prevent oxidation of the side surface S1 of the first sidewall pattern SW1. For example, when the side surface S1 of the first sidewall pattern SW1 is oxidized to form an oxide film, the oxide film may have a high contact resistance when contacting the common electrode CE and / or the auxiliary electrode AE. The high contact resistance may cause heating problems, reduced brightness, and weak signal transmission, resulting in reduced reliability of the display device DD.

[0085] According to an embodiment, the encapsulation pattern CLP may cover at least a portion of the side surface S1 of the first sidewall pattern SW1. Accordingly, the side surface S1 of the first sidewall pattern SW1 may be less exposed to oxygen in the air, or may not be exposed to oxygen at all. Accordingly, the formation of an oxide film on the side surface S1 of the first sidewall pattern SW1 may be reduced or prevented. Additionally, even when combined with oxygen in the air, the conductive material (e.g., molybdenum (Mo)) included in the encapsulation pattern CLP may not form an oxide film, or may only form a water-soluble and easily removable oxide film. Accordingly, the encapsulation pattern CLP may have a low contact resistance when contacting the common electrode CE and / or the auxiliary electrode AE. Accordingly, the reliability of the display device DD may be effectively improved.

[0086] The first light-emitting layer to the third light-emitting layer EL1, EL2, and EL3 may be disposed on the pixel electrode PE. In one embodiment, for example, the first light-emitting layer EL1 may be disposed on the pixel electrode PE in the pixel opening PO that defines the first pixel region PXA1, the second light-emitting layer EL2 may be disposed on the pixel electrode PE in the pixel opening PO that defines the second pixel region PXA2, and the third light-emitting layer EL3 may be disposed on the pixel electrode PE in the pixel opening PO that defines the third pixel region PXA3.

[0087] The first to third light-emitting layers EL1, EL2, and EL3 may include a light-emitting material. In one embodiment, for example, the first to third light-emitting layers EL1, EL2, and EL3 may include an organic light-emitting material. However, the present invention is not necessarily limited thereto.

[0088] Each of the first to third light-emitting layers EL1, EL2, and EL3 may include a light-emitting material layer and a functional layer. The functional layer may include a hole transport layer, a hole injection layer, an electron transport layer, an electron injection layer, and the like.

[0089] The light-emitting material layer of the first light-emitting layer EL1 may include a material that emits a first light, the light-emitting material layer of the second light-emitting layer EL2 may include a material that emits a second light, and the light-emitting material layer of the third light-emitting layer EL3 may include a material that emits a third light. In one embodiment, the first light may be red light, the second light may be green light, and the third light may be blue light.

[0090] However, the present invention is not necessarily limited thereto, and in another embodiment, each of the first to third light-emitting layers EL1, EL2, and EL3 may include two or more light-emitting material layers, and the light-emitting material layers may be combined to emit white light.

[0091] The first to third dummy light-emitting layers DEL1, DEL2, and DEL3 may be disposed on the second sidewall pattern SW2. In one embodiment, for example, the first to third dummy light-emitting layers DEL1, DEL2, and DEL3 may be in contact with the second sidewall pattern SW2.

[0092] The first to third dummy light-emitting layers DEL1, DEL2, and DEL3 may be disconnected from the first to third light-emitting layers EL1, EL2, and EL3. In one embodiment, for example, when performing a deposition process to form the first to third light-emitting layers EL1, EL2, and EL3 and the first to third dummy light-emitting layers DEL1, DEL2, and DEL3, the first to third light-emitting layers EL1, EL2, and EL3 and the first to third dummy light-emitting layers DEL1, DEL2, and DEL3 may be disconnected from each other through the undercut structure UC of the sidewall pattern SW. That is, the first to third light-emitting layers EL1, EL2, and EL3 and the first to third dummy light-emitting layers DEL1, DEL2, and DEL3 may be disconnected from each other through the end structure of the second sidewall pattern SW2.

[0093] Specifically, the first dummy light-emitting layer DEL1 may be disposed on the second sidewall pattern SW2 adjacent to the first pixel region PXA1. The first light-emitting layer EL1 and the first dummy light-emitting layer DEL1 may include the same material and may be disconnected from each other. In one embodiment, for example, when performing a deposition process to form the first light-emitting layer EL1 on the pixel electrode PE corresponding to the first pixel region PXA1, the first dummy light-emitting layer DEL1 disconnected from the first light-emitting layer EL1 may be formed together with the first light-emitting layer EL1 through the undercut structure UC of the sidewall pattern SW.

[0094] In addition, the second dummy light-emitting layer DEL2 may be disposed on the second sidewall pattern SW2 adjacent to the second pixel region PXA2. The second light-emitting layer EL2 and the second dummy light-emitting layer DEL2 may include the same material and may be disconnected from each other. In one embodiment, for example, when performing a deposition process to form the second light-emitting layer EL2 on the pixel electrode PE corresponding to the second pixel region PXA2, the second dummy light-emitting layer DEL2 disconnected from the second light-emitting layer EL2 may be formed together with the second light-emitting layer EL2 through the undercut structure UC of the sidewall pattern SW.

[0095] In addition, the third dummy light-emitting layer DEL3 may be disposed on the second sidewall pattern SW2 adjacent to the third pixel region PXA3. The third light-emitting layer EL3 and the third dummy light-emitting layer DEL3 may include the same material and may be disconnected from each other. In one embodiment, for example, when performing a deposition process to form the third light-emitting layer EL3 on the pixel electrode PE corresponding to the third pixel region PXA3, the third dummy light-emitting layer DEL3 disconnected from the third light-emitting layer EL3 may be formed together with the third light-emitting layer EL3 through the undercut structure UC of the sidewall pattern SW.

[0096] The common electrode CE may be disposed on the first to third light-emitting layers EL1, EL2, and EL3. The common electrode CE may be electrically connected to the first sidewall pattern SW1. In one embodiment, for example, the common electrode CE may be in contact with the coating pattern CLP, and correspondingly, the common electrode CE may be electrically connected to the first sidewall pattern SW1 through the coating pattern CLP. However, the present invention is not limited thereto, and when the coating pattern CLP only covers a part of the side surface S1 of the first sidewall pattern SW1, the common electrode CE may be in direct contact with the first sidewall pattern SW1.

[0097] Since the common electrode CE is electrically connected to the first sidewall pattern SW1, when a power supply voltage is applied to the first sidewall pattern SW1, the power supply voltage may be transmitted to the common electrode CE. The common electrode CE may include a metal, an alloy, a metal oxide, a transparent conductive material, etc.

[0098] The dummy common electrode DCE may be disposed on the first to third dummy light-emitting layers DEL1, DEL2, and DEL3. In one embodiment, for example, the dummy common electrode DCE may be in contact with the first to third dummy light-emitting layers DEL1, DEL2, and DEL3 on the second sidewall pattern SW2.

[0099] The dummy common electrode DCE may be disconnected from the common electrode CE. In one embodiment, for example, when a deposition process is performed to form the common electrode CE and the dummy common electrode DCE, the common electrode CE and the dummy common electrode DCE may be disconnected from each other through the undercut structure UC of the sidewall pattern SW. The common electrode CE and the dummy common electrode DCE may comprise the same material.

[0100] The auxiliary electrode AE may be disposed on the common electrode CE. The auxiliary electrode AE may be in contact with the encapsulation pattern CLP. Accordingly, the auxiliary electrode AE may be electrically connected to the encapsulation pattern CLP. Accordingly, the auxiliary electrode AE may be electrically connected to the first sidewall pattern SW1 through the encapsulation pattern CLP. Since the auxiliary electrode AE is electrically connected to the first sidewall pattern SW1, when a power supply voltage is applied to the first sidewall pattern SW1, the power supply voltage may be transmitted to the auxiliary electrode AE.

[0101] The auxiliary electrode AE may be in contact with the common electrode CE. That is, the auxiliary electrode AE may be electrically connected to the common electrode CE. Accordingly, the auxiliary electrode AE may transmit the power supply voltage to the common electrode CE. In summary, the auxiliary electrode AE may assist the common electrode CE and receive the power supply voltage from the first sidewall pattern SW1 together with the common electrode CE.

[0102] In one embodiment, the contact area between the encapsulation pattern CLP and the auxiliary electrode AE may be larger than the contact area between the encapsulation pattern CLP and the common electrode CE. Accordingly, the contact resistance between the encapsulation pattern CLP and the auxiliary electrode AE may be smaller than the contact resistance between the encapsulation pattern CLP and the common electrode CE. Therefore, when the auxiliary electrode AE and the common electrode CE receive the power supply voltage from the first sidewall pattern SW1 together, the contact resistance may be smaller than the contact resistance generated when the power supply voltage is transmitted from the first sidewall pattern SW1 only through the common electrode CE.

[0103] In one embodiment, the auxiliary electrode AE may comprise a conductive oxide. In one embodiment, for example, the auxiliary electrode AE may comprise a transparent conductive oxide. Examples of the transparent conductive oxide that may be used as the auxiliary electrode AE may include indium zinc oxide (IZO), indium tin oxide (ITO), etc. These may be used alone or in combination with each other.

[0104] The dummy auxiliary electrode DAE may be disposed on the dummy common electrode DCE. In one embodiment, for example, the dummy auxiliary electrode DAE may be in contact with the dummy common electrode DCE on the second sidewall pattern SW2.

[0105] The dummy auxiliary electrode DAE may be disconnected from the auxiliary electrode AE. In one embodiment, for example, when a deposition process is performed to form the auxiliary electrode AE and the dummy auxiliary electrode DAE, the auxiliary electrode AE and the dummy auxiliary electrode DAE may be disconnected from each other through the undercut structure UC of the sidewall pattern SW. The auxiliary electrode AE and the dummy auxiliary electrode DAE may comprise the same material.

[0106] The encapsulation pattern ECP may be disposed on the auxiliary electrode AE and the dummy auxiliary electrode DAE. The encapsulation pattern ECP may be disposed to correspond to the first light-emitting element to the third light-emitting elements LED1, LED2, and LED3, respectively. In one embodiment, the encapsulation pattern ECP may comprise an inorganic material.

[0107] In one embodiment, the encapsulation pattern ECP may have a structure that is disconnected on the sidewall pattern SW. That is, the encapsulation pattern ECP covering one light-emitting element may not be connected to the encapsulation pattern ECP covering another adjacent light-emitting element. However, the present invention is not necessarily limited thereto, and in another embodiment, the encapsulation pattern ECP may also continuously extend over the first light-emitting element to the third light-emitting elements LED1, LED2, and LED3.

[0108] The first encapsulation layer ECL1 may be disposed on the sidewall pattern SW and the encapsulation pattern ECP. In one embodiment, the first encapsulation layer ECL1 may comprise an organic material. The second encapsulation layer ECL2 may be disposed on the first encapsulation layer ECL1. In one embodiment, the second encapsulation layer ECL2 may comprise an inorganic material.

[0109] The encapsulation pattern ECP, the first encapsulation layer ECL1, and the second encapsulation layer ECL2 may form an encapsulation member. The encapsulation member may protect the first light-emitting element to the third light-emitting elements LED1, LED2, and LED3 and the auxiliary electrode AE from external impurities. At the same time, the structure of the encapsulation member is not necessarily limited thereto, and the stacking structure of the encapsulation member may be changed in various ways.

[0110] Although not illustrated, the display device DD may further include various functional members disposed on the second encapsulation layer ECL2. Examples of the functional members may include a touch member that detects a touch from the outside, an optical member that adjusts the characteristics of light emitted from the light-emitting element, and a cover member that protects the component from an external impact. The touch member may include at least one touch electrode. The optical member may include a color filter, a light-blocking member, a color conversion member, a polarization layer, and the like. The cover member may include a cover window, a protective film, a hard coat, an anti-fingerprint layer, and the like.

[0111] A display device DD according to an embodiment of the present invention may include a sidewall pattern SW provided on a pixel definition layer PDL and having an undercut structure UC. Accordingly, a light-emitting layer may be independently formed for each pixel region through the undercut structure UC of the sidewall pattern SW, and leakage current between adjacent pixel regions may be effectively reduced or prevented. Therefore, even in a case where it is difficult to form a light-emitting layer using a fine metal mask (FMM) due to the interval between pixel regions and / or the size (e.g., area) of the pixel regions being too small, a high-resolution display device DD may be realized.

[0112] In addition, in a display device DD according to an embodiment of the present invention, the sidewall pattern SW may include a first sidewall pattern SW1 and a second sidewall pattern SW2 stacked in sequence, and a coating pattern CLP covering at least a part of a side surface S1 of the first sidewall pattern SW1 and containing a conductive material may be provided on the side surface S1 of the first sidewall pattern SW1. Accordingly, the side surface S1 of the first sidewall pattern SW1 may be exposed to air with relatively little or no oxygen. Accordingly, the coating pattern CLP may effectively reduce or prevent the formation of an oxide film on the side surface S1 of the first sidewall pattern SW1. In addition, even when combined with oxygen in the air, a material (e.g., molybdenum (Mo)) contained in the coating pattern CLP may not form an oxide film, or may only form a water-soluble and easily removable oxide film. Accordingly, when in contact with a common electrode CE and / or an auxiliary electrode AE receiving a power supply voltage, the coating pattern CLP may have a low contact resistance. Accordingly, the reliability of the display device DD may be effectively improved.

[0113] Figures 4 to 14 It is a diagram for explaining a method of manufacturing a display device according to an embodiment of the present invention.

[0114] Reference Figures 4 to 14 The method of manufacturing the display device DD described may be the method of manufacturing the display device DD described in reference Figures 1 to 3 In the following, descriptions overlapping with the description of the display device DD described above with reference Figures 1 to 3 will be omitted or simplified.

[0115] Reference Figure 4 , a pixel electrode PE and a capping film CPF may be formed on a substrate SUB. Specifically, a circuit layer CEL may be formed on the substrate SUB, and the pixel electrode PE and the capping film CPF may be formed on the circuit layer CEL.

[0116] The substrate SUB may be formed of various materials. In one embodiment, for example, the substrate SUB may be formed of glass, quartz, plastic, silicon semiconductor, etc.

[0117] As described above, the circuit layer CEL can be formed by forming an insulating layer, a semiconductor layer, and a conductive layer on the substrate SUB via coating, deposition, etc., and selectively patterning the insulating layer, the semiconductor layer, and the conductive layer.

[0118] The pixel electrode PE can be formed on the circuit layer CEL. The pixel electrode PE can be formed of metal, alloy, metal oxide, transparent conductive material, etc. The pixel electrode PE can be formed to be electrically connected to at least one of the transistors in the circuit layer CEL.

[0119] The capping film CPF can be formed on the pixel electrode PE. In one embodiment, for example, the capping film CPF can be formed to cover the entire upper surface of the pixel electrode PE. The capping film CPF can be formed of a conductive oxide. Examples of the conductive oxide that can be used as the capping film CPF include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), etc. These can be used alone or in combination with each other. The capping film CPF can protect the pixel electrode PE during the etching process of the coating film (CLF, see Figure 9 ) to be described later.

[0120] Reference Figure 5 , the pixel defining layer PDL can be formed on the circuit layer CEL. The pixel defining layer PDL can be formed to cover at least a part of the pixel electrode PE and at least a part of the capping film CPF. The pixel defining layer PDL can be formed to define a pixel opening PO. As described above, the first pixel region to the third pixel region PXA1, PXA2, and PXA3 can be defined by the pixel opening PO. That is, the pixel defining layer PDL can be formed to correspond to the non-pixel region NPXA.

[0121] In one embodiment, the pixel defining layer PDL can be formed of an inorganic material. Examples of the inorganic material that can be used as the pixel defining layer PDL can include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (Si x N y O z ), magnesium fluoride (MgF x ), etc. These can be used alone or in combination with each other. The pixel defining layer PDL can be formed as a single-layer structure or a multi-layer structure including multiple layers.

[0122] Reference Figure 6, a sidewall pattern SW may be formed on the pixel defining layer PDL. The sidewall pattern SW may be formed in a structure in which a first sidewall pattern SW1 and a second sidewall pattern SW2 are stacked in sequence. Each of the first sidewall pattern SW1 and the second sidewall pattern SW2 may be formed by a patterning process. In one embodiment, for example, the patterning process for forming the first sidewall pattern SW1 and the patterning process for forming the second sidewall pattern SW2 may be performed in sequence. Again, for example, the first sidewall pattern SW1 and the second sidewall pattern SW2 may be formed simultaneously by a single patterning process.

[0123] The first sidewall pattern SW1 may be formed of a conductive material. Examples of the conductive material that can be used as the first sidewall pattern SW1 may include aluminum (Al), chromium (Cr), titanium (Ti), gold (Au), silver (Ag), indium tin oxide (ITO), etc. These may be used alone or in combination with each other. Preferably, the first sidewall pattern SW1 may be formed of aluminum (Al).

[0124] In one embodiment, the second sidewall pattern SW2 may be formed of a material different from that of the first sidewall pattern SW1. In one embodiment, for example, the first sidewall pattern SW1 may be formed of aluminum (Al), and the second sidewall pattern SW2 may be formed of titanium (Ti). However, the present invention is not necessarily limited thereto.

[0125] Reference Figure 7 and Figure 8 , an undercut structure UC may be formed by removing a part of the first sidewall pattern SW1. In one embodiment, for example, a part of the first sidewall pattern SW1 may be removed by a first etching process ETC1. In one embodiment, the first etching process ETC1 may be a dry etching process or a wet etching process.

[0126] The etching rate of the second sidewall pattern SW2 for the first etching process ETC1 may be lower than the etching rate of the first sidewall pattern SW1 for the first etching process ETC1. In one embodiment, for example, the second sidewall pattern SW2 may not be etched by the first etching process ETC1.

[0127] Accordingly, as Figure 8As illustrated, the side surface S1 of the first sidewall pattern SW1 that is located inside the sidewall pattern SW compared to the end of the second sidewall pattern SW2 can be defined. That is, the width of the lower surface S2 of the second sidewall pattern SW2 in the first direction DR1 can be greater than the width of the upper surface S3 of the first sidewall pattern SW1 in the first direction DR1. Accordingly, the second sidewall pattern SW2 can protrude in the first direction DR1 or in the direction opposite to the first direction DR1 from the point where the side surface S1 of the first sidewall pattern SW1 intersects the upper surface S3 of the first sidewall pattern SW1. That is, the second sidewall pattern SW2 can define a terminal structure. In other words, the lower surface S2 of the second sidewall pattern SW2 can have a portion that protrudes from the upper surface S3 of the first sidewall pattern SW1 in the first direction DR1 or in the direction opposite to the first direction DR1. Accordingly, the undercut structure UC can be defined by the side surface S1 of the first sidewall pattern SW1 and the lower surface S2 of the second sidewall pattern SW2.

[0128] Reference Figure 9 , a coating film CLF can be formed on the capping film CPF, the pixel defining layer PDL, and the sidewall pattern SW. In one embodiment, for example, the coating film CLF can be formed on the entire surface of the substrate SUB (or the circuit layer CEL). In one embodiment, for example, the coating film CLF can be formed to cover all of the capping film CPF, the pixel defining layer PDL, and the sidewall pattern SW. In one embodiment, the coating film CLF can be formed to cover all of the first sidewall pattern SW1 and the second sidewall pattern SW2.

[0129] The coating film CLF can be formed of a conductive material. In one embodiment, for example, the coating film CLF can be formed of molybdenum (Mo).

[0130] The coating film CLF can be formed of a material different from that of the first sidewall pattern SW1. In one embodiment, for example, the first sidewall pattern SW1 can be formed of aluminum (Al), and the second sidewall pattern SW2 can be formed of titanium (Ti). Additionally, the coating film CLF can be formed of a material different from that of the capping film CPF. In one embodiment, for example, the capping film CPF can be formed of a conductive oxide, and the coating film CLF can be formed of molybdenum (Mo).

[0131] Reference Figure 10 and Figure 11 , a coating pattern CLP can be formed by removing a portion of the coating film CLF. In one embodiment, for example, a portion of the coating film CLF can be removed by a second etching process ETC2.

[0132] The second etching process ETC2 can be a whole surface etching process. Additionally, the second etching process ETC2 can be an anisotropic dry etching process. That is, the second etching process ETC2 can be a re-etching process using an anisotropic dry etching process.

[0133] Accordingly, when the second etching process ETC2 is performed on the encapsulation film CLF, an encapsulation pattern CLP can be formed within the undercut structure UC. In other words, when the second etching process ETC2 is performed on the encapsulation film CLF, the portion of the encapsulation film CLF shielded by the end structure of the second sidewall pattern SW2 may not be etched and remains as the encapsulation pattern CLP. Accordingly, the encapsulation pattern CLP can be formed within the undercut structure UC of the sidewall pattern SW. That is, the encapsulation pattern CLP can be formed to overlap with the second sidewall pattern SW2 in a plan view.

[0134] The etching rate of the capping film CPF for the second etching process ETC2 can be lower than the etching rate of the encapsulation film CLF for the second etching process ETC2. That is, the capping film CPF can be formed of a material having a relatively low etching rate for the second etching process ETC2, and the encapsulation film CLF can be formed of a material having a relatively high etching rate for the second etching process ETC2. In one embodiment, for example, the capping film CPF may not be etched by the second etching process ETC2.

[0135] Accordingly, in the second etching process ETC2, the capping film CPF can be used as an etch stop layer. That is, in the second etching process ETC2, the etching is stopped by the capping film CPF, so that the pixel electrode PE is not affected by the second etching process ETC2. Accordingly, the pixel electrode PE is not damaged by the second etching process ETC2 for forming the encapsulation pattern CLP.

[0136] Reference Figure 12 and Figure 13 , the capping pattern CPP can be formed by removing a portion of the capping film CPF. In one embodiment, for example, a portion of the capping film CPF can be removed by the third etching process ETC3. Specifically, the portion of the capping film CPF exposed from the pixel defining layer PDL can be removed by the third etching process ETC3 to form the capping pattern CPP. Accordingly, as Figure 13 illustrated, due to the gap between the capping patterns CPP, an air gap can be defined over the pixel electrode PE. Through this air gap, the leakage current between adjacent pixel regions can be further reduced. In one embodiment, the third etching process ETC3 can be a dry etching process or a wet etching process.

[0137] The etching rate of the cladding pattern CLP for the third etching process ETC3 can be lower than the etching rate of the capping film CPF for the third etching process ETC3. That is, the cladding pattern CLP can be formed of a material having a relatively low etching rate for the third etching process ETC3, and the capping film CPF can be formed of a material having a relatively high etching rate for the third etching process ETC3. In one embodiment, for example, the cladding pattern CLP may not be etched by the third etching process ETC3. Accordingly, the cladding pattern CLP will not be damaged by the third etching process ETC3 for forming the capping pattern CPP.

[0138] In addition, the etching rate of the first sidewall pattern SW1 for the third etching process ETC3 can be lower than the etching rate of the capping film CPF for the third etching process ETC3. That is, the first sidewall pattern SW1 can be formed of a material having a relatively low etching rate for the third etching process ETC3, and the capping film CPF can be formed of a material having a relatively high etching rate for the third etching process ETC3. In one embodiment, for example, the first sidewall pattern SW1 may not be etched by the third etching process ETC3. Thus, even if the first sidewall pattern SW1 is partially exposed from the cladding pattern CLP, the first sidewall pattern SW1 will not be damaged by the third etching process ETC3 for forming the capping pattern CPP.

[0139] In addition, the etching rate of the second sidewall pattern SW2 for the third etching process ETC3 can be lower than the etching rate of the capping film CPF for the third etching process ETC3. That is, the second sidewall pattern SW2 can be formed of a material having a relatively low etching rate for the third etching process ETC3, and the capping film CPF can be formed of a material having a relatively high etching rate for the third etching process ETC3. In one embodiment, for example, the second sidewall pattern SW2 may not be etched by the third etching process ETC3. Accordingly, the second sidewall pattern SW2 will not be damaged by the third etching process ETC3 for forming the capping pattern CPP.

[0140] Reference Figure 14 , the first light-emitting layer to the third light-emitting layer EL1, EL2, and EL3, the first dummy light-emitting layer to the third dummy light-emitting layer DEL1, DEL2, and DEL3, the common electrode CE, the dummy common electrode DCE, the auxiliary electrode AE, the dummy auxiliary electrode DAE, and the encapsulation pattern ECP can be formed.

[0141] First, the first light-emitting layer EL1 may be formed on the pixel electrode PE corresponding to the first pixel region PXA1. In this process, the first dummy light-emitting layer DEL1 disconnected from the first light-emitting layer EL1 through the undercut structure UC of the sidewall pattern SW may be formed adjacent to the first pixel region PXA1 on the second sidewall pattern SW2. That is, the first light-emitting layer EL1 and the first dummy light-emitting layer DEL1 may be formed together in the same process.

[0142] Thereafter, the common electrode CE corresponding to the first pixel region PXA1 may be formed on the first light-emitting layer EL1. As a result, the first light-emitting element LED1 including the pixel electrode PE, the first light-emitting layer EL1, and the common electrode CE may be formed in the first pixel region PXA1. In this process, the dummy common electrode DCE disconnected from the common electrode CE through the undercut structure UC of the sidewall pattern SW may be formed on the first dummy light-emitting layer DEL1.

[0143] Thereafter, the auxiliary electrode AE corresponding to the first pixel region PXA1 may be formed on the common electrode CE corresponding to the first pixel region PXA1. In this process, the dummy auxiliary electrode DAE disconnected from the auxiliary electrode AE through the undercut structure UC of the sidewall pattern SW may be formed adjacent to the first pixel region PXA1 on the dummy common electrode DCE.

[0144] Thereafter, the encapsulation pattern ECP corresponding to the first pixel region PXA1 may be formed. In one embodiment, for example, the encapsulation pattern ECP corresponding to the first pixel region PXA1 may be formed to cover the first light-emitting element LED1.

[0145] Thereafter, the second light-emitting layer EL2 may be formed on the pixel electrode PE corresponding to the second pixel region PXA2. In this process, the second dummy light-emitting layer DEL2 disconnected from the second light-emitting layer EL2 through the undercut structure UC of the sidewall pattern SW may be formed adjacent to the second pixel region PXA2 on the second sidewall pattern SW2. That is, the second light-emitting layer EL2 and the second dummy light-emitting layer DEL2 may be formed together in the same process.

[0146] Thereafter, the common electrode CE corresponding to the second pixel region PXA2 may be formed on the second light-emitting layer EL2. As a result, the second light-emitting element LED2 including the pixel electrode PE, the second light-emitting layer EL2, and the common electrode CE may be formed in the second pixel region PXA2. In this process, the dummy common electrode DCE disconnected from the common electrode CE through the undercut structure UC of the sidewall pattern SW may be formed on the second dummy light-emitting layer DEL2.

[0147] Thereafter, an auxiliary electrode AE corresponding to the second pixel region PXA2 may be formed on a common electrode CE corresponding to the second pixel region PXA2. In this process, a dummy auxiliary electrode DAE disconnected from the auxiliary electrode AE through an undercut structure UC of the sidewall pattern SW may be formed adjacent to the second pixel region PXA2 on a dummy common electrode DCE.

[0148] Thereafter, an encapsulation pattern ECP corresponding to the second pixel region PXA2 may be formed. In one embodiment, for example, the encapsulation pattern ECP corresponding to the second pixel region PXA2 may be formed to cover the second light-emitting element LED2.

[0149] Thereafter, a third light-emitting layer EL3 may be formed on a pixel electrode PE corresponding to the third pixel region PXA3. In this process, a third dummy light-emitting layer DEL3 disconnected from the third light-emitting layer EL3 through an undercut structure UC of the sidewall pattern SW may be formed adjacent to the third pixel region PXA3 on a second sidewall pattern SW2. That is, the third light-emitting layer EL3 and the third dummy light-emitting layer DEL3 may be formed together in the same process.

[0150] Thereafter, a common electrode CE corresponding to the third pixel region PXA3 may be formed on the third light-emitting layer EL3. As a result, a third light-emitting element LED3 including the pixel electrode PE, the third light-emitting layer EL3, and the common electrode CE may be formed in the third pixel region PXA3. In this process, a dummy common electrode DCE disconnected from the common electrode CE through an undercut structure UC of the sidewall pattern SW may be formed on the third dummy light-emitting layer DEL3.

[0151] Thereafter, an auxiliary electrode AE corresponding to the third pixel region PXA3 may be formed on a common electrode CE corresponding to the third pixel region PXA3. In this process, a dummy auxiliary electrode DAE disconnected from the auxiliary electrode AE through an undercut structure UC of the sidewall pattern SW may be formed adjacent to the third pixel region PXA3 on a dummy common electrode DCE.

[0152] Thereafter, an encapsulation pattern ECP corresponding to the third pixel region PXA3 may be formed. In one embodiment, for example, the encapsulation pattern ECP corresponding to the third pixel region PXA3 may be formed to cover the third light-emitting element LED3.

[0153] In one embodiment, the first to third light-emitting layers EL1, EL2, and EL3 and the first to third dummy light-emitting layers DEL1, DEL2, and DEL3 may be formed by a process of depositing an organic material. In one embodiment, for example, the organic material may include an organic light-emitting material. However, the present invention is not necessarily limited thereto.

[0154] In addition, the common electrode CE and the dummy common electrode DCE can be formed by a process of depositing a conductive material. In one embodiment, for example, the conductive material may include a metal, an alloy, a metal oxide, a transparent conductive material, and the like.

[0155] In addition, the auxiliary electrode AE and the dummy auxiliary electrode DAE can be formed of a transparent conductive oxide. The transparent conductive oxide may include indium zinc oxide (IZO), indium tin oxide (ITO), and the like.

[0156] In addition, in one embodiment, the encapsulation pattern ECP can be formed of an inorganic material.

[0157] After forming the encapsulation pattern ECP, as Figure 2 illustrated in, the first encapsulation layer ECL1 and the second encapsulation layer ECL2 can be formed. As a result, an encapsulation member including the encapsulation pattern ECP, the first encapsulation layer ECL1, and the second encapsulation layer ECL2 can be formed. In one embodiment, the first encapsulation layer ECL1 can be formed of an organic material, and the second encapsulation layer ECL2 can be formed of an inorganic material.

[0158] In the method of manufacturing the display device DD according to an embodiment of the present invention, the undercut structure UC of the sidewall pattern SW can be used to form the coating pattern CLP through an etching process (e.g., Figure 10 the second etching process ETC2) performed on the coating film CLF. In one embodiment, for example, the coating pattern CLP can be formed by etching the coating film CLF through an etch-back process using an anisotropic dry etching process. Accordingly, the coating pattern CLP can be formed without a separate mask or photoresist pattern. Accordingly, the display device DD can be easily formed, and the efficiency of the manufacturing process of the display device DD can be effectively improved.

[0159] In addition, in the method of manufacturing the display device DD according to an embodiment of the present invention, the etching rate of the capping film CPF for the etching process can be lower than the etching rate of the coating film CLF for the etching process. Accordingly, in the etching process for forming the coating pattern CLP, the capping film CPF can be used as an etch stop layer. Accordingly, the pixel electrode PE under the capping film CPF will not be damaged by the etching process for forming the coating pattern CLP. Accordingly, the reliability of the display device DD will not deteriorate.

[0160] Figure 15 For example, a cross-sectional view of another example taken along the Figure 1 line I-I' is illustrated.

[0161] Except that the coating pattern CLP only covers a part of the side surface of the first sidewall pattern SW1, the example of the display device DD described with reference to Figure 15 can be the same as the example of the display device DD described with reference to Figure 2The example of the described display device DD is substantially the same. Thus, repeated descriptions will be omitted.

[0162] Reference Figure 15 , as described above, in one embodiment, the coating pattern CLP may cover only a part of the side surface S1 of the first sidewall pattern SW1. In one embodiment, for example, by adjusting the length of the end structure of the second sidewall pattern SW2 in the first direction DR1, the coverage area of the coating pattern CLP formed by the second etching process ETC2 (see Figure 10 ) on the side surface S1 of the first sidewall pattern SW1 can be changed in various ways.

[0163] In this case, as Figure 15 illustrated, the common electrode CE may be in direct contact with the first sidewall pattern SW1. However, the present invention is not necessarily limited thereto. For another example, even when the coating pattern CLP covers only a part of the side surface S1 of the first sidewall pattern SW1, the common electrode CE may not be in direct contact with the side surface S1 of the first sidewall pattern SW1, but may be electrically connected to the first sidewall pattern SW1 through the coating pattern CLP.

[0164] In addition to forming the coating pattern CLP that covers only a part of the side surface S1 of the sidewall pattern SW1 by adjusting the process conditions of the first etching process (ETC1, see Figure 7 ) and / or the second etching process (ETC2, see Figure 10 ), Figure 15 the method of manufacturing the display device DD may be substantially the same as the method of manufacturing the display device DD described in reference Figures 4 to 14 . Thus, detailed descriptions will be omitted.

[0165] Figure 16 For example, a cross-sectional view of another example taken along the line I-I' of Figure 1 .

[0166] Except for further including a dummy coating pattern DCLP, the example of the display device DD described in reference Figure 16 may be substantially the same as the example of the display device DD described in reference Figure 2 . Thus, repeated descriptions will be omitted.

[0167] Reference Figure 16 , in one embodiment, the display device DD may further include a dummy coating pattern DCLP. The dummy coating pattern DCLP may be disposed on the second sidewall pattern SW2. In one embodiment, for example, the dummy coating pattern DCLP may be in contact with the upper surface of the second sidewall pattern SW2.

[0168] The dummy coating pattern DCLP may include the same material as that of the coating pattern CLP. That is, the dummy coating pattern DCLP may include a conductive material. In one embodiment, for example, the dummy coating pattern DCLP may include molybdenum (Mo).

[0169] The dummy coating pattern DCLP may be formed as a part of the coating film CLF remaining on the second sidewall pattern SW2 after a second etching process (ETC2, see Figure 10 ). That is, the dummy coating pattern DCLP may be a residue of the coating film CLF on the second sidewall pattern SW2 that has not been removed even after the second etching process ETC2 used to form the coating pattern CLP. That is, the dummy coating pattern DCLP may be formed in the same process as the coating pattern CLP.

[0170] When the display device DD further includes the dummy coating pattern DCLP, the position of the dummy coating pattern DCLP is not limited to Figure 16 the positions illustrated in. Again, for example, the position of the dummy coating pattern DCLP may be changed in various ways on the second sidewall pattern SW2.

[0171] The present disclosure can be applied to display panel inspection devices for various display devices. For example, the present disclosure is applicable to display panel inspection devices for various display devices such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for exhibitions or information transmission, medical display devices, and the like.

[0172] The foregoing is illustrative of the embodiments and should not be construed as limiting the embodiments. Although some embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims. Therefore, it should be understood that the foregoing is illustrative of various embodiments and should not be construed as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, comprising: A pixel electrode, on a substrate; a pixel defining layer, on the substrate and the pixel electrode, and defining a pixel opening exposing at least a portion of the pixel electrode; a first sidewall pattern on the pixel defining layer and comprising a conductive material; a second sidewall pattern on the first sidewall pattern and having a lower surface defining an undercut structure together with a side surface of the first sidewall pattern in a cross-sectional view; a cladding pattern covering at least a portion of the side surface of the first sidewall pattern and comprising a conductive material; a light emitting layer on the pixel electrode in the pixel opening; as well as A common electrode is on the light emitting layer and electrically connected to the cladding pattern. 2 . The display device of claim 1 , wherein the capping pattern contacts the side surface of the first sidewall pattern and the lower surface of the second sidewall pattern. 3 . The display device of claim 1 , wherein the capping pattern covers an entire portion of the lower surface of the second sidewall pattern that protrudes from an upper surface of the first sidewall pattern. 4 . The display device of claim 1 , wherein the capping pattern continuously extends from the side surface of the first sidewall pattern to the lower surface of the second sidewall pattern. The display device according to claim 1 , wherein the encapsulation pattern is located within the undercut structure. The display device of claim 1 , wherein the capping pattern overlaps the second sidewall pattern in a plan view. 7 . The display device of claim 1 , wherein the capping pattern and the first sidewall pattern comprise different materials from each other. The display device according to claim 1 , wherein the cladding pattern comprises molybdenum.

9. The display device according to claim 1, further comprising: An auxiliary electrode is on the common electrode and contacts the cladding pattern. 10 . The display device according to claim 9 , wherein a contact area between the encapsulation pattern and the auxiliary electrode is larger than a contact area between the encapsulation pattern and the common electrode. The display device according to claim 9 , wherein the auxiliary electrode comprises a conductive oxide.

12. The display device according to claim 1, further comprising: A capping pattern, on the pixel electrode, is at least partially covered by the pixel defining layer and includes a material different from that of the cladding pattern. The display device of claim 12 , wherein the capping pattern comprises a conductive oxide.

14. The display device according to claim 1, further comprising: A dummy cladding pattern is in contact with an upper surface of the second sidewall pattern and includes a material that is the same as that of the cladding pattern. 15 . The display device of claim 1 , wherein the capping pattern covers the entire side surface of the first sidewall pattern. 16 . The display device of claim 1 , wherein the capping pattern covers a portion of the side surface of the first sidewall pattern.

17. The display device according to claim 1, further comprising: a dummy light emitting layer, the dummy light emitting layer being disconnected from the light emitting layer, comprising a material that is the same as that of the light emitting layer, and being disposed on the second sidewall pattern; as well as A dummy common electrode is disconnected from the common electrode, includes a material that is the same as that of the common electrode, and is disposed on the dummy light emitting layer.

18. A method for manufacturing a display device, the method comprising: forming a pixel electrode on a substrate; forming a capping film on the pixel electrode; forming a pixel defining layer on the substrate to cover at least a portion of the pixel electrode and at least a portion of the capping film; forming a first sidewall pattern including a conductive material on the pixel defining layer, and forming a second sidewall pattern including a material different from that of the first sidewall pattern on the first sidewall pattern; removing a portion of the first sidewall pattern to form an undercut structure defined by a side surface of the first sidewall pattern and a lower surface of the second sidewall pattern in a cross-sectional view; forming a coating film including a conductive material on the capping film, the pixel defining layer, the first sidewall pattern, and the second sidewall pattern; forming a capping pattern covering at least a portion of the side surface of the first sidewall pattern by removing a portion of the capping film through a first etching process; as well as A capping pattern is formed by removing a portion of the capping film through a second etching process. 19 . The method of claim 18 , wherein an etching rate of the capping film used in the first etching process is lower than an etching rate of the covering film used in the first etching process. 20 . The method of claim 18 , wherein an etching rate of each of the first sidewall pattern, the second sidewall pattern, and the cladding pattern used in the second etching process is lower than an etching rate of the capping film used in the second etching process. The method of claim 18 , wherein the first etching process is a whole surface etching process.

22. The method of claim 18, wherein the first etching process is an anisotropic dry etching process. 23 . The method according to claim 18 , wherein in the forming the cladding pattern, the cladding film is etched so that the cladding pattern is located within the undercut structure. 24 . The method of claim 18 , wherein in the forming the cladding pattern, the cladding film is etched so that the cladding pattern overlaps the second sidewall pattern in a plan view. 25 . The method of claim 18 , wherein the capping film is formed to cover the entirety of the first sidewall pattern and the second sidewall pattern.

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