Display device and manufacturing method thereof

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device may include a pixel circuit layer disposed on a substrate and a display element layer disposed on the pixel circuit layer, wherein the display element layer includes first, second, and third light emitting elements spaced apart from each other, and a bank layer disposed between the first, second, and third light emitting elements.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0185084, filed with the Korean Intellectual Property Office on December 18, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] One or more embodiments relate to apparatuses and methods, and more particularly, to a display device and a method of manufacturing a display device. Background art

[0004] Electronic devices based on portability have been widely used. In addition to small electronic devices such as mobile phones, tablet personal computers (PCs) have recently been widely used as mobile electronic devices.

[0005] Such mobile electronic devices include a display device to support various functions and provide visual information such as images or videos to a user. Recently, as other components for driving the display device have become smaller, the proportion of the display device in the electronic device has gradually increased, and a structure capable of bending from a flat state to a certain angle is also being developed. Summary of the invention

[0006] One or more embodiments include a display device that can be manufactured using a reduced number of deposition masks.

[0007] However, this object is an example, and the objects to be solved by the present disclosure are not limited thereto.

[0008] Additional aspects will be partially described in the following description, and will be partially apparent from the description, or may be learned by practicing the embodiments of the present disclosure presented.

[0009] According to one or more embodiments, a display device includes a pixel circuit layer disposed on a substrate and a display element layer disposed on the pixel circuit layer, wherein the display element layer includes a first light - emitting element, a second light - emitting element, and a third light - emitting element spaced apart from each other and a bank layer disposed between the first light - emitting element, the second light - emitting element, and the third light - emitting element. The first light - emitting element includes a first pixel electrode, a first intermediate layer disposed on the first pixel electrode, and a first common electrode disposed on the first intermediate layer, the second light - emitting element includes a second pixel electrode, a second intermediate layer disposed on the second pixel electrode, and a second common electrode disposed on the second intermediate layer, the third light - emitting element includes a third pixel electrode, a third intermediate layer disposed on the third pixel electrode, and a third common electrode disposed on the third intermediate layer, and the height of each of the first intermediate layer, the second intermediate layer, and the third intermediate layer is greater than the height of the bank layer.

[0010] In an embodiment, the first common electrode, the second common electrode, and the third common electrode may be electrically connected to each other.

[0011] In an embodiment, the first common electrode, the second common electrode, and the third common electrode may be integrally formed with each other.

[0012] In an embodiment, the first pixel electrode and the first intermediate layer may be connected to each other without forming a step.

[0013] In an embodiment, the first light-emitting element, the second light-emitting element, and the third light-emitting element may emit lights of different colors.

[0014] According to one or more embodiments, a method of manufacturing a display device includes disposing a pixel circuit layer on a substrate and disposing a display element layer on the pixel circuit layer, wherein disposing the display element layer includes disposing a pixel electrode layer on the pixel circuit layer, disposing a first intermediate layer on the pixel electrode layer, disposing a first sacrificial layer on the first intermediate layer, patterning the first intermediate layer and the first sacrificial layer, and forming a first pixel electrode by patterning the pixel electrode layer to overlap with the first sacrificial layer.

[0015] In an embodiment, forming the first pixel electrode may include etching the pixel electrode layer by using the first sacrificial layer as a mask.

[0016] In an embodiment, the first pixel electrode and the first intermediate layer may be connected to each other without forming a step.

[0017] In an embodiment, disposing the display element layer may further include disposing a second intermediate layer on the pixel electrode layer, disposing a second sacrificial layer on the second intermediate layer, patterning the second intermediate layer and the second sacrificial layer, and forming a second pixel electrode by patterning the pixel electrode layer to overlap with the second sacrificial layer. Forming the first pixel electrode and forming the second pixel electrode may be performed simultaneously.

[0018] In an embodiment, forming the second pixel electrode may include etching the pixel electrode layer by using the second sacrificial layer as a mask.

[0019] In an embodiment, the second pixel electrode and the second intermediate layer may be connected to each other without forming a step.

[0020] In an embodiment, disposing the display element layer may further include disposing a third intermediate layer on the pixel electrode layer, disposing a third sacrificial layer on the third intermediate layer, patterning the third intermediate layer and the third sacrificial layer, and forming a third pixel electrode by patterning the pixel electrode layer to overlap with the third sacrificial layer. Forming the second pixel electrode and forming the third pixel electrode may be performed simultaneously.

[0021] In an embodiment, forming the third pixel electrode may include etching the pixel electrode layer by using the third sacrificial layer as a mask.

[0022] In an embodiment, the third pixel electrode and the third intermediate layer may be connected to each other without forming a step.

[0023] In an embodiment, disposing the display element layer may further include disposing a bank layer on the pixel circuit layer to cover each of the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer.

[0024] In an embodiment, disposing the display element layer may further include etching the bank layer to expose portions of the first intermediate layer, the second intermediate layer, and the third intermediate layer.

[0025] In an embodiment, the height of each of the first intermediate layer, the second intermediate layer, and the third intermediate layer may be greater than the height of the etched bank layer.

[0026] In an embodiment, disposing the display element layer may further include removing each of the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer.

[0027] In an embodiment, disposing the display element layer may further include disposing a common electrode on the bank layer to cover the first intermediate layer, the second intermediate layer, and the third intermediate layer.

[0028] In an embodiment, the common electrode may be electrically connected to each of the first intermediate layer, the second intermediate layer, and the third intermediate layer.

[0029] By referring to the drawings, claims, and detailed description of the present disclosure, other aspects, features, and advantages other than those described above will become apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a schematic plan view of a display device according to an embodiment;

[0032] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment;

[0033] Figure 3 is a schematic diagram of an equivalent circuit of any pixel of a display device according to an embodiment;

[0034] Figure 4 is a schematic flowchart of a method of manufacturing a display device according to an embodiment;

[0035] Figure 5is a schematic flowchart of an operation of arranging a display element layer on a pixel circuit layer according to an embodiment; and

[0036] Figures 6 to 24 is a schematic cross-sectional view that is part of a manufacturing process of a display device. Detailed Embodiments

[0037] Embodiments will now be described in detail with reference to examples illustrated in the accompanying drawings, in which like reference numerals always denote like elements. At this point, the embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain the described aspects.

[0038] The term "and / or" includes all combinations of one or more of the related configurations that can be defined. For example, "A and / or B" can be understood to mean "A, B, or A and B".

[0039] For the purposes of this disclosure, the phrase "at least one of A and B" can be construed to mean only A, only B, or any combination of A and B. Further, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be construed to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0040] Various modifications can be made to the embodiments, and specific embodiments will be shown in the accompanying drawings and described in the detailed description section. The effects and features of the embodiments and the methods for achieving the effects and features will become clearer with reference to the following detailed description in conjunction with the accompanying drawings. However, the embodiments can be implemented in various forms and are not limited by the embodiments presented below.

[0041] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings, and in the description with reference to the accompanying drawings, the same or corresponding components may be denoted by the same reference numerals or characters, and redundant descriptions thereof will be omitted.

[0042] In the following embodiments, it will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These elements are only used to distinguish one element from another.

[0043] In the following embodiments, as used herein, the singular forms such as "a" and "an" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0044] In the following embodiments, it will also be understood that the terms "comprising", "including", "having" and / or their variants as used herein specify the presence of the stated features or elements, but do not preclude the presence or addition of one or more other features or components.

[0045] In the following embodiments, it will be understood that when an element such as a layer, film, region or plate is referred to as being "on" another element, the element can be directly on the other element or an intervening element can be present therebetween.

[0046] For ease of explanation, the sizes of the elements in the drawings may be exaggerated. For example, since the sizes and thicknesses of the elements in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0047] In the following embodiments, the x-axis, y-axis and z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other or can represent different directions that are not perpendicular to each other.

[0048] When a certain embodiment is implemented differently, a specific process order can be executed differently from the described order. For example, two consecutively described processes can be executed substantially simultaneously or in an order opposite to the described order.

[0049] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and disclosure, and should not be interpreted in an idealized or overly formal sense unless clearly so defined herein.

[0050] Figure 1 is a schematic plan view of a display device 1 according to an embodiment.

[0051] Reference Figure 1 , the display device 1 manufactured according to an embodiment may include a display area DA and a peripheral area PA located outside the display area DA. The display device 1 can provide an image in the display area DA through an array of one or more pixels PX arranged two-dimensionally.

[0052] The peripheral area PA (which is an area that does not provide an image) may be adjacent to the display area DA or may completely or partially surround the display area DA. A driver or the like for supplying an electrical signal or power to each of the pixel circuits corresponding to the pixels PX may be disposed in the peripheral area PA. A pad area (which is an area to which an electronic device, a printed circuit board, etc. can be electrically connected) may be provided in the peripheral area PA.

[0053] In an embodiment, the display device 1 may include an organic light-emitting diode (OLED) as a light-emitting element, but the display device 1 according to one or more embodiments is not limited thereto. In another embodiment, the display device 1 may be a light-emitting display device including an inorganic light-emitting diode, for example, an inorganic light-emitting display device. The inorganic light-emitting diode may include a PN junction diode including a material based on an inorganic semiconductor. When a voltage is applied to the PN junction diode in the forward direction, holes and electrons are injected, and the energy generated by the recombination of the holes and electrons may be converted into light energy, thereby emitting light of a certain color. The inorganic light-emitting diode described above may have a width of several to several hundred micrometers, and in some embodiments, the inorganic light-emitting diode may be referred to as a micro light-emitting diode (LED). In another embodiment, the display device 1 may be a quantum dot light-emitting display device.

[0054] The display device 1 may be used as a display screen for various products, and various products include not only portable electronic devices such as tablet personal computers (PCs), mobile communication terminals (e.g., mobile phones, smart phones), electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, ultra-mobile PCs (UMPCs), etc., but also televisions, laptop computers, monitors, billboards, Internet of Things (IoT) devices, etc. In addition, the display device 1 according to an embodiment may be used for wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, the display device 1 according to an embodiment may be used as an instrument panel of a vehicle, a central information display (CID) provided in a center fascia or an instrument panel of a vehicle, an in-vehicle mirror display replacing a side mirror of a vehicle, or a display screen of an entertainment device provided on the rear surface of a front seat as a rear seat of a vehicle.

[0055] Figure 2 is a schematic cross-sectional view of the display device 1 according to an embodiment taken along the line II-II'. Figure 1

[0056] Referring Figure 2 to, the display device 1 may include a substrate 100, a pixel circuit layer PCL, a display element layer DEL, and a packaging layer 300.

[0057] The substrate 100 may have a multi-layer structure including a base layer and an inorganic layer, where the base layer includes a polymer resin. For example, the substrate 100 may include a base layer containing a polymer resin and a barrier layer (which is an inorganic insulating layer). For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and / or a second barrier layer 104 stacked in sequence. The first base layer 101 and the second base layer 103 may include, for example, polyimide (PI), polyethersulfone (PES), polyarylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polycarbonate, triacetyl cellulose (TAC), cellulose acetate propionate (CAP), and / or the like. The first barrier layer 102 and the second barrier layer 104 may each include an inorganic insulating material such as silicon oxide, silicon oxynitride, and / or silicon nitride. The substrate 100 may be flexible.

[0058] The pixel circuit layer PCL may be disposed on the substrate 100. The pixel circuit layer PCL may include a first thin film transistor TFT1, a second thin film transistor TFT2, and a third thin film transistor TFT3 spaced apart from each other. The first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 may each include a semiconductor layer Act, a gate electrode GE, a drain electrode DE, and a source electrode SE.

[0059] For example, the semiconductor layer Act may include polysilicon (poly-Si). As another example, the semiconductor layer Act may include amorphous silicon (a-Si), an oxide semiconductor, an organic semiconductor, etc. The semiconductor layer Act may include a channel region C and a drain region D and a source region S disposed on opposite sides of the channel region C. The gate electrode GE may overlap the channel region C.

[0060] The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a single layer or multiple layers including the materials described above.

[0061] The drain electrode DE may be connected to the drain region D, and the source electrode SE may be connected to the source region S. The drain electrode DE and the source electrode SE may each include a material having excellent or desired conductivity. The drain electrode DE and the source electrode SE may each include a conductive material, for example, including Mo, Al, Cu, Ti, etc., and may each be formed as a multiple layer or a single layer including the materials described above. In an embodiment, the drain electrode DE and the source electrode SE may each have a multi-layer structure of Ti / Al / Ti.

[0062] The pixel circuit layer PCL may include a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 114, a first planarization insulating layer 115, and a second planarization insulating layer 116.

[0063] The buffer layer 111 may reduce or prevent foreign substances, moisture, or external air from infiltrating from below the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride, and has a single-layer or multi-layer structure including the above-described (those) materials.

[0064] The semiconductor layer Act may be disposed on the buffer layer 111, and the first gate insulating layer 112 may be disposed between the semiconductor layer Act and the gate electrode GE. The first gate insulating layer 112 may include inorganic insulating materials such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO x ), etc. For example, ZnO x may include zinc oxide (ZnO) and / or zinc peroxide (ZnO2).

[0065] The second gate insulating layer 113 may cover the gate electrode GE (or overlap with the gate electrode GE). Similar to the first gate insulating layer 112, the second gate insulating layer 113 may include inorganic insulating materials such as SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO x . For example, ZnO x may include ZnO and / or ZnO2.

[0066] The upper electrode Cst2 of the storage capacitor Cst may be disposed above the second gate insulating layer 113. The upper electrode Cst2 may overlap with the gate electrode GE therebelow. In this state, the gate electrode GE and the upper electrode Cst2 that overlap with each other with the second gate insulating layer 113 therebetween may form the storage capacitor Cst. In other words, the gate electrode GE may serve as the lower electrode Cst1 of the storage capacitor Cst.

[0067] The upper electrode Cst2 may include Al, platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), Mo, Ti, tungsten (W), and / or Cu, and may be formed as a single layer or multi-layer including the above-described materials.

[0068] The interlayer insulating layer 114 may cover (or overlap with) the upper electrode Cst2. The interlayer insulating layer 114 may include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, ZnO x , etc. For example, ZnO x may include ZnO and / or ZnO2. The interlayer insulating layer 114 may be a single layer or multiple layers including the inorganic insulating materials described above.

[0069] The drain electrode DE and the source electrode SE may each be disposed on the interlayer insulating layer 114. The drain electrode DE and the source electrode SE may be respectively connected to the drain region D and the source region S through contact holes formed in the underlying insulating layer.

[0070] The first planarization insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first planarization insulating layer 115 may include an organic insulating material, such as a general polymer including polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a parylene-based polymer, a polyvinyl alcohol-based polymer, and mixtures thereof.

[0071] The second planarization insulating layer 116 may be disposed on the first planarization insulating layer 115. The second planarization insulating layer 116 and the first planarization insulating layer 115 may include the same material, and the second planarization insulating layer 116 may include an organic insulating material, such as a general polymer including polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a parylene-based polymer, a polyvinyl alcohol-based polymer, and mixtures thereof.

[0072] The display element layer DEL may be disposed on the pixel circuit layer PCL. The display element layer DEL may include a first light-emitting element ED1, a second light-emitting element ED2, a third light-emitting element ED3, and / or a bank layer 117.

[0073] The first light-emitting element ED1 can emit first light, the second light-emitting element ED2 can emit second light, and the third light-emitting element ED3 can emit third light. The first light, the second light, and the third light can each be any one of red light, green light, and blue light. The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 can emit lights of different colors. For example, the first light-emitting element ED1 can emit red light, the second light-emitting element ED2 can emit green light, and the third light-emitting element ED3 can emit blue light. However, this is an example, and the lights emitted by the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 are not limited to this.

[0074] The first light-emitting element ED1 can include a first pixel electrode 211, a first intermediate layer 221, and a first common electrode 231.

[0075] The first pixel electrode 211 can be disposed on the pixel circuit layer PCL. The first pixel electrode 211 can be disposed on the second planarization insulating layer 116. The first pixel electrode 211 can be electrically connected to the first thin-film transistor TFT1 through a contact hole formed in the second planarization insulating layer 116 and the first planarization insulating layer 115 and a first contact metal CM1 disposed on the first planarization insulating layer 115.

[0076] The first intermediate layer 221 can be disposed on the first pixel electrode 211. The first intermediate layer 221 can be in contact with the first pixel electrode 211. The first pixel electrode 211 and the first intermediate layer 221 can be connected to each other without forming a step. In other words, the ends of the first pixel electrode 211 and the first intermediate layer 221 can match each other. In addition, the side surfaces of the first pixel electrode 211 and the first intermediate layer 221 can be formed on the same plane.

[0077] The first common electrode 231 can be disposed on the first intermediate layer 221. The first common electrode 231 can be in contact with the upper surface and the side surface of the first intermediate layer 221. The first common electrode 231 can overlap with the first pixel electrode 211.

[0078] The second pixel electrode 212 can be disposed on the pixel circuit layer PCL. The second pixel electrode 212 can be disposed on the second planarization insulating layer 116. The second pixel electrode 212 can be electrically connected to the second thin-film transistor TFT2 through a contact hole formed in the second planarization insulating layer 116 and the first planarization insulating layer 115 and a second contact metal CM2 disposed on the first planarization insulating layer 115.

[0079] The second intermediate layer 222 may be disposed on the second pixel electrode 212. The second intermediate layer 222 may be in contact with the second pixel electrode 212. The second pixel electrode 212 and the second intermediate layer 222 may be connected to each other without forming a step. In other words, the ends of the second pixel electrode 212 and the second intermediate layer 222 may match each other. In addition, the side surfaces of the second pixel electrode 212 and the second intermediate layer 222 may be formed on the same plane.

[0080] The second common electrode 232 may be disposed on the second intermediate layer 222. The second common electrode 232 may be in contact with the upper surface and the side surface of the second intermediate layer 222. The second common electrode 232 may overlap with the second pixel electrode 212.

[0081] The third pixel electrode 213 may be disposed on the pixel circuit layer PCL. The third pixel electrode 213 may be disposed on the second planarization insulating layer 116. The third pixel electrode 213 may be electrically connected to the third thin film transistor TFT3 through a contact hole formed in the first planarization insulating layer 115 and the second planarization insulating layer 116 and a third contact metal CM3 disposed on the first planarization insulating layer 115.

[0082] The third intermediate layer 223 may be disposed on the third pixel electrode 213. The third intermediate layer 223 may be in contact with the third pixel electrode 213. The third pixel electrode 213 and the third intermediate layer 223 may be connected to each other without forming a step. In other words, the ends of the third pixel electrode 213 and the third intermediate layer 223 may match each other. In addition, the side surfaces of the third pixel electrode 213 and the third intermediate layer 223 may be formed on the same plane.

[0083] The third common electrode 233 may be disposed on the third intermediate layer 223. The third common electrode 233 may be in contact with the upper surface and the side surface of the third intermediate layer 223. The third common electrode 233 may overlap with the third pixel electrode 213.

[0084] The first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may each include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x) indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may each include a reflective film including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture (or combination) thereof. In another embodiment, the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 may also each include a film formed of ITO, IZO, ZnO, or In2O3 above / below the reflective film described above.

[0085] The first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223 may each include an emission layer, and the emission layer may include a polymer or a low-molecular-weight organic material that emits light of a certain color. As another example, the emission layer may include an inorganic light-emitting material or quantum dots. The first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223 may each include a hole transport layer (HTL) and / or a hole injection layer (HIL) disposed below the emission layer. In addition, the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223 may each include an electron transport layer (ETL) and / or an electron injection layer (EIL) disposed above the emission layer.

[0086] The first common electrode 231, the second common electrode 232, and the third common electrode 233 may be connected to each other to form a common electrode 230. In other words, the common electrode 230 may include the first common electrode 231, the second common electrode 232, and the third common electrode 233. The first common electrode 231, the second common electrode 232, and the third common electrode 233 may be integrally formed to completely cover the substrate 100.

[0087] The common electrode 230 may include a conductive material having a low work function. For example, the common electrode 230 may include a (semi)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), Ca, or an alloy thereof, etc. As another example, the common electrode 230 may also include a layer including ITO, IZO, ZnO, or In2O3 on the (semi)transparent layer including the materials described above.

[0088] The bank layer 117 can be disposed between the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3. The bank layer 117 can be accommodated in the space between the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223. In this state, the heights of the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223 can be the same as each other. In addition, the heights of the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223 can be greater than the height of the bank layer 117.

[0089] The bank layer 117 can be in contact with the side surfaces of the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213. The bank layer 117 isolates the first pixel electrode 211, the second pixel electrode 212, and the third pixel electrode 213 from being electrically connected to each other. In addition, the bank layer 117 can be in contact with the side surfaces of the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223. The bank layer 117 isolates the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223 from being electrically connected to each other. The bank layer 117 can include an organic insulating material and / or an inorganic insulating material.

[0090] The common electrode 230 can be disposed on the bank layer 117. In other words, the common electrode 230 can be in contact with the upper surface of the bank layer 117. Due to the arrangement of the bank layer 117, the height difference of the common electrode 230 can be reduced. In this structure, short circuits or disconnections of the common electrode 230 can be reduced.

[0091] The encapsulation layer 300 can be disposed on the display element layer DEL. The encapsulation layer 300 can cover the display element layer DEL (or overlap with the display element layer DEL). The encapsulation layer 300 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer, and in an embodiment, Figure 2 it is shown that the encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and / or a second inorganic encapsulation layer 330 stacked in sequence.

[0092] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can each include one or more inorganic materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 can include a polymer-based material. The polymer-based material can include acrylic resin, epoxy resin, polyimide, polyethylene, etc. In an embodiment, the organic encapsulation layer 320 can include acrylate. The organic encapsulation layer 320 can be formed by curing a monomer or coating a polymer. The organic encapsulation layer 320 can be transparent.

[0093] Although not shown, a touch sensor layer may be disposed on the encapsulation layer 300, and an optical function layer may be disposed on the touch sensor layer. The touch sensor layer may obtain coordinate information in accordance with an external input (e.g., a touch event). The optical function layer may reduce a reflectance of external light (ambient light) incident on the display device 1, and / or improve color purity of light emitted from the display device 1. In an embodiment, the optical function layer may include a retarder and / or a polarizer. The retarder may be a film type or a liquid crystal coating type, and may include, for example, a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a stretchable synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a certain array. The retarder and the polarizer may each further include a protective film.

[0094] An adhesive member may be disposed between the touch electrode layer and the optical function layer. The adhesive member may be any conventional member in the art without limitation. For example, the adhesive member may include a pressure sensitive adhesive (PSA).

[0095] Figure 3 is a schematic diagram of an equivalent circuit of any pixel of the display device 1 according to an embodiment.

[0096] Each pixel PX may include a pixel circuit PC and a display element (e.g., an organic light emitting diode OLED) connected to the pixel circuit PC. The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. Each pixel PX may emit light, such as red, green, blue, or white light, through the organic light emitting diode OLED.

[0097] The switching thin film transistor T2 may be connected to a scan line SL and a data line DL, and may transmit a data voltage input through the data line DL to the driving thin film transistor T1 based on a switching voltage input through the scan line SL. The storage capacitor Cst may be connected to the switching thin film transistor T2 and a driving voltage line PL, and may store a voltage corresponding to a difference between a voltage received from the switching thin film transistor T2 and a first power supply voltage ELVDD supplied to the driving voltage line PL.

[0098] The driving thin film transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing into the organic light emitting diode OLED from the driving voltage line PL in response to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a certain luminance based on the driving current. An opposite electrode (e.g., a cathode) of the organic light emitting diode OLED may receive a second power supply voltage ELVSS.

[0099] Although Figure 3The pixel circuit PC is shown to include two thin film transistors and a storage capacitor, but the present disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors can be variably changed according to the design of the pixel circuit PC. For example, in addition to the two thin film transistors described above, the pixel circuit PC may further include four or five or more thin film transistors.

[0100] Figure 4 is a schematic flowchart of Method 2 for manufacturing a display device according to an embodiment.

[0101] Figure 5 is a schematic flowchart of the operation of arranging the display element layer DEL (S2) on the pixel circuit layer PCL according to an embodiment. Figures 6 to 24 is a schematic cross-sectional view of a part during the manufacturing process of the display device 1.

[0102] Referring to Figures 4 to 24 , it can be seen that Method 2 for manufacturing a display device is to manufacture the display device 1 described with reference to Figures 1 to 3 .

[0103] In Figures 4 to 24 , since the same reference numerals / characters as those used in Figures 1 to 3 can denote the same elements, redundant descriptions thereof are omitted.

[0104] Referring to Figure 4 and Figure 6 , Method 2 for manufacturing a display device may include arranging the pixel circuit layer PCL (S1) on the substrate 100.

[0105] The substrate 100 may have a multilayer structure including a base layer and an inorganic layer, where the base layer includes a polymer resin. For example, the substrate 100 may include a base layer containing a polymer resin and a barrier layer (which is an inorganic insulating layer). For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and / or a second barrier layer 104 stacked in sequence.

[0106] The pixel circuit layer PCL may be disposed on the substrate 100. The pixel circuit layer PCL may include a first thin film transistor TFT1, a second thin film transistor TFT2, and a third thin film transistor TFT3 spaced apart from each other. In addition, the pixel circuit layer PCL may include a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 114, a first planarization insulating layer 115, and / or a second planarization insulating layer 116.

[0107] Referring to Figures 4 to 23 , Method 2 for manufacturing a display device may include arranging the display element layer DEL (S2) on the pixel circuit layer PCL.

[0108] First, referring to Figure 5 and Figure 6 , disposing the display element layer DEL (S2) on the pixel circuit layer PCL may include disposing the pixel electrode layer 210 on the pixel circuit layer PCL (S201).

[0109] The pixel electrode layer 210 may be disposed on the pixel circuit layer PCL and may be connected to each of the first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3.

[0110] The pixel electrode layer 210 may be electrically connected to the first thin film transistor TFT1 through a contact hole formed in the second planarization insulating layer 116 and the first planarization insulating layer 115 and a first contact metal CM1 disposed on the first planarization insulating layer 115.

[0111] In addition, the pixel electrode layer 210 may be electrically connected to the second thin film transistor TFT2 through a contact hole formed in the second planarization insulating layer 116 and the first planarization insulating layer 115 and a second contact metal CM2 disposed on the first planarization insulating layer 115.

[0112] The pixel electrode layer 210 may be electrically connected to the third thin film transistor TFT3 through a contact hole formed in the second planarization insulating layer 116 and the first planarization insulating layer 115 and a third contact metal CM3 disposed on the first planarization insulating layer 115.

[0113] The pixel electrode layer 210 may include a conductive oxide such as ITO, IZO, ZnO, In2O3, IGO, or AZO. In another embodiment, the pixel electrode layer 210 may include a reflective film including, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture thereof. In another embodiment, the pixel electrode layer 210 may further include a film formed of ITO, IZO, ZnO, or In2O3 above / below the reflective film described above.

[0114] Referring to Figure 5 and Figure 7 , disposing the display element layer DEL (S2) on the pixel circuit layer PCL may include disposing a first intermediate layer 221 on the pixel electrode layer 210 (S202) and disposing a first sacrificial layer SL1 on the first intermediate layer 221 (S203).

[0115] The first intermediate layer 221 may be disposed on the pixel electrode layer 210 to cover the pixel electrode layer 210 (or overlap with the pixel electrode layer 210). The first sacrificial layer SL1 may be disposed on the first intermediate layer 221 to cover the first intermediate layer 221. The first sacrificial layer SL1 may include at least one material of IZO and indium gallium zinc oxide (IGZO).

[0116] Reference Figure 5 and Figures 8 to 10 , disposing the display element layer DEL(S2) on the pixel circuit layer PCL may include patterning the first intermediate layer 221 and the first sacrificial layer SL1 (S204). Patterning the first intermediate layer 221 and the first sacrificial layer SL1 (S204) may include a photolithography process.

[0117] Reference Figure 8 , a patterned first photoresist layer PR1 may be disposed on the first sacrificial layer SL1. Reference Figure 9 , the first intermediate layer 221 and the first sacrificial layer SL1 may be etched. For example, the first intermediate layer 221 and the first sacrificial layer SL1 may be dry-etched by using an etching gas. In this process, the first intermediate layer 221 and the first sacrificial layer SL1 overlapping with the first photoresist layer PR1 may be retained. The first intermediate layer 221 and the first sacrificial layer SL1 not overlapping with the first photoresist layer PR1 may be etched and removed. Reference Figure 10 , the first photoresist layer PR1 may be removed.

[0118] Reference Figure 5 and Figure 11 , disposing the display element layer DEL(S2) on the pixel circuit layer PCL may include disposing a second intermediate layer 222 on the pixel electrode layer 210 (S205) and disposing a second sacrificial layer SL2 on the second intermediate layer 222 (S206).

[0119] The second intermediate layer 222 may be disposed on the pixel electrode layer 210 to cover the pixel electrode layer 210 (or overlap with the pixel electrode layer 210). A part of the second intermediate layer 222 may be disposed on the first intermediate layer 221 and the first sacrificial layer SL1. The second sacrificial layer SL2 may be disposed on the second intermediate layer 222 to cover the second intermediate layer 222. The second sacrificial layer SL2 may include at least one material of IZO and IGZO.

[0120] Reference Figure 5 and Figures 12 to 14 , disposing the display element layer DEL(S2) on the pixel circuit layer PCL may include patterning the second intermediate layer 222 and the second sacrificial layer SL2 (S207). Patterning the second intermediate layer 222 and the second sacrificial layer SL2 (S207) may include a photolithography process.

[0121] Reference Figure 12 A patterned second photoresist layer PR2 may be disposed on the second sacrificial layer SL2. Reference Figure 13 The second intermediate layer 222 and the second sacrificial layer SL2 may be etched. For example, the second intermediate layer 222 and the second sacrificial layer SL2 may be dry-etched by using an etching gas. In this process, the second intermediate layer 222 and the second sacrificial layer SL2 overlapping with the second photoresist layer PR2 may be retained. The second intermediate layer 222 and the second sacrificial layer SL2 not overlapping with the second photoresist layer PR2 may be etched and removed. Reference Figure 14 The second photoresist layer PR2 may be removed.

[0122] Reference Figure 5 and Figure 15 Disposing the display element layer DEL(S2) on the pixel circuit layer PCL may include disposing a third intermediate layer 223(S208) on the pixel electrode layer 210 and disposing a third sacrificial layer SL3(S209) on the third intermediate layer 223.

[0123] The third intermediate layer 223 may be disposed on the pixel electrode layer 210 to cover the pixel electrode layer 210 (or overlap with the pixel electrode layer 210). A part of the third intermediate layer 223 may be disposed on the first intermediate layer 221 and the first sacrificial layer SL1. In addition, a part of the third intermediate layer 223 may be disposed on the second intermediate layer 222 and the second sacrificial layer SL2. The third sacrificial layer SL3 may be disposed on the third intermediate layer 223 to cover the third intermediate layer 223 (or overlap with the third intermediate layer 223). The third sacrificial layer SL3 may include at least one material of IZO and IGZO.

[0124] Reference Figure 5 and Figures 16 to 18 Disposing the display element layer DEL(S2) on the pixel circuit layer PCL may include patterning the third intermediate layer 223 and the third sacrificial layer SL3(S210). Patterning the third intermediate layer 223 and the third sacrificial layer SL3(S210) may include a photolithography process.

[0125] Reference Figure 16 A patterned third photoresist layer PR3 may be disposed on the third sacrificial layer SL3. Reference Figure 17 The third intermediate layer 223 and the third sacrificial layer SL3 may be etched. For example, the third intermediate layer 223 and the third sacrificial layer SL3 may be dry-etched by using an etching gas. In this process, the third intermediate layer 223 and the third sacrificial layer SL3 overlapping with the third photoresist layer PR3 may be retained. The third intermediate layer 223 and the third sacrificial layer SL3 not overlapping with the third photoresist layer PR3 may be etched and removed. Reference Figure 18, the third photoresist layer PR3 can be removed.

[0126] Reference Figure 5 and Figure 19 , disposing the display element layer DEL(S2) on the pixel circuit layer PCL may include forming a first pixel electrode 211(S2111), forming a second pixel electrode 212(S2112), and forming a third pixel electrode 213(S2113).

[0127] For example, the first pixel electrode 211 is formed by patterning the pixel electrode layer 210 to overlap with the first sacrificial layer SL1, the second pixel electrode 212 is formed by patterning the pixel electrode layer 210 to overlap with the second sacrificial layer SL2, and the third pixel electrode 213 is formed by patterning the pixel electrode layer 210 to overlap with the third sacrificial layer SL3. For example, the pixel electrode layer 210 can be dry-etched using an etching gas. In this state, the first sacrificial layer SL1, the second sacrificial layer SL2, and the third sacrificial layer SL3 can act as masks.

[0128] In other words, forming the first pixel electrode 211(S2111) may include etching the pixel electrode layer 210 using the first sacrificial layer SL1 as a mask. In addition, forming the second pixel electrode 212(S2112) may include etching the pixel electrode layer 210 using the second sacrificial layer SL2 as a mask. Forming the third pixel electrode 213(S2113) may include etching the pixel electrode layer 210 using the third sacrificial layer SL3 as a mask. Forming the first pixel electrode 211(S2111), forming the second pixel electrode 212(S2112), and forming the third pixel electrode 213(S2113) can be performed simultaneously.

[0129] Therefore, the first pixel electrode 211 overlapping with the first sacrificial layer SL1, the second pixel electrode 212 overlapping with the second sacrificial layer SL2, and the third pixel electrode 213 overlapping with the third sacrificial layer SL3 can be retained.

[0130] In this process, the first pixel electrode 211 and the first intermediate layer 221 can be connected to each other without forming a step. In other words, the ends of the first pixel electrode 211 and the first intermediate layer 221 can match each other. The side surfaces of the first pixel electrode 211 and the first intermediate layer 221 can be formed on the same plane.

[0131] In addition, the second pixel electrode 212 and the second intermediate layer 222 can be connected to each other without forming a step. In other words, the ends of the second pixel electrode 212 and the second intermediate layer 222 can match each other. The side surfaces of the second pixel electrode 212 and the second intermediate layer 222 can be formed on the same plane.

[0132] The third pixel electrode 213 and the third intermediate layer 223 may be connected to each other without forming a step. In other words, the ends of the third pixel electrode 213 and the third intermediate layer 223 may match each other. The side surfaces of the third pixel electrode 213 and the third intermediate layer 223 may be formed on the same plane.

[0133] Reference Figure 5 and Figure 20 , disposing the display element layer DEL (S2) on the pixel circuit layer PCL may include disposing a bank layer 117 (S212) on the pixel circuit layer PCL.

[0134] The bank layer 117 may cover each of the pixel circuit layer PCL, the first pixel electrode 211, the second pixel electrode 212, the third pixel electrode 213, the first intermediate layer 221, the second intermediate layer 222, the third intermediate layer 223, the first sacrificial layer SL1, the second sacrificial layer SL2, and the third sacrificial layer SL3 (or overlap with each of the pixel circuit layer PCL, the first pixel electrode 211, the second pixel electrode 212, the third pixel electrode 213, the first intermediate layer 221, the second intermediate layer 222, the third intermediate layer 223, the first sacrificial layer SL1, the second sacrificial layer SL2, and the third sacrificial layer SL3).

[0135] Reference Figure 5 and Figure 21 , disposing the display element layer DEL (S2) on the pixel circuit layer PCL may include etching the bank layer 117 (S213).

[0136] The first sacrificial layer SL1, the second sacrificial layer SL2, and the third sacrificial layer SL3 may be exposed from the bank layer 117. In addition, portions of the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223 may be exposed from the bank layer 117. The heights of the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223 may be greater than the height of the etched bank layer 117.

[0137] Reference Figure 5 and Figure 22 , disposing the display element layer DEL (S2) on the pixel circuit layer PCL may include removing each of the first sacrificial layer SL1, the second sacrificial layer SL2, and the third sacrificial layer SL3 (S214).

[0138] Reference Figure 5 and Figure 23, disposing the display element layer DEL on the pixel circuit layer PCL (S2) may include disposing the common electrode 230 on the bank layer 117 (S215). The common electrode 230 may cover the bank layer 117, the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223 (or overlap with the bank layer 117, the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223). The common electrode 230 may be electrically connected to the first intermediate layer 221, the second intermediate layer 222, and the third intermediate layer 223. Due to the arrangement of the bank layer 117, the height difference of the common electrode 230 can be reduced. In this structure, short circuits or disconnections of the common electrode 230 can be reduced.

[0139] Reference Figure 4 and Figure 24 , the method 2 of manufacturing a display device may include disposing the encapsulation layer 300 on the display element layer DEL (S3).

[0140] The first inorganic encapsulation layer 310 may be disposed on the display element layer DEL, the organic encapsulation layer 320 may be disposed on the first inorganic encapsulation layer 310, and the second inorganic encapsulation layer 330 may be disposed on the organic encapsulation layer 320.

[0141] Finally, the first pixel electrode 211, the first intermediate layer 221, and the first common electrode 231 may constitute the first light-emitting element ED1. In addition, the second pixel electrode 212, the second intermediate layer 222, and the second common electrode 232 may constitute the second light-emitting element ED2. The third pixel electrode 213, the third intermediate layer 223, and the third common electrode 233 may constitute the third light-emitting element ED3.

[0142] According to an embodiment, by simplifying the manufacturing process of the display device, the cost and time spent on manufacturing the display device can be reduced.

[0143] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Therefore, the disclosed embodiments described above may be implemented alone or in combination with each other.

[0144] The embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the appended claims, and it should be understood that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. A display device, comprising: A pixel circuit layer is disposed on the substrate; as well as A display element layer is arranged on the pixel circuit layer, Wherein, the display element layer comprises: The first light emitting element, the second light emitting element, and the third light emitting element are spaced apart from each other; and a bank layer disposed between the first light emitting element, the second light emitting element and the third light emitting element, The first light emitting element comprises: a first pixel electrode; A first intermediate layer, disposed on the first pixel electrode; and A first common electrode is disposed on the first intermediate layer, The second light emitting element comprises: a second pixel electrode; A second intermediate layer, disposed on the second pixel electrode; and a second common electrode, disposed on the second intermediate layer, The third light emitting element comprises: a third pixel electrode; A third intermediate layer, disposed on the third pixel electrode; and a third common electrode, disposed on the third intermediate layer, and A height of each of the first intermediate layer, the second intermediate layer, and the third intermediate layer is greater than a height of the bank layer.

2. The display device according to claim 1, wherein: The first common electrode, the second common electrode, and the third common electrode are connected to each other.

3. The display device according to claim 2, wherein: The first common electrode, the second common electrode and the third common electrode are integrated with each other.

4. The display device according to claim 1, wherein: The first pixel electrode and the first intermediate layer are connected to each other without forming a step.

5. The display device according to claim 1, wherein: The first light emitting element, the second light emitting element, and the third light emitting element emit light of different colors.

6. A method for manufacturing a display device, the method comprising: Arranging a pixel circuit layer on a substrate; as well as Arranging a display element layer on the pixel circuit layer, Wherein, arranging the display element layer comprises: Arranging a pixel electrode layer on the pixel circuit layer; Arranging a first intermediate layer on the pixel electrode layer; disposing a first sacrificial layer on the first intermediate layer; patterning the first intermediate layer and the first sacrificial layer; and A first pixel electrode is formed by patterning the pixel electrode layer to overlap the first sacrificial layer.

7. The method according to claim 6, wherein: Forming the first pixel electrode includes etching the pixel electrode layer by using the first sacrificial layer as a mask.

8. The method according to claim 6, wherein: The first pixel electrode and the first intermediate layer are connected to each other without forming a step.

9. The method according to claim 6, wherein: Arranging the display element layer further includes: Arranging a second intermediate layer on the pixel electrode layer; disposing a second sacrificial layer on the second intermediate layer; patterning the second intermediate layer and the second sacrificial layer; and forming a second pixel electrode by patterning the pixel electrode layer to overlap the second sacrificial layer, and Forming the first pixel electrode and forming the second pixel electrode are performed simultaneously.

10. The method according to claim 9, wherein: Forming the second pixel electrode includes etching the pixel electrode layer by using the second sacrificial layer as a mask.

11. The method according to claim 9, wherein: The second pixel electrode and the second intermediate layer are connected to each other without forming a step.

12. The method according to claim 9, wherein: Arranging the display element layer further includes: Arranging a third intermediate layer on the pixel electrode layer; disposing a third sacrificial layer on the third intermediate layer; patterning the third intermediate layer and the third sacrificial layer; and forming a third pixel electrode by patterning the pixel electrode layer to overlap the third sacrificial layer, and The forming of the second pixel electrode and the forming of the third pixel electrode are performed simultaneously.

13. The method according to claim 12, wherein: Forming the third pixel electrode includes etching the pixel electrode layer by using the third sacrificial layer as a mask.

14. The method according to claim 12, wherein: The third pixel electrode and the third intermediate layer are connected to each other without forming a step.

15. The method according to claim 12, wherein: Arranging the display element layer further includes arranging a bank layer on the pixel circuit layer to cover each of the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer.

16. The method according to claim 15, wherein: Arranging the display element layer further includes etching the bank layer to expose portions of the first intermediate layer, the second intermediate layer, and the third intermediate layer.

17. The method according to claim 16, wherein: A height of each of the first intermediate layer, the second intermediate layer, and the third intermediate layer is greater than a height of the etched bank layer.

18. The method according to claim 16, wherein: Arranging the display element layer further includes removing each of the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer.

19. The method according to claim 15, wherein: Arranging the display element layer further includes arranging a common electrode on the bank layer to cover the first intermediate layer, the second intermediate layer, and the third intermediate layer.

20. The method according to claim 19, wherein: The common electrode is electrically connected to each of the first intermediate layer, the second intermediate layer, and the third intermediate layer.

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