Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device may include sub-pixel regions, and the light emitting element layer may include lines electrically connected to the pixel circuits. At least a portion of the capping layer is in contact with the pixel defining layer. The lines are disposed on the pixel defining layer and include a first line and a second line spaced apart from each other, the first line and the second line each forming a closed loop. The first line surrounds the sub-pixel region in a plan view, and the second line surrounds the first line in a plan view. A light emitting portion is provided in a region surrounded by the first wire.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2023-0185804, filed with the Korean Intellectual Property Office on December 19, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0004] With the development of information technology, the importance of a display device as a connection medium between a user and information is increasing. The display device may include light-emitting elements, and sub-pixels adjacent to each other may be formed using the light-emitting elements.

[0005] As the demand for high-quality display devices increases, the structure of sub-pixels becomes more refined, and a structure in which leakage current does not occur between sub-pixels is required.

[0006] In order to re-evaluate the reliability of an electrical signal supplied to a sub-pixel, it is necessary to reduce the risk of voltage drop caused by an increase in the resistance of a conductive structure to which the electrical signal is supplied. Summary of the Invention

[0007] One aspect of the present disclosure provides a display device and a method of manufacturing the display device in which a risk of voltage drop of a cathode electrode is reduced.

[0008] One aspect of the present disclosure provides a display device and a method of manufacturing the display device in which a risk of leakage current is reduced.

[0009] One aspect of the present disclosure provides a display device and a method of manufacturing the display device having excellent display quality capable of providing a high-resolution image.

[0010] One aspect of the present disclosure provides a display device and a method of manufacturing the display device in which the convenience of its manufacturing process is improved.

[0011] According to an embodiment, a display device may include a sub-pixel region. The display device may include a pixel circuit layer including a substrate layer and a pixel circuit disposed on the substrate layer, and a light-emitting element layer disposed on the pixel circuit layer. The light-emitting element layer includes a light-emitting element, a pixel defining layer, a capping layer, and a line electrically connected to the pixel circuit. The light-emitting element may include an anode electrode, a cathode electrode, and a light-emitting portion, and at least a part of the light-emitting portion is disposed between the anode electrode and the cathode electrode. The pixel defining layer may cover at least a part of the anode electrode. At least a part of the capping layer may be in contact with the pixel defining layer. The line may be disposed on the pixel defining layer, and the line may include a first line and a second line spaced apart from each other, and each of the first line and the second line may be disposed in a closed loop. The first line may surround the sub-pixel region in a plan view, and the second line may surround the first line in a plan view. The light-emitting portion may be disposed in a region surrounded by the first line.

[0012] According to an embodiment, the line may include a conductive material having a conductivity of less than about 4.0×10 7 (S / m) at about 20 °C.

[0013] According to an embodiment, the line may include aluminum (Al) or molybdenum (Mo).

[0014] According to an embodiment, the first line and the second line may include the same material, and each of the first line and the second line may be disposed on a surface of the pixel defining layer.

[0015] According to an embodiment, the first line may be disposed around the sub-pixel region. The second line may be disposed around the first line. The sub-pixel region may include a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region. The first line may include a first line portion surrounding the first sub-pixel region, a second line portion surrounding the second sub-pixel region, and a third line portion surrounding the third sub-pixel region.

[0016] According to an embodiment, the cathode electrode may include a first cathode electrode overlapping with the first sub-pixel region, a second cathode electrode overlapping with the second sub-pixel region, and a third cathode electrode overlapping with the third sub-pixel region. The first cathode electrode, the second cathode electrode, and the third cathode electrode may be physically separated from each other.

[0017] According to an embodiment, the pixel circuit layer may include a first power line and a second power line having different potentials. The first power line may be electrically connected to the pixel circuit. The second power line may be electrically connected to the cathode electrode through the first line.

[0018] According to an embodiment, the display device may further include a display area and a non-display area surrounding at least a part of the display area. The first line may be electrically connected to the second power line through a contact member that at least partially passes through the pixel defining layer. The second power line may have a thickness greater than the thickness of the cathode electrode. The contact member may be disposed in the display area.

[0019] According to an embodiment, the capping layer may include a first capping layer and a second capping layer disposed on the first capping layer. The first capping layer may cover the first line and may not cover the second line. The second capping layer may cover the second line.

[0020] According to an embodiment, each of the second capping layer and the pixel defining layer may include an inorganic material, and the second capping layer and the pixel defining layer may be in contact with each other in a region adjacent to the second line.

[0021] According to an embodiment, the display device may include a display area and a non-display area surrounding at least a part of the display area; a pixel circuit layer including a substrate layer, a pixel circuit, a power line disposed on the substrate layer, and a via layer covering the power line; and a light-emitting element layer disposed on the pixel circuit layer, and the light-emitting element layer includes a light-emitting element, a pixel defining layer, and a line electrically connected to the pixel circuit. The light-emitting element may include an anode electrode, a cathode electrode, and a light-emitting portion, and at least a part of the light-emitting portion may be disposed between the anode electrode and the cathode electrode. The pixel defining layer may overlap with the anode electrode in a plan view. The line may be directly disposed on the pixel defining layer, and the line may include a first line and a second line spaced apart from each other. The power line may be disposed across the display area and the non-display area. The cathode electrode and the power line may be electrically connected in the display area through a contact member passing through the via layer. The power line may have a thickness greater than the thickness of the cathode electrode.

[0022] According to an embodiment of the present disclosure, a method of manufacturing a display device may include manufacturing a pixel circuit layer and manufacturing a light-emitting element layer disposed on the pixel circuit layer, and the light-emitting element layer may include light-emitting elements. The manufacturing of the light-emitting element layer may include forming an anode electrode, a pixel defining layer, and lines on the pixel circuit layer, and forming sub-pixels by patterning a plurality of layers near the lines. The lines may be disposed on the pixel defining layer and may include a first line and a second line spaced apart from each other, and the first line may be disposed closer to the anode electrode than the second line. The patterning of the plurality of layers near the lines may include: forming a matrix light-emitting portion; removing at least a portion of the matrix light-emitting portion adjacent to the first line by supplying a first voltage to the first line; forming a matrix cathode electrode and a first matrix capping layer; and removing at least a portion of the matrix cathode electrode, at least a portion of the first matrix capping layer, and at least a portion of the matrix light-emitting portion adjacent to the second line by supplying a second voltage to the second line.

[0023] According to an embodiment, the pixel circuit layer may include a pixel circuit, a first power line electrically connected to the pixel circuit, and a second power line having a potential different from that of the first power line. The forming of the lines may include electrically connecting the first line to the second power line.

[0024] According to an embodiment, the forming of the matrix light-emitting portion may include depositing the matrix light-emitting portion entirely on the pixel circuit layer.

[0025] According to an embodiment, the removing of the at least a portion of the matrix light-emitting portion adjacent to the first line includes providing a first light-emitting portion disposed in a region surrounded by the first line.

[0026] According to an embodiment, the forming of the matrix cathode electrode may include electrically connecting the matrix cathode electrode to the first line and causing the matrix cathode electrode to contact the pixel defining layer in a region adjacent to the first line.

[0027] According to an embodiment, the removing of the at least a portion of the matrix light-emitting portion adjacent to the first line may include forming a first opening exposing at least a portion of the pixel defining layer. The removing of the at least a portion of the matrix cathode electrode, at least a portion of the first matrix capping layer, and at least a portion of the matrix light-emitting portion adjacent to the second line may include forming a second opening exposing at least a portion of the pixel defining layer.

[0028] According to an embodiment, the method may further include forming a second substrate capping layer; and removing at least a portion of the first substrate capping layer, at least a portion of the substrate cathode electrode, and at least a portion of the substrate light-emitting part disposed outside the second line.

[0029] According to an embodiment, the second substrate capping layer may contact the pixel defining layer in a region adjacent to the second line. Each of the second substrate capping layer and the pixel defining layer may include an inorganic material.

[0030] According to an embodiment, the method may further include depositing an encapsulation layer entirely on the pixel circuit layer.

[0031] According to an embodiment of the present disclosure, a display device and a method of manufacturing a display device in which the risk of voltage drop of a cathode electrode is reduced may be provided.

[0032] According to an embodiment of the present disclosure, a display device and a method of manufacturing a display device in which the risk of leakage current is reduced may be provided.

[0033] According to an embodiment of the present disclosure, a display device and a method of manufacturing a display device having excellent display quality capable of providing a high-resolution image may be provided.

[0034] According to an embodiment of the present disclosure, a display device and a method of manufacturing a display device in which the convenience of its manufacturing process is improved may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] By further describing embodiments of the present disclosure in detail with reference to the drawings, the above and other features of the present disclosure will become more apparent. In the drawings:

[0036] Figure 1 is a schematic plan view showing a display device according to an embodiment;

[0037] Figure 2 is a schematic plan view showing a display area according to an embodiment;

[0038] Figure 3 and Figure 4 is a schematic cross-sectional view showing a display device according to an embodiment;

[0039] Figure 5 is a schematic block diagram showing a connection structure of a sub-pixel including a light-emitting element according to an embodiment;

[0040] Figure 6 is a schematic cross-sectional view showing a light-emitting element and a capping layer according to an embodiment;

[0041] Figure 7is a schematic block diagram showing a circuit path through which a cathode signal is supplied according to an embodiment;

[0042] Figure 8 is a schematic cross-sectional view showing a thickness relationship between a second power line and a cathode electrode according to an embodiment;

[0043] Figure 9 is a flowchart showing a method of manufacturing a display device according to an embodiment;

[0044] Figure 10 is a flowchart showing steps of manufacturing a light-emitting element layer according to an embodiment;

[0045] Figure 11 is a flowchart of a step of patterning sub-pixels; and

[0046] Figures 12 to 25 is a schematic cross-sectional view of each process step of a method of manufacturing a display device according to an embodiment. Detailed Description

[0047] In the following description, for purposes of illustration, numerous specific details are set forth to provide a thorough understanding of the various embodiments or implementations disclosed herein. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of the devices or methods disclosed herein. However, it is apparent that the various embodiments can be implemented without these specific details or with one or more equivalent arrangements. Here, the various embodiments need not be exclusive or limit the present disclosure. For example, the specific shape, configuration, and characteristics of one embodiment can be used or implemented in another embodiment.

[0048] Unless otherwise specified, the illustrated embodiments should be understood to provide features of the present disclosure. Thus, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments can be otherwise combined, separated, interchanged, and / or rearranged without departing from the inventive concept.

[0049] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other feature, attribute, characteristic, etc. of the elements. Additionally, in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or for descriptive purposes. When embodiments may be implemented differently, a particular process sequence may be performed differently from the sequence described. For example, two consecutively described processes may be performed simultaneously on a substrate or in an order opposite to the described order. Further, like reference numerals and / or reference characters denote like elements.

[0050] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, no intervening elements or layers are present. For this reason, the term "connected" can refer to physical connection, electrical connection, and / or fluid connection with or without intervening elements. Additionally, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other or can represent different directions that are not perpendicular to each other.

[0051] For the purposes of this disclosure, "at least one of A and B" can be interpreted as only A, only B, or any combination of A and B. Additionally, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0052] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of this disclosure, the first element discussed later may be named the second element.

[0053] In this document, for descriptive purposes, spatial relative terms such as "under", "below", "beneath", "lower", "above", "upper", "over", "higher", and "side" (e.g., as in "sidewall") may be used and thereby describe the relationship between one element and another (or elements) as shown in the figures. In addition to the orientation depicted in the figures, spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacturing. For example, if the device is flipped in the figures, an element described as "under" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the term "under" can include both the above and below orientations. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and thus, the spatial relative descriptors used herein are to be interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. Unless the context clearly dictates otherwise, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms. Additionally, when used in this specification, the terms "comprises", "comprising", "includes", and "including" specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and are thus used to interpret the inherent deviations in measured, calculated, and / or provided values that would be recognized by one of ordinary skill in the art.

[0055] The various embodiments herein are described with reference to sectional and / or exploded views that are schematic illustrations of embodiments and / or intermediate structures. Accordingly, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein are not necessarily to be construed as limited to the specific shapes of the regions shown, but will include deviations in shape due to, for example, manufacturing. In this manner, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device and, thus, are not necessarily intended to be restrictive.

[0056] In accordance with the convention in the art, some embodiments are described and illustrated in the drawings in the form of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform various functions discussed herein, and can optionally be driven by firmware and / or software. It is also conceivable that each block, unit, and / or module can be implemented by dedicated hardware or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Additionally, without departing from the scope of the inventive concept of the present invention, each block, unit, and / or module of some embodiments can be physically separated into two or more interacting and discrete blocks, units, and / or modules. Further, without departing from the scope of the inventive concept of the present invention, the blocks, units, and / or modules of some embodiments can be physically combined into more complex blocks, units, and / or modules.

[0057] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, unless explicitly defined herein, and should not be interpreted in an idealized or overly formal sense.

[0058] The present disclosure relates to a display device and a method of manufacturing a display device. Hereinafter, a display device and a method of manufacturing a display device according to an embodiment will be described with reference to the drawings.

[0059] Figure 1 is a schematic plan view showing a display device according to an embodiment.

[0060] Referring to Figure 1 , the display device DD may include a substrate layer BSL and pixels PXL disposed on the substrate layer BSL. Although not shown in the drawings, the display device DD may further include a driving circuit portion (e.g., a scan driver and a data driver) for driving the pixels PXL, lines (or heating lines for heating wiring or resistive Joule heating lines), and pads.

[0061] The display device DD (or the base layer BSL) may include a display area DA and a non-display area NDA. The non-display area NDA may represent an area other than the display area DA. The non-display area NDA may surround at least a part of the display area DA.

[0062] The base layer BSL may form the base surface of the display device DD. The base layer BSL may be a rigid or flexible substrate or film. For example, the base layer BSL may include a glass material. The base layer BSL may include a silicon material. The base layer BSL may include polyimide. However, the present disclosure is not limited thereto.

[0063] The display area DA may represent an area where pixels PXL are provided. The non-display area NDA may represent an area where pixels PXL may not be provided. A driving circuit portion, lines, and pads electrically connected to the pixels PXL in the display area DA may be provided in the non-display area NDA.

[0064] According to an embodiment, the pixel PXL (or sub-pixel SPX) may be arranged according to a stripe or layout structure, but is not limited thereto, and various embodiments may be applied to the present disclosure.

[0065] According to an embodiment, the pixel PXL (or sub-pixel SPX) may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be a sub-pixel. At least one of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may form a pixel portion capable of emitting light of various colors.

[0066] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may emit light of one color.

[0067] For example, the first sub-pixel SPX1 may be a red sub-pixel that emits red (e.g., the first color) light, the second sub-pixel SPX2 may be a green sub-pixel that emits green (e.g., the second color) light, and the third sub-pixel SPX3 may be a blue sub-pixel that emits blue (e.g., the third color) light. The red sub-pixel may provide light in a wavelength range of 600 nm to 750 nm. The green sub-pixel may provide light in a wavelength range of 480 nm to 560 nm. The blue sub-pixel may provide light in a wavelength range of 370 nm to 460 nm.

[0068] According to an embodiment, the number of second sub-pixels SPX2 may be greater than the number of first sub-pixels SPX1 and the number of third sub-pixels SPX3. However, the colors, types, and / or numbers, etc. of the first sub-pixels SPX1, second sub-pixels SPX2, and third sub-pixels SPX3 forming each pixel portion are not limited to specific examples.

[0069] Figure 2 is a schematic plan view showing a display area according to an embodiment. For ease of description, Figure 2 shows a structure in which the first sub-pixels SPX1 to the third sub-pixels SPX3 may be sequentially arranged in a first direction DR1. However, the present disclosure is not limited thereto.

[0070] Referring to Figure 2 , the display device DD may further include a line L disposed adjacent to the sub-pixels SPX.

[0071] According to an embodiment, the sub-pixels SPX may form a sub-pixel region SPXA. The sub-pixel region SPXA may be a region of light of a visible color. For example, the sub-pixel region SPXA may include: a first sub-pixel region SPXA1 in which the first sub-pixels SPX1 may be formed and which may provide light of a first color; a second sub-pixel region SPXA2 in which the second sub-pixels SPX2 may be formed and which may provide light of a second color; and a third sub-pixel region SPXA3 in which the third sub-pixels SPX3 may be formed and which may provide light of a third color.

[0072] The line L may include a plurality of lines L corresponding to each of the sub-pixels SPX. For example, the line L may include a first line portion surrounding the first sub-pixel region SPXA1, a second line portion surrounding the second sub-pixel region SPXA2, and a third line portion surrounding the third sub-pixel region SPXA3. The shape of the line L may be determined by the shape of each of the sub-pixel regions SPXA. For example, the shape of the line L may correspond to the edge shape of the sub-pixel region SPXA.

[0073] The line L may include a first line L1 and a second line L2. In a plan view, the first line L1 and the second line L2 may be spaced apart from each other and may not overlap each other. The first line L1 and the second line L2 may be physically spaced apart from each other. The first line L1 and the second line L2 may be electrically separated from each other.

[0074] The first line L1 may be disposed around the sub-pixel region SPXA. The first line L1 may be disposed between the sub-pixel region SPXA and the second line L2. In a plan view, the first line L1 may form a closed loop and may surround the sub-pixel region SPXA.

[0075] The second line L2 may be disposed around the first line L1. The second line L2 may be disposed outside the closed loop formed by the first line L1. In a plan view, the second line L2 may form a closed loop and may surround the first line L1.

[0076] According to an embodiment, the first line L1 and the second line L2 may be formed in the same process. Accordingly, the first line L1 and the second line L2 may include the same material and may be disposed on the same layer. The first line L1 and the second line L2 may be disposed on the same layer (e.g., a pixel defining layer PDL (refer to Figure 3 ))). Each of the first line L1 and the second line L2 may be disposed on the surface of the pixel defining layer PDL.

[0077] Hereinafter, a display device DD including a line L will be described with reference to Figures 3 to 8 FIGs.

[0078] Figure 3 and Figure 4 are schematic cross-sectional views showing a display device according to an embodiment. Figure 3 and Figure 4 schematically show a display area DA including first to third sub-pixel areas SPXA1 to SPXA3. Figure 3 and Figure 4 are schematic cross-sectional views taken along line A-A' of Figure 2 FIG. Figure 5 is a schematic block diagram showing a connection structure of a sub-pixel including a light-emitting element according to an embodiment. For example, Figure 5 may show an electrical connection structure including a pixel circuit PXC corresponding to each of the sub-pixels SPX. Figure 6 is a schematic cross-sectional view showing a light-emitting element and a capping layer according to an embodiment. Figure 7 is a schematic block diagram showing a circuit path through which a cathode signal is supplied according to an embodiment. For example, Figure 7 may schematically show an electrical connection relationship between positions and structures based on the structure of the display area DA and the non-display area NDA. Figure 8 is a schematic cross-sectional view showing a thickness relationship between a second power line and a cathode electrode according to an embodiment.

[0079] Referring to Figure 3 and Figure 4 , the display device DD may include a pixel circuit layer PCL and a light-emitting element layer LEL.

[0080] The pixel circuit layer PCL may include a substrate layer BSL, a pixel circuit PXC, a first power line PL1, a second power line PL2, and a via layer VIA.

[0081] The base layer BSL can form a base, on which a pixel circuit PXC configured to drive a light-emitting element LD, a first power line PL1, and a second power line PL2 are provided. The pixel circuit PXC can be provided on the base layer BSL and can be configured to drive the light-emitting element LD. The pixel circuit layer PCL can include a conductive layer and an insulating layer, and the conductive layer can form the pixel circuit PXC, the first power line PL1, and the second power line PL2. The pixel circuit PXC can be included in the corresponding sub-pixel SPX.

[0082] The pixel circuit PXC can include one or more circuit elements. For example, the pixel circuit PXC can include three transistors and a storage capacitor. For example, the pixel circuit PXC can include a driving transistor, a switching transistor, and a storage capacitor. However, the present disclosure is not necessarily limited thereto.

[0083] The pixel circuit PXC can include: a first pixel circuit PXC1 configured to drive a first sub-pixel SPX1 and electrically connected to the light-emitting element LD of the first sub-pixel SPX1; a second pixel circuit PXC2 configured to drive a second sub-pixel SPX2 and electrically connected to the light-emitting element LD of the second sub-pixel SPX2; and a third pixel circuit PXC3 configured to drive a third sub-pixel SPX3 and electrically connected to the light-emitting element LD of the third sub-pixel SPX3.

[0084] Referring together Figure 5 , the pixel circuit PXC can be electrically connected to a scan line SL and a data line DL. The scan line SL can supply a scan signal to the pixel circuit PXC, and according to an embodiment, the scan line SL can be electrically connected to the gate electrode of the switching transistor of the pixel circuit PXC. The light-emitting element LD can be configured to emit light corresponding to a data signal provided from the data line DL.

[0085] The pixel circuit PXC can be electrically connected to the first power line PL1 and the second power line PL2. For example, the anode electrode AE of the light-emitting element LD can be electrically connected to the pixel circuit PXC and the first power line PL1, and the cathode electrode CE of the light-emitting element LD can be electrically connected to the second power line PL2. The first power line PL1 and the second power line PL2 can be provided on the base layer BSL.

[0086] The power of the first power line PL1 and the power of the second power line PL2 can have different potentials. For example, the power of the first power line PL1 can be a high-potential pixel power receiving a first voltage potential VDD (refer to Figure 5 ), and the power of the second power line PL2 can be a low-potential pixel power receiving a second voltage potential VSS (refer to Figure 7) low-potential pixel power. The potential difference between the power of the first power line PL1 and the power of the second power line PL2 can be set to be equal to or greater than the threshold voltage of the light-emitting element LD.

[0087] The first power line PL1 can be electrically connected to the pixel circuit PXC (e.g., the driving transistor). The second power line PL2 can be electrically connected to the cathode electrode CE of the light-emitting element LD.

[0088] Each light-emitting element LD can be electrically connected between the first power line PL1 and the second power line PL2 in the forward direction to form each effective light source. These effective light sources can be aggregated together to configure the light-emitting elements LD of the sub-pixel SPX.

[0089] The light-emitting element LD can emit light having a brightness corresponding to the driving current supplied through the pixel circuit PXC. During each frame period, the pixel circuit PXC can supply a driving current corresponding to the data signal to the light-emitting element LD. The light-emitting element LD can emit light having a brightness corresponding to the current flowing in the light-emitting element LD.

[0090] The first power line PL1 and the second power line PL2 can be patterned on the substrate layer BSL. According to an embodiment, the first power line PL1 can be patterned in the sub-pixel region SPXA and the region adjacent thereto. The second power line PL2 can be patterned in the sub-pixel region SPXA and the region adjacent thereto. For ease of description, multiple first power lines PL1 and multiple second power lines PL2 corresponding to each of the first sub-pixel SPX1 to the third sub-pixel SPX3 can be shown separately, but according to an embodiment, the multiple first power lines PL1 corresponding to each of the first sub-pixel SPX1 to the third sub-pixel SPX3 can be electrically connected to each other and can be integrally formed. The multiple second power lines PL2 corresponding to each of the first sub-pixel SPX1 to the third sub-pixel SPX3 can be electrically connected to each other and can be integrally formed.

[0091] According to an embodiment, the first power line PL1 and the second power line PL2 can include a conductive material. For example, the first power line PL1 and the second power line PL2 can include one or more of the group consisting of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt). However, the present disclosure is not limited thereto.

[0092] The first power line PL1 can be electrically connected to the pixel circuit PXC. The second power line PL2 can be electrically connected to the first line L1.

[0093] The via layer VIA may form an upper structure of the pixel circuit layer PCL. The via layer VIA may be a planarization layer. The via layer VIA may cover the pixel circuit PXC, the first power line PL1, and the second power line PL2.

[0094] At least a part of the contact member CNP that electrically connects the second power line PL2 and the cathode electrode CE may be formed in the via layer VIA. At least a part of the contact portion CNT that electrically connects the pixel circuit PXC and the anode electrode AE may be formed in the via layer VIA.

[0095] The via layer VIA may include an organic material. For example, the organic material may include one or more of the group consisting of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. However, the present disclosure is not limited thereto.

[0096] The light-emitting element layer LEL may be disposed on the pixel circuit layer PCL. According to an embodiment, the light-emitting element layer LEL may include a light-emitting element LD, a pixel defining layer PDL, a capping layer CPL, a line L, and a packaging layer TFE. According to an embodiment (refer to Figure 4 ), the light-emitting element layer LEL may further include a void VO.

[0097] The light-emitting element LD may include an organic light-emitting diode (OLED) including an organic material. However, the present disclosure is not limited thereto. According to an embodiment, the light-emitting element LD may be a quantum dot light-emitting element including an inorganic material.

[0098] Referring together to Figure 6 , the light-emitting element LD may include an anode electrode AE, a light-emitting portion EL, and a cathode electrode CE. The light-emitting element LD may include a first light-emitting element LD1 for forming a first sub-pixel SPX1, a second light-emitting element LD2 for forming a second sub-pixel SPX2, and a third light-emitting element LD3 for forming a third sub-pixel SPX3.

[0099] According to an embodiment, the first light-emitting element LD1 to the third light-emitting element LD3 may emit light of different colors. For example, the first light-emitting element LD1 may emit light of a first color. The second light-emitting element LD2 may emit light of a second color. The third light-emitting element LD3 may emit light of a third color.

[0100] The anode electrode AE may be disposed on the pixel circuit layer PCL (e.g., the via layer VIA). The anode electrode AE may be electrically connected to the pixel circuit PXC through the contact portion CNT. The anode electrode AE may include a first anode electrode AE1 electrically connected to the first pixel circuit PXC1, a second anode electrode AE2 electrically connected to the second pixel circuit PXC2, and a third anode electrode AE3 electrically connected to the third pixel circuit PXC3.

[0101] The anode electrode AE can include various conductive materials. For example, the anode electrode AE can include a transparent conductive material. For example, the anode electrode AE can include at least one of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). The anode electrode AE can include an opaque conductive material that can reflect light. For example, the anode electrode AE can include one or more of the group consisting of titanium nitride (TiN), silver (Ag), and aluminum (Al).

[0102] The light-emitting unit EL can be disposed on the anode electrode AE. The light-emitting unit EL can include a first light-emitting unit EL1 disposed on the first anode electrode AE1 and configured to form a first sub-pixel SPX1, a second light-emitting unit EL2 disposed on the second anode electrode AE2 and configured to form a second sub-pixel SPX2, and a third light-emitting unit EL3 disposed on the third anode electrode AE3 and configured to form a third sub-pixel SPX3.

[0103] The light-emitting unit EL can include a multilayer structure. The light-emitting unit EL can include a light-emitting layer EML configured to generate light, an electron transport region ETU configured to transport electrons, and a hole transport region HTU configured to transport holes. The light-emitting unit EL can include various organic materials, and according to an embodiment, the light-emitting unit EL can further include a metal-containing compound or an inorganic material (such as quantum dots), etc.

[0104] The hole transport region HTU can include a multilayer structure having multiple layers each including a different material. As an example, the hole transport region HTU can include at least one of a hole injection layer and a hole transport layer, and according to an embodiment, the hole transport region HTU can further include a light-emission assisting layer and an electron blocking layer, etc.

[0105] The hole injection layer can be a layer that performs or improves the hole injection function from the anode electrode AE to another adjacent organic layer. The hole transport layer can be a layer that supplies holes to the light-emitting layer EML. The light-emission assisting layer can be a layer that compensates for the resonance distance based on the wavelength of the light provided by the light-emitting layer EML. The electron blocking layer can be a layer that prevents electrons from being injected from the electron transport region ETU to reduce the number of carriers (e.g., holes or electrons) leaving the light-emitting layer EML. For example, the hole transport region HTU can have a multilayer structure such as a hole injection layer / hole transport layer, a hole injection layer / hole transport layer / light-emission assisting layer, a hole injection layer / light-emission assisting layer, a hole transport layer / light-emission assisting layer, an electron blocking layer / hole injection layer / hole transport layer, multiple hole transport layers or hole injection layers / hole transport layers / electron blocking layers that are sequentially disposed and include different materials. However, the present disclosure is not limited thereto.

[0106] According to an embodiment, the hole transport region HTU may include various hole transport organic materials. However, the present disclosure is not particularly limited thereto.

[0107] The emission layer EML may be disposed between the hole transport region HTU and the electron transport region ETU. The emission layer EML may include a material that can emit light of one color. The emission layer EML may include a host and a dopant. The host of the emission layer EML may be a light-emitting material that can capture carriers (electrons and holes) for light generation and can induce efficient exciton generation. The dopant may include a phosphorescent dopant or a fluorescent dopant. According to an embodiment, examples of the dopant may not be particularly limited. According to an embodiment, the dopant may include an organic material or may include a metal complex.

[0108] The electron transport region ETU may include a multi-layer structure having multiple layers each including a different material. The electron transport region ETU may include at least one of an electron injection layer and an electron transport layer, and according to an embodiment, the electron transport region ETU may further include an electron buffer layer, a hole blocking layer, and the like.

[0109] The electron injection layer may be a layer that performs or improves the electron injection function from the cathode electrode CE to another adjacent organic layer. The electron transport layer may be a layer that provides the supplied electrons to the emission layer EML. The hole blocking layer may be a layer that prevents holes from being injected from the hole transport region HTU to reduce the number of carriers leaving the emission layer EML.

[0110] For example, the electron transport region ETU may have a multi-layer structure such as an electron transport layer / electron injection layer, a hole blocking layer / electron transport layer / electron injection layer, an electron control layer / electron transport layer / electron injection layer, or an electron buffer layer / electron transport layer / electron injection layer. However, the present disclosure is not limited thereto.

[0111] According to an embodiment, the electron transport region ETU may include various electron transport compounds. For example, the electron transport region ETU may include a metal-free organic material, or may include a metal-containing organic material or various metal materials (e.g., alkaline earth metals and / or rare earth metals, etc.). However, the present disclosure is not limited thereto.

[0112] The cathode electrode CE may be disposed on the light-emitting portion EL, and at least a part of the cathode electrode CE may be disposed on the pixel defining layer PDL. According to an embodiment, the cathode electrode CE may be disposed in a region adjacent to the first line L1. The cathode electrode CE may cover the first line L1 and may not cover the second line L2. In a plan view, the cathode electrode CE may overlap with the first line L1 and may not overlap with the second line L2. According to an embodiment, the cathode electrode CE may be in contact with the first line L1. According to an embodiment, the cathode electrode CE may not be in contact with the second line L2.

[0113] The cathode electrode CE may contact the pixel defining layer PDL in a region adjacent to the first line L1. According to an embodiment, Joule heat may be formed through the first line L1, and thus the layer adjacent to the first line L1 may be removed. Thereafter, the cathode electrode CE may be formed, and thus the exposed pixel defining layer PDL and the cathode electrode CE may be directly adjacent to each other in the region adjacent to the first line L1.

[0114] The cathode electrode CE may be electrically connected to the first line L1. The first line L1 may be electrically connected to the second power line PL2 through the contact member CNP, and the cathode electrode CE may receive a cathode voltage through the first line L1. According to an embodiment, the contact member CNP may pass through the pixel defining layer PDL and the via layer VIA, and according to an embodiment, the contact member CNP may pass through the insulating layer(s) on the second power line PL2.

[0115] According to an embodiment, the cathode electrodes CE for each of the sub-pixels SPX may be spaced apart from each other. The cathode electrode CE may include a first cathode electrode CE1 included in the first sub-pixel SPX1 and electrically connected to the first light-emitting portion EL1, a second cathode electrode CE2 included in the second sub-pixel SPX2 and electrically connected to the second light-emitting portion EL2, and a third cathode electrode CE3 included in the third sub-pixel SPX3 and electrically connected to the third light-emitting portion EL3. According to an embodiment, the first cathode electrode CE1 to the third cathode electrode CE3 may be physically separated from each other.

[0116] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light-emitting portion EL. The cathode electrode CE may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. In an embodiment, the cathode electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, tin zinc oxide, or gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited thereto.

[0117] In each of the sub-pixels SPX, holes injected from the anode electrode AE and electrons injected from the cathode electrode CE can be transmitted to the light-emitting portion EL to form excitons, and light can be generated when the excitons can transition from the excited state to the ground state. The brightness of the light can be determined according to the amount of current flowing through the light-emitting portion EL. According to the structure of the light-emitting portion EL, the wavelength range of the generated light can be determined.

[0118] Since the cathode electrode CE has a relatively thin thickness, the cathode electrode CE can have a relatively high resistance. Experimentally, when a voltage is applied through a conductive structure with a high resistance, a voltage drop risk may occur, and thus it may be difficult to supply the expected electrical signal to the light-emitting element LD.

[0119] Refer together to Figure 7 and Figure 8 , the circuit path through which the cathode voltage can be supplied according to the embodiment can be defined so that the voltage drop risk can be reduced.

[0120] According to the embodiment, the cathode voltage can generally be supplied through the second power line PL2. The second power line PL2 generally has a thick thickness and can be electrically connected to the cathode electrode CE through the contact member CNP. The contact member CNP is in the area adjacent to the target cathode electrode CE, and the cathode voltage can be supplied to the cathode electrode CE.

[0121] The second power line PL2 can have a power thickness T_PL. The cathode electrode CE can have a cathode thickness T_CE. According to the embodiment, the cathode thickness T_CE can be thinner than the power thickness T_PL. For example, the power thickness T_PL can be in the range of to . The cathode thickness T_CE can be in the range of to . However, the present disclosure is not limited thereto. According to the embodiment, since the cathode thickness T_CE can be thinner than the power thickness T_PL, the cathode electrode CE can have a resistance greater than that of the second power line PL2.

[0122] The second power line PL2 may receive the second voltage potential VSS in the non-display area NDA. The second power line PL2 may be electrically connected to the cathode electrode CE in the display area DA. The first cathode electrode CE1 may be electrically connected to a part (e.g., the first part) of the second power line PL2 through the contact member CNP, the second cathode electrode CE2 may be electrically connected to another part (e.g., the second part) of the second power line PL2 through the contact member CNP, and the third cathode electrode CE3 may be electrically connected to yet another part (e.g., the third part) of the second power line PL2 through the contact member CNP. The contact member CNP may be disposed in the display area DA. In a plan view, the contact member CNP may overlap with the cathode electrode CE and may overlap with the second power line PL2.

[0123] Therefore, as described above, the path to which the cathode voltage can be applied can generally be defined in the second power line PL2 having a relatively small resistance, and the path to which the cathode voltage can be applied can be defined as a small part in the cathode electrode CE having a relatively large resistance. Ultimately, the risk of voltage drop of the cathode voltage can be substantially reduced.

[0124] The pixel defining layer PDL may cover at least a part of the anode electrode AE. The pixel defining layer PDL may overlap with at least a part of the anode electrode AE in a plan view. The pixel defining layer PDL may form an opening, and the anode electrode AE may be exposed in the opening.

[0125] The pixel defining layer PDL may form a substrate on which the line L can be provided. For example, the pixel defining layer PDL may be in contact with the line L.

[0126] The pixel defining layer PDL may include an inorganic material. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ). However, the present disclosure is not limited thereto.

[0127] The pixel defining layer PDL may include a multilayer structure. For example, the pixel defining layer PDL may include a multilayer structure in which layers containing silicon oxide (SiO x ) and layers containing silicon nitride (SiN x ) can be alternately provided.

[0128] The capping layer CPL may be disposed on the light-emitting element LD (e.g., the cathode electrode CE). The capping layer CPL may passivate the first light-emitting element LD1 to the third light-emitting element LD3.

[0129] The capping layer CPL may include a first capping layer CPL1 and a second capping layer CPL2. The first capping layer CPL1 and the second capping layer CPL2 may include an inorganic material. For example, the first capping layer CPL1 and the second capping layer CPL2 may independently include one or more selected from the group consisting of silicon nitride (SiN x ), aluminum nitride (AlN x ), titanium nitride (TiN x ), silicon oxide (SiO x ), aluminum oxide (Al x O y ), titanium oxide (TiO x ), silicon oxycarbide (SiO x C y ), and silicon oxynitride (SiO x N y ). However, the present disclosure is not limited thereto.

[0130] The first capping layer CPL1 may be disposed on each of the first light-emitting element LD1 to the third light-emitting element LD3. The first capping layer CPL1 may passivate each of the first light-emitting element LD1 to the third light-emitting element LD3 in the process of sequentially manufacturing the first light-emitting element LD1 to the third light-emitting element LD3 to reduce the risk of occurrence of defects. The first capping layer CPL1 may cover the first line L1 and may not cover the second line L2. In a plan view, the first capping layer CPL1 may overlap with the first line L1 and may not overlap with the second line L2.

[0131] The second capping layer CPL2 may be disposed on each of the first light-emitting element LD1 to the third light-emitting element LD3 and may be further disposed outside each of the first light-emitting element LD1 to the third light-emitting element LD3. The second capping layer CPL2 may cover the first line L1 and the second line L2. According to an embodiment, the second capping layer CPL2 may be directly adjacent to the second line L2. The second capping layer CPL2 may cover the light-emitting portion EL, the cathode electrode CE, and the side surfaces of the first capping layer CPL1.

[0132] The second capping layer CPL2 may seal the light-emitting element LD and reduce risks such as moisture penetration. The second capping layer CPL2 may physically contact the pixel defining layer PDL in a region adjacent to the second line L2. Joule heat may be formed through the second line L2, and thus the layer adjacent to the second line L2 may be removed. Thereafter, the second capping layer CPL2 may be formed, and thus the exposed pixel defining layer PDL and the second capping layer CPL2 may be directly adjacent to each other within the region adjacent to the second line L2.

[0133] As described above, since the second capping layer CPL2 may include an inorganic material and the pixel defining layer PDL may include an inorganic material, the inorganic material and the inorganic material may be directly adjacent to each other, and thus an inorganic encapsulation structure may be formed around the light-emitting element LD. The inorganic encapsulation structure may prevent moisture penetration problems that may occur in the light-emitting element LD, and thus may improve the lifespan and element characteristics of the light-emitting element LD.

[0134] The line L may be disposed on the pixel defining layer PDL. According to an embodiment, the line L may be directly adjacent to the pixel defining layer PDL. Each of the first line L1 and the second line L2 may be disposed adjacent to the first sub-pixel region SPXA1 to the third sub-pixel region SPXA3.

[0135] The line L may be a resistive conductive structure that forms Joule heat. According to an embodiment, when a pulsed voltage is supplied to the line L, heat may be applied to the region adjacent to the line L. The applied heat may remove at least a portion of the layer (e.g., a layer including an organic material) disposed around the line L. According to an embodiment, the magnitude of the voltage supplied to the line L and the time in the case of supplying the voltage may be adjusted, and thus the amount of the layer disposed around the line L that can be removed may be adjusted.

[0136] According to an embodiment, the line L may include a conductive material having resistance. The line L may include a metal material suitable for forming Joule heat. For example, the line L may include a conductive material having a conductivity of less than about 4.0×10 7 (S / m) (Siemens per meter) at about 20°C. Thus, the line L may have characteristics suitable for forming Joule heat. For example, the line L may include aluminum (Al), and the line L may include molybdenum (Mo). According to an embodiment, since the range in which Joule heat can diffuse can be adjusted based on the intensity of the voltage supplied to the line L and the voltage supply time, a display device DD with high-resolution display quality can be provided even when the structure of the display device DD (e.g., the sub-pixel SPX) can be miniaturized.

[0137] Since the line L may form Joule heat in the manufacturing process of the display device DD, the line L may expose the pixel defining layer PDL in the region adjacent to the line L. The cathode electrode CE may be disposed on the first line L1. The second capping layer CPL2 may be disposed on the second line L2.

[0138] As described above, since the first line L1 may form a closed-loop structure, the light-emitting portion EL may be disposed in the region surrounded by the first line L1 and may include an edge portion on the inner side of the first line L1. Since the second line L2 may form a closed-loop structure, the light-emitting element LD may be disposed in the region surrounded by the second line L2 and may include an edge portion on the inner side of the second line L2.

[0139] The first line L1 may include a first (1-1) line portion (also referred to as the (1-1) line) L1-1 and a first (1-2) line portion (also referred to as the (1-2) line) L1-2. The second line L2 may include a second (2-1) line portion (also referred to as the (2-1) line) L2-1 and a second (2-2) line portion (also referred to as the (2-2) line) L2-2. The first (1-1) line portion L1-1 may be disposed on a first side of the light-emitting portion EL, and may be disposed between the second (2-1) line portion L2-1 and the light-emitting portion EL. The first (1-2) line portion L1-2 may be disposed on a second side of the light-emitting portion EL, and may be disposed between the second (2-2) line portion L2-2 and the light-emitting portion EL.

[0140] According to an embodiment (refer to Figure 3 ), a void VO may be further formed in a region adjacent to the second line L2. The void VO may be disposed between the first line L1 and the second line L2. The void VO may be directly formed on the pixel defining layer PDL. The void VO may be surrounded by a layer formed in the same process as the cathode electrode CE, the first capping layer CPL1, and the light-emitting portion EL. The void VO may be an air gap.

[0141] The encapsulation layer TFE may be disposed on the light-emitting element LD and the capping layer CPL. The encapsulation layer TFE may remove a step formed by the light-emitting element LD. The encapsulation layer TFE may form an outer layer of the light-emitting element layer LEL.

[0142] The encapsulation layer TFE may include a multi-layer structure. For example, the encapsulation layer TFE may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. According to an embodiment, the first encapsulation layer TFE1 may include an inorganic material, the second encapsulation layer TFE2 may include an organic material, and the third encapsulation layer TFE3 may include an inorganic material. However, the present disclosure is not limited thereto.

[0143] Refer to Figures 9 to 25 , and a method of manufacturing a display device DD according to an embodiment is described. Briefly describe or do not repeat the content that may be repeated with the above.

[0144] Figure 9 is a flowchart showing a method of manufacturing a display device according to an embodiment. Figure 10 is a flowchart showing steps of manufacturing a light-emitting element layer according to an embodiment. Figure 11 is a flowchart of a step of patterning sub-pixels.

[0145] Figures 12 to 25 is a schematic cross-sectional view of each process step of a method of manufacturing a display device according to an embodiment. For convenience of description, Figure 12 、 Figure 13 、Figure 24 and Figure 25 shows a schematic cross-sectional structure (e.g., a partial cross-sectional structure of the display area DA), and Figures 14 to 23 shows a schematic cross-sectional structure based on the first sub-pixel SPX1 among the sub-pixels SPX. According to an embodiment, Figure 19 、 Figure 21 and Figure 23 show an embodiment in which the display device DD described above with reference to Figure 4 includes a void VO.

[0146] Referring to Figure 9 , a method of manufacturing a display device according to an embodiment may include manufacturing a pixel circuit layer (S100) and manufacturing a light-emitting element layer (S200).

[0147] Referring to Figure 10 , manufacturing the light-emitting element layer (S200) may include forming an anode electrode, a pixel defining layer and a line (S220), patterning a layer for defining a first sub-pixel (S240), patterning a layer for defining a second sub-pixel (S260), patterning a layer for defining a third sub-pixel (S280), and forming a encapsulation layer (S290).

[0148] Referring to Figure 11 , patterning the layer for defining the first sub-pixel (S240) may include forming a matrix light-emitting portion (S2410), removing at least a part of the layer adjacent to the first line (S2420), forming a matrix cathode electrode and a first matrix capping layer (S2430), removing at least a part of the layer adjacent to the second line (S2440), forming a second matrix capping layer (S2450), and removing at least a part of the layer disposed outside the second line (S2460).

[0149] Referring to Figure 9 and Figure 12 , in manufacturing the pixel circuit layer (S100), the layer for forming the pixel circuit layer PCL on the substrate layer BSL may be patterned.

[0150] In step S100, the pixel circuit PXC, the first power line PL1 and the second power line PL2 may be patterned on the substrate layer BSL, and a via layer VIA may be formed on the pixel circuit PXC, the first power line PL1 and the second power line PL2.

[0151] In step S100, the first power line PL1 and the pixel circuit PXC may be electrically connected, and according to an embodiment, a contact hole may be formed to expose the second power line PL2 and for forming a contact member CNP in a subsequent process.

[0152] According to an embodiment, a conductive layer or an insulating layer on the substrate layer BSL may be formed based on typical processes for manufacturing a semiconductor device. For example, a conductive layer or an insulating layer on the substrate layer BSL may be formed by a photolithography process, may be etched by various methods (such as wet etching and dry etching), and may be deposited by various methods (such as sputtering and chemical vapor deposition). The present disclosure is not necessarily limited to specific examples.

[0153] Referring to Figure 9 , Figure 10 , Figure 13 and Figure 14 , in forming the anode electrode, the pixel defining layer, and the lines (S220), the anode electrode AE may be patterned on the pixel circuit layer PCL (e.g., the substrate layer BSL and the via layer VIA), the pixel defining layer PDL may be patterned adjacent to the anode electrode AE, and the lines L may be formed on the pixel defining layer PDL.

[0154] In step S220, the first anode electrode AE1 to the third anode electrode AE3 may be patterned in regions corresponding to the first sub-pixel region SPXA1 to the third sub-pixel region SPXA3 to be formed. The first anode electrode AE1 to the third anode electrode AE3 may be electrically connected to the first pixel circuit PXC1 to the third pixel circuit PXC3 respectively through contact portions CNT passing through the via layer VIA.

[0155] In step S220, the pixel defining layer PDL may be patterned to overlap regions adjacent to the first sub-pixel region SPXA1 to the third sub-pixel region SPXA3, may be patterned to cover the first anode electrode AE1 to the third anode electrode AE3, and may be patterned to expose at least a part of the first anode electrode AE1 to the third anode electrode AE3.

[0156] In step S220, the lines L may be patterned on the pixel defining layer PDL, and thus the first line L1 and the second line L2 spaced apart from each other may be provided. For example, the (1-1) line L1-1, the (1-2) line L1-2, the (2-1) line L2-1, and the (2-2) line L2-2 may be formed in a region adjacent to the first sub-pixel region SPXA1, the (1-1) line L1-1, the (1-2) line L1-2, the (2-1) line L2-1, and the (2-2) line L2-2 may be formed in a region adjacent to the second sub-pixel region SPXA2, and the (1-1) line L1-1, the (1-2) line L1-2, the (2-1) line L2-1, and the (2-2) line L2-2 may be formed in a region adjacent to the third sub-pixel region SPXA3.

[0157] In step S220, a contact member CNP at least a part of which passes through the pixel defining layer PDL may be formed, and at least a part of the first line L1 may be electrically connected to the second power line PL2. For example, the (1-2)th line L1-2 adjacent to one side of each of the sub-pixel regions SPXA may be electrically connected to the second power line PL2 through the contact member CNP. However, the part of the first line L1 that is electrically connected to the contact member CNP is not limited to the (1-2)th line L1-2, and according to an embodiment, the contact member CNP may be electrically connected to at least another part of the first line L1.

[0158] The first light-emitting unit EL1 to the third light-emitting unit EL3 according to an embodiment may be manufactured without using a fine metal mask (FMM). According to an embodiment, the first light-emitting unit EL1 to the third light-emitting unit EL3 may be structures included in each of the sub-pixels SPX for emitting lights of different colors, and it may be necessary to space apart the first light-emitting unit EL1 to the third light-emitting unit EL3 adjacent to each other. According to an embodiment, the first light-emitting unit EL1 to the third light-emitting unit EL3 may be separately provided from each other by using Joule heat generated by the lines L.

[0159] According to an embodiment, after forming the anode electrode, the pixel defining layer, and the lines (S220), the layers for forming the sub-pixels SPX may be sequentially formed. Hereinafter, for ease of description, a process of forming the formation layers of the sub-pixels SPX in the order of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be described. However, the present disclosure is not limited thereto.

[0160] Referring to Figures 9 to 11 and Figure 15 , in patterning the layer for defining the first sub-pixel (S240), forming a base light-emitting unit (S2410) may be performed.

[0161] In step S2410, a base light-emitting unit EL1_B may be formed in the display area DA (referring to Figure 1 ). The base light-emitting unit EL1_B may be formed without using a fine metal mask. For example, the base light-emitting unit EL1_B may be deposited as a whole (i.e., blanket deposition without being patterned) on the pixel circuit layer PCL. The base light-emitting unit EL1_B may cover the exposed anode electrode AE (e.g., the first anode electrode AE1), and may cover the lines L. For example, the base light-emitting unit EL1_B may cover the first line L1 and the second line L2. The base light-emitting unit EL1_B may cover the pixel defining layer PDL, and the pixel defining layer PDL may not be exposed.

[0162] Referring to Figures 9 to 11 and Figure 16, in the layer (S240) patterned to define the first sub-pixel, at least a part of the layer adjacent to the first line may be removed (S2420). The layer adjacent to the first line L1 removed in step S2420 may include the matrix light-emitting portion EL1_B (refer to Figure 15 ), and after step S2420 can be performed, the layer adjacent to the first line L1 may include the remaining light-emitting portion EL1_R.

[0163] Step S2420 may be a step of separating the light-emitting portion EL (refer to Figure 4 ) for emitting light of one color from the light-emitting portion EL for emitting light of another color. When step S2420 is performed, the light-emitting portion EL may be divided for each of the sub-pixels SPX (refer to Figure 13 ), leakage current can be prevented, and the risk of emitting color light in a color different from the expected color can be prevented. Since the light-emitting portion EL can be divided for each of the sub-pixels SPX using Joule heat, an additional separation structure may not be required, and the convenience of the manufacturing process can be improved.

[0164] In step S2420, a first voltage may be supplied to the first line L1 (e.g., the (1-1)th line L1-1 and the (1-2)th line L1-2), and the first line L1 may generate Joule heat. For example, a pulse input of the voltage may be provided to the first line L1, and thermal energy may be applied to the region adjacent to the first line L1. The numerical range of the first voltage and the input method by which the first voltage can be provided are not limited to specific examples.

[0165] In step S2420, the portion of the pixel defining layer PDL adjacent to the first line L1 may be exposed. For example, due to the heat generated by the first line L1, a part of the matrix light-emitting portion EL1_B may be removed, and thus a first opening OP1 exposing the pixel defining layer PDL may be formed.

[0166] Referring together to Figure 2 , since the first line L1 may have a closed-loop shape surrounding the region, the first opening OP1 may also have a closed-loop shape surrounding the region.

[0167] In step S2420, at least a part of the base light-emitting portion EL1_B can be removed, and the first light-emitting portion EL1 and the remaining light-emitting portion EL1_R can be provided (or patterned). For example, a part of the base light-emitting portion EL1_B adjacent to the first line L1 can be removed, and the first light-emitting portion EL1 and the remaining light-emitting portion EL1_R spaced apart from each other can be formed. Accordingly, the first light-emitting portion EL1 can be disposed in the region surrounded by the first line L1, and the remaining light-emitting portion EL1_R can be disposed outside the first line L1. By performing step S2420, the first light-emitting portion EL1 that can be separately provided in the region where the first sub-pixel region SPXA1 is to be formed can be manufactured.

[0168] In the case of performing step S2420, the second line L2 can be covered by the remaining light-emitting portion EL1_R and can not be exposed.

[0169] Referring to Figures 9 to 11 and Figure 17 , in patterning the layer for defining the first sub-pixel (S240), forming the base cathode electrode and the first base capping layer (S2430) can be performed.

[0170] In step S2430, the base cathode electrode CE_B and the first base capping layer CPL1_B can be formed in the display area DA (refer to Figure 1 ). For example, the base cathode electrode CE_B and the first base capping layer CPL1_B can be deposited integrally.

[0171] In step S2430, the base cathode electrode CE_B can cover the first line L1 and can be electrically connected to the first line L1. The base cathode electrode CE_B can be physically in contact with the first line L1. Accordingly, the base cathode electrode CE_B can be electrically connected to the second power line PL2 through the first line L1 and the contact member CNP. At least a part of the base cathode electrode CE_B can fill the first opening OP1 (refer to Figure 16 ), can contact the pixel defining layer PDL in the region corresponding to the first opening OP1, and can cover the first light-emitting portion EL1 and the remaining light-emitting portion EL1_R.

[0172] In step S2430, the first base capping layer CPL1_B can cover the base cathode electrode CE_B. The first base capping layer CPL1_B can passivate the base cathode electrode CE_B and the layer thereunder.

[0173] Referring to Figures 9 to 11 , Figure 18 and Figure 19, in the layer (S240) patterned to define the first sub-pixel, at least a part of the layer adjacent to the second line may be removed (S2440). The layer adjacent to the second line L2 removed in step S2440 may include a remaining light-emitting portion EL1_R, a part of the base cathode electrode CE_B (refer to Figure 17 ), and a part of the first base capping layer CPL1_B (refer to Figure 17 ).

[0174] In step S2440, a second voltage may be supplied to the second line L2 (e.g., the (2-1)th line L2-1 and the (2-2)th line L2-2), and the second line L2 may generate Joule heat. For example, a pulsed input of voltage may be provided to the second line L2, and thermal energy may be applied to the region adjacent to the second line L2. The numerical range of the second voltage and the input method by which the second voltage may be provided are not limited to specific examples.

[0175] According to an embodiment, the second voltage may be different from the first voltage supplied to the first line L1 described above. For example, as the second voltage increases, the size of the second opening OP2 may increase. The size of the second opening OP2 may correspond to the range in which an inorganic encapsulation structure may be formed. Therefore, the range in which an inorganic encapsulation structure may be formed may be controlled based on the magnitude of the second voltage.

[0176] In step S2440, a part of the pixel defining layer PDL adjacent to the second line L2 may be exposed. For example, due to the heat generated by the second line L2, a part of the remaining light-emitting portion EL1_R, a part of the base cathode electrode CE_B, and a part of the first base capping layer CPL1_B may be removed, and thus a second opening OP2 exposing the pixel defining layer PDL may be formed. The size of the second opening OP2 may be determined based on the intensity of the voltage applied to the second line L2 and the time in the case where voltage may be applied, etc.

[0177] Referring together to Figure 2 , since the second line L2 may have a closed-loop shape surrounding the region, the second opening OP2 may also have a closed-loop shape surrounding the region.

[0178] In step S2440, at least a portion of the base cathode electrode CE_B can be removed, and a first cathode electrode CE1 and a remaining cathode electrode CE_R can be provided. For example, a portion of the base cathode electrode CE_B adjacent to the second line L2 can be removed, the first cathode electrode CE1 can be disposed within the region surrounded by the second line L2, and the remaining cathode electrode CE_R can be disposed outside the second line L2. By performing step S2440, the first cathode electrode CE1 for forming the first sub-pixel SPX1 can be fabricated. As described above, since the base cathode electrode CE_B can be electrically connected to the first line L1, the first cathode electrode CE1 that is electrically connected to the second power line PL2 through the contact member CNP in the display area DA can be provided.

[0179] In step S2440, at least a portion of the first base capping layer CPL1_B can be removed, and a first capping layer CPL1 and a remaining capping layer CPL1_R can be provided. For example, a portion of the first base capping layer CPL1_B adjacent to the second line L2 can be removed, the first capping layer CPL1 can be disposed within the region surrounded by the second line L2, and the remaining capping layer CPL1_R can be disposed outside the second line L2.

[0180] In step S2440, according to an embodiment (refer to Figure 19 ), compared with the base cathode electrode CE_B and the first base capping layer CPL1_B, the remaining light-emitting portion EL1_R can be further etched, and compared with the cathode electrode CE and the first base capping layer CPL1_B, the first light-emitting portion EL1 can be further etched, and thus a void VO can be formed. For example, the remaining light-emitting portion EL1_R can be formed deeper than the base cathode electrode CE_B and the first base capping layer CPL1_B, and a void VO can be formed under the remaining cathode electrode CE_R and the remaining capping layer CPL1_R. The first light-emitting portion EL1 can be formed deeper than the cathode electrode CE and the first base capping layer CPL1_B, and a void VO can be formed under the cathode electrode CE and the first capping layer CPL1. Therefore, the void VO can overlap with the remaining cathode electrode CE_R and the remaining capping layer CPL1_R in a plan view, and the void VO can overlap with the cathode electrode CE and the first capping layer CPL1 in a plan view.

[0181] Refer to Figures 9 to 11 、 Figure 20 and Figure 21 , in patterning the layer for defining the first sub-pixel (S240), forming the second base capping layer (S2450) can be performed.

[0182] In step S2450, in the display area DA (refer to Figure 1) A second substrate capping layer CPL2_B is formed. The second substrate capping layer CPL2_B can be deposited integrally.

[0183] In step S2450, the second substrate capping layer CPL2_B can cover the remaining capping layer CPL1_R, the second line L2, and the first capping layer CPL1. The second substrate capping layer CPL2_B can passivate the layers disposed below the second substrate capping layer CPL2_B.

[0184] In step S2450, according to an embodiment (refer to Figure 21 ), the second substrate capping layer CPL2_B can be formed directly adjacent to the void VO. For example, the second substrate capping layer CPL2_B can cover one side of the void VO. Thus, one or more layers can surround the void VO.

[0185] In step S2450, the second substrate capping layer CPL2_B can contact the pixel defining layer PDL in the region corresponding to the second opening OP2, and thus an inorganic encapsulation structure can be formed.

[0186] Refer to Figures 9 to 11 、 Figure 22 and Figure 23 , in patterning the layer for defining the first sub-pixel (S240), at least a part of the layer disposed outside the second line can be removed (S2460), and thus the first sub-pixel SPX1 can be provided. The layer disposed outside the second line L2 removed in step S2460 can include a part of the remaining light-emitting portion EL1_R (refer to Figure 18 ), a part of the remaining cathode electrode CE_R (refer to Figure 21 ), and a part of the remaining capping layer CPL1_R (refer to Figure 21 ).

[0187] In step S2460, an external region RA exposing a part of the pixel defining layer PDL can be formed outside the second line L2. For example, the layer disposed outside the second line L2 can be etched, and the first capping layer CPL1 and the second capping layer CPL2 can passivate the layers disposed below the first capping layer CPL1 (e.g., the first light-emitting element LD1 (refer to Figure 7 )). According to an embodiment, the second capping layer CPL2 can cover the outer surface of the second line L2.

[0188] In step S2460, at least a part of the second capping layer CPL2 adjacent to the second line L2 can not be removed. As described above, the second capping layer CPL2 and the pixel defining layer PDL can contact each other to form an inorganic encapsulation structure. In step S2460, the amount of the second substrate capping layer CPL2_B that can be removed can be adjusted (refer to Figure 21) range, and thus the inorganic encapsulation structure can be maintained.

[0189] In step S2460, among the layers for forming the first sub-pixel SPX1, the portions formed in the second sub-pixel region SPXA2 (refer to Figure 13 ) and the third sub-pixel region SPXA3 (refer to Figure 13 ) can be removed.

[0190] In step S2460, according to the embodiment (refer to Figure 23 ), a part of the void VO adjacent to the remaining cathode electrode CE_R and the remaining capping layer CPL1_R can be removed, and another part of the void VO adjacent to the cathode electrode CE and the first capping layer CPL1 can be not removed.

[0191] Refer to Figure 9 、 Figure 10 and Figure 24 , patterning the layer for defining the second sub-pixel (S260) and patterning the layer for defining the third sub-pixel (S280) can be performed, and the second sub-pixel SPX2 and the third sub-pixel SPX3 can be provided. Figure 24 It is also shown that the layer for the first sub-pixel SPX1 is provided by performing the step S240 of patterning the layer for defining the first sub-pixel.

[0192] According to the embodiment, patterning the layer for defining the second sub-pixel (S260) can be performed in a similar (e.g., substantially equivalent) manner to the above-described patterning the layer for defining the first sub-pixel (S240). For example, the cathode connection structure for the second sub-pixel SPX2 can be formed using the first line L1, the second light-emitting portion EL2 can be separated from other light-emitting portions EL using the first line L1, and the inorganic-inorganic bonding structure can be formed using the second line L2.

[0193] According to the embodiment, patterning the layer for defining the third sub-pixel (S280) can be performed in a similar (e.g., substantially equivalent) manner to the above-described patterning the layer for defining the first sub-pixel (S240). For example, the cathode connection structure for the third sub-pixel SPX3 can be formed using the first line L1, the third light-emitting portion EL3 can be separated from other light-emitting portions EL using the first line L1, and the inorganic-inorganic bonding structure can be formed using the second line L2.

[0194] Refer to Figure 9 、 Figure 10 and Figure 25 , in forming the encapsulation layer (S290), the encapsulation layer TFE can be formed to cover the first sub-pixel region SPXA1 to the third sub-pixel region SPXA3.

[0195] In step S290, the encapsulation layer TFE may be deposited integrally, may cover the first light-emitting element LD1 to the third light-emitting element LD3, and may cover the capping layer CPL.

[0196] According to an embodiment, the first encapsulation layer TFE1 to the third encapsulation layer TFE3 may be formed (e.g., deposited) sequentially to form the encapsulation layer TFE.

[0197] According to an embodiment, the light-emitting element LD may be protected by the pixel defining layer PDL and the second capping layer CPL2 that form an inorganic encapsulation structure, and may be further protected by the encapsulation layer TFE.

[0198] According to an alternative embodiment, an additional structure (e.g., a window, etc.) may be further formed on the encapsulation layer TFE, and a display device DD (refer to Figure 1 ) may be provided according to an embodiment.

[0199] As described above, although the present disclosure has been described with reference to the above embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that the present disclosure can be variously modified and changed without departing from the spirit and technical scope of the present disclosure described in the appended claims.

[0200] Therefore, the technical scope of the present disclosure should not be limited to the content described in the detailed description of the specification, but should be defined by the claims.

Claims

1. A display device comprising a sub-pixel region, wherein: The display device comprises: a pixel circuit layer, comprising a base layer and a pixel circuit disposed on the base layer; and A light emitting element layer is disposed on the pixel circuit layer, and the light emitting element layer includes a light emitting element, a pixel defining layer, a capping layer, and a line electrically connected to the pixel circuit, wherein: The light emitting element includes an anode electrode, a cathode electrode and a light emitting portion. At least a portion of the light emitting portion is disposed between the anode electrode and the cathode electrode, The pixel defining layer covers at least a portion of the anode electrode, At least a portion of the capping layer is in contact with the pixel defining layer, The lines are disposed on the pixel defining layer, and the lines include first lines and second lines spaced apart from each other, Each of the first line and the second line is arranged in a closed loop, The first line surrounds the sub-pixel region in a plan view, the second line surrounds the first line in a plan view, and The light emitting section is provided in a region surrounded by the first line.

2. The display device according to claim 1, wherein: The wire includes a layer having a temperature of less than 4.0×10 7 Conductive material with electrical conductivity in Siemens per meter.

3. The display device according to claim 2, wherein: The wire includes aluminum or molybdenum.

4. The display device according to claim 1, wherein: The first wire and the second wire include the same material, and Each of the first line and the second line is disposed on a surface of the pixel defining layer.

5. The display device according to claim 1, wherein: The first line is arranged around the sub-pixel area, The second line is arranged around the first line, The sub-pixel region includes a first sub-pixel region, a second sub-pixel region and a third sub-pixel region, and The first line includes a first line portion surrounding the first sub-pixel region, a second line portion surrounding the second sub-pixel region, and a third line portion surrounding the third sub-pixel region.

6. The display device according to claim 5, wherein: The cathode electrode includes a first cathode electrode overlapping the first sub-pixel region, a second cathode electrode overlapping the second sub-pixel region, and a third cathode electrode overlapping the third sub-pixel region, and The first cathode electrode, the second cathode electrode, and the third cathode electrode are physically separated from each other.

7. The display device according to claim 1, wherein: The pixel circuit layer includes a first power line and a second power line with different potentials. The first power line is electrically connected to the pixel circuit, and The second power line is electrically connected to the cathode electrode through the first line.

8. The display device according to claim 7, wherein: The display device further comprises: A display area and a non-display area surrounding at least a portion of the display area, wherein The first line is electrically connected to the second power line through a contact member at least partially passing through the pixel defining layer, The second power line has a thickness greater than that of the cathode electrode, and The contact member is disposed in the display area.

9. The display device according to claim 1, wherein: The capping layer comprises a first capping layer and a second capping layer disposed on the first capping layer, The first capping layer covers the first line and does not cover the second line, and The second capping layer covers the second line.

10. The display device according to claim 9, wherein: Each of the second capping layer and the pixel defining layer includes an inorganic material, and The second capping layer and the pixel defining layer contact each other in a region adjacent to the second line.

11. A display device, wherein: The display device comprises: a display area and a non-display area surrounding at least a portion of the display area; a pixel circuit layer, comprising a substrate layer, a pixel circuit, a power line disposed on the substrate layer, and a via layer covering the power line; and A light emitting element layer is disposed on the pixel circuit layer, and the light emitting element layer includes a light emitting element, a pixel defining layer and a line electrically connected to the pixel circuit, wherein: The light emitting element includes an anode electrode, a cathode electrode and a light emitting portion. At least a portion of the light emitting portion is disposed between the anode electrode and the cathode electrode, The pixel defining layer overlaps with the anode electrode in a plan view, The lines are directly disposed on the pixel defining layer, and the lines include first lines and second lines spaced apart from each other, The power lines are arranged across the display area and the non-display area, The cathode electrode and the power line are electrically connected in the display area through a contact member passing through the via layer, and The electric force lines have a thickness greater than a thickness of the cathode electrode.

12. A method for manufacturing a display device, wherein: The method comprises: manufacturing a pixel circuit layer; and A light emitting element layer is manufactured, wherein the light emitting element layer is disposed on the pixel circuit layer, and the light emitting element layer includes a light emitting element, wherein: The manufacturing of the light emitting element layer comprises: forming an anode electrode, a pixel defining layer, and a line on the pixel circuit layer; and Sub-pixels are formed by patterning multiple layers around the line, The line is disposed on the pixel defining layer and includes a first line and a second line spaced apart from each other, and the first line is disposed closer to the anode electrode than the second line, and The patterning of the plurality of layers about the line comprises: forming a substrate light emitting portion; removing at least a portion of the base light emitting portion adjacent to the first line by supplying a first voltage to the first line; forming a substrate cathode electrode and a first substrate capping layer; and At least a portion of the base cathode electrode, at least a portion of the first base capping layer, and at least a portion of the base light emitting portion adjacent to the second line are removed by supplying a second voltage to the second line.

13. The method according to claim 12, wherein: The pixel circuit layer comprises: Pixel circuit; a first power line electrically connected to the pixel circuit; and A second power line has a potential different from that of the first power line, and forming the line includes electrically connecting the first line to the second power line.

14. The method according to claim 13, wherein: The forming of the base light emitting portion includes depositing the base light emitting portion integrally on the pixel circuit layer.

15. The method according to claim 12, wherein: The removing of the at least a portion of the base light emitting portion adjacent to the first line includes providing the first light emitting portion disposed in a region surrounded by the first line.

16. The method according to claim 12, wherein: The forming of the substrate cathode electrode comprises: electrically connecting the substrate cathode electrode to the first line; and The base cathode electrode is brought into contact with the pixel defining layer in a region adjacent to the first line.

17. The method according to claim 12, wherein: The removing of the at least a portion of the base light emitting portion adjacent to the first line comprises forming a first opening exposing at least a portion of the pixel defining layer, and The removing of the at least a portion of the substrate cathode electrode, the at least a portion of the first substrate capping layer, and the at least a portion of the substrate light emitting portion adjacent to the second line includes forming a second opening exposing at least a portion of the pixel defining layer.

18. The method according to claim 12, wherein: The method further comprises: forming a second base capping layer; and At least a portion of the first substrate capping layer, at least a portion of the substrate cathode electrode, and at least a portion of the substrate light emitting portion disposed outside the second line are removed.

19. The method according to claim 18, wherein: The second base capping layer contacts the pixel defining layer in a region adjacent to the second line, and Each of the second base capping layer and the pixel defining layer includes an inorganic material.

20. The method according to claim 12, wherein: The method further comprises: An encapsulation layer is deposited integrally on the pixel circuit layer.

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