Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes an anode electrode on a light emitting region of a substrate; a light emitting layer on the anode electrode; a first pixel defining layer on the non-emission area of the substrate, the first pixel defining layer including a first side oriented toward the emission area; a bank layer on the first pixel defining layer, the bank layer including an end portion protruding more than a first side of the first pixel defining layer toward the light emitting region; a residual pattern overlapping the non-emission region and disposed between the anode electrode and the first pixel defining layer; a cathode electrode on the light emitting layer and the bank layer; and an encapsulation layer on the cathode electrode. The first pixel defining layer and the bank layer are entirely covered by the cathode electrode, and an entire first side of the first pixel defining layer physically contacts the cathode electrode.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0186631, filed with the Korean Intellectual Property Office on December 20, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0004] As the information age has advanced, the demand for display devices for displaying images has increased in various forms. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigators, and smart televisions. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among flat panel display devices, a self-emitting display device includes light emitting elements in which each of a plurality of pixels of a display panel can emit light by itself, so that an image can be displayed even without a backlight unit for providing light to the display panel.

[0005] Recently, with the development of various electronic devices, the demand for high-resolution display devices has been increasing. In the case of a high-resolution display device, since high pixel integration is involved, the interval between light emitting elements overlapping each light emitting region may become narrow. Therefore, a high-resolution display device can be formed by a patterning process for forming a single pixel rather than a mask process.

[0006] It should be understood that this background art of the technical part is partly intended to provide a useful background for understanding the technology. However, this background art of the technical part may also include concepts, ideas, or understandings that were not known or understood by those skilled in the relevant art before the effective filing date of the corresponding application of the subject matter disclosed herein. Summary of the Invention

[0007] An aspect of the present disclosure is to provide a display device in which a light emitting element is formed by a light patterning process without a fine metal mask to provide high resolution and to solve contact defects (separable defects) and moisture penetration defects between a bank structure and a cathode electrode.

[0008] Aspects of the present disclosure are not limited to those mentioned above, and additional aspects of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0009] According to an aspect of the present disclosure, a display device may include: a substrate including a light-emitting region and a non-light-emitting region; an anode electrode on the light-emitting region of the substrate; a light-emitting layer on the anode electrode; a first pixel defining layer on the non-light-emitting region of the substrate, the first pixel defining layer including a first side oriented toward the light-emitting region; a bank layer on the first pixel defining layer, the bank layer including an end portion protruding toward the light-emitting region more than the first side of the first pixel defining layer; a residual pattern overlapping with the non-light-emitting region and disposed between the anode electrode and the first pixel defining layer in a direction perpendicular to the substrate; a cathode electrode on the light-emitting layer and the bank layer; and a encapsulation layer on the cathode electrode. The first pixel defining layer and the bank layer may be completely covered by the cathode electrode, and the entire first side of the first pixel defining layer may physically contact the cathode electrode.

[0010] In an embodiment, the first pixel defining layer may further include a second side facing away from the first side, and the entire second side may completely physically contact the cathode electrode.

[0011] In an embodiment, the cathode electrode that can physically contact the first side and the cathode electrode that can physically contact the second side may be integral with each other.

[0012] In an embodiment, the bank layer may further include an end portion protruding more than the second side.

[0013] In an embodiment, the end portion of the bank layer protruding toward the light-emitting region may protrude more than the first side, the end portion of the bank layer protruding more than the first side may overlap with the light-emitting region, and the end portion of the bank layer protruding more than the second side may overlap with the non-light-emitting region.

[0014] In an embodiment, the end portion of the bank layer protruding toward the light-emitting region may protrude more than the first side, and the end portion of the first bank layer protruding more than the first side and the end portion protruding more than the second side may overlap with two light-emitting regions.

[0015] In an embodiment, the height of the first pixel defining layer in the direction perpendicular to the substrate may be greater than the height of the bank layer.

[0016] In an embodiment, the first pixel defining layer and the bank layer may include different materials.

[0017] In an embodiment, the first pixel defining layer may include at least one of silicon oxide and silicon oxynitride, and the bank layer may include at least one of titanium, silicon oxide, and silicon oxynitride.

[0018] In an embodiment, the display device may further include an organic pattern between the bank layer and the cathode electrode in a direction perpendicular to the substrate. The organic pattern and the light-emitting layer may include the same material, the organic pattern may be separated from the light-emitting layer, and the cathode electrode may overlap the light-emitting layer and the organic pattern.

[0019] In an embodiment, the bank layer may define a first opening, the first pixel defining layer may define a second opening, and the first opening may be disposed within the second opening.

[0020] In an embodiment, in a plan view, the first opening may be completely surrounded by the second opening.

[0021] In an embodiment, the display device may further include a second pixel defining layer that is separated from the first pixel defining layer in a direction parallel to the substrate by overlapping with the non-light-emitting region.

[0022] In an embodiment, the substrate may include a first surface oriented toward the anode electrode, and by overlapping with the non-light-emitting region, the first surface may include a first portion physically contacting the first pixel defining layer, a second portion physically contacting the second pixel defining layer, and a third portion physically contacting the cathode electrode.

[0023] In an embodiment, the first portion and the second portion may be separated from each other, and the third portion may be disposed between the first portion and the second portion.

[0024] In an embodiment, the display device may further include a cover layer and a cover pattern. The cover layer is disposed on the cathode electrode at a portion overlapping with the light-emitting region, and the cover pattern is on the first bank layer. The cover pattern and the cover layer may include the same material, and the cover layer and the cover pattern may be separated from each other.

[0025] According to an aspect of the present disclosure, a display device may include: a substrate including a light-emitting region and a non-light-emitting region; an anode electrode on the light-emitting region of the substrate; a light-emitting layer on the anode electrode; a pixel defining layer on the non-light-emitting region of the substrate, the pixel defining layer having an inverted tapered shape; an organic pattern on the first pixel defining layer, and the organic pattern being separated from the light-emitting layer; a residual pattern overlapping with the non-light-emitting region and disposed between the anode electrode and the pixel defining layer in a direction perpendicular to the substrate; and a cathode electrode on the light-emitting layer and the organic pattern. The organic pattern and the light-emitting layer may include the same material, the cathode electrode may completely cover the pixel defining layer and the organic pattern, and both sides of the first pixel defining layer may be in complete physical contact with the cathode electrode.

[0026] In an embodiment, the display device may further include a second pixel defining layer, the second pixel defining layer being separated from the pixel defining layer in a direction parallel to the substrate by overlapping with the non-light-emitting region, wherein the second pixel defining layer has an inverted tapered shape.

[0027] In an embodiment, the pixel defining layer and the second pixel defining layer may physically contact the residual pattern.

[0028] According to an aspect of the present disclosure, a method of manufacturing a display device may include: forming a substrate including a light-emitting region and a non-light-emitting region; forming an anode electrode on the light-emitting region of the substrate; forming a sacrificial layer on the anode electrode; forming a pixel defining material layer completely overlapping with the substrate and the sacrificial layer; and forming a bank layer completely overlapping with the pixel defining layer. The method may further include: forming a photoresist on the bank layer and performing a first etching process using the photoresist as a mask to form a first hole overlapping with the anode electrode and a second hole not overlapping with the anode electrode, such that the anode electrode is exposed by overlapping with the first hole, the sacrificial layer is formed as a residual pattern, and the bank layer forms ends protruding toward both sides more than both sides of the pixel defining layer. The method may further include: completely forming a light-emitting layer and a temporary blocking layer on the anode electrode and the bank layer, and forming a photoresist at a portion overlapping with the anode electrode and the periphery of the anode electrode; and removing the light-emitting layer and the temporary blocking layer at a portion where the photoresist is not formed by performing a second etching process. The method may further include: removing the temporary blocking layer disposed on the light-emitting layer in a vacuum chamber by a dry etching process, and completely forming a cathode electrode and a encapsulation layer. Both sides of the pixel defining layer may be in complete physical contact with the cathode electrode.

[0029] Details of other embodiments are included in the detailed description and the drawings.

[0030] The display device according to an embodiment may include a pixel defining layer and a bank layer overlapping a non-light emitting region, such that a light emitting element overlapping each light emitting region may be formed without a fine metal mask. Further, during a manufacturing process of the display device, the display device according to an embodiment may also include a temporary blocking layer covering a plurality of light emitting layers disposed to be separated from each other at a portion overlapping each light emitting region, and a cathode electrode may be completely grown in a subsequent process. Accordingly, the display device according to an embodiment may solve contact defects of the cathode electrode and moisture penetration defects of the display device caused during the manufacturing process.

[0031] The effects according to embodiments of the present disclosure are not limited to those mentioned above, and more various effects are included in the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by referring to the following detailed description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is a schematic perspective view showing an electronic device according to an embodiment;

[0034] Figure 2 is a schematic perspective view showing a display device included in the electronic device according to an embodiment;

[0035] Figure 3 is a schematic cross-sectional view showing Figure 2 a display device;

[0036] Figure 4 is a schematic cross-sectional view showing Figure 3 an arrangement of light emitting regions in a display area;

[0037] Figure 5 is a schematic cross-sectional view showing a display device taken along line X1-X1' of Figure 4 ;

[0038] Figure 6 is a schematic cross-sectional view showing Figure 5 a first light emitting region in an enlarged view;

[0039] Figure 7 is a schematic cross-sectional view showing Figure 5 a non-light emitting region disposed between a first light emitting region and a second light emitting region in an enlarged view;

[0040] Figure 8 is a schematic cross-sectional view showing, as another embodiment, a display device taken along Figure 4Schematic cross-sectional view of a display device taken along line X1-X1';

[0041] Figure 9 shows Figure 8 An enlarged schematic cross-sectional view of a non-light-emitting region provided between a first light-emitting region and a second light-emitting region in;

[0042] Figure 10 shows as another embodiment Figure 3 Schematic plan view of the arrangement of light-emitting regions in the display area of;

[0043] Figure 11 shows along Figure 10 Schematic cross-sectional view of a display device taken along line X3-X3'; and

[0044] Figures 12 to 22 shows a method for manufacturing a display element layer and a thin-film encapsulation layer included in a display device in Figure 5 Schematic cross-sectional view. DETAILED DESCRIPTION

[0045] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable terms that are non-limiting examples of the devices or methods disclosed herein. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, the various embodiments need not be exclusive or limit the present disclosure. For example, the specific shapes, configurations, and characteristics of an embodiment can be used or implemented in another embodiment. The same reference numerals and / or reference characters denote the same elements.

[0046] Unless otherwise stated, the embodiments shown should be understood to provide features of the present disclosure. Thus, unless otherwise stated, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments can be combined, separated, interchanged, and / or rearranged in other ways without departing from the present disclosure.

[0047] The use of cross-hatching and / or shading in the figures generally provides to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, scale, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements. Additionally, in the figures, for clarity and / or descriptive purposes, the dimensions and relative dimensions of the elements may be exaggerated. When embodiments can be implemented differently, a particular process order may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously, or in an order opposite to that described.

[0048] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, the element or layer can be directly on, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. However, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there may be no intervening elements or layers. The term "connected" can refer to a physical connection, an electrical connection, and / or a fluid connection, with or without intervening elements. Additionally, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" can be interpreted as only A, only B, or any combination of A and B. Additionally, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0049] Although terms such as "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of this disclosure, a first element discussed later can be named a second element.

[0050] Spatial relative terms, such as "under", "below", "beneath", "lower", "above", "upper", "on", "higher", and "side" (e.g., in "sidewall"), may be used herein for descriptive purposes and, thus, to describe the relationship of one element to another (or other elements) as shown in the figures. Except for the orientation depicted in the figures, spatial relative terms are intended to encompass different orientations of the device during use, operation, and / or manufacturing. For example, if the device is flipped in the figures, an element described as "under" or "beneath" another element or feature would then be oriented "above" the other element or feature. Thus, the term "under" can encompass both an upper and a lower orientation. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and, as such, the spatial relative descriptors used herein can be interpreted accordingly.

[0051] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly dictates otherwise, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms. Also, when used in this specification, the terms "comprises", "comprising", "has", "have", "having", and / or "includes", "including" specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and, as such, are used to account for the inherent deviations in measured, calculated, and / or provided values that would be recognized by one of ordinary skill in the art.

[0052] Various embodiments are described herein with reference to sectional views and / or exploded views, which are schematic illustrations of the embodiments and / or intermediate structures. As such, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances can be expected. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the specific shapes of the regions shown, but include shape deviations resulting from, for example, manufacturing. In this manner, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and, as such, are not necessarily intended to be limiting.

[0053] The term "overlap" or "overlaps with" means that a first object can be above or below or to a side of a second object, and vice versa. Additionally, the term "overlap" can include superposing, stacking, facing or being oriented towards, extending throughout, covering or partially covering, or any other suitable term that would be recognized and understood by one of ordinary skill in the art.

[0054] When an element is described as "not overlapping" or "not overlaps with" another element, this can include the elements being separated from each other, offset from each other, or apart from each other, or any other suitable term that would be recognized and understood by one of ordinary skill in the art.

[0055] The terms "face" and "be oriented towards" mean that a first element can be directly or indirectly opposite a second element. In the case where a third element is between the first element and the second element, the first element and the second element can be understood to be indirectly opposite each other, although still facing each other.

[0056] In accordance with the convention in the art, some embodiments are described and illustrated in the drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, etc.), which can be formed using semiconductor-based manufacturing technologies or other manufacturing technologies. In the case where the blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. Additionally, each block, unit, and / or module of some embodiments can be physically divided into two or more interacting and discrete blocks, units, and / or modules without departing from the scope of the present disclosure. Furthermore, without departing from the scope of the present disclosure, the blocks, units, and / or modules of some embodiments can be physically combined into more complex blocks, units, and / or modules.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0058] Figure 1 is a schematic perspective view showing an electronic device 1 according to an embodiment.

[0059] Referring to Figure 1 , the electronic device 1 may display a dynamic image or a still image. The electronic device 1 may be an electronic device providing a display screen. For example, the electronic device 1 may be a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, smart glasses, a smartwatch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic diary, an e-book, a portable multimedia player (PMP), a navigator, a game console, a digital camera, and a camcorder, etc. that provide a display screen.

[0060] In Figure 1 , a first direction (X-axis direction), a second direction (Y-axis direction), and a third direction (Z-axis direction) are defined. The first direction (X-axis direction) and the second direction (Y-axis direction) may be perpendicular to each other, the first direction (X-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other, and the second direction (Y-axis direction) and the third direction (Z-axis direction) may be perpendicular to each other. The first direction (X-axis direction) refers to the horizontal direction in the figure, the second direction (Y-axis direction) refers to the vertical direction in the figure, and the third direction (Z-axis direction) refers to the up-and-down direction in the figure, i.e., the thickness direction. In the following description, unless otherwise specified, "direction" may refer to two directions extending along that direction. In addition, in the case where it is desired to distinguish between two "directions" extending to both sides, one side will be referred to as the "side direction" and the other side will be referred to as the "other side direction". Based on Figure 1 , the direction pointed by the arrow indicating the direction will be referred to as one side, and the opposite direction thereof will be referred to as the other side.

[0061] Hereinafter, for convenience of description, in the case of referring to a plurality of surfaces of the electronic device 1 or each component constituting the electronic device 1, the surface on which the image is displayed, i.e., the surface pointing to one side in the third direction (Z-axis direction), will be referred to as one surface, and the opposite surface thereof will be referred to as the other surface, but the present disclosure is not limited thereto. The one surface and the other surface of the component may be referred to as the front surface and the rear surface, respectively, or may be referred to as the first surface or the second surface. In addition, when describing the relative positions of each component of the electronic device 1, one side in the third direction (Z-axis direction) may be referred to as the upper portion, and the other side in the third direction (Z-axis direction) may be referred to as the lower portion.

[0062] The shape of the electronic device 1 may be variously modified. For example, the electronic device 1 may have a shape such as a rectangle with a long width, a rectangle with a long length, a square, a rectangle with rounded corners (vertices), other polygons, or a circle.

[0063] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where an image can be displayed, and the non-display area NDA is an area where an image cannot be displayed. The display area DA may be referred to as an active area, and the non-display area NDA may be referred to as a non-active area. The display area DA generally may occupy the center of the electronic device 1.

[0064] Figure 2 is a schematic perspective view showing a display device 10 included in the electronic device 1 according to an embodiment (see Figure 1 ).

[0065] Referring to Figure 2 , the electronic device 1 according to an embodiment may include a display device 10. The display device 10 may provide an image to be displayed by the electronic device 1. Examples of the display device 10 may include an inorganic light-emitting diode display device, an organic light-emitting diode display device, a quantum dot light-emitting display device, a plasma display device, and a field emission display device. The following description will be based on the case where the display device 10 is an organic light-emitting diode display device, but the present disclosure is not limited thereto, and the display device 10 may be another type of display device.

[0066] The display device 10 may have a planar shape similar to the planar shape of the electronic device 1. For example, the display panel 100 may have a planar shape similar to a rectangle having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). The corners where the short side in the first direction (X-axis direction) intersects the long side in the second direction (Y-axis direction) may be rounded to have a predetermined or selected curvature, but right angles may be formed without being limited thereto. The planar shape of the display device 10 may have another polygonal shape or a shape similar to a circle or an ellipse, without being limited to the rectangular shape.

[0067] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400.

[0068] The display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NDA provided near the display area DA, and the display area DA includes a plurality of pixels for displaying an image.

[0069] The display area DA can emit light from a light-emitting area or an opening. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining a light-emitting area or an opening, and a self-luminous element. For example, the self-luminous element may include at least one of an organic light-emitting diode, a quantum dot light-emitting diode (LED) including a quantum dot light-emitting layer, an inorganic light-emitting diode (inorganic LED) including an inorganic semiconductor, and a micro light-emitting diode (micro LED), but is not limited thereto. In the following drawings, as an example, the self-luminous element is an organic light-emitting diode.

[0070] The non-display area NDA may be an external area of the display area DA. The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100.

[0071] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material capable of withstanding bending, folding, curling, etc. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (e.g., the third direction (Z-axis direction)). The sub-area SBA may include a pad portion connected to the display driver 200 and the circuit board 300. In another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be provided in the non-display area NDA.

[0072] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may be formed of an integrated circuit (IC), and may be attached to the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be provided in the sub-area SBA, and may overlap with the main area MA in the thickness direction by bending the sub-area SBA. As another example, the display driver 200 may be attached to the circuit board 300.

[0073] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0074] The touch driver 400 may be attached to the circuit board 300. The touch driver 400 may be connected to the touch sensor layer ( Figure 3 of the touch sensor layer 180) of the display panel 100. The touch driver 400 may be formed of an integrated circuit (IC).

[0075] Figure 3 is a schematic cross-sectional view of Figure 2 the display device 10.

[0076] Referring to Figure 3 , the display panel 100 may include a display layer DPL, a touch sensor layer 180, and a color filter layer 190. The display layer DPL may include a substrate 110, a thin film transistor layer 130, a display element layer 150, and a thin film encapsulation layer 170.

[0077] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate capable of withstanding bending, folding, curling, etc. For example, the substrate 110 may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate 110 may include a glass material or a metal material.

[0078] The thin film transistor layer 130 may be positioned (disposed) on the substrate 110. The thin film transistor layer 130 may be positioned in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor layer 130 may include thin film transistors ( Figure 4 forming the pixels ( Figure 5 of the pixel PX)

[0079] The display element layer 150 may be positioned on the thin film transistor layer 130. The display element layer 150 may be positioned to overlap with the display area DA. The display element layer 150 may include light emitting elements ( Figure 5 the light emitting element ED). For example, according to an embodiment, the display element may include at least one of an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode (LED) including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, and a micro light emitting diode (micro LED), but is not limited thereto.

[0080] The thin film encapsulation layer 170 may be positioned on the display element layer 150. The thin film encapsulation layer 170 may be positioned to overlap with the display area DA and the non-display area NDA. The thin film encapsulation layer 170 may cover the upper surface and the side surfaces of the display element layer 150, and may protect the display element layer 150 from external oxygen and moisture. The thin film encapsulation layer 170 may include at least one inorganic layer and at least one organic layer for encapsulating the display element layer 150.

[0081] The touch sensor layer 180 may be positioned on the thin film encapsulation layer 170. The touch sensor layer 180 may be positioned to overlap with the display area DA and the non-display area NDA. The touch sensor layer 180 may sense a user's touch in a mutual capacitance manner or a self-capacitance manner.

[0082] The color filter layer 190 may be positioned on the touch sensor layer 180. The color filter layer 190 may be positioned to overlap with the display area DA and the non-display area NDA. The color filter layer 190 may reduce the reflected light caused by external light by absorbing a part of the light introduced from the outside of the display device 10. Accordingly, the color filter layer 190 may prevent color distortion from occurring due to the reflection of external light.

[0083] Since the color filter layer 190 is directly disposed on the touch sensor layer 180, the display device 10 may not require a separate substrate for the color filter layer 190. Accordingly, the thickness of the display device 10 may be relatively small. In addition, depending on the embodiment, the color filter layer 190 may be omitted.

[0084] As Figure 3 shown, a part of the display layer DPL overlapping with the sub-region SBA may be bent. In the case where a part of the display layer DPL is bent, the display driver 200, the circuit board 300, and the touch driver 400 may overlap with the main region MA in the third direction (Z-axis direction).

[0085] Figure 4 is a schematic plan view showing Figure 3 the arrangement of the light-emitting regions EA in the display area DA.

[0086] Referring to Figure 4 , the display area DA according to an embodiment may include a plurality of first light-emitting regions EA1, a plurality of second light-emitting regions EA2, and a plurality of third light-emitting regions EA3, and a non-light-emitting region NLA. The non-light-emitting region NLA may be positioned to surround the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3.

[0087] The non-light-emitting region NLA may shield the light emitted from each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. To this end, the non-light-emitting region NLA may help prevent the light emitted from the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 from being mixed. The pixel defining layer ( Figure 5 the pixel defining layer 151 of Figure 5 ) and the bank layer (

[0088] The light-emitting region EA may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3 that emit lights of different colors. Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may emit red light, green light, or blue light, and the color of the light emitted from each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may vary depending on the type of the light-emitting element ED (see Figure 5 ). For example, the first light-emitting region EA1 may emit red light of a first color, the second light-emitting region EA2 may emit green light of a second color, and the third light-emitting region EA3 may emit blue light of a third color, but the present disclosure is not limited thereto. Although the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are shown as having the same size and shape, the present disclosure is not limited thereto. The size and shape of each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be freely adjusted according to desired characteristics.

[0089] Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be defined by a first opening OP1 and a second opening OP2. For example, the first opening OP1 may be defined by a bank layer 161 to be described later, and the second opening OP2 may be defined by a pixel defining layer 151 to be described later. The first opening OP1 may be disposed within the second opening OP2. In a plan view, the first opening OP1 may be completely surrounded by the second opening OP2.

[0090] In some embodiments, at least one first light-emitting region EA1, at least one second light-emitting region EA2, and at least one third light-emitting region EA3 disposed adjacent to each other may constitute a pixel group PXG. The pixel group PXG may be the smallest unit that emits white light. However, depending on the embodiment, various modifications may be made to the type and / or number of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 that constitute the pixel group PXG.

[0091] Figure 5 is a schematic cross-sectional view of the display device 10 taken along the line X1-X1' of Figure 4 . Figure 5 shows a schematic cross-section of the display layer DPL of the display device 10 according to an embodiment. Since the substrate 110 has been described in Figure 3 , its redundant description will be omitted.

[0092] Referring to Figure 5, the thin film transistor layer 130 may be positioned on the substrate 110. The thin film transistor layer 130 may include a first buffer layer 111, thin film transistors TFTs, a gate insulating layer 113, a first interlayer insulating layer 121, capacitor electrodes CPEs, a second interlayer insulating layer 123, a first connection electrode CNE1, a first via layer 125, a second connection electrode CNE2, and a second via layer 127.

[0093] The first buffer layer 111 may be positioned on the substrate 110. The first buffer layer 111 may include an inorganic layer capable of preventing the penetration of air or moisture. For example, the first buffer layer 111 may include a plurality of inorganic layers stacked on top of each other.

[0094] The thin film transistors TFTs may be disposed on the first buffer layer 111 and may constitute pixel circuits connected to each of a plurality of pixels PX (see Figure 4 ). For example, the thin film transistors TFTs may be driving transistors or switching transistors of the pixel circuits. The thin film transistors TFTs may include an active layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0095] The active layer ACT may be disposed on the first buffer layer 111. The active layer ACT may overlap with the gate electrode GE in the third direction (Z-axis direction) and may be insulated from the gate electrode GE by the gate insulating layer 113. A part of the active layer ACT may be made conductive to form the source electrode SE and the drain electrode DE.

[0096] The gate electrode GE may be positioned on the gate insulating layer 113. The gate electrode GE may overlap with the active layer ACT with the gate insulating layer 113 therebetween.

[0097] The gate insulating layer 113 may be positioned on the active layer ACT. The gate insulating layer 113 may cover the active layer ACT and the first buffer layer 111, and the gate insulating layer 113 may insulate the active layer ACT from the gate electrode GE. The gate insulating layer 113 may include contact holes through which the first connection electrode CNE1 passes.

[0098] The first interlayer insulating layer 121 may cover the gate electrode GE and the gate insulating layer 113. The first interlayer insulating layer 121 may include contact holes through which the first connection electrode CNE1 passes. The contact holes of the first interlayer insulating layer 121 may be connected to the contact holes of the gate insulating layer 113 and the contact holes of the second interlayer insulating layer 123.

[0099] The capacitor electrodes CPEs may be positioned on the first interlayer insulating layer 121. The capacitor electrodes CPEs may overlap with the gate electrode GE in the third direction (Z-axis direction). The capacitor electrodes CPEs and the gate electrode GE may form a capacitance.

[0100] The second interlayer insulating layer 123 may cover the capacitor electrode CPE and the first interlayer insulating layer 121. The second interlayer insulating layer 123 may include contact holes through which the first connection electrode CNE1 passes. The contact holes of the second interlayer insulating layer 123 may be connected to the contact holes of the first interlayer insulating layer 121 and the contact holes of the gate insulating layer 113.

[0101] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer 123. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into the contact holes formed in the first interlayer insulating layer 121, the second interlayer insulating layer 123, and the gate insulating layer 113, and thus the first connection electrode CNE1 may contact the drain electrode DE of the thin film transistor TFT.

[0102] The first via layer 125 may cover the first connection electrode CNE1 and the second interlayer insulating layer 123. The first via layer 125 may planarize the underlying structure. The first via layer 125 may include contact holes through which the second connection electrode CNE2 passes.

[0103] The second connection electrode CNE2 may be positioned on the first via layer 125. The second connection electrode CNE2 may be inserted into the contact holes formed in the first via layer 125 to contact the first connection electrode CNE1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3.

[0104] The second via layer 127 may cover the second connection electrode CNE2 and the first via layer 125. The second via layer 127 may include contact holes through which the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 pass.

[0105] The display element layer 150 may be positioned on the second via layer 127. The display element layer 150 may include a light-emitting element ED, a pixel defining layer 151, a residual pattern 153, a cover layer CPL, and a bank layer 161.

[0106] The light-emitting element ED of the embodiment may include a first light-emitting element ED1 disposed at a portion overlapping with the first light-emitting region EA1, a second light-emitting element ED2 disposed at a portion overlapping with the second light-emitting region EA2, and a third light-emitting element ED3 disposed at a portion overlapping with the third light-emitting region EA3. The first light-emitting element ED1 may include a first anode electrode AE1, a first light-emitting layer EL1, and a cathode electrode CE. The second light-emitting element ED2 may include a second anode electrode AE2, a second light-emitting layer EL2, and a cathode electrode CE. And the third light-emitting element ED3 may include a third anode electrode AE3, a third light-emitting layer EL3, and a cathode electrode CE. Depending on the materials of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, the light-emitting elements ED1, ED2, and ED3 may emit light of different colors. For example, the first light-emitting element ED1 may emit red light of a first color, the second light-emitting element ED2 may emit green light of a second color, and the third light-emitting element ED3 may emit blue light of a third color.

[0107] The anode electrode AE of the embodiment may be positioned on the second via layer 127. The anode electrode AE may be electrically connected to the drain electrode DE of the thin-film transistor TFT through a first connection electrode CNE1 and a second connection electrode CNE2.

[0108] The anode electrode AE of the embodiment may include a first anode electrode AE1 disposed in the first light-emitting region EA1, a second anode electrode AE2 disposed in the second light-emitting region EA2, and a third anode electrode AE3 disposed in the third light-emitting region EA3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be disposed to be separated from each other on the second via layer 127.

[0109] The anode electrode AE of the embodiment may have a stacked-layer structure in which a material layer having a high work function and a reflective material layer are stacked. The material layer having a high work function includes materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In2O3). The reflective material layer includes materials such as Ag, Mg, Al, Pt, Pb, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or a mixture thereof. For example, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, and ITO / Ag / ITO, but is not limited thereto.

[0110] The pixel defining layer 151 of the embodiment may be positioned at a portion overlapping with the non-light emitting region NLA, and the pixel defining layer 151 may be positioned on the second via layer 127 and the anode electrode AE. The pixel defining layer 151 of the embodiment may define a second opening OP2, and the pixel defining layer 151 may expose the anode electrode AE at a portion overlapping with the second opening OP2.

[0111] The pixel defining layer 151 of the embodiment may separate and insulate the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 from each other at portions overlapping with the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3. The pixel defining layer 151 of the embodiment may help to form the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 separated from each other at portions overlapping with the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 during the manufacturing process of the display device 10.

[0112] In some embodiments, the pixel defining layer 151 may include a first pixel defining layer 151A, a second pixel defining layer 151B, and a third pixel defining layer 151C. The first pixel defining layer 151A of the embodiment may be disposed toward the first light emitting region EA1, the second pixel defining layer 151B may be disposed toward the second light emitting region EA2, and the third pixel defining layer 151C may be disposed toward the third light emitting region EA3. The first pixel defining layer 151A and the second pixel defining layer 151B may be separated from each other in a first direction (X-axis direction) at a portion overlapping with the non-light emitting region NLA. The second pixel defining layer 151B and the third pixel defining layer 151C may be separated from each other in a first direction (X-axis direction) at a portion overlapping with the non-light emitting region NLA. The first pixel defining layer 151A, the second pixel defining layer 151B, and the third pixel defining layer 151C may be integrally formed during the manufacturing process of the display device 10, and then may be formed to be separated from each other by a subsequent etching process. This manufacturing process will be described later.

[0113] The bank layer 161 of the embodiment may be positioned at a portion overlapping with the non-light emitting region NLA, and may be positioned on the pixel defining layer 151. The bank layer 161 of the embodiment may define a first opening OP1.

[0114] The bank layer 161 of the embodiment may include ends TIP protruding toward the first light-emitting region EA1, the second light-emitting region EA2, the third light-emitting region EA3, and the non-light-emitting region NLA on both sides. In the display device 10 according to the embodiment, since the bank layer 161 includes the ends TIP, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 that are disposed to be separated from each other at portions overlapping with the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be formed even without a separate fine metal mask during the manufacturing process of the display device 10.

[0115] In some embodiments, the bank layer 161 of the embodiment may include a first bank layer 161A, a second bank layer 161B, and a third bank layer 161C. The first bank layer 161A of the embodiment may be disposed on the first pixel defining layer 151A, the second bank layer 161B may be disposed on the second pixel defining layer 151B, and the third bank layer 161C may be positioned on the third pixel defining layer 151C. The first bank layer 161A and the second bank layer 161B may be separated from each other in a first direction (X-axis direction) at a portion overlapping with the non-light-emitting region NLA. The second bank layer 161B and the third bank layer 161C may be separated from each other in the first direction (X-axis direction) at a portion overlapping with the non-light-emitting region NLA. The first bank layer 161A, the second bank layer 161B, and the third bank layer 161C may be integrally formed during the manufacturing process of the display device 10, and then may be formed to be separated from each other by a subsequent etching process. This manufacturing process will be described later.

[0116] The light-emitting layer EL of the embodiment may be disposed on the anode electrode AE. The light-emitting layer EL may be an organic light-emitting layer made of an organic material. In a case where the thin film transistor TFT applies a predetermined or selected voltage to the anode electrode AE and the cathode electrode CE receives a common voltage, holes and electrons may move to the light-emitting layer EL through the hole transport layer and the electron transport layer, respectively, and may be recombined with each other in the light-emitting layer EL to emit light.

[0117] The light-emitting layer EL of the embodiment may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3 respectively disposed in a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3. As described above, the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 of the embodiment may be separated from each other by the pixel defining layer 151 and the bank layer 161 and respectively positioned in the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. For example, the first light-emitting layer EL1 may be a light-emitting layer for emitting red light of a first color, the second light-emitting layer EL2 may be a light-emitting layer for emitting green light of a second color, and the third light-emitting layer EL3 may be a light-emitting layer for emitting blue light of a third color, but the present disclosure is not limited thereto.

[0118] The residual pattern 153 will be described later.

[0119] The organic pattern ELP of the embodiment may be positioned on the bank layer 161. The organic pattern ELP of the embodiment may be positioned to surround the periphery of the first opening OP1. The organic pattern ELP of the embodiment may be positioned at a portion overlapping with the light-emitting region EA and the non-light-emitting region NLA.

[0120] The organic pattern ELP of the embodiment may include a first organic pattern ELP1, a second organic pattern ELP2, and a third organic pattern ELP3. The first organic pattern ELP1 may be positioned on the first bank layer 161A, the second organic pattern ELP2 may be positioned on the second bank layer 161B, and the third organic pattern ELP3 may be positioned on the third bank layer 161C.

[0121] The first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3 may include the same materials as those of each of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3. As described above, during the manufacturing process of the display device 10, the light-emitting layer EL of the embodiment may be formed by a deposition and photolithography process without using a separate fine metal mask. Therefore, the materials for forming the light-emitting layer EL may be deposited not only on the anode electrode AE but also on the bank layer 161. That is, since the bank layer 161 of the embodiment includes the end portion TIP, the organic pattern ELP of the embodiment may be a trace formed by disconnecting the materials of the light-emitting layer EL deposited on the bank layer 161 from the light-emitting layer EL deposited on the anode electrode AE. In other words, it can be seen that the display device 10 of the embodiment includes the organic pattern ELP on the bank layer 161, and thus the process of forming the light-emitting layer EL is performed by a photolithography process. However, depending on the process, the organic pattern ELP may be omitted.

[0122] The cathode electrode CE of the embodiment can be integrally formed by overlapping with the light-emitting region EA and the non-light-emitting region NLA. The cathode electrode CE of the embodiment can be in contact with the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 at the portions overlapping with the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, and can be in contact with the first organic pattern ELP1, the second organic pattern ELP2, the third organic pattern ELP3, and the second via layer 127 at the portions overlapping with the non-light-emitting region NLA. The cathode electrode CE of the embodiment can be a common electrode.

[0123] The cathode electrode CE of the embodiment can include a transparent conductive material. For example, the cathode electrode CE can include a material layer having a small work function, and the material layer can include, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or their compounds or mixtures (e.g., a mixture of Ag and Mg), or a material having a multi-layer structure such as LiF / Ca or LiF / Al. The cathode electrode CE can also include a transparent metal oxide layer disposed on the material layer having the small work function.

[0124] The cover layer CPL of the embodiment can be positioned on the cathode electrode CE. The cover layer CPL can include an inorganic insulating material to prevent the light-emitting element ED from being damaged by external air. In addition, the cover layer CPL can prevent the light-emitting element ED from being peeled off during the manufacturing process of the display device 10.

[0125] The cover layer CPL can include a first cover layer CPL1 disposed at the portion overlapping with the first light-emitting region EA1, a second cover layer CPL2 disposed at the portion overlapping with the second light-emitting region EA2, and a third cover layer CPL3 disposed at the portion overlapping with the third light-emitting region EA3. The first cover layer CPL1, the second cover layer CPL2, and the third cover layer CPL3 can be separated from each other and the pixel defining layer 151 is interposed therebetween.

[0126] The cover layer CPL of the embodiment can include an inorganic insulating material. For example, the cover layer CPL can include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0127] The cover pattern CP of the embodiment can be positioned at the portion overlapping with the bank layer 161 and can be in contact with the cathode electrode CE. The cover pattern CP of the embodiment can be positioned at the portions overlapping with the light-emitting region EA and the non-light-emitting region NLA.

[0128] The cover pattern CP of the embodiment may include a first cover pattern CP1, a second cover pattern CP2, and a third cover pattern CP3. The first cover pattern CP1 may be positioned on the first bank layer 161A, the second cover pattern CP2 may be positioned on the second bank layer 161B, and the third cover pattern CP3 may be positioned on the third bank layer 161C.

[0129] The first cover pattern CP1, the second cover pattern CP2, and the third cover pattern CP3 may include the same materials as those of the first cover layer CPL1, the second cover layer CPL2, and the third cover layer CPL3. During the manufacturing process of the display device 10, the cover layer CPL may be formed by a deposition and photolithography process without using a separate fine metal mask. Therefore, during the manufacturing process of the display device 10, the material for forming the cover layer CPL may be deposited not only on the anode electrode AE but also on the bank layer 161. That is to say, since the bank layer 161 includes the end portion TIP, the cover pattern CP of the embodiment may be a trace formed by disconnecting the material of the cover layer CPL deposited on the bank layer 161 from the cover layer CPL deposited on the anode electrode AE. In other words, it can be seen that the display device 10 of the embodiment includes the cover pattern CP on the bank layer 161, and thus the process of forming the cover layer CPL is performed by a photolithography process. However, depending on the process, the cover pattern CP may be omitted.

[0130] In addition, the cover pattern CP of the embodiment may include a cover residue pattern CPn. At a portion overlapping with the non-emitting area NLA, the cover residue pattern CPn is deposited on the cathode electrode CE at portions between the first pixel defining layer 151A and the second pixel defining layer 151B and between the second pixel defining layer 151B and the third pixel defining layer 151C. The first cover pattern CP1, the second cover pattern CP2, and the third cover pattern CP3 formed on the bank layer 161 and the cover residue pattern CPn formed between the pixel defining layers 151 may be separated from each other.

[0131] The thin film encapsulation layer 170 of the embodiment may be positioned on the display element layer 150. The thin film encapsulation layer 170 may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the display element layer 150. The thin film encapsulation layer 170 may include at least one organic layer to protect the display element layer 150 from particles such as dust. The thin film encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 stacked on each other.

[0132] The first encapsulation layer 171 of the embodiment may be positioned on the cover layer CPL and the cover pattern CP. Since the first encapsulation layer 171 of the embodiment may be formed by a chemical vapor deposition (CVD) process, it may be formed to have a uniform thickness along the contour of the lower structure. That is, the first encapsulation layer 171 of the embodiment may include a step difference at a portion overlapping with the light-emitting region EA and the non-light-emitting region NLA.

[0133] The first encapsulation layer 171 of the embodiment may include a single-layer structure or a multi-layer structure and may include an inorganic insulating material. For example, the first encapsulation layer 171 may include at least one of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0134] The second encapsulation layer 173 of the embodiment may be positioned on the first encapsulation layer 171. The second encapsulation layer 173 may planarize the step difference formed by the first encapsulation layer 171 at a portion overlapping with the light-emitting region EA and the non-light-emitting region NLA.

[0135] The second encapsulation layer 173 may include a polymer-based material. For example, the second encapsulation layer 173 may include an acrylic-based resin, a silicon-based resin, a silicone acrylic-based resin, an epoxy-based resin, etc. The second encapsulation layer 173 may be formed by curing a monomer or coating a polymer.

[0136] The third encapsulation layer 175 of the embodiment may be positioned on the second encapsulation layer 173 and may completely cover the second encapsulation layer 173. The third encapsulation layer 175 may include an inorganic material and may include the same material as that of the first encapsulation layer 171. Redundant descriptions will be omitted.

[0137] Figure 6 is a magnified schematic cross-sectional view showing Figure 5 the first light-emitting region EA1 in Figure 6 Although the first pixel defining layer 151A of the pixel defining layer 151 (see Figure 5 ) and the first bank layer 161A of the bank layer 161 (see Figure 5 ) are shown in

[0138] For ease of description, hereinafter, the pixel defining layer 151 and the bank layer 161 will be described.

[0138] Referring to Figure 6 , the residual pattern 153 of the embodiment may be positioned between the pixel defining layer 151 and the first anode electrode AE1 in the third direction (Z-axis direction). The residual pattern 153 of the embodiment may be positioned to contact both sides of the first light-emitting layer EL1 in the first direction (X-axis direction).

[0139] The display device 10 according to the embodiment may include a sacrificial layer on the anode electrode AE during the manufacturing process ( Figure 12sacrificial layer SFL). The sacrificial layer SFL can be disposed between the pixel defining layer 151 and the anode electrode AE, and can then be partially removed by a subsequent etching process. In this case, the sacrificial layer SFL that is not partially removed can remain as a residual pattern 153 between the pixel defining layer 151 and the anode electrode AE. This manufacturing process will be described later.

[0140] The residual pattern 153 of the embodiment can include an oxide semiconductor. For example, the residual pattern 153 can include at least one of indium gallium zinc oxide (IGZO), tin oxide zinc (ZTO), and indium tin oxide (IZO).

[0141] The pixel defining layer 151 of the embodiment can be positioned to contact the second via layer 127 and the first anode electrode AE1. In addition, the pixel defining layer 151 can contact the residual pattern 153. The pixel defining layer 151 of the embodiment can include an inorganic insulating material. For example, the pixel defining layer 151 can include any one of silicon oxide and silicon oxynitride.

[0142] In some embodiments, the pixel defining layer 151 of the embodiment can include a first side (first side surface) 151c oriented toward the first opening OP1. The first side 151c of the embodiment can be completely covered by the cathode electrode CE, and the first side 151c can be completely in contact with the cathode electrode CE.

[0143] In the display device 10 of the embodiment, the first side 151c of the pixel defining layer 151 and the cathode electrode CE are formed to be completely in contact with each other, so that the contact force between the pixel defining layer 151 and the cathode electrode CE can be improved. Therefore, the display device 10 of the embodiment can solve the separable defect between the pixel defining layer 151 and the cathode electrode CE and the moisture penetration defect caused by the separable defect.

[0144] The bank layer 161 of the embodiment can be positioned to contact the pixel defining layer 151. The bank layer 161 of the embodiment can include a material that is more stable than the material of the pixel defining layer 151 with respect to the etching process. For example, the bank layer 161 can include a conductive metal material or an inorganic insulating material.

[0145] For example, in the case where the bank layer 161 of the embodiment includes a conductive metal material, the bank layer 161 can include one or more metals selected from titanium (Ti), molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), tantalum (Ta), tungsten (W), and copper (Cu).

[0146] For example, when the bank layer 161 of the embodiment includes an inorganic insulating material, the bank layer 161 may include at least one of silicon oxide and silicon oxynitride. When the bank layer 161 includes an inorganic insulating material, the bank layer 161 and the pixel defining layer 151 may include different materials from each other. For example, when the pixel defining layer 151 includes silicon oxynitride, the bank layer 161 may be formed of silicon oxide.

[0147] In some embodiments, the bank layer 161 of the embodiment may include a first side (first side surface) 161c oriented toward the first opening OP1. The first side 161c of the bank layer 161 may protrude toward the first light emitting region EA1 in the first direction (X-axis direction). In other words, the first side 151c of the pixel defining layer 151 according to the embodiment may have a shape that is recessed in the first direction (X-axis direction) compared to the first side 161c of the bank layer 161.

[0148] The pixel defining layer 151 and the bank layer 161 according to the embodiment may be formed by the same etching process during the manufacturing process of the display device 10. Since the bank layer 161 of the embodiment includes a material that is more stable than the material of the pixel defining layer 151 with respect to the etching process, in the same etching process, the bank layer 161 may have an etching rate lower than that of the pixel defining layer 151. Therefore, the bank layer 161 of the embodiment may have an end portion TIP that protrudes toward the light emitting region EA more than the first side 151c of the pixel defining layer 151, and an undercut may be formed between the first side 151c of the pixel defining layer 151 and the protruding end portion TIP of the bank layer 161.

[0149] The height H151 of the pixel defining layer 151 according to the embodiment may be greater than the height H161 of the bank layer 161.

[0150] The first organic pattern ELP1 of the embodiment may be positioned in contact with the bank layer 161. The first organic pattern ELP1 may overlap with the end portion TIP and the residual pattern 153 of the bank layer 161 in the third direction (Z-axis direction). Other redundant descriptions will be omitted.

[0151] The cathode electrode CE of the embodiment may be positioned in contact with the first light emitting layer EL1 at a portion overlapping the first opening OP1, and may completely cover the first light emitting layer EL1. The cathode electrode CE of the embodiment may completely cover the first side 151c of the pixel defining layer 151, the end portion TIP of the bank layer 161, and the first organic pattern ELP1 at a portion overlapping the second opening OP2, and the cathode electrode CE may be in contact with the pixel defining layer 151, the bank layer 161, and the first organic pattern ELP1. In addition, the cathode electrode CE may completely cover the first organic pattern ELP1 at a portion overlapping the non-light emitting region NLA, and may be in contact with the first organic pattern ELP1.

[0152] The first capping layer CPL1 of the embodiment may be positioned on the first light-emitting element ED1 at a portion overlapping with the first opening OP1, and may be in contact with the cathode electrode CE. The first capping pattern CP1 of the embodiment may overlap with the end portion TIP of the bank layer 161 and the residual pattern 153 in the third direction (Z-axis direction). Other redundant descriptions will be omitted.

[0153] The first encapsulation layer 171 of the embodiment may completely cover the first light-emitting element ED1 at a portion overlapping with the first opening OP1, and may completely cover the pixel defining layer 151, the bank layer 161, the first organic pattern ELP1, and the first capping pattern CP1 at a portion overlapping with the non-light-emitting region NLA. The second encapsulation layer 173 of the embodiment may planarize the step difference formed by the first encapsulation layer 171 at a portion overlapping with the first opening OP1. Other redundant descriptions will be omitted.

[0154] Figure 7 is a schematic enlarged cross-sectional view showing Figure 5 the non-light-emitting region NLA provided between the first light-emitting region EA1 and the second light-emitting region EA2.

[0155] Referring to Figure 7 , the anode electrode AE, the pixel defining layer 151, and the cathode electrode CE may be positioned on the second via layer 127 of the embodiment.

[0156] In some embodiments, the second via layer 127 of the embodiment may include a first surface 127a oriented toward the pixel defining layer 151. At a portion overlapping with the non-light-emitting region NLA, depending on the contact structure, the first surface 127a of the second via layer 127 may be divided into a first portion a1, a second portion a2, a third portion a3, and a fourth portion a4.

[0157] Specifically, the first portion a1 may be a portion in contact with the first pixel defining layer 151A, the second portion a2 may be a portion in contact with the second pixel defining layer 151B, the third portion a3 may be a portion in contact with the cathode electrode CE, and the fourth portion a4 may be a portion in contact with the anode electrode AE. The third portion a3 may be positioned between the first portion a1 and the second portion a2, and may overlap with the protruding end portion TIP of the bank layer 161 in the third direction (Z-axis direction). In addition, the fourth portion a4 may overlap with the residual pattern 153 in the third direction (Z-axis direction).

[0158] The first pixel defining layer 151A and the second pixel defining layer 151B according to the embodiment may be separated from each other in the first direction (X-axis direction), and the cathode electrode CE, the capping residual pattern CPn, the first encapsulation layer 171, and the second encapsulation layer 173 are interposed therebetween.

[0159] In some embodiments, the first pixel defining layer 151A may include a first side 151c oriented toward the light-emitting region EA and a second side (second side surface) 151d facing away from the first side 151c. The first side 151c and the second side 151d may be completely covered by the cathode electrode CE and may be in complete contact with the cathode electrode CE. In an embodiment, the cathode electrode CE covering the first side 151c and the cathode electrode CE covering the second side 151d may be integrally formed.

[0160] According to an embodiment, the first bank layer 161A and the second bank layer 161B may be separated from each other in a first direction (X-axis direction), and the cathode electrode CE, the first encapsulation layer 171, and the second encapsulation layer 173 may be interposed therebetween.

[0161] In some embodiments, the first bank layer 161A may include a first side 161c oriented toward the light-emitting region EA and a second side (second side surface) 161d facing away from the first side 161c. The first side 161c and the second side 161d may be completely covered by the cathode electrode CE and may be in complete contact with the cathode electrode CE. In an embodiment, the cathode electrode CE covering the first side 161c and the cathode electrode CE covering the second side 161d may be integrally formed.

[0162] According to an embodiment, the first side 161c of the bank layer 161 (e.g., the first bank layer 161A) may protrude toward the light-emitting region EA more than the first side 151c of the pixel defining layer 151 (e.g., the first pixel defining layer 151A), and the second side 161d of the bank layer 161 (e.g., the first bank layer 161A) may protrude toward one side in the first direction (X-axis direction) more than the second side 151d of the pixel defining layer 151 (e.g., the first pixel defining layer 151A) at a portion overlapping with the non-light-emitting region NLA. Accordingly, the bank layer 161 (e.g., the first bank layer 161A) of the embodiment may have ends TIP protruding toward both sides in the first direction (X-axis direction).

[0163] According to an embodiment, the first organic pattern ELP1 and the second organic pattern ELP2 may be separated from each other in a first direction (X-axis direction), and the cathode electrode CE, the first encapsulation layer 171, and the second encapsulation layer 173 may be interposed therebetween. The first organic pattern ELP1 of the embodiment may be in contact with the ends TIP protruding toward both sides of the first bank layer 161A, and the second organic pattern ELP2 may be in contact with the ends TIP protruding toward both sides of the second bank layer 161B.

[0164] The first cover pattern CP1 and the second cover pattern CP2 according to the embodiment may be separated from each other in the first direction (X-axis direction), and the first encapsulation layer 171 and the second encapsulation layer 173 may be interposed therebetween. The first cover pattern CP1 of the embodiment may overlap with the end portions TIP protruding to both sides of the first bank layer 161A, and the second cover pattern CP2 may overlap with the end portions TIP protruding to both sides of the second bank layer 161B.

[0165] During the manufacturing process of the display device 10, since the bank layer 161 includes end portions TIP at portions overlapping with the non-light emitting region NLA, the cover residue pattern CPn provided between the first pixel defining layer 151A and the second pixel defining layer 151B may be formed in such a manner that the material for forming the cover layer CPL is deposited not only at portions overlapping with the bank layer 161 but also at portions overlapping with the region between the first pixel defining layer 151A and the second pixel defining layer 151B. The cover residue pattern CPn provided between the first pixel defining layer 151A and the second pixel defining layer 151B may be positioned to contact the cathode electrode CE.

[0166] The first encapsulation layer 171 may completely cover the first cover pattern CP1 and the second cover pattern CP2 at portions overlapping with the non-light emitting region NLA, and may contact the first cover pattern CP1 and the second cover pattern CP2. In addition, at portions overlapping with the non-light emitting region NLA, the first encapsulation layer 171 may completely cover the cover residue pattern CPn deposited at portions overlapping with the region between the first pixel defining layer 151A and the second pixel defining layer 151B.

[0167] The second encapsulation layer 173 of the embodiment may planarize the step difference formed by the first encapsulation layer 171 at portions overlapping with the non-light emitting region NLA. Other redundant descriptions will be omitted.

[0168] For ease of description, although only the structures overlapping with the first light emitting region EA1 and the structures overlapping with the non-light emitting region NLA positioned between the first light emitting region EA1 and the second light emitting region EA2 have been shown and described, the structures overlapping with the second light emitting region EA2 and the third light emitting region EA3 and their features may be the same as those of the structures overlapping with the first light emitting region EA1.

[0169] Figure 8 is a schematic cross-sectional view of the display device 30 taken along the Figure 4 line X1-X1' as another embodiment, and Figure 9 is a schematic cross-sectional view showing Figure 8 an enlarged view of the non-light emitting region NLA provided between the first light emitting region EA1 and the second light emitting region EA2 in

[0170] Reference Figure 8 and Figure 9 In this regard, the display device 30 of the embodiment may be different from the above-described display device 10 at least in terms of the structure of the portion overlapping with the non-light-emitting area NLA. Hereinafter, redundant descriptions of the structure of the display device 30 overlapping with the light-emitting area EA will be omitted, and differences from the display device 10 will be described.

[0171] The pixel defining layer 151 of the embodiment may be positioned on the second via layer 127, the anode electrode AE, and the residual pattern 153 at the portion overlapping with the non-light-emitting area NLA. Only the anode electrode AE and the pixel defining layer 151 may be positioned on the second via layer 127 of the embodiment. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 of the embodiment may be separated from each other and insulated by the pixel defining layer 151.

[0172] In some embodiments, the pixel defining layer 151 of the embodiment may include a first side (first side surface) 151s and a second side (second side surface) 151p. The first side 151s may be the side oriented toward the first light-emitting area EA1, and the second side 151p may be the side oriented toward the second light-emitting area EA2. The first side 151s and the second side 151p may face away from each other.

[0173] The first side 151s and the second side 151p of the embodiment may be completely covered by the cathode electrode CE and may be in contact with the cathode electrode CE. The cathode electrode CE in contact with the first side 151s and the cathode electrode CE in contact with the second side 151p may be integrally formed.

[0174] In the display device 30 of the embodiment, the first side 151s and the second side 151p of the pixel defining layer 151 may be formed to be completely in contact with the cathode electrode CE, so that the contact force between the pixel defining layer 151 and the cathode electrode CE can be improved. Accordingly, the display device 30 of the embodiment may solve the separable defect between the pixel defining layer 151 and the cathode electrode CE and the moisture penetration defect of the display device caused by the separable defect.

[0175] The bank layer 161 of the embodiment may be positioned on the pixel defining layer 151 at the portion overlapping with the non-light-emitting area NLA.

[0176] In some embodiments, the bank layer 161 of the embodiment may include a first side (first side surface) 161s and a second side (second side surface) 161p. The first side 161s may be the side oriented toward the first light-emitting area EA1, and the second side 161p may be the side oriented toward the second light-emitting area EA2. The first side 161s and the second side 161p may face away from each other.

[0177] The first side 161s of the embodiment may protrude toward the first light-emitting region EA1 more than the first side 151s of the pixel defining layer 151, and thus the bank layer 161 may have an end portion TIP protruding toward the first light-emitting region EA1. In addition, the second side 161p of the embodiment may protrude toward the second light-emitting region EA2 more than the second side 151p of the pixel defining layer 151, and thus the bank layer 161 may have an end portion TIP protruding toward the second light-emitting region EA2. That is, the bank layer 161 of the embodiment may have end portions TIP protruding toward the light-emitting region EA on both sides.

[0178] The first side 161s and the second side 161p of the embodiment may be completely covered by the cathode electrode CE and may be in contact with the cathode electrode CE. The cathode electrode CE in contact with the first side 161s and the cathode electrode CE in contact with the second side 161p may be integrally formed.

[0179] In some embodiments, the bank layer 161 of the embodiment may further include a first surface 161t. The first surface 161t of the bank layer 161 may be a surface oriented toward the cover residue pattern CPn.

[0180] Depending on the contact structure, the first surface 161t of the embodiment may be divided into a first portion t1, a second portion t2, and a third portion t3. The first portion t1 of the embodiment may be in contact with the first organic pattern ELP1, the second portion t2 may be in contact with the second organic pattern ELP2, and the third portion t3 may be in contact with the cathode electrode CE. The first portion t1 and the second portion t2 according to the embodiment may be separated from each other and the third portion t3 may be interposed therebetween. In other words, the first organic pattern ELP1 and the second organic pattern ELP2 according to the embodiment may be separated from each other on the bank layer 161 and the cathode electrode CE may be interposed therebetween.

[0181] The cathode electrode CE of the embodiment may be positioned on the organic pattern ELP and the bank layer 161 at a portion overlapping the non-light-emitting region NLA and may be in contact with the organic pattern ELP and the bank layer 161.

[0182] The cover residue pattern CPn of the embodiment may completely cover the cathode electrode CE at a portion overlapping the non-light-emitting region NLA and may be in contact with the cathode electrode CE. The cover layer CPL of the embodiment may be formed in such a way that during the manufacturing process of the display device 30, the material for forming the cover layer CPL is formed not only on the anode electrode AE but also on the bank layer 161. Therefore, since the bank layer 161 includes protruding end portions TIP, the cover residue pattern CPn may be the result of the material for forming the cover layer CPL being disconnected from the first cover layer CPL1, the second cover layer CPL2, and the third cover layer CPL3 provided in the light-emitting region EA.

[0183] The first encapsulation layer 171 of the embodiment may completely cover the cover residual pattern CPn at the portion overlapping with the non-light-emitting region NLA and may be in contact with the cover residual pattern CPn. The second encapsulation layer 173 of the embodiment may completely cover the first encapsulation layer 171 at the portion overlapping with the non-light-emitting region NLA. The second encapsulation layer 173 of the embodiment may planarize the step difference formed by the first encapsulation layer 171 at the portion overlapping with the non-light-emitting region NLA. Other redundant descriptions will be omitted.

[0184] For ease of description, although only the structures overlapping with the first light-emitting region EA1 and the second light-emitting region EA2 have been shown and described, the third light-emitting region EA3 may have the same structure and characteristics as those of the first light-emitting region EA1 and the second light-emitting region EA2.

[0185] Figure 10 is a schematic plan view showing the arrangement of the light-emitting regions EA in the display area DA of Figure 3 as another embodiment.

[0186] Referring to Figure 10 , the display device 50 according to the embodiment is different from the above-described display device 10 (see Figure 5 ) at least in that each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be defined by one opening OP. The pixel defining layer ( Figure 11 the pixel defining layer 151 of

[0187] Figure 11 ) to be described later may be positioned in the non-light-emitting region NLA of the embodiment. Other redundant descriptions will be omitted. Figure 10 is a schematic cross-sectional view of the display device 50 taken along the line X3-X3' of Figure 5 . The display device 50 according to the embodiment is different from the above-described display device 10 (see Figure 8 ) and the display device 30 (see

[0188] at least in that the pixel defining layer 151 may have an inverted tapered shape and the organic pattern ELP may be directly provided on the pixel defining layer 151. Hereinafter, redundant descriptions of the same aspects of the display device 50 as those of the display device 10 and the display device 30 will be omitted, and the differences from the display device 10 and the display device 30 will be described. Figure 11 Referring to , the display device 50 according to the embodiment may include the pixel defining layer 151 at the portion overlapping with the non-light-emitting region NLA, and the pixel defining layer 151 may define the opening OP. Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 of the embodiment may be defined by the opening OP.

[0189] The pixel defining layer 151 of the embodiment may be positioned on the second via layer 127 and the anode electrode AE. The pixel defining layer 151 of the embodiment may have an inverted tapered shape. That is, the width of the lower surface of the pixel defining layer 151 oriented toward the second via layer 127 may be smaller than the width of the upper surface of the pixel defining layer 151 oriented toward the organic pattern ELP.

[0190] In the display device 50 according to the embodiment, since the pixel defining layer 151 includes an inverted tapered shape, the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 separated from each other may be formed at portions overlapping with the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 without using a separate fine metal mask.

[0191] The pixel defining layer 151 of the embodiment may include both sides oriented toward the light-emitting region EA and the non-light-emitting region NLA. Both sides of the pixel defining layer 151 according to the embodiment may be completely covered by the cathode electrode CE and may be in contact with the cathode electrode CE.

[0192] In the display device 50 of the embodiment, both sides of the pixel defining layer 151 may be formed to be completely in contact with the cathode electrode CE, so that the contact force between the pixel defining layer 151 and the cathode electrode CE may be improved. Therefore, the display device 50 of the embodiment may solve the separable defect of the pixel defining layer 151 and the cathode electrode CE and the moisture penetration defect of the display device 50 caused by the separable defect.

[0193] In some embodiments, the pixel defining layer 151 may include a first pixel defining layer 151J, a second pixel defining layer 151K, and a third pixel defining layer 151L. In the embodiment, the first pixel defining layer 151J may be disposed toward the first light-emitting region EA1, the second pixel defining layer 151K may be disposed toward the second light-emitting region EA2, and the third pixel defining layer 151L may be disposed toward the third light-emitting region EA3. At a portion overlapping with the non-light-emitting region NLA, the first pixel defining layer 151J and the second pixel defining layer 151K may be separated from each other in a first direction (X-axis direction), and the second pixel defining layer 151K and the third pixel defining layer 151L may be separated from each other in the first direction (X-axis direction). The first pixel defining layer 151J, the second pixel defining layer 151K, and the third pixel defining layer 151L may be integrally formed during the manufacturing process of the display device 10 and then may be formed to be separated from each other by a subsequent etching process.

[0194] The organic pattern ELP of the embodiment may be positioned in contact with the pixel defining layer 151. The organic pattern ELP of the embodiment may be positioned to surround the opening OP simultaneously. The organic pattern ELP of the embodiment may include a first organic pattern ELP1, a second organic pattern ELP2, and a third organic pattern ELP3. The first organic pattern ELP1 may be positioned on the first pixel defining layer 151J, the second organic pattern ELP2 may be positioned on the second pixel defining layer 151K, and the third organic pattern ELP3 may be positioned on the third pixel defining layer 151L.

[0195] In the manufacturing process of the display device 50, the light-emitting layer EL of the embodiment may be formed through a deposition and photolithography process without using a separate fine metal mask. Therefore, in the manufacturing process of the display device 50, the material for forming the light-emitting layer EL may be deposited not only on the anode electrode AE but also on the pixel defining layer 151. That is to say, since the pixel defining layer 151 has an inverted tapered shape, the organic pattern ELP of the embodiment may be a trace formed by disconnecting the material of the light-emitting layer EL deposited on the pixel defining layer 151 from the light-emitting layer EL deposited on the anode electrode AE. In other words, it can be seen that the display device 50 of the embodiment includes the organic pattern ELP on the pixel defining layer 151, and thus the process of forming the light-emitting layer EL is performed through a photolithography process.

[0196] The cover pattern CP of the embodiment may be positioned at a portion overlapping with the pixel defining layer 151 and may be in contact with the cathode electrode CE. The cover pattern CP of the embodiment may be positioned at a portion overlapping with the light-emitting region EA and the non-light-emitting region NLA.

[0197] The cover pattern CP of the embodiment may include a first cover pattern CP1, a second cover pattern CP2, and a third cover pattern CP3. The first cover pattern CP1 may be positioned on the first pixel defining layer 151J, the second cover pattern CP2 may be positioned on the second pixel defining layer 151K, and the third cover pattern CP3 may be positioned on the third pixel defining layer 151L.

[0198] Since the pixel defining layer 151 has an inverted tapered shape, the cover pattern CP of the embodiment may be a trace formed by disconnecting the material of the cover layer CPL deposited on the pixel defining layer 151 from the cover layer CPL deposited on the anode electrode AE. In other words, it can be seen that the display device 50 of the embodiment includes the cover pattern CP on the pixel defining layer 151, and thus the process of forming the cover layer CPL is performed through a photolithography process. Other redundant descriptions will be omitted.

[0199] In addition, the cover pattern CP of the embodiment may include a cover residue pattern CPn. At a portion overlapping with the non-light-emitting region NLA, the cover residue pattern CPn is deposited on the cathode electrode CE at a portion overlapping with a region between the first pixel defining layer 151J and the second pixel defining layer 151K and at a portion overlapping with a region between the second pixel defining layer 151K and the third pixel defining layer 151L. The first cover pattern CP1, the second cover pattern CP2, and the third cover pattern CP3 formed on the bank layer 161 and the cover residue pattern CPn formed between the pixel defining layers 151 may be separated from each other. Other redundant descriptions will be omitted.

[0200] Figures 12 to 22 is a schematic cross-sectional view showing a method of manufacturing a display element layer 150 and a thin film encapsulation layer 170 included in Figure 5 the display device 10.

[0201] Referring to Figure 12 , an anode electrode AE, a sacrificial layer SFL, a pixel defining material layer 151L0, and a bank material layer 161L may be formed on the thin film transistor layer 130. Although not shown in the figure, the thin film transistor layer 130 may be positioned on the substrate 110, and the structure of the thin film transistor layer 130 is the same as that described with reference to Figure 5 . Detailed descriptions of these elements will be omitted.

[0202] The anode electrodes AE may be positioned to be separated from each other on the thin film transistor layer 130. For example, the anode electrodes AE may include a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3. The sacrificial layer SFL may be positioned on each of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The sacrificial layer SFL may help prevent the upper surface of the anode electrode AE from contacting the pixel defining material layer 151L0.

[0203] The sacrificial layer SFL may include an oxide semiconductor. For example, the sacrificial layer SFL may include at least one of indium gallium zinc oxide (IGZO), tin zinc oxide (ZTO), and indium tin oxide (IZO).

[0204] The pixel defining material layer 151L0 may be provided to completely cover the sacrificial layer SFL and the thin film transistor layer 130, and the bank material layer 161L may be positioned to completely cover the pixel defining material layer 151L0.

[0205] According to an embodiment, the pixel defining material layer 151L0 and the bank material layer 161L may include their respective different materials from each other, and the bank material layer 161L may include a material that is more stable than the material of the pixel defining material layer 151L0 with respect to an etching solution. For example, in a case where the pixel defining material layer 151L0 includes silicon oxide, the bank material layer 161L may include titanium (Ti), and in a case where the pixel defining material layer 151L0 includes silicon oxynitride, the bank material layer 161L may include silicon oxide, but the present disclosure is not limited thereto.

[0206] Referring to Figure 13 and Figure 14 , a photoresist PR may be formed on the bank material layer 161L, and a first etching process may be performed using the photoresist PR as a mask. For example, the first etching process may be performed in such a manner that a dry etching process and a wet etching process are alternately performed.

[0207] In this process, portions of the pixel defining material layer 151L0, the bank material layer 161L, and the sacrificial layer SFL on which the photoresist PR is not formed may be removed. Accordingly, a first hole HOL1 may be formed at a portion overlapping each of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3, and a second hole HOL2 may be formed at a portion not overlapping the anode electrode AE.

[0208] In this process, a part of the sacrificial layer SFL may be removed at a portion overlapping the first hole HOL1, and accordingly, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be exposed at a portion overlapping the first hole HOL1. A part of the sacrificial layer SFL that is not removed in this process may remain as the Figure 5 residual pattern 153 shown in

[0209] In this process, the pixel defining material layer 151L0 and the bank material layer 161L may be formed in the form of the pixel defining layer 151 and the bank layer 161 as shown in Figure 5 . As described above, since the bank material layer 161L of the embodiment includes a material that is more stable than the material of the pixel defining material layer 151L0 with respect to an etching process, the bank layer 161 may have end portions TIP protruding from both sides more than both sides of the pixel defining layer 151.

[0210] Through this process, a part of the thin film transistor layer 130 may be exposed again at a portion overlapping the second hole HOL2, and the pixel defining layer 151 may be separated from another pixel defining layer 151 in a first direction (X-axis direction) with the first hole HOL1 and the second hole HOL2 therebetween.

[0211] Referring toFigure 15 , the first light-emitting layer EL1 may be formed on the first anode electrode AE1. In the display device 10 according to the embodiment, since the bank layer 161 includes end portions TIP protruding to both sides, the material for forming the first light-emitting layer EL1 may be formed on the first anode electrode AE1 by a deposition and photolithography process without using a separate fine metal mask.

[0212] The first light-emitting layer EL1 of the embodiment may be performed by a thermal deposition process. The first light-emitting layer EL1 of the embodiment may be formed by depositing at an angle of 45° to 50° from the upper surface of the first anode electrode AE1 by a deposition process. Therefore, the first light-emitting layer EL1 may also be formed on the first anode electrode AE1 positioned under the end portion of the bank layer 161. The first light-emitting layer EL1 may also be in contact with the residual pattern 153 formed on the first anode electrode AE1.

[0213] In this process, the first light-emitting layer EL1 may be deposited on the second anode electrode AE2 and the third anode electrode AE3 at a portion overlapping with the first hole HOL1, may be deposited on the thin-film transistor layer 130 at a portion overlapping with the second hole HOL2, and may also be deposited on the bank layer 161.

[0214] Referring to Figure 16 and Figure 17 , the first temporary blocking layer BR1 may be completely formed on the first light-emitting layer EL1. In a subsequent etching process, the first temporary blocking layer BR1 may protect the first light-emitting layer EL1, the pixel defining layer 151, and the bank layer 161 at a portion overlapping with the first anode electrode AE1. The first temporary blocking layer BR1 may include an inorganic insulating material such as silicon nitride.

[0215] A photoresist PR (see Figure 18 ) may be formed at a portion overlapping with the first anode electrode AE1 and the periphery of the first anode electrode AE1, and a second etching process may be performed using the photoresist PR as a mask. For example, the second etching process may be a dry etching process.

[0216] In this process, the first temporary blocking layer BR1 and the first light-emitting layer EL1 overlapping with the first anode electrode AE1 and the periphery of the first anode electrode AE1 may be retained, and the first light-emitting layer EL1 formed on the bank layer 161 positioned near the first anode electrode AE1 may be formed in the form of the first organic pattern ELP1 shown in Figure 5 .

[0217] In addition, the first temporary barrier layer BR1 and the first light-emitting layer EL1 overlapping with the second anode electrode AE2 and the third anode electrode AE3 can be removed. As a result, the second anode electrode AE2 and the third anode electrode AE3 can be exposed, and the first hole HOL1 can be formed at the portion overlapping with the second anode electrode AE2 and the third anode electrode AE3. In addition, the second hole HOL2 can be formed at the portion not overlapping with the anode electrode AE, and the thin-film transistor layer 130 at the portion overlapping with the second hole HOL2 can be exposed.

[0218] Referring Figure 18 , the above process can be repeated such that the second light-emitting layer EL2 is formed on the second anode electrode AE2. Specifically, the second light-emitting layer EL2 can be deposited not only on the second anode electrode AE2, but also on the first temporary barrier layer BR1 at the portion overlapping with the first anode electrode AE1, and can also be deposited on the third anode electrode AE3 at the portion overlapping with the third anode electrode AE3. In addition, the second light-emitting layer EL2 can also be deposited at the portion not overlapping with the bank layer 161 and the anode electrode AE.

[0219] The second temporary barrier layer BR2 can be completely formed on the second light-emitting layer EL2. In the subsequent etching process, the second temporary barrier layer BR2 can protect the second light-emitting layer EL2, the pixel defining layer 151, and the bank layer 161 at the portion overlapping with the second anode electrode AE2. The second temporary barrier layer BR2 can be deposited not only on the second anode electrode AE2, but also on the first temporary barrier layer BR1 and the third anode electrode AE3. The second temporary barrier layer BR2 can include an inorganic insulating material such as silicon nitride.

[0220] The photoresist PR can be formed at the portion overlapping with the second anode electrode AE2 and the periphery of the second anode electrode AE2, and the second etching process can be performed again using the photoresist PR as a mask. Redundant descriptions will be omitted.

[0221] Referring Figure 18 and Figure 19 , after the third light-emitting layer EL3 is formed on the third anode electrode AE3 by repeating the above process, the third temporary barrier layer BR3 can be formed, the photoresist PR can be formed at the portion overlapping with the third anode electrode AE3 and the periphery of the third anode electrode AE3, and the second etching process can be performed again. Redundant descriptions will be omitted.

[0222] As Figure 19As shown, through the above process, the second temporary blocking layer BR2 and the second light-emitting layer EL2 that overlap with the second anode electrode AE2 and the periphery of the second anode electrode AE2 can be retained, and the second light-emitting layer EL2 formed on the bank layer 161 positioned near the second anode electrode AE2 can be in the form of Figure 5 the second organic pattern ELP2 shown.

[0223] The third temporary blocking layer BR3 and the third light-emitting layer EL3 that overlap with the third anode electrode AE3 and the periphery of the third anode electrode AE3 can be retained, and the third light-emitting layer EL3 formed on the bank layer 161 positioned near the third anode electrode AE3 can be in the form of Figure 5 the third organic pattern ELP3 shown.

[0224] In this process, the second hole HOL2 can be formed at a portion that does not overlap with the anode electrode AE, and a part of the thin film transistor layer 130 can be exposed at the portion that overlaps with the second hole HOL2.

[0225] Referring to Figure 20 , the display device 10 can be introduced into a vacuum chamber so that a third etching process can be performed. For example, the third etching process can be performed by a dry etching process. In this process, the first temporary blocking layer BR1, the second temporary blocking layer BR2, and the third temporary blocking layer BR3 can be removed, and thus the light-emitting layer EL and the organic pattern ELP can be exposed.

[0226] Referring to Figure 21 , the cathode electrode CE can be completely deposited at the portions that overlap with the anode electrode AE, the organic pattern ELP, and the second hole HOL2 while maintaining a vacuum state. The cathode electrode CE of the embodiment can be a completely deposited common electrode. As a result, the cathode electrode CE can completely cover the thin film transistor layer 130 that overlaps with the anode electrode AE, the organic pattern ELP, and the second hole HOL2.

[0227] The cathode electrode CE of the embodiment can be performed by a sputtering or thermal deposition method. The process of forming the cathode electrode CE of the embodiment can have a high step coverage ratio compared to the process of forming the light-emitting layer EL. Therefore, in the display device 10 according to the embodiment, in the process of forming the cathode electrode CE, the light-emitting layer EL, the pixel defining layer 151, the bank layer 161, and the organic pattern ELP can be completely covered.

[0228] Referring to Figure 22, the capping layer CPL can be completely formed on the cathode electrode CE. In the display device 10 according to the embodiment, since the bank layer 161 includes end portions protruding to both sides, even without a separate fine metal mask, the capping layer CPL can be formed as the first capping layer CPL1, the second capping layer CPL2, and the third capping layer CPL3 that are separated from each other at the portions overlapping with the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. Through this process, the material for forming the capping layer CPL formed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be formed by the material forming Figure 5 the first capping layer CPL1, the second capping layer CPL2, and the third capping layer CPL3 shown therein.

[0229] In addition, the material for forming the capping layer CPL can also be formed on the bank layer 161 or on the thin film transistor layer 130 at the portions not overlapping with the anode electrode AE. Through this process, the material of the capping layer CPL formed on the bank layer 161 can be formed in the form of Figure 5 the first capping pattern CP1, the second capping pattern CP2, and the third capping pattern CP3 shown therein, and the material of the capping layer CPL formed at the portions not overlapping with the anode electrode AE can be formed in the form of Figure 5 the capping residue pattern CPn between the pixel defining layers 151 shown therein.

[0230] A first encapsulation layer 171 can be formed to completely cover the capping layer CPL and the capping pattern CP. The first encapsulation layer 171 can be formed by a chemical vapor deposition (CVD) process, and a uniform film can be formed regardless of the step difference of the underlying structure.

[0231] A second encapsulation layer 173 can be formed to flatten the steps included in the first encapsulation layer 171, and a third encapsulation layer 175 can be formed. As a result, the display element layer 150 and the thin film encapsulation layer 170 shown in Figure 5 can be formed.

[0232] The display device 10 according to the embodiment can include a pixel defining layer 151 and a bank layer 161, so as to form the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 that are separated from each other at the portions overlapping with the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The display device 10 according to the embodiment can include a cathode electrode CE that completely covers both sides of the pixel defining layer 151, thereby improving the contact force between the pixel defining layer 151 and the cathode electrode CE. In addition, the display device 10 according to the embodiment can have high contact characteristics between the pixel defining layer 151 and the cathode electrode CE, and can include a first encapsulation layer 171 that completely covers the underlying structure, thereby solving the moisture penetration defect of the display device 10.

[0233] Embodiments have been disclosed herein, and although terms are used, they are used and interpreted only in a general and descriptive sense and not for purposes of limitation. In some instances, unless otherwise specifically noted, features, characteristics, and / or elements described in connection with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, wherein: The display device comprises: A substrate including a light-emitting region and a non-light-emitting region; an anode electrode, on the light emitting region of the substrate; A light-emitting layer, on the anode electrode; a first pixel defining layer on the non-light emitting area of ​​the substrate, the first pixel defining layer comprising a first side oriented toward the light emitting area; a bank layer on the first pixel defining layer, the bank layer including an end portion protruding toward the light emitting region from the first side of the first pixel defining layer; a residual pattern, overlapping the non-luminescent region and disposed between the anode electrode and the first pixel defining layer in a direction perpendicular to the substrate; a cathode electrode on the light emitting layer and the bank layer; and an encapsulation layer on the cathode electrode, wherein The first pixel defining layer and the bank layer are completely covered by the cathode electrode, and The entire first side of the first pixel defining layer physically contacts the cathode electrode.

2. The display device according to claim 1, wherein: The first pixel defining layer further includes a second side facing away from the first side, and The entire second side is in full physical contact with the cathode electrode.

3. The display device according to claim 2, wherein: The cathode electrode physically contacting the first side and the cathode electrode physically contacting the second side are integral with each other.

4. The display device according to claim 2, wherein: The bank layer further includes an end portion protruding beyond the second side.

5. The display device according to claim 4, wherein: The end of the bank layer protruding toward the light emitting region protrudes more than the first side, The end portion of the bank layer protruding from the first side overlaps with the light emitting region, and The end portion of the bank layer protruding beyond the second side overlaps the non-light emitting region.

6. The display device according to claim 4, wherein: The end of the bank layer protruding toward the light emitting region protrudes more than the first side, and The end portion of the bank layer protruding from the first side and the end portion protruding from the second side overlap with the two light emitting regions.

7. The display device according to claim 1, wherein: A height of the first pixel defining layer in the direction perpendicular to the substrate is greater than a height of the bank layer.

8. The display device according to claim 7, wherein: The first pixel defining layer and the bank layer include different materials.

9. The display device according to claim 8, wherein: The first pixel defining layer includes at least one of silicon oxide and silicon oxynitride, and The bank layer includes at least one of titanium, silicon oxide, and silicon oxynitride.

10. The display device according to claim 1, wherein: The display device further includes: an organic pattern between the bank layer and the cathode electrode in the direction perpendicular to the substrate, wherein The organic pattern and the light emitting layer include the same material, The organic pattern is separated from the light emitting layer, and The cathode electrode overlaps the light emitting layer and the organic pattern.

11. The display device according to claim 1, wherein: The bank defines a first opening, The first pixel defining layer defines a second opening, and The first opening is disposed within the second opening.

12. The display device according to claim 11, wherein: In a plan view, the first opening is completely surrounded by the second opening.

13. The display device according to claim 1, wherein: The display device further includes: The second pixel defining layer is spaced apart from the first pixel defining layer in a direction parallel to the substrate by overlapping with the non-light emitting area.

14. The display device according to claim 13, wherein: The substrate includes a first surface oriented toward the anode electrode, and By overlapping with the non-luminescent area, the first surface includes: a first portion, physically contacting the first pixel defining layer; a second portion physically contacting the second pixel defining layer; and A third part is in physical contact with the cathode electrode.

15. The display device according to claim 14, wherein: The first portion and the second portion are spaced apart from each other, and The third portion is disposed between the first portion and the second portion.

16. The display device according to claim 14, wherein: The display device further includes: a cap layer disposed on the cathode electrode at a portion overlapping the light emitting region; and A cap pattern on the bank layer, wherein The cap pattern and the cap layer include the same material, and The capping layer and the capping pattern are spaced apart from each other.

17. A display device, wherein: The display device comprises: A substrate including a light-emitting region and a non-light-emitting region; an anode electrode, on the light emitting region of the substrate; A light-emitting layer, on the anode electrode; a pixel defining layer, on the non-luminescent area of ​​the substrate, the pixel defining layer having an inverse tapered shape; an organic pattern on the pixel defining layer, and the organic pattern is separated from the light emitting layer; a residual pattern overlapping the non-light emitting area and disposed between the anode electrode and the pixel defining layer in a direction perpendicular to the substrate; and A cathode electrode is on the light emitting layer and the organic pattern, wherein: The organic pattern and the light emitting layer include the same material, The cathode electrode completely covers the pixel defining layer and the organic pattern, and Both sides of the pixel defining layer completely physically contact the cathode electrode.

18. The display device according to claim 17, further comprising: a second pixel defining layer, spaced apart from the pixel defining layer in a direction parallel to the substrate by overlapping with the non-luminescent region, Wherein, the second pixel defining layer has an inverse tapered shape.

19. The display device according to claim 18, wherein: The pixel defining layer and the second pixel defining layer physically contact the residual pattern.

20. A method for manufacturing a display device, wherein: The method comprises: forming a substrate including a light-emitting region and a non-light-emitting region, forming an anode electrode on the light-emitting region of the substrate, forming a sacrificial layer on the anode electrode, forming a pixel-defining material layer completely overlapping the substrate and the sacrificial layer, and forming a bank layer completely overlapping the pixel-defining layer; forming a photoresist on the bank layer and performing a first etching process using the photoresist as a mask to form a first hole overlapping the anode electrode and a second hole not overlapping the anode electrode, so that the anode electrode is exposed by overlapping the first hole, the sacrificial layer is formed as a residual pattern, and the bank layer forms an end portion protruding toward both sides than both sides of the pixel defining layer; forming a light emitting layer and a temporary blocking layer completely on the anode electrode and the bank layer and forming a photoresist at a portion overlapping the anode electrode and a periphery of the anode electrode, and removing the light emitting layer and the temporary blocking layer at a portion where the photoresist is not formed by performing a second etching process; and removing the temporary blocking layer disposed on the light emitting layer in a vacuum chamber by a dry etching process, and completely forming a cathode electrode and an encapsulation layer, Wherein, the two sides of the pixel defining layer are completely in physical contact with the cathode electrode.

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