Display device and manufacturing method thereof

Abstract

The invention relates to a display device and a manufacturing method thereof. The display device includes: a first bank pattern over a substrate; a second bank pattern including a side portion that protrudes more than a side portion of the first bank pattern; and a pixel electrode over the second bank pattern.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the same. Background Art

[0002] With the development of the information age, the demand for display devices for displaying images has increased in various forms. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigators, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. In such a flat panel display device, a self-emitting display device includes light emitting elements, where each of the pixels in the display panel can emit light by itself, so that an image is displayed even without a backlight unit that provides light to the display panel.

[0003] Recently, display devices have been applied to glasses-type devices for providing virtual reality and augmented reality. To be applied to glasses-type devices, the display device may be implemented in a very small size of about 2 inches or less, but it should have a high pixel integration so that it can be implemented at a high resolution. For example, the display device may have a high pixel integration of about 1000 pixels per inch (PPI) or more.

[0004] As described above, the display device is implemented in a very small size, but when the display device has a high pixel integration, the area of the light emitting region where the light emitting elements are located may be reduced. Therefore, it may be difficult to implement light emitting elements separated for each light emitting region through a mask process. Summary of the Invention

[0005] One aspect of the present disclosure provides a display device capable of forming pixel electrodes spaced apart from each other without performing a mask process.

[0006] Another aspect of the present disclosure provides a light emitting element having a narrow non-display region.

[0007] Aspects of the present disclosure are not limited to those mentioned above, and additional aspects of the present disclosure not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0008] According to one or more embodiments of the present disclosure, a display device includes: a first bank pattern above a substrate; a second bank pattern including sides protruding farther than sides of the first bank pattern; and a pixel electrode above the second bank pattern.

[0009] The first bank pattern and the second bank pattern may include different metals or alloys.

[0010] The first bank pattern may include aluminum or an aluminum alloy, and the second bank pattern includes titanium or a titanium alloy.

[0011] The substrate may include a first light-emitting region and a second light-emitting region spaced apart from each other, wherein the display device further includes a residual pattern in a space between the first light-emitting region and the second light-emitting region.

[0012] The residual pattern may include the same material as the pixel electrode.

[0013] The residual pattern may be lower than the second bank pattern.

[0014] The display device may further include a pixel defining layer that surrounds the first bank pattern, the second bank pattern, and the pixel electrode in a plan view and is above the residual pattern.

[0015] The pixel defining layer may be on a lower surface of the second bank pattern.

[0016] A distance between a side of the first bank pattern and a side of the second bank pattern may be greater than a thickness of the first bank pattern.

[0017] The distance between the side of the first bank pattern and the side of the second bank pattern may be about three to about five times the thickness of the first bank pattern.

[0018] The pixel electrode may be on an upper surface and a side of the second bank pattern.

[0019] The pixel electrode may include: a first layer including a metal, above the second bank pattern; and a second layer including a transparent conductive oxide (TCO), above the first layer.

[0020] The pixel electrode may further include a third layer including a transparent conductive oxide, between the second bank pattern and the first layer.

[0021] The display device may further include a first interlayer insulating layer between the substrate and the first bank pattern in the first light-emitting region and in the second light-emitting region.

[0022] The first interlayer insulating layer in the first light-emitting region may be spaced apart from the first interlayer insulating layer in the second light-emitting region, wherein the residual pattern is in a gap space of the first interlayer insulating layer.

[0023] The first bank pattern and the second bank pattern may include island patterns.

[0024] According to one or more embodiments of the present disclosure, a display device includes: a substrate including light-emitting regions spaced apart from each other; a first bank pattern above the substrate in the light-emitting regions; a second bank pattern above the first bank pattern and including side portions protruding farther than side portions of the first bank pattern; a pixel electrode above the second bank pattern; a residual pattern above the substrate between the light-emitting regions; a pixel defining layer above the residual pattern and the pixel electrode; and a light-emitting layer above the pixel electrode and the pixel defining layer.

[0025] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes: forming a first bank layer above a substrate; forming a second bank layer above the first bank layer; removing a portion of the second bank layer and a portion of the first bank layer; etching side portions of the first bank layer to expose a portion of a lower surface of the second bank layer; forming a pixel electrode above the second bank layer; and forming a residual pattern above the substrate.

[0026] Forming a pixel electrode above the second bank layer and forming a residual pattern above the substrate may include: dividing a material deposited on the substrate into a pixel electrode and a residual pattern by disconnecting the material deposited on the substrate by protruding side portions of the second bank layer, the protruding side portions of the second bank layer extending farther than etched side portions of the first bank layer.

[0027] Removing a portion of the second bank layer and a portion of the first bank layer may include: forming a mask pattern above the second bank layer; and etching the second bank layer and the first bank layer in regions not covered by the mask pattern.

[0028] In a display device and a manufacturing method thereof according to one or more embodiments, a bank structure with an undercut structure is provided under a pixel electrode, whereby a gap between pixel electrodes can be reduced and high resolution can be achieved.

[0029] Aspects of embodiments according to the present disclosure are not limited to those mentioned above, and more different aspects are included in the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which: Figure 1 is a perspective view showing a head-mounted display device according to one or more embodiments; Figure 2 is a perspective view showing Figure 1 an example of the head-mounted display device; Figure 3 is a perspective view showing a head-mounted display device according to one or more embodiments; Figure 4 is an exploded perspective view showing a display device according to one or more embodiments; Figure 5 is a cross-sectional view showing an example of cutting a part of a display panel according to one or more embodiments; Figure 6 is a view showing Figure 5 an enlarged view of region A1 of; Figures 7 to 9 is a cross-sectional view showing a part of a display panel according to one or more embodiments; and Figures 10 to 16 is a cross-sectional view sequentially showing the process of manufacturing a display device according to one or more embodiments. DETAILED DESCRIPTION

[0031] Aspects of some embodiments of the present disclosure and methods of implementing the same can be more easily understood by referring to the detailed description of the embodiments and the accompanying drawings. The described embodiments are provided by way of example so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, irrelevant to the description of the embodiments, or unnecessary for those of ordinary skill in the art to fully understand the aspects of the present disclosure may be omitted. Unless otherwise stated, in all the drawings and the written description, the same reference numerals, characters, or combinations thereof represent the same elements, and thus, their repeated description may be omitted.

[0032] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "may", "can", or "may not" when describing the embodiments corresponds to one or more embodiments of the present disclosure.

[0033] Taking the present disclosure as a whole, those of ordinary skill in the art will understand that the present disclosure covers all modifications, equivalents, and substitutions within the spirit and technical scope of the present disclosure. Each of the features of the embodiments of the present disclosure may be partially or wholly combined with each other, and various close combinations and operations are technically possible, and each embodiment may be implemented independently of each other, or may be implemented in association with each other, unless otherwise stated or implied.

[0034] In the drawings, for clarity and / or for purposes of description, the relative dimensions of elements, layers, and regions may be exaggerated. Additionally, cross-hatching and / or shading are generally used in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, ratio, commonality between illustrated elements, and / or any other characteristic, attribute, property, etc. of the elements.

[0035] Various embodiments are described herein with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. As such, deviations from the illustrated shapes, for example due to manufacturing techniques and / or tolerances, are to be expected. Additionally, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments in accordance with the concepts of the present disclosure. Thus, the embodiments disclosed herein should not be construed as being limited to the shown shapes of elements, layers, or regions, but will include, for example, deviations in shape resulting from manufacturing.

[0036] For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of implantation concentration, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs.

[0037] For ease of explanation, spatial relative terms such as "below", "beneath", "lower", "bottom", "under", "above", "upper", "top", etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below", "beneath", or "under" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an above and a below orientation. The device may have additional orientations (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being disposed "on" a second part, this indicates that the first part is disposed at the upper or lower side of the second part, and is not limited to the upper side based on the direction of gravity.

[0038] In addition, the phrase "in a plan view" means when the object part is viewed from above, and the phrase "in a schematic cross-sectional view" means when the schematic cross-section obtained by vertically cutting the object part is viewed from the side. The term "overlap" or "overlapped" means that the first object can be above or below the second object, or on one side of the second object, and means that the second object can be above or below the first object, or on one side of the first object. Additionally, the term "overlap" can include stacking, facing or being oriented towards, extending over, covering or partially covering, or any other suitable term as would be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separate from", "set beside", "offset from", and any other suitable equivalents as would be understood and appreciated by one of ordinary skill in the art. The terms "face" and "be oriented towards" can mean that the first object can be directly or indirectly opposite the second object. In the case where a third object is interposed between the first object and the second object, the first object and the second object can be understood to be indirectly opposite each other but still face each other.

[0039] It will be understood that when an element, layer, region, or component is referred to as being "formed on", "on", "connected to", or "(operatively or communicatively) coupled to" another element, layer, region, or component, it can be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component such that there can be one or more intervening elements, layers, regions, or components. Additionally, this can generally mean a direct or indirect connection or coupling, and an integral or non-integral connection or coupling. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it can be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or there can be one or more intervening layers, regions, or components. One or more intervening components can include switches, resistors, capacitors, etc. In describing embodiments, unless explicitly described as a direct connection, the expression of connection indicates an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or coupled to another component or directly on another component without an intermediate component.

[0040] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the forming direction is not limited to the upward direction, but includes forming the part on a side surface or in the downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly below" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components, such as "between...", "directly between...", "adjacent to", and "directly adjacent to", can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intermediate elements or layers.

[0041] For the purposes of this disclosure, when located after a list of elements, expressions such as "at least one of...", "any of...", or "one or more of..." modify the elements of the entire list rather than individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, or only Y, or only Z, or any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ), or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, when located before or after a list of elements, expressions such as "at least one of...", "a plurality of", "one of...", and other prepositional phrases modify the elements of the entire list rather than individual elements in the list.

[0042] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms do not correspond to a particular order, position or priority, but are only used to distinguish one element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Thus, without departing from the scope of the present disclosure, the first element, first component, first region, first layer or first part described below may be referred to as a second element, second component, second region, second layer or second part. Describing an element as a "first" element may not require or may not imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish different categories or different groups of elements. For the sake of brevity, the terms "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0043] In an example, the X-axis, Y-axis and / or Z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. This also applies to the first direction DR1, the second direction DR2 and / or the third direction DR3.

[0044] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, while the plural forms are intended to also include the singular forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes" and "including" specify the presence of the recited features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0045] When one or more embodiments can be implemented differently, a particular order of processing may be performed differently from the order described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the order described.

[0046] As used herein, the terms "substantially", "about", "approximate" and similar terms are used as approximating terms and not as terms of degree, and are intended to account for the inherent deviations in the values being measured or calculated that would be recognized by a person of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Given the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximate" includes the stated value and means within an acceptable deviation of the particular value as determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within + / - 30%, + / - 20%, + / - 10%, + / - 5% of the stated value. Additionally, "may" as used in describing embodiments of the present disclosure means "one or more embodiments of the present disclosure".

[0047] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0048] Figure 1 is a perspective view showing a head-mounted display device according to one or more embodiments. Figure 2 is showing Figure 1 an exploded perspective view of an example of the head-mounted display device.

[0049] Referring Figure 1 and Figure 2 , a head-mounted display device 1 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing portion 110, a storage cover (e.g., a display device housing cover) 120, a first eyepiece 131, a second eyepiece 132, a head mounting strap 140, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170, and a connector.

[0050] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 that will be described with reference to Figure 4 and Figure 5 . Accordingly, the description of the first display device 10_1 and the second display device 10_2 will be replaced by the description made with reference to Figure 4 and Figure 5 .

[0051] The first optical member 151 may be located between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be located between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0052] The intermediate frame 160 may be located between the first display device 10_1 and the control circuit board 170, and may be located between the second display device 10_2 and the control circuit board 170. The intermediate frame 160 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0053] The control circuit board 170 may be located between the intermediate frame 160 and the display device housing portion 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may convert an image source input from the outside into digital video data, and may transmit the digital video data to the first display device 10_1 and the second display device 10_2 through the connector.

[0054] The control circuit board 170 may transmit digital video data corresponding to a left-eye image suitable for the user's left eye to the first display device 10_1, and may transmit digital video data corresponding to a right-eye image suitable for the user's right eye to the second display device 10_2. Optionally, the control circuit board 170 may transmit the same digital video data to the first display device 10_1 and the second display device 10_2.

[0055] The display device housing portion 110 is used to house the first display device 10_1, the second display device 10_2, the intermediate frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The storage cover 120 is positioned to cover an opening surface of the display device housing portion 110. The first eyepiece 131 and the second eyepiece 132 may be located in the storage cover 120, with the user's left eye located in the first eyepiece 131 and the user's right eye located in the second eyepiece 132. Although Figure 1 and Figure 2 the first eyepiece 131 and the second eyepiece 132 are shown positioned separately, the present disclosure is not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be combined into one.

[0056] The first eyepiece 131 can be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 can be aligned with the second display device 10_2 and the second optical member 152. Accordingly, the user can view the image of the first display device 10_1 through the first eyepiece 131, which is magnified into a virtual image by the first optical member 151, and the user can view the image of the second display device 10_2 through the second eyepiece 132, which is magnified into a virtual image by the second optical member 152.

[0057] The head mounting band 140 is for fixing the display device housing part 110 to the user's head such that the first eyepiece 131 and the second eyepiece 132 in the storage cover 120 are respectively positioned over the user's left eye and right eye. When the display device housing part 110 is implemented to be lightweight and small, the head-mounted display device 1 can include, as Figure 3 shown, a spectacle frame instead of the head mounting band 140.

[0058] In addition, the head-mounted display device 1 may further include a battery for providing power, an external memory slot capable of accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a Universal Serial Bus (USB) terminal, a DisplayPort, or a High-Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi ® module, or a Bluetooth ® (Bluetooth) module (Wi-Fi ® is a registered trademark of the non-profit Wi-Fi Alliance, and Bluetooth ® (Bluetooth) is a registered trademark of Bluetooth Sig, Inc., Kirkland, WA).

[0059] Figure 3 is a perspective view showing a head-mounted display device according to one or more embodiments.

[0060] Refer to Figure 3 , the head-mounted display device 1_1 according to one or more embodiments may be a glasses-type display device, in which the display device housing part 120_1 is implemented to be lightweight and small. The head-mounted display device 1_1 according to one or more embodiments may include a display device 10_3, a left spectacle lens 311, a right spectacle lens 312, a support frame 350, temple arms 341 and 342, an optical member 320, an optical path conversion member 330, and a display device housing part 120_1.

[0061] Figure 3 The shown display device 10_3 is the same as that in the referenceFigure 4 and Figure 5 is substantially the same as the display device 10 described. Accordingly, the description of the display device 10_3 will be replaced by the description made with reference to Figure 4 and Figure 5 Thereby.

[0062] The display device accommodation part 120_1 can accommodate the display device 10_3, the optical member 320, and the optical path conversion member 330. The image displayed on the display device 10_3 can be magnified by the optical member 320, and the optical path can be converted by the optical path conversion member 330 so that the image can be provided to the right eye of the user through the right eyepiece 312. For this purpose, the user can view an augmented reality image in which the virtual image displayed on the display device 10_3 and the real image viewed through the right eyepiece 312 are combined through the right eye.

[0063] Although Figure 3 it is shown that the display device accommodation part 120_1 is located at the right end of the support frame 350, the present disclosure is not limited thereto. For example, the display device accommodation part 120_1 can be located at the left end of the support frame 350, and in this case, the image of the display device 10_3 can be provided to the left eye of the user. Alternatively, the display device accommodation part 120_1 can be located at both the left end and the right end of the support frame 350, and in this case, the user can view the image displayed on the display device 10_3 through both the left eye and the right eye.

[0064] Figure 4 is an exploded perspective view showing a display device according to one or more embodiments.

[0065] Referring to Figure 4 , the display device 10 according to one or more embodiments is a device for displaying moving images or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic diaries, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied to televisions, laptop computers, monitors, signboards, or display units of Internet of Things (IoT) devices. In addition, the display device 10 can be applied to smart watches, watch phones, and head-mounted displays (HMDs) for realizing virtual reality and augmented reality.

[0066] The display device 10 according to one or more embodiments includes a display panel 410, a heat dissipation layer 420, a circuit board 430, a driving circuit 440, and a power supply circuit 450.

[0067] The display panel 410 may be formed in a planar shape similar to a rectangular shape. For example, the display panel 410 may have a planar shape similar to a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2. Corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect in the display panel 410 may be rounded to have a curvature (e.g., a predetermined curvature), or formed at right angles. The planar shape of the display panel 410 may be formed to be similar to other polygonal shapes, circular shapes, or elliptical shapes, and is not limited to the rectangular shape. The planar shape of the display device 10 may follow the planar shape of the display panel 410, but the present disclosure is not limited thereto.

[0068] The display panel 410 includes a display area for displaying an image and a non-display area for not displaying an image.

[0069] The display area includes a plurality of pixels, and each of the pixels includes a plurality of sub-pixels ( Figure 5 SP1, SP2, and SP3). The plurality of sub-pixels SP1, SP2, and SP3 include a plurality of pixel transistors. The plurality of pixel transistors may be formed by a semiconductor process and may be located on a semiconductor substrate ( Figure 5 SSUB) (as used herein, "located on" may mean "above"). For example, the plurality of pixel transistors may be formed of complementary metal oxide semiconductor (CMOS).

[0070] The heat dissipation layer 420 may overlap the display panel 410 in a third direction DR3 (which is the thickness direction of the display panel 410). The heat dissipation layer 420 may be located on one surface (e.g., the rear surface) of the display panel 410. The heat dissipation layer 420 is used to dissipate heat generated from the display panel 410. The heat dissipation layer 420 may include graphite having high thermal conductivity or a metal layer such as silver (Ag), copper (Cu), or aluminum (Al).

[0071] The circuit board 430 may be electrically connected to a plurality of pads in a pad area of the display panel 410 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board or a flexible film having a flexible material. Although Figure 4 the circuit board 430 is shown unfolded, the circuit board 430 may be bent. In this case, one end of the circuit board 430 may be located on the rear surface of the display panel 410. One end of the circuit board 430 may be opposite to the other end of the circuit board 430, and the other end of the circuit board 430 is connected to a plurality of pads in the pad area of the display panel 410 by using a conductive adhesive member.

[0072] The driving circuit 440 can receive digital video data and timing signals from the outside. The driving circuit 440 can generate a scan timing control signal, a transmission timing control signal, and a data timing control signal, which are intended to control the display panel 410 according to the timing signals.

[0073] The power supply circuit 450 can generate a plurality of panel driving voltages based on a power voltage from the outside. For example, the power supply circuit 450 can generate a first driving voltage, a second driving voltage, and a third driving voltage, and can supply them to the display panel 410.

[0074] Each of the driving circuit 440 and the power supply circuit 450 can be formed of an integrated circuit (IC) and can be attached to one surface of the circuit board 430.

[0075] Figure 5 is a cross-sectional view showing an example of cutting a part of the display panel according to one or more embodiments. For example, Figure 5 shows including Figure 5 a partial cross-sectional structure of a display area of a plurality of sub-pixels SP1, SP2, and SP3.

[0076] Reference Figure 5 In one or more embodiments, the display panel 410 may include a semiconductor backplane SBP, a light-emitting element backplane EBP, a light-emitting element layer EML, a packaging layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate.

[0077] The semiconductor backplane SBP includes a semiconductor substrate SSUB, a plurality of pixel transistors PTR disposed on the semiconductor substrate SSUB, a plurality of semiconductor insulating layers SINS1, SINS2, and SINS3 covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR.

[0078] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions may be located on the upper surface of the semiconductor substrate SSUB. The plurality of well regions may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Optionally, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0079] Each of the plurality of well regions includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH located between the source region SA and the drain region DA.

[0080] Each of the source region SA and the drain region DA may be doped with a second type of impurity. The gate electrode GE of the pixel transistor PTR may overlap with the well region in the third direction DR3. The channel region CH may overlap with the gate electrode GE in the third direction DR3. The source region SA may be located at one side of the gate electrode GE, and the drain region DA may be located at the other side of the gate electrode GE.

[0081] The first semiconductor insulating layer SINS1 may be located on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 may be formed of an inorganic film of silicon carbonitride (SiCN) or silicon oxide (SiO x )), but the present disclosure is not limited thereto.

[0082] The second semiconductor insulating layer SINS2 may be located on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be formed of an inorganic film of silicon oxide (SiO x )), but the present disclosure is not limited thereto.

[0083] A plurality of contact terminals CTE may be located on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The contact terminal CTE may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0084] The third semiconductor insulating layer SINS3 may be located on the side of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may be exposed and not covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be formed of an inorganic film of silicon oxide (SiO x )), but the present disclosure is not limited thereto.

[0085] The semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate (such as a polyimide substrate). In this case, the thin film transistor may be located on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that is not bent, and the polymer resin substrate may be a flexible substrate that can be bent or curved.

[0086] The light-emitting element backplane EBP may include a first metal layer ML1, a second metal layer ML2, a third metal layer ML3, a fourth metal layer ML4, a fifth metal layer ML5, a sixth metal layer ML6, a seventh metal layer ML7, an eighth metal layer ML8, a plurality of vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, VA8, and VA9, and a plurality of interlayer insulating layers INS1 to INS10.

[0087] The first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7, and the eighth metal layer ML8 are used to implement the circuits of the sub-pixels SP1, SP2, and SP3 by connecting a plurality of contact terminals CTE exposed from the semiconductor backplane SBP.

[0088] The first interlayer insulating layer INS1 may be located on the semiconductor backplane SBP. The first via VA1 may be connected to the contact terminal CTE exposed from the semiconductor backplane SBP by passing through the first interlayer insulating layer INS1. The first metal layer ML1 may be located on the first interlayer insulating layer INS1 and may be connected to the first via VA1.

[0089] The second interlayer insulating layer INS2 may be located on the first interlayer insulating layer INS1 and the first metal layer ML1. The second via VA2 may be connected to the exposed first metal layer ML1 by passing through the second interlayer insulating layer INS2. The second metal layer ML2 may be located on the second interlayer insulating layer INS2 and may be connected to the second via VA2.

[0090] The third interlayer insulating layer INS3 may be located on the second interlayer insulating layer INS2 and the second metal layer ML2. The third via VA3 may be connected to the exposed second metal layer ML2 by passing through the third interlayer insulating layer INS3. The third metal layer ML3 may be located on the third interlayer insulating layer INS3 and may be connected to the third via VA3.

[0091] The fourth interlayer insulating layer INS4 may be located on the third interlayer insulating layer INS3 and the third metal layer ML3. The fourth via VA4 may be connected to the exposed third metal layer ML3 by passing through the fourth interlayer insulating layer INS4. The fourth metal layer ML4 may be located on the fourth interlayer insulating layer INS4 and may be connected to the fourth via VA4.

[0092] The fifth interlayer insulating layer INS5 may be located on the fourth interlayer insulating layer INS4 and the fourth metal layer ML4. The fifth via VA5 may be connected to the exposed fourth metal layer ML4 by passing through the fifth interlayer insulating layer INS5. The fifth metal layer ML5 may be located on the fifth interlayer insulating layer INS5 and may be connected to the fifth via VA5.

[0093] The sixth interlayer insulating layer INS6 can be located on the fifth interlayer insulating layer INS5 and the fifth metal layer ML5. The sixth via hole VA6 can be connected to the exposed fifth metal layer ML5 by passing through the sixth interlayer insulating layer INS6. The sixth metal layer ML6 can be located on the sixth interlayer insulating layer INS6 and can be connected to the sixth via hole VA6.

[0094] The seventh interlayer insulating layer INS7 can be located on the sixth interlayer insulating layer INS6 and the sixth metal layer ML6. The seventh via hole VA7 can be connected to the exposed sixth metal layer ML6 by passing through the seventh interlayer insulating layer INS7. The seventh metal layer ML7 can be located on the seventh interlayer insulating layer INS7 and can be connected to the seventh via hole VA7.

[0095] The eighth interlayer insulating layer INS8 can be located on the seventh interlayer insulating layer INS7 and the seventh metal layer ML7. The eighth via hole VA8 can be connected to the exposed seventh metal layer ML7 by passing through the eighth interlayer insulating layer INS8. The eighth metal layer ML8 can be located on the eighth interlayer insulating layer INS8 and can be connected to the eighth via hole VA8.

[0096] The contact terminal CTE of the semiconductor backplane SBP and the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 of the light-emitting element backplane EBP can be connected to the drain region DA, the source region SA, and the gate electrode GE of the pixel transistor PTR. The seventh metal layer ML7 and the eighth metal layer ML8 can be not connected to the source region SA and the gate electrode GE, but can be connected to the drain region DA.

[0097] The first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7, and the eighth metal layer ML8, as well as the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7, and the eighth via VA8 may include substantially the same material. The first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7, and the eighth metal layer ML8, as well as the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7, and the eighth via VA8 may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The first interlayer insulating layer INS1, the second interlayer insulating layer INS2, the third interlayer insulating layer INS3, the fourth interlayer insulating layer INS4, the fifth interlayer insulating layer INS5, the sixth interlayer insulating layer INS6, the seventh interlayer insulating layer INS7, the eighth interlayer insulating layer INS8, and the ninth interlayer insulating layer INS9 may include an inorganic film of silicon oxide (SiO x ), but the present disclosure is not limited thereto.

[0098] The thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6, respectively. Each of the thicknesses of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thicknesses of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be substantially the same as each other.

[0099] Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the seventh via hole VA7 and the thickness of the eighth via hole VA8. Each of the thickness of the seventh via hole VA7 and the thickness of the eighth via hole VA8 may be greater than each of the thickness of the first via hole VA1, the thickness of the second via hole VA2, the thickness of the third via hole VA3, the thickness of the fourth via hole VA4, the thickness of the fifth via hole VA5, and the thickness of the sixth via hole VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same as each other.

[0100] The ninth interlayer insulating layer INS9 may be located on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. The ninth interlayer insulating layer INS9 may be formed of an inorganic layer based on silicon oxide (SiO x ), but the present disclosure is not limited thereto.

[0101] Each of the ninth via holes VA9 may be connected to the exposed eighth metal layer ML8 by passing through the ninth interlayer insulating layer INS9. The ninth via holes VA9 may be formed of aluminum (Al) or an aluminum alloy.

[0102] The tenth interlayer insulating layer INS10 may be located on the ninth interlayer insulating layer INS9. The tenth interlayer insulating layer INS10 may overlap with the pixel electrodes AND of the light-emitting regions EA1, EA2, and EA3 to be described later, and the tenth interlayer insulating layer INS10 may be spaced apart from each other. The tenth interlayer insulating layer INS10 may be formed of an inorganic layer based on silicon nitride (SiN x ), but the present disclosure is not limited thereto. The ninth via holes VA9 may pass through the tenth interlayer insulating layer INS10.

[0103] The light-emitting element layer EML may be located on the light-emitting element backplane EBP. The light-emitting element layer EML may include a bank structure BNS, light-emitting elements, and a pixel defining layer PDL, wherein the light-emitting elements include pixel electrodes AND, light-emitting layers IL1, IL2, and IL3, and a common electrode CAT.

[0104] Figure 6 is an enlarged view of region A1 showing Figure 5 and shows the bank structure BNS, the light-emitting elements, and the pixel defining layer PDL of the light-emitting element layer EML.

[0105] Reference Figure 5 and Figure 6, the bank structure BNS may be located on the tenth interlayer insulating layer INS10 and may include a first bank pattern BN1 and a second bank pattern BN2. The bank structure BNS may overlap each of the light-emitting regions EA1, EA2, and EA3.

[0106] The bank structure BNS may be located on the tenth interlayer insulating layer INS10. The bank structure BNS may include a first bank pattern BN1 and a second bank pattern BN2 stacked in sequence. The bank structure BNS may include a plurality of patterns separated or spaced apart from each other, and each of the spaced-apart patterns of the bank structure BNS may overlap with one of the light-emitting regions EA1, EA2, or EA3. Due to the spaced-apart patterns of the bank structure BNS, separate pixel electrodes AND can be formed without a mask.

[0107] The first bank pattern BN1 may be located on the tenth interlayer insulating layer INS10. The first bank pattern BN1 may include a plurality of patterns, and the corresponding patterns may be spaced apart from each other. In one or more embodiments, the first bank pattern BN1 may be an island pattern. The planar shape of each island of the first bank pattern BN1 may be circular or a polygon such as a triangle and a square. The first bank pattern BN1 may be connected to the ninth via VA9. The first bank pattern BN1 and the ninth via VA9 may include the same material.

[0108] The first bank pattern BN1 may be located within each of the light-emitting regions EA1, EA2, and EA3. The first bank pattern BN1 of the first light-emitting region EA1, the first bank pattern BN1 of the second light-emitting region EA2, and the first bank pattern BN1 of the third light-emitting region EA3 may be spaced apart from each other.

[0109] The sides of the first bank pattern BN1 may be recessed much more towards the center of the light-emitting regions EA1, EA2, and EA3 than the sides of the second bank pattern BN2 and the sides of the pixel electrode AND.

[0110] The second bank pattern BN2 may be located on the first bank pattern BN1. The second bank pattern BN2 may include a plurality of patterns that may be spaced apart from each other. One second bank pattern BN2 may be formed on the upper surface of each of the plurality of first bank patterns BN1. In the same manner as the first bank pattern BN1, the second bank pattern BN2 may be separated or spaced apart from each other. The second bank pattern BN2 of the first light-emitting region EA1, the second bank pattern BN2 of the second light-emitting region EA2, and the second bank pattern BN2 of the third light-emitting region EA3 may be spaced apart from each other. In one or more embodiments, the second bank pattern BN2 may be an island pattern.

[0111] The second bank pattern BN2 may include a tip TIP, which is a region that protrudes much farther than the first bank pattern BN1. The width of the second bank pattern BN2 may be greater than the width of the first bank pattern BN1. The sides of the second bank pattern BN2 may protrude farther than the sides of the first bank pattern BN1 in a direction opposite to the direction oriented toward the centers of the light-emitting regions EA1, EA2, and EA3. Since the sides of the second bank pattern BN2 have a shape that protrudes farther than the sides of the first bank pattern BN1, an undercut structure of the first bank pattern BN1 may be formed below the tip TIP of the second bank pattern BN2. A part of the lower surface of the second bank pattern BN2 and the lower surface of the tip TIP may be exposed and not covered by the first bank pattern BN1.

[0112] To fabricate the ultra-high resolution display device 10, the gap between the pixel electrodes AND may be very narrow. To fabricate the pixel electrodes AND through a mask process, a structure for holding the mask may be required, or an unnecessarily wide non-display area may be required to control the dispersion according to the mask process. In addition, when the pixel electrodes AND are fabricated through a wet etching process, due to etch skew, the width of the pixel electrodes AND may be narrower than the target width, and the non-display area may be widened.

[0113] Since the bank structure BNS of the display device 10 according to one or more embodiments includes a tip TIP and an undercut portion, layers spaced apart from each other may be formed on top of the bank structure BNS through a deposition process instead of a mask process. For example, even if the pixel electrodes AND are formed through a deposition process without using a mask, the material deposited on the entire surface of the display device 10 may be disconnected between the light-emitting regions EA1, EA2, and EA3 by the tip TIP of the second bank pattern BN2 and not connected. In addition, the etching process after the mask process may be omitted. In the display device 10, unnecessary elements such as a structure for holding the mask may be omitted, and the non-display area for dispersion control may be reduced or minimized. In addition, the interval between pixels may be reduced, thereby enabling an extremely high resolution.

[0114] The lateral shapes of the first bank pattern BN1 and the second bank pattern BN2 may have a structure in which the first bank pattern BN1 and the second bank pattern BN2 include different materials and are formed due to different etching rates during the etching process. According to one or more embodiments, the second bank pattern BN2 may include a material having an etching rate slower than that of the first bank pattern BN1, and the first bank pattern BN1 may be further etched during the etching process, whereby an undercut portion may be formed below the tip TIP of the second bank pattern BN2.

[0115] The first bank pattern BN1 and the second bank pattern BN2 may include different metals or alloys. In one or more embodiments, the first bank pattern BN1 may include aluminum (Al) or an aluminum alloy, and the second bank pattern BN2 may include titanium (Ti) or a titanium alloy.

[0116] The distance d2 between the side of the first bank pattern BN1 and the side of the second bank pattern BN2 (i.e., the width d2 on the lower surface of the tip TIP of the second bank pattern BN2) may be greater than the thickness d1 of the first bank pattern BN1. In one or more embodiments, the distance d2 between the side of the first bank pattern BN1 and the side of the second bank pattern BN2 may be about three to about five times the thickness d1 of the first bank pattern BN1. Within this range, when depositing the pixel electrode AND, the pixel electrode AND is not formed on the side of the first bank pattern BN1, and the possibility of short - circuit of the light - emitting element can be reduced or prevented.

[0117] The light - emitting element may be located on the second bank pattern BN2 and may include a pixel electrode AND, light - emitting layers IL1, IL2, and IL3, and a common electrode CAT, respectively. The light - emitting regions EA1, EA2, and EA3 are regions where the pixel electrode AND, the light - emitting layers IL1, IL2, and IL3, and the common electrode CAT are sequentially stacked, and may be defined by a pixel defining layer PDL described later.

[0118] The pixel electrode AND may be located on the second bank pattern BN2. The pixel electrode AND may be electrically connected to the ninth via VA9 through a conductive bank structure BNS, and then may be connected to the drain region DA or the source region SA of the pixel transistor PTR through the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7, the eighth via VA8, the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7, and the eighth metal layer ML8, and the contact terminal CTE.

[0119] The pixel electrode AND may be located not only on the upper surface of the second bank pattern BN2 but also on the side(s) of the second bank pattern BN2. The pixel electrode AND may be formed by a sputtering process, and a part of the pixel electrode AND may also be formed on the side(s) of the second bank pattern BN2.

[0120] The pixel electrode AND can be made of any one of metals such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a transparent conductive oxide (TCO), or a metal alloy. One or more of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc indium tin oxide (ZITO), indium gallium zinc oxide (IGZO), and zinc tin oxide (ZTO) can be used as materials for the transparent conductive oxide (TCO).

[0121] The pixel electrode AND can have a single-layer structure or a multi-layer structure. In one or more embodiments, the pixel electrode AND can have a multi-layer structure. The pixel electrode AND can include a first layer AND1 and a second layer AND2. The first layer AND1 is located on the second bank pattern BN2 and includes a metal, and the second layer AND2 is located on the first layer AND1 and includes a transparent conductive oxide (TCO). In one or more embodiments, the first layer AND1 can include silver (Ag), and the second layer AND2 can include ITO.

[0122] The residual patterns RSD1 and RSD2 can be located on the ninth interlayer insulating layer INS9 in the gap space between the plurality of light-emitting regions EA1, EA2, and EA3.

[0123] The material deposited on the entire surface of the semiconductor substrate SSUB during the deposition of the pixel electrode AND is disconnected by the tip TIP of the second bank pattern BN2, and the residual patterns RSD1 and RSD2 are formed on the ninth interlayer insulating layer INS9. The residual patterns RSD1 and RSD2 can be located in the gap space of the tenth interlayer insulating layer INS10 and can overlap with the gap space or gap between the pixel electrodes AND. The residual patterns RSD1 and RSD2 can be located at a position or level lower than the position or level of the second bank pattern BN2.

[0124] The residual patterns RSD1 and RSD2 can include the same material as the material of the pixel electrode AND. When the pixel electrode AND has a multi-layer structure, the residual patterns RSD1 and RSD2 can also have a multi-layer structure, and the stacking structure of the residual patterns RSD1 and RSD2 can be the same as the stacking structure of the pixel electrode AND. In one or more embodiments, the residual patterns RSD1 and RSD2 can include a first residual pattern RSD1, which is located on the ninth interlayer insulating layer INS9 and includes the same material as the material of the first layer AND1, and can include a second residual pattern RSD2, which is located on the first residual pattern RSD1 and includes the same material as the material of the second layer AND2.

[0125] Figure 7is a cross-sectional view showing a part of a display panel according to one or more embodiments. Figure 7 is a magnified view showing a region A1' corresponding to region A1 of Figure 5 . Figure 7 is different from Figure 6 in that the pixel electrode AND' further includes a third layer AND3 at its lower part.

[0126] The third layer AND3 may be located between the second bank pattern BN2 and the first layer AND1, and may include a transparent conductive oxide (TCO). In one or more embodiments, the third layer AND3 may include the same material as that of the second layer AND2.

[0127] Since the pixel electrode AND' further includes the third layer AND3, the residual pattern may also include a third residual pattern RSD3 at its lower part. The third residual pattern RSD3 may be located between the ninth interlayer insulating layer INS9 and the first residual pattern RSD1. Other elements except for the third layer AND3 and the third residual pattern RSD3 of the pixel electrode AND' may be the same as those described in Figure 6 .

[0128] Referring to Figure 5 and Figure 6 , the pixel defining layer PDL may surround the first bank pattern BN1, the second bank pattern BN2, and the pixel electrode AND in a plan view, and may be located on the residual patterns RSD1 and RSD2 and the tenth interlayer insulating layer INS10. A part of the pixel defining layer PDL may be located on the edge of the pixel electrode AND. The pixel defining layer PDL may define a first light emitting region EA1, a second light emitting region EA2, and a third light emitting region EA3.

[0129] The first light emitting region EA1 may be defined as a region where the pixel electrode AND, the first light emitting layer IL1, and the common electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second light emitting region EA2 may be defined as a region where the pixel electrode AND, the second light emitting layer IL2, and the common electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third light emitting region EA3 may be defined as a region where the pixel electrode AND, the third light emitting layer IL3, and the common electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0130] The pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, tantalum oxide, hafnium oxide, zinc oxide, and amorphous silicon, but is not limited thereto.

[0131] The pixel definition layer PDL can fill the undercut portion of the first bank pattern BN1 under the tip TIP of the second bank pattern BN2. The pixel definition layer PDL can be located on the lower surface of the second bank pattern BN2, the side portion of the first bank pattern BN1, the upper surface of the tenth interlayer insulating layer INS10, and the upper surfaces of the residual patterns RSD1 and RSD2.

[0132] Figure 8 is a cross-sectional view showing a part of a display panel according to one or more embodiments. Figure 8 is a view showing Figure 5 an enlarged view of the region A1'' corresponding to the region A1 of. Figure 8 different from Figure 6 in that the tenth interlayer insulating layer INS10 between the bank structure BNS and the ninth interlayer insulating layer INS9 is removed. Figure 8 The first bank pattern BN1, the pixel definition layer PDL, and the first residual pattern RSD1 of can be directly formed on the ninth interlayer insulating layer INS9.

[0133] Referring to Figure 5 , the light-emitting layers IL1, IL2, and IL3 can include a first light-emitting layer IL1, a second light-emitting layer IL2, and a third light-emitting layer IL3. The light-emitting layers IL1, IL2, and IL3 can be organic light-emitting layers made of an organic material and can be formed on the pixel electrode AND. Some of the light-emitting layers IL1, IL2, and IL3 can be located on the pixel definition layer PDL.

[0134] The light-emitting layers IL1, IL2, and IL3 can have a multilayer structure, and a hole injection material, a hole transport material, a light-emitting material, an electron transport material, and / or an electron injection material can form corresponding layers. When the pixel transistor PTR applies a voltage (e.g., a predetermined voltage) to the pixel electrode AND of the light-emitting element, and when the common electrode CAT of the light-emitting element receives a common voltage or a cathode voltage, holes and electrons can be respectively injected and transported therein to recombine with each other in the light-emitting layers IL1, IL2, and IL3 to emit light.

[0135] The first light-emitting layer IL1, the second light-emitting layer IL2, and the third light-emitting layer IL3 may be located in the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, respectively, to emit lights of different colors. For example, the first light-emitting layer IL1 located in the first light-emitting region EA1 may emit red light having a peak wavelength in the range of about 610 nm to about 650 nm, and the second light-emitting layer IL2 located in the second light-emitting region EA2 may emit green light having a peak wavelength in the range of about 510 nm to about 550 nm, and the third light-emitting layer IL3 located in the third light-emitting region EA3 may emit blue light having a peak wavelength in the range of about 440 nm to about 480 nm. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 constituting one pixel may include light-emitting elements for emitting lights of different colors to present a white gray level. Optionally, the light-emitting layers IL1, IL2, and IL3 may include two or more materials for emitting lights of different colors such that one light-emitting layer may emit mixed light. For example, one of the light-emitting layers IL1, IL2, and IL3 may include a material for emitting red light and a material for emitting green light to emit yellow light, and another one of the light-emitting layers IL1, IL2, and IL3 may emit blue light.

[0136] The light-emitting layers IL1, IL2, and IL3 may cover the pixel electrode AND in the opening of the pixel defining layer PDL and may cover the pixel defining layer PDL between adjacent sub-pixels SP1, SP2, and SP3, but a part of the light-emitting layers IL1, IL2, and IL3 may be disconnected.

[0137] Figure 9 is a cross-sectional view showing a part of a display panel according to one or more embodiments. Refer to Figure 9 , the light-emitting layer IL' of the display panel 410' may have a tandem structure including a plurality of light-emitting layers IL1', IL2', and IL3' for emitting lights of different colors. For example, the light-emitting layer IL' may include a first light-emitting layer IL1' for emitting light of a first color, a second light-emitting layer IL2' for emitting light of a second color, and a third light-emitting layer IL3' for emitting light of a third color. The first light-emitting layer IL1', the second light-emitting layer IL2', and the third light-emitting layer IL3' may be sequentially stacked. The light-emitting layer IL' may be formed on the entire surface of the semiconductor substrate SSUB without being disconnected.

[0138] Refer to Figure 5, the common electrode CAT can be located on the light-emitting layers IL1, IL2, and IL3 and on the pixel definition layer PDL. The common electrode CAT can be formed of a transparent conductive oxide (TCO) (such as ITO or IZO) capable of transmitting light or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). When the common electrode CAT is formed of a semi-transmissive conductive material, the light-emitting efficiency from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be increased by a microcavity.

[0139] The encapsulation layer TFE can be located on the light-emitting element layer EML. The encapsulation layer TFE can include at least one inorganic layer TFE1 or TFE3 to reduce or prevent oxygen or moisture from penetrating into the light-emitting element layer EML. In addition, the encapsulation layer TFE can include at least one organic layer to protect the light-emitting element layer EML from particles such as dust. For example, the encapsulation layer TFE can include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0140] The first encapsulation inorganic layer TFE1 can be located on the common electrode CAT, the encapsulation organic layer TFE2 can be located on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 can be located on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 can be formed of a multilayer in which silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), and aluminum oxide (AlO x ) are alternately stacked. The encapsulation organic layer TFE2 can be a monomer. Optionally, the encapsulation organic layer TFE2 can be an organic layer including an organic resin such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0141] The adhesive layer ADL can be a layer for bonding the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive member. In addition, the adhesive layer ADL can be a transparent adhesive member, such as a transparent adhesive or a transparent adhesive resin.

[0142] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The color filters CF1, CF2, and CF3 can include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be located on the adhesive layer ADL.

[0143] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 corresponding to different light-emitting regions EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may include colorants such as dyes or pigments that absorb light in wavelength bands other than the wavelength bands of the light corresponding to the colors of the light emitted from the light-emitting regions EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter that overlaps with the first light-emitting region EA1 and transmits only red light. The second color filter CF2 may be a green color filter that overlaps with the second light-emitting region EA2 and transmits only green light. The third color filter CF3 may be a blue color filter that overlaps with the third light-emitting region EA3 and transmits only blue light.

[0144] Multiple lenses LNS may be respectively located on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the multiple lenses LNS may be a structure for increasing the ratio of light toward the front surface of the display device 10. Each of the multiple lenses LNS may have a cross-sectional shape that bulges upward.

[0145] The filling layer FIL may be located on the multiple lenses LNS. The filling layer FIL may have a refractive index (e.g., a predetermined refractive index) such that light moves in the third direction DR3 at the interface between the multiple lenses LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer including, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0146] The cover layer CVL may be located on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to adhere the cover layer CVL. When the cover layer CVL is a glass substrate, the cover layer CVL may be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, the cover layer CVL may be directly coated on the filling layer FIL.

[0147] In one or more embodiments, a polarizing plate may be located on one surface of the cover layer CVL. The polarizing plate may be a structure for reducing or preventing deterioration of visibility that may be caused by reflection of external light. The polarizing plate may include a linear polarizing plate and a phase retardation film. For example, the phase retardation film may be a quarter-wave plate (λ / 4 plate), but the present disclosure is not limited thereto. However, when deterioration of visibility caused by reflection of external light is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate may be omitted.

[0148] Hereinafter, a manufacturing process of the display device 10 according to one or more embodiments will be described with reference to other drawings.

[0149] Figures 10 to 16 are cross-sectional views sequentially showing a process of manufacturing a display device according to one or more embodiments. Figures 10 to 16 Schematically shows a process of forming a bank structure BNS, a pixel electrode AND, and a pixel defining layer PDL. Hereinafter, a description of the process of forming each layer related to the manufacturing process of the display device 10 will be omitted, and the formation order of each layer will be described.

[0150] Reference Figure 10 , a tenth interlayer insulating layer INS10, a first bank layer BNL1, and a second bank layer BNL2 are sequentially formed on the ninth interlayer insulating layer INS9. In one or more embodiments, the ninth interlayer insulating layer INS9 may be located on the semiconductor backplane SBP and on the first interlayer insulating layer INS1, the second interlayer insulating layer INS2, the third interlayer insulating layer INS3, the fourth interlayer insulating layer INS4, the fifth interlayer insulating layer INS5, the sixth interlayer insulating layer INS6, the seventh interlayer insulating layer INS7, and the eighth interlayer insulating layer INS8 of the light-emitting element backplane EBP, and on the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7, and the eighth metal layer ML8, and its detailed structure may be the same as those described in reference Figure 5 and the corresponding repeated detailed description will be omitted.

[0151] Reference Figure 11 , a photoresist PR is formed on the second bank layer BNL2. The photoresist PR may be located in the area(s) overlapping with the light-emitting regions EA1, EA2, and EA3.

[0152] Next, referring to Figure 12 , a first etching process of patterning the second bank layer BNL2, the first bank layer BNL1, and the tenth interlayer insulating layer INS10 may be performed using the photoresist PR as a mask pattern. In one or more embodiments, the first etching process may be an anisotropic dry etching. Through the first etching process, the second bank layer BNL2, the first bank layer BNL1, and the tenth interlayer insulating layer INS10 in the area(s) not covered by the mask pattern may be removed to form a plurality of holes.

[0153] Subsequently, referring to Figure 13, a second etching process for etching the side portions of the first bank layer BNL1 can be performed such that a portion of the lower surface of the second bank layer BNL2 is exposed. In one or more embodiments, the second etching process can be an isotropic wet etching. The first bank pattern BN1 and the second bank pattern BN2 including an undercut structure can be obtained through the second etching process.

[0154] Next, referring to Figure 14 , the photoresist PR of the mask pattern can be removed.

[0155] Subsequently, referring to Figure 15 , a pixel electrode AND can be formed on the second bank pattern BN2, and a residual pattern RSD1 and a residual pattern RSD2 can be formed on the ninth interlayer insulating layer INS9. The material of the pixel electrode AND can be deposited over its entire surface, and then the material of the pixel electrode AND can be disconnected by the tip TIP of the second bank pattern BN2, whereby the material of the pixel electrode AND can be divided into the pixel electrode AND and the residual patterns RSD1 and RSD2. The pixel electrode AND includes a first layer AND1 and a second layer AND2, and the residual patterns RSD1 and RSD2 can include a first residual pattern RSD1 and a second residual pattern RSD2.

[0156] Next, referring to Figure 16 , a pixel defining layer PDL can be formed to fill the undercut portion of the bank structure BNS and can cover the residual patterns RSD1 and RSD2. The pixel defining layer PDL can cover the edge of the pixel electrode AND while surrounding the pixel electrode AND.

[0157] Subsequently, in one or more embodiments, a light emitting layer IL1, IL2, and IL3, a common electrode CAT, a encapsulation layer TFE, an adhesive layer ADL, an optical layer OPL, and a cover layer CVL are formed, thereby manufacturing the display device 10. The descriptions of the light emitting layer IL1, IL2, and IL3, the common electrode CAT, the encapsulation layer TFE, the adhesive layer ADL, the optical layer OPL, and the cover layer CVL can be the same as those described above, and thus the repeated detailed descriptions thereof will be omitted.

[0158] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that the present disclosure can be fabricated in various forms without being limited to the above-described embodiments, and the present disclosure can be implemented in other forms without departing from the relevant features of the claims (and including their functional equivalents). Therefore, the above embodiments will be considered illustrative in all respects and not restrictive.

Claims

1. A display device, comprising: a first bank pattern over the substrate; a second bank pattern including side portions protruding further than side portions of the first bank pattern; as well as The pixel electrode is above the second bank pattern.

2. The display device according to claim 1, wherein: The first bank pattern and the second bank pattern include different metals or alloys.

3. The display device according to claim 2, wherein: The first bank pattern includes aluminum or an aluminum alloy, and Wherein, the second bank pattern comprises titanium or titanium alloy.

4. The display device according to claim 1, wherein: The substrate includes a first light emitting region and a second light emitting region spaced apart from each other, and Wherein, the display device further includes a residual pattern in a space between the first light emitting area and the second light emitting area.

5. The display device according to claim 4, wherein: The residual pattern includes the same material as the pixel electrode.

6. The display device according to claim 4, wherein: The residual pattern is lower than the second bank pattern. 7 . The display device of claim 4 , further comprising a pixel defining layer surrounding the first bank pattern, the second bank pattern, and the pixel electrode in a plan view and being above the residual pattern.

8. The display device according to claim 7, wherein: The pixel defining layer is on a lower surface of the second bank pattern.

9. The display device according to claim 1, wherein: A distance between the side of the first bank pattern and the side of the second bank pattern is greater than a thickness of the first bank pattern.

10. The display device according to claim 9, wherein: The distance between the side of the first bank pattern and the side of the second bank pattern is three to five times the thickness of the first bank pattern.

11. The display device according to claim 1, wherein: The pixel electrode is on an upper surface and the side of the second bank pattern.

12. The display device according to claim 1, wherein: The pixel electrode comprises: a first layer, including metal, over the second bank pattern; and A second layer, including a transparent conductive oxide, is over the first layer.

13. The display device according to claim 12, wherein: The pixel electrode further includes a third layer including a transparent conductive oxide, the third layer being between the second bank pattern and the first layer.

14. The display device according to claim 4, wherein: The display device further includes a first interlayer insulating layer between the substrate and the first bank pattern in the first light emitting region and in the second light emitting region.

15. The display device according to claim 14, wherein: The first interlayer insulating layer in the first light emitting region and the first interlayer insulating layer in the second light emitting region are spaced apart from each other, and Wherein, the residual pattern is in the gap space of the first interlayer insulating layer.

16. The display device according to claim 1, wherein: The first bank pattern and the second bank pattern include an island pattern.

17. A display device comprising: a substrate including light emitting regions spaced apart from each other; a first bank pattern, in the light emitting region, over the substrate; a second bank pattern above the first bank pattern and including a side portion protruding further than a side portion of the first bank pattern; a pixel electrode, above the second bank pattern; a residual pattern above the substrate between the light emitting regions; a pixel defining layer, above the residual pattern and the pixel electrode; as well as A light emitting layer is above the pixel electrode and the pixel defining layer.

18. A method for manufacturing a display device, the method comprising: forming a first bank layer over the substrate; forming a second bank layer over the first bank layer; removing a portion of the second bank layer and a portion of the first bank layer; etching a side portion of the first bank layer to expose a portion of a lower surface of the second bank layer; forming a pixel electrode on the second bank layer; as well as A residual pattern is formed over the substrate.

19. The method according to claim 18, wherein: Forming the pixel electrode above the second embankment layer and forming the residual pattern above the substrate includes: separating the material deposited on the substrate into the pixel electrode and the residual pattern by disconnecting the material deposited on the substrate by the protruding side of the second embankment layer, and the protruding side of the second embankment layer extends farther than the etched side of the first embankment layer.

20. The method according to claim 18, wherein: Removing the portion of the second bank layer and the portion of the first bank layer includes: forming a mask pattern over the second bank layer; and The second bank layer and the first bank layer are etched in regions not covered by the mask pattern.

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