Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a display area and a non-display area, the edge, close to the display area, of the non-display area comprises a first edge, and the display panel comprises a substrate; the first conductive layer is located on one side of the substrate, and the first conductive layer comprises a first gate line and a wire; the wires are located on the sides, close to the first edges, of the first gate lines. The pixel circuits are adjacent to the first edge and located on one side of the substrate, the pixel circuits are located in the display area, each pixel circuit comprises a first transistor close to the first edge, the first transistor comprises a first grid electrode, and at least part of the first grid electrode line is multiplexed as the first grid electrode. According to the technical scheme, the problem of poor display of the edge of the display panel can be solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, Active Matrix Organic Light-Emitting Diode (AMOLED) display technology is widely used in various display products due to its thin, light and flexible characteristics. However, the edge pixels of current AMOLED display panels have poor display problems. Summary of the invention

[0003] In view of this, embodiments of the present application are directed to providing a display panel and a display device to solve the problem of poor display at the edge of the display panel.

[0004] In a first aspect, the present application provides a display panel, including a display area and a non-display area, wherein the edge of the non-display area close to the display area includes a first edge, and the display panel includes: a substrate; a first conductive layer, located on one side of the substrate, the first conductive layer includes a first gate line and a routing line; the routing line is located on a side of the first gate line close to the first edge; a plurality of pixel circuits adjacent to the first edge, located on one side of the substrate, the pixel circuits are located in the display area, the pixel circuits include a first transistor close to the first edge, the first transistor includes a first gate, and at least part of the first gate line is reused as the first gate.

[0005] In one embodiment, the display panel also includes an interlayer insulating layer located on the side of the first conductive layer facing away from the substrate, and the interlayer insulating layer is provided with a plurality of first dummy holes penetrating the interlayer insulating layer, and the orthographic projection of the first dummy holes on the substrate is located on the side where the orthographic projection of the routing on the substrate is away from the orthographic projection of the first gate line on the substrate.

[0006] In one embodiment, the distance between the orthographic projection of the first dummy hole close to the first gate line on the substrate and the orthographic projection of the first gate line on the substrate is less than or equal to 20um; and / or, on the side of each pixel circuit adjacent to the first edge close to the non-display area, the number of the first dummy holes is greater than or equal to 5.

[0007] In one embodiment, the display panel also includes: a first active layer, located between the first conductive layer and the substrate; at least one first insulating layer, located between the first active layer and the first conductive layer; a second active layer, located between the first insulating layer and the first conductive layer; a gate insulating layer, located between the second active layer and the first conductive layer; a plurality of first dummy holes including a first hole, the first hole penetrating the interlayer insulating layer, the gate insulating layer and the first insulating layer; and / or a plurality of first dummy holes including a second hole, the second hole penetrating the interlayer insulating layer and the gate insulating layer; optionally, the second active layer includes an active portion of the first transistor; optionally, the material of the first active layer includes polysilicon; optionally, the material of the second active layer includes metal oxide; optionally, the material of the second active layer includes indium gallium zinc oxide; optionally, the material of the interlayer insulating layer includes an inorganic material.

[0008] In one embodiment, the display panel further comprises a plurality of gate driving circuits adjacent to the first edge and located in the non-display area; the plurality of gate driving circuits comprise at least one effective driving circuit and at least one dummy driving circuit arranged adjacent to each other; the display panel comprises at least one connecting hole located on a side of the effective driving circuit close to the display area, the display panel comprises at least one second dummy hole located on a side of the dummy driving circuit close to the display area, and the distribution pattern of the connecting hole is the same as the distribution pattern of the second dummy hole; optionally, the number of connecting holes corresponding to the same effective driving circuit is equal to the number of second dummy holes corresponding to the same dummy driving circuit; optionally, the relative positions of the plurality of connecting holes corresponding to the same effective driving circuit are the same as the relative positions of the plurality of second dummy holes corresponding to the same dummy driving circuit; optionally, the effective driving circuit is electrically connected to the pixel circuit through the connecting hole; optionally, the dummy driving circuit and the pixel circuit are insulated; optionally, the display panel comprises at least one connecting line located on a side of the effective driving circuit close to the display area, the connecting line connects the connecting hole, the display panel comprises at least one dummy connecting line located on a side of the dummy driving circuit close to the display area, the dummy connecting line connects the second dummy hole, and the shape of the connecting line is the same as the shape of the dummy connecting line; optionally, the non-display area is arranged around at least part of the display area.

[0009] In one embodiment, the effective driving circuit includes a first output terminal, the virtual driving circuit includes a second output terminal, the first output terminal and the second output terminal have the same structure, the first output terminal is electrically connected to the pixel circuit, and the second output terminal is suspended; and / or, the display panel also includes an interlayer insulating layer, which is located on the side of the first conductive layer away from the substrate, and the interlayer insulating layer is provided with a plurality of second dummy holes that penetrate the interlayer insulating layer.

[0010] In one embodiment, the routing line and the first gate line extend in a first direction; and / or, the first transistor further includes a second gate and an active portion, the first gate and the second gate are located on opposite sides of the active portion along the thickness direction of the substrate, and the second gate is located between the active portion and the substrate; and / or, the display panel includes a second gate line, and at least a part of the second gate line is multiplexed as the second gate; and / or, the first edge includes an arc-shaped edge; and / or, a plurality of pixel circuits adjacent to the first edge are arranged along the extending direction of the first edge; and / or, a plurality of pixel circuits adjacent to the first edge are arranged in a stepped manner; and / or, the routing line is located in the display area; and / or, the display panel includes a first reference voltage signal line, the pixel circuit includes a driving transistor, the first transistor is connected between the first reference voltage signal line and the gate of the driving transistor, and the positive projection of the first reference voltage signal line on the substrate is located between the positive projection of the routing line on the substrate and the positive projection of the first gate line on the substrate; or, the positive projection of the first reference voltage signal line on the substrate overlaps with the positive projection of the routing line on the substrate; or, the positive projection of the first part of the first reference voltage signal line on the substrate is located between the positive projection of the routing line on the substrate and the positive projection of the first gate line on the substrate; the positive projection of the second part of the first reference voltage signal line on the substrate overlaps with the positive projection of the routing line on the substrate; and / or, the first transistor is a first reset transistor; and / or, the material of the routing line includes molybdenum and titanium; and / or, the first transistor includes a metal oxide transistor; optionally, the first transistor includes an indium gallium zinc oxide transistor; optionally, the routing line is connected to a DC potential or a power supply potential, optionally, the film layer where the first reference voltage signal line is located is between the substrate and the film layer where the first gate line is located; optionally, the routing line is a reference voltage signal line; optionally, the pixel circuit includes a second reset transistor, the display panel further includes a light-emitting device, the second reset transistor is connected between the second reference voltage signal line and the first end of the light-emitting device, and the routing line is connected to the second reference voltage signal line.

[0011] A second aspect of the present application provides a display panel, including a display area and a non-display area. The edge of the non-display area close to the display area includes a first edge. The display panel includes: a substrate; a first conductive layer located on one side of the substrate, the first conductive layer including a first gate line; a plurality of pixel circuits adjacent to the first edge, located on one side of the substrate, the pixel circuits are located in the display area, the pixel circuits include a first transistor close to the first edge, the first transistor includes a first gate, and at least a part of the first gate line is multiplexed as the first gate; an interlayer insulating layer located on the side of the first conductive layer away from the substrate, the interlayer insulating layer is provided with a first dummy hole penetrating the interlayer insulating layer, and the positive projection of the first dummy hole on the substrate is located on the side of the positive projection of the first gate line on the substrate close to the non-display area.

[0012] A third aspect of the present application provides a display panel, including a display area and a non-display area. The edge of the non-display area adjacent to the display area includes a first edge. The display panel includes: a plurality of gate driving circuits adjacent to the first edge, located in the non-display area; the gate driving circuit includes at least one effective driving circuit and at least one virtual driving circuit arranged adjacent to each other, at least one connection hole, located on the side of the effective driving circuit close to the display area, and at least one second dummy hole, located on the side of the virtual driving circuit close to the display area. The distribution pattern of the connection holes is the same as that of the second dummy holes.

[0013] A fourth aspect of the present application provides a display device, including: the display panel mentioned in any of the above embodiments.

[0014] In the technical solution provided by the present application, a trace is arranged on the side of the first gate line close to the first edge and is on the same conductive layer as the first gate line. Since the trace is closer to the edge than the first gate line, during the manufacturing process of the display panel, the trace is used to protect the first gate line, avoiding the variation of the line width of the first gate line. This setting avoids the influence on the electrical performance of the edge pixel circuit and solves the problem of poor display at the edge of the display panel.

[0015] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0017] Figure 1 Shown is a schematic structural diagram of a display panel provided by an embodiment of the present application.

[0018] Figure 2 Shown is provided by an embodiment of the present application Figure 1 A schematic cross-sectional structure diagram along the section line A-A'.

[0019] Figure 3 Shown is a partial layout of a display panel provided by an embodiment of the present application.

[0020] Figure 4 Shown is provided by another embodiment of the present application Figure 1 A schematic cross-sectional structure diagram along the section line A-A'.

[0021] Figure 5A The figure shows a partial layout of a display panel provided by another embodiment of the present application.

[0022] Figure 5B The figure shows a partial layout of a display panel provided by another embodiment of the present application.

[0023] Figure 6 The figure shows another embodiment provided by the present application Figure 1 A schematic cross-sectional structure diagram along the section line A-A'.

[0024] Figure 7 The figure shows another embodiment provided by the present application Figure 1 A schematic cross-sectional structure diagram along the section line A-A'.

[0025] Figure 8 The figure shows a partial layout of a display panel provided by another embodiment of the present application.

[0026] Figure 9 The figure shows a partial layout of a display panel provided by another embodiment of the present application.

[0027] Figure 10 The figure shows an embodiment provided by the present application Figure 1 A partial enlarged schematic diagram in region B.

[0028] Figure 11 The figure shows a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.

[0029] Figure 12 The figure shows a partial layout of a display panel provided by another embodiment of the present application.

[0030] Figure 13 The figure shows another embodiment provided by the present application Figure 1 A schematic cross-sectional structure diagram along the section line A-A'. Detailed implementation manners

[0031] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0032] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0033] In the related art, the edge of a flexible AMOLED display panel includes an arc angle, and the pixels located at the arc angle are arranged in a stepped shape. After research by the inventor, it is found that for the pixels located on the outermost side of the arc angle, due to the difference in pattern density from the pixels inside the panel, the change in the chemical solution concentration during the development and etching steps in the manufacturing process will affect the line width of each layer of the edge pixels. This change in line width will directly affect the electrical performance of the pixels, resulting in poor display at the edge of the display panel.

[0034] In view of this, the embodiments of the present application provide a display panel and a display device to solve the problem of poor display at the edge of the display panel.

[0035] Figure 1 The following shows a schematic structural diagram of a display panel provided by an embodiment of the present application. Figure 2 The following shows Figure 1 a schematic cross-sectional structure along the section line A-A'. Figure 3 The following shows a partial layout of a display panel provided by an embodiment of the present application. Refer to Figures 1 - 3 , the display panel 100 includes a display area 101 and a non-display area 102. The edge of the non-display area 102 close to the display area 101 includes a first edge 103. The display panel 100 includes: a substrate 110, a first conductive layer 120, and a plurality of pixel circuits 150.

[0036] The first conductive layer 120 is located on one side of the substrate 110; the first conductive layer 120 includes a first gate line GATO1 and a trace GATO2; the trace GATO2 is located on the side of the first gate line GATO1 close to the first edge 103. A plurality of pixel circuits 150 are adjacent to the first edge 103 and are located on one side of the substrate 110. The pixel circuits 150 are located in the display area 101. The pixel circuit 150 includes a first transistor T4 close to the first edge 103. The first transistor T4 includes a first gate, and at least a part of the first gate line GATO1 is multiplexed as the first gate.

[0037] Specifically, the display area 101 and the non-display area 102 are adjacent to each other. Exemplarily, the non-display area 102 surrounds at least part of the display area 101. The substrate 110 is the basic support structure of the display panel 100 and is used to carry a plurality of pixel circuits 150. Exemplarily, the substrate 110 is a flexible substrate 110, and its material includes polyimide. The plurality of pixel circuits 150 are arranged along the extending direction of the first edge 103. Exemplarily, the first edge 103 can be an arc-shaped edge. Each pixel circuit 150 includes at least one first transistor T4 for controlling the display state of the pixel circuit 150. A first conductive layer 120 is provided on one side of the substrate 110, on which a first gate line GATO1 and a trace GATO2 are provided. In the related art, during the manufacturing process of the display panel 100, the concentration change of the liquid medicine such as the developer or the etching solution will cause uneven erosion of the first gate near the edge of the display panel 100, resulting in the variation of its line width. The line width of the first gate is affected, which may cause abnormal display of the pixels near the edge of the display panel 100. The trace GATO2 is provided on the side of the first gate line GATO1 close to the first edge 103, and the trace GATO2 can be used as a protective layer to protect the first gate line GATO1 and reduce this erosion risk.

[0038] The technical solution provided in this embodiment protects the first gate line GATO1 by arranging the trace GATO2 on the side of the first gate line GATO1 close to the first edge 103 and on the same conductive layer as the first gate line GATO1. Since the trace GATO2 is closer to the edge than the first gate line GATO1, during the manufacturing process of the display panel 100, the trace GATO2 is used to protect the first gate line GATO1, avoiding the variation of the line width of the first gate line GATO1. By setting like this, the electrical performance of the edge pixel circuit 150 is not affected, and the problem of poor display at the edge of the display panel 100 is solved. Further, the difference in the pattern density between the edge pixel circuit 150 and the pixel circuit 150 inside the panel is avoided, the display consistency of the pixels in the display panel 100 is improved, and the display quality of the entire display panel 100 is improved.

[0039] Figure 4 The following shows another embodiment provided by the present application Figure 1 The schematic cross-sectional structure along the section line A-A'. Figure 5A The following shows the partial layout of the display panel provided by another embodiment of the present application. Refer to Figure 4 and Figure 5A As shown, the display panel 100 further includes an interlayer insulating layer 130, which is located on the side of the first conductive layer 120 away from the substrate 110. For example, the active part of the first transistor T4 is located between the first gate line GATO1 and the substrate 110.

[0040] In the related art, during the annealing process of the interlayer insulating layer 130, there are differences in the release of hydrogen, and the accumulation of hydrogen gas may cause the semiconductor material in the transistor channel region to be hydrogenated, thereby causing the conduction of the transistor channel and affecting the normal operation of the transistor. By providing the trace GATO2 to increase the conductive layer around the first transistor T4, it is possible to effectively prevent hydrogen from passing downward to the active part of the first transistor T4, resulting in the conduction of the active part of the first transistor T4, and the negative bias of its characteristics can be improved. The trace GATO2 may include a metal material, such as titanium, which can block the transfer of hydrogen to the active part of the first transistor T4.

[0041] Optionally, the interlayer insulating layer 130 is provided with a plurality of first dummy holes 131 penetrating through the interlayer insulating layer 130, and the orthographic projection of the first dummy holes 131 on the substrate 110 is located on a side of the orthographic projection of the trace GATO2 on the substrate 110 away from the orthographic projection of the first gate line GATO1 on the substrate 110. The orthographic projection of the first dummy holes 131 on the substrate 110 is located on a side of the orthographic projection of the trace GATO2 on the substrate 110 close to the first edge 103.

[0042] Specifically, the interlayer insulating layer 130 is provided on a side of the first conductive layer 120 facing away from the substrate 110, for isolating the electrical signals between different conductive layers and preventing short circuits. Exemplarily, the material of the interlayer insulating layer 130 may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, and their laminates, and can be realized by a chemical vapor deposition process.

[0043] In the related art, there are differences in the density of inorganic vias around the pixel circuit 150 adjacent to the first edge 103. During the annealing process of the interlayer insulating layer 130, there are differences in the release of hydrogen, and the accumulation of hydrogen gas may cause the semiconductor material in the transistor channel region to be hydrogenated, thereby causing the conduction of the transistor channel and affecting the normal operation of the transistor. For example, the threshold voltage of an oxide transistor shows a negative bias, resulting in the transistor being unable to be completely turned off. Therefore, the pixel circuit 150 at the edge of the display panel 100 in the related art is prone to display defects when displaying low gray-scale images. Especially when designing a narrow-bezel flexible AMOLED product, since there is not enough space to place virtual pixels (i.e., auxiliary pixels, used to simulate the electrical performance of actual pixels), the above problems will be more prominent. The solution of this embodiment is provided with a plurality of penetrating first dummy holes 131 on the interlayer insulating layer 130, and the orthographic projection of some or all of the first dummy holes 131 on the substrate 110 is located in the non-display area 102 and on a side of the orthographic projection of the trace GATO2 on the substrate 110 away from the first gate line GATO1. During the annealing process of the interlayer insulating layer 130, hydrogen can be released through these first dummy holes 131, thereby avoiding the diffusion of hydrogen between the various film layers of the transistor and effectively reducing the risk of channel conduction of the oxide transistor.

[0044] Exemplarily, in other embodiments, a plurality of through-conductive vias may also be provided on the interlayer insulating layer 130, and signal lines arranged on different conductive layers are electrically connected through the plurality of conductive vias.

[0045] In this embodiment, by providing a plurality of first dummy holes 131 on the interlayer insulating layer 130 as release channels, hydrogen gas is allowed to escape from the interlayer insulating layer 130 without accumulating in the underlying layers. By providing the first dummy holes 131 on the interlayer insulating layer 130, the risk of channel conduction of the oxide transistor can be effectively reduced, and the reliability and stability of the transistor are improved, thereby improving the performance and lifespan of the entire display panel 100.

[0046] In one embodiment, the distance between the orthographic projection of the first dummy hole 131 near the first gate line GATO1 on the substrate 110 and the orthographic projection of the first gate line GATO1 on the substrate 110 (e.g., the distance in a direction perpendicular to the extension direction of the first edge 103 or the first gate line GATO1) is less than or equal to 20 um.

[0047] Specifically, a plurality of first dummy holes 131 are provided on the interlayer insulating layer 130 to release hydrogen gas generated during the annealing process of the interlayer insulating layer 130, thereby reducing the risk of channel conduction of the first transistor T4. The improvement effect of the channel conductivity of the first transistor T4 is related to the distance between the first dummy hole 131 and the first gate line GATO1. By adjusting this distance, the performance of the first transistor T4 can be optimized. It is defined that the distance between the orthographic projection of the first dummy hole 131 near the first gate line GATO1 (i.e., the vertical projection of the first dummy hole 131 on the substrate 110) and the orthographic projection of the first gate line GATO1 is less than or equal to 20 um. Exemplarily, it can be 5 um, 10 um, 15 um, 20 um, etc. Such a setting can significantly improve the electrical characteristics of the first transistor T4.

[0048] In this embodiment, the distance between the orthographic projection of the first dummy hole 131 near the first gate line GATO1 on the substrate 110 and the orthographic projection of the first gate line GATO1 on the substrate 110 is defined. Since the first dummy hole 131 is close to the first gate line GATO1, hydrogen gas can be released more directly from the interlayer insulating layer 130 adjacent to the first transistor T4, thereby reducing the accumulation of hydrogen gas in the film layer under the first gate line GATO1 and reducing the risk of channel conduction of the first transistor T4. This is further beneficial to improving the display performance of the pixel circuit 150, thereby optimizing the display quality of the entire display panel 100.

[0049] In one embodiment, on the side of each pixel circuit 150 adjacent to the first edge 103 and close to the non-display area 102, the number of the first dummy holes 131 is greater than or equal to 5. For example, at least some of the first dummy holes 131 are arranged along the extending direction of the first edge 103.

[0050] Specifically, the improvement effect of the channel conductivity of the first transistor T4 is related to the number of the first dummy holes 131. By adjusting the number of the first dummy holes 131, the performance of the first transistor T4 can be optimized. Along the extension direction of the first edge 103 at the junction of the non-display area 102 and the display area 101 of the display panel 100, on the side of each pixel circuit 150 close to the first edge 103, at least 5 first dummy holes 131 are provided for the release of hydrogen.

[0051] In the technical solution of this embodiment, by defining that on the side of each pixel circuit 150 close to the non-display area 102, the number of the first dummy holes 131 is greater than or equal to 5, for example, it can be 6, 7, 8, 9, or 10, etc., the release efficiency of hydrogen during the annealing process of the interlayer insulating layer 130 can be significantly improved, thereby more effectively reducing the risk of channel conductivity of the first transistor T4. Further, the multiple first dummy holes 131 are evenly distributed, which helps to ensure that the hydrogen in the entire first edge 103 area can be evenly released, reducing local process deviations. Increasing the number of the first dummy holes 131 at the position of the first edge 103 that is easily affected by the process helps to improve the stability of the entire process and reduce process abnormalities caused by hydrogen accumulation. Further, it is beneficial to improve the reliability and long-term stability of the display panel 100 and extend the service life of the product. On the side of each pixel circuit 150 close to the non-display area 102, the first dummy holes 131 can be arranged in multiple rows and columns. The row direction can be parallel to the extending direction of the first edge 103. Alternatively, the row direction can be parallel to the extending direction of the first gate line GATO1, and the column direction can be parallel to the extending direction of the data line. The row direction can intersect with the column direction, for example, be perpendicular.

[0052] Figure 6 Shown is a Figure 1 cross-sectional structure schematic diagram along the section line A-A', Figure 7 Shown is a Figure 1 cross-sectional structure schematic diagram along the section line A-A'. Refer to Figure 6 and Figure 7 , the display panel 100 further includes:

[0053] A first active layer P-si, located between the first conductive layer 120 and the substrate 110;

[0054] At least one first insulating layer, located between the first active layer P-si and the first conductive layer 120;

[0055] A second active layer of IGZO is located between the first insulating layer and the first conductive layer 120;

[0056] A gate insulating layer 140 is located between the second active layer of IGZO and the first conductive layer 120;

[0057] The plurality of first dummy holes 131 include a first hole 1311 that penetrates the interlayer insulating layer 130, the gate insulating layer 140, and the first insulating layer; and / or, the plurality of first dummy holes 131 include a second hole 1312 that penetrates the interlayer insulating layer 130 and the gate insulating layer 140; Optionally, the second active layer of IGZO includes the active portion of the first transistor T4; Optionally, the material of the first active layer of P-si includes polysilicon; Optionally, the material of the second active layer of IGZO includes metal oxide; Optionally, the material of the second active layer of IGZO includes indium gallium zinc oxide, and optionally, the material of the interlayer insulating layer 130 includes inorganic material. The material of the interlayer insulating layer 130 may include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride. Part or all of the first dummy holes 131 may be filled with an organic insulating material, for example, a part of the planarization layer PIN may be filled in the first dummy holes 131.

[0058] Specifically, a first active layer of P-si is disposed between the first conductive layer 120 and the substrate 110, and the material of the first active layer of P-si includes a polysilicon semiconductor material. Using polysilicon as the material of the first active layer of P-si can provide a relatively high mobility, thereby improving the switching speed and overall performance of the transistor. Between the first active layer of P-si and the first conductive layer 120, at least one first insulating layer is provided to isolate the first active layer of P-si and the first conductive layer 120 and prevent short circuit. A second active layer of IGZO is provided between the first insulating layer and the first conductive layer 120, and the active portion of the first transistor T4 is disposed in the second active layer of IGZO. The material of the second active layer of IGZO includes an indium gallium zinc oxide semiconductor material. Using indium gallium zinc oxide as the material of the second active layer of IGZO has high transparency and good electrical characteristics, which helps to improve the light transmittance and electrical stability of the display panel 100. A gate insulating layer 140 is provided between the second active layer of IGZO and the first conductive layer 120 to isolate the gate of the transistor and the active layer and maintain the electrical characteristics of the transistor. Exemplarily, the material of the first insulating layer may include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride and their laminates, and can be realized by chemical vapor deposition process, and / or, the material of the gate insulating layer 140 may include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride and their laminates, and can be realized by chemical vapor deposition process.

[0059] In one embodiment, refer to Figure 6, the first dummy hole 131 includes a first hole 1311 that penetrates through the interlayer insulating layer 130, the gate insulating layer 140, and the first insulating layer. The advantage of this arrangement is to further improve the release efficiency of hydrogen during the annealing process of the interlayer insulating layer 130, thereby more effectively reducing the risk of channel conduction of the first transistor T4. In another embodiment, refer to Figure 7 , the first dummy hole 131 includes a second hole 1312 that penetrates through the interlayer insulating layer 130 and the gate insulating layer 140. The advantage of this arrangement is to further improve the release efficiency of hydrogen during the annealing process of the interlayer insulating layer 130, thereby more effectively reducing the risk of channel conduction of the first transistor T4. And compared with the first hole 1311, the depth of the second hole 1312 is shallower, which is beneficial to preventing the erosion of water and oxygen on the underlying film layer and ensuring the reliability of the display panel 100. In yet another embodiment, the first dummy hole 131 includes a combination of the first hole 1311 and the second hole 1312.

[0060] In this embodiment, the design of the first dummy hole 131 takes into account the characteristics of the multi-layer structure, which helps to improve the process compatibility and flexibility while maintaining the electrical performance. By providing the first hole 1311 and the second hole 1312, the hydrogen generated during the annealing process can be released more effectively, reducing the accumulation of hydrogen in the interlayer and lowering the risk of channel conduction of the transistor.

[0061] Figure 8 The partial layout of the display panel provided by another embodiment of the present application is shown as Figure 9 The partial layout of the display panel provided by another embodiment of the present application is shown as Figure 10 The one provided by an embodiment of the present application is shown as Figure 1 The partial enlarged schematic diagram in area B. Refer to Figures 3 - 9 , the trace GATO2 and the first gate line GATO1 extend along the first direction F1. The trace GATO2 and the first gate line GATO1 are arranged along the second direction F2. The data line can extend along the second direction F2. The first direction F1 and the second direction F2 intersect, for example, perpendicularly.

[0062] Each trace or signal line (such as the trace GATO2 and the first gate line GATO1) can extend along its own extension direction in a straight line, a broken line, a curve, an irregular shape, or a combination of one or more of them.

[0063] For example, the first transistor T4 further includes a second gate and an active portion. The first gate and the second gate are located on opposite sides of the active portion along the thickness direction Z of the substrate 110, and the second gate is located between the active portion and the substrate 110. For example, the positive projections of the active portion and the first gate of the first transistor T4 on the substrate 110 overlap. For example, the positive projections of the active portion and the second gate of the first transistor T4 on the substrate 110 overlap. For example, the positive projections of the first gate and the second gate of the first transistor T4 on the substrate 110 overlap.

[0064] For example, the display panel 100 includes a second gate line SN1-1, and at least a part of the second gate line SN1-1 is multiplexed as the second gate. The second gate line SN1-1 extends along the first direction F1.

[0065] For example, a plurality of pixel circuits 150 adjacent to the first edge 103 are arranged along the extending direction of the first edge 103. The first edge 103 may include a curve or a broken line. For example, the first edge 103 includes an arc-shaped edge.

[0066] For example, refer to Figure 10 , a plurality of pixel circuits 150 adjacent to the first edge 103 are arranged in a stepped manner.

[0067] For example, the trace GATO2 is located in the display area 101. In other embodiments, the trace GATO2 may be located in the non-display area 102.

[0068] For example, the display panel 100 includes a first reference voltage signal line ref1, the pixel circuit 150 includes a driving transistor T1, and the first transistor T4 is connected between the first reference voltage signal line ref1 and the gate of the driving transistor T1. For example, the positive projection of the first reference voltage signal line ref1 on the substrate 110 is located between the positive projection of the first gate line GATO1 on the substrate 110 and the first edge 103.

[0069] For example, the positive projection of the first reference voltage signal line ref1 on the substrate 110 is located between the positive projection of at least a part of the trace GATO2 on the substrate 110 and the positive projection of the first gate line GATO1 on the substrate 110.

[0070] For example, as Figure 5A and Figure 5BAs shown, at least a part of the positive projection of the first reference voltage signal line ref1 on the substrate 110 overlaps with at least a part of the positive projection of the trace GATO2 on the substrate 110. With such an arrangement, it is beneficial to provide space for setting more first dummy holes 131. A part of the positive projection of the first reference voltage signal line ref1 on the substrate 110 overlaps with a part of the positive projection of the trace GATO2 on the substrate 110. A part of the positive projection of the first reference voltage signal line ref1 on the substrate 110 does not overlap with a part of the positive projection of the trace GATO2 on the substrate 110. For example, the positive projection of the first part of the first reference voltage signal line ref1 on the substrate 110 is located between the positive projection of the trace GATO2 on the substrate 110 and the positive projection of the first gate line GATO1 on the substrate 110; the positive projection of the second part of the first reference voltage signal line ref1 on the substrate 110 overlaps with the positive projection of the trace GATO2 on the substrate 110.

[0071] Optionally, the film layer where the first reference voltage signal line ref1 is located is between the substrate and the film layer where the first gate line GATO1 is located.

[0072] In one embodiment, the trace GATO2 is connected to a DC potential or a power supply potential.

[0073] Optionally, the trace GATO2 is a reference voltage signal line.

[0074] Optionally, the pixel circuit 150 includes a second reset transistor and a light-emitting device OLED. The second reset transistor is connected between the second reference voltage signal line (which can transmit the second reference voltage signal Vrefn2) and the first end (such as the anode) of the light-emitting device OLED, and the trace GATO2 is connected to the second reference voltage signal line.

[0075] Hereinafter, taking the 8T1C pixel circuit 150 as an example, the technical solution of the present application will be described. Figure 11 As shown is a schematic structural diagram of the pixel circuit 150 provided by an embodiment of the present application. As Figure 11 shown, the pixel circuit 150 includes some or all of the first transistor T4, the second transistor T2, the third transistor T3, the driving transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the storage capacitor Cst. The display panel 100 may further include a light-emitting device OLED.

[0076] Among them, the first pole of the first transistor T4 is connected to the first reference voltage signal Vrefn1, the second pole of the first transistor T4 is connected to the control pole or the second pole of the driving transistor T1, and the control pole of the first transistor T4 (such as the first reset transistor) is connected to the first scan signal line SN1 (which may include the first gate line GATO1 and / or the second gate line SN1-1, and accesses the first control signal, which may be the first scan signal). The positive projection of the first gate line GATO1 on the substrate 110 may overlap with the positive projection of the second gate line SN1-1 on the substrate 110. The first transistor T4 may include an N-type transistor, such as a metal oxide transistor. The active part of the first transistor T4 may be located in the second active layer.

[0077] The first pole of the second transistor T2 (such as a data writing transistor) is connected to the data signal Data, the second pole of the second transistor T2 is connected to the first pole of the driving transistor T1, and the control pole of the second transistor T2 is connected to the second scan signal line SP1 (which accesses the second control signal, such as the second scan signal). The second transistor T2 may include a P-type transistor, such as a polysilicon transistor. The active part of the second transistor T2 may be located in the first active layer.

[0078] The first pole of the third transistor T3 is connected to the gate of the driving transistor T1, the second pole of the third transistor T3 is connected to the second pole of the driving transistor T1, and the control pole of the third transistor T3 (such as a compensation transistor) is connected to the third scan signal line SN2 (which may include the third gate line SN2-1 and / or the fourth gate line SN2-2, and accesses the third control signal, which may be the third scan signal). The positive projection of the third gate line SN2-1 on the substrate 110 may overlap with the positive projection of the fourth gate line SN2-2 on the substrate 110. The fourth gate line SN2-2 and the first gate line GATO1 may be arranged in the same layer, such as in the first conductive layer. The third gate line SN2-1 and the second gate line SN1-1 may be arranged in the same layer. The third transistor T3 may include an N-type transistor, such as a metal oxide transistor. The active part of the third transistor T3 may be located in the second active layer.

[0079] The first end of the storage capacitor Cst is connected to the first power supply voltage ELVDD, and the second end of the storage capacitor Cst is connected to the control pole of the driving transistor T1.

[0080] The first pole of the fifth transistor T5 (such as a light emission control transistor) is connected to the first power supply voltage ELVDD, the second pole of the fifth transistor T5 is connected to the first pole of the driving transistor T1, and the control pole of the fifth transistor T5 is connected to the light emission control signal line EM (which accesses the fourth control signal, such as the light emission control signal). The fifth transistor T5 may include a P-type transistor, such as a polysilicon transistor. The active part of the fifth transistor T5 may be located in the first active layer.

[0081] The first pole of the sixth transistor T6 (e.g., a light-emitting control transistor) is connected to the second pole of the driving transistor T1, and the second pole of the sixth transistor T6 is connected to the first end of the light-emitting device OLED. The control pole of the sixth transistor T6 is connected to the light-emitting control signal line EM (receiving a fourth control signal, e.g., a light-emitting control signal). The sixth transistor T6 may include a P-type transistor, e.g., a polysilicon transistor. The active part of the sixth transistor T6 may be located in the first active layer.

[0082] The first pole of the seventh transistor T7 receives the second reference voltage signal Vrefn2, the second pole of the seventh transistor T7 is connected to the first end of the light-emitting device OLED, and the control pole of the seventh transistor T7 is connected to the fifth scanning signal line SP2 (receiving a fifth control signal, which may be a fourth scanning signal). The seventh transistor T7 may include a P-type transistor, e.g., a polysilicon transistor. The active part of the seventh transistor T7 may be located in the first active layer.

[0083] The first pole of the eighth transistor T8 receives the third reference voltage signal Vrefp, the second pole of the eighth transistor T8 is connected to the first pole or the second pole of the driving transistor T1, and the control pole of the eighth transistor T8 is connected to the fifth scanning signal line SP2 (receiving a fifth control signal, which may be a fourth scanning signal).

[0084] The second end of the light-emitting device OLED is connected to the second power supply voltage ELVSS. The eighth transistor T8 may include a P-type transistor, e.g., a polysilicon transistor. The active part of the eighth transistor T8 may be located in the first active layer.

[0085] Exemplarily, the first transistor T4 is the first reset transistor, and the seventh transistor T7 is the second reset transistor.

[0086] For example, the display panel 100 includes a third gate line SN2-1, and at least a part of the third gate line SN2-1 is multiplexed as the third gate. The third gate line SN2-1 extends along the first direction F1. Exemplarily, the third transistor T3 is a vertical double-gate transistor, and the third transistor T3 further includes a third gate, and at least a part of the third gate line SN2-1 is multiplexed as the third gate. The third transistor T3 further includes a fourth gate, and at least a part of the fourth gate line SN2-2 is multiplexed as the fourth gate. The third gate and the fourth gate are located on opposite sides of the active part of the third transistor T3 along the thickness direction Z of the substrate 110, and the third gate is located between the active part and the substrate 110.

[0087] Exemplarily, referring to Figure 3 and Figure 5A , the first reference voltage signal line ref1 is used to provide the first reference voltage signal Vrefn1 to the pixel circuit 150. The second reference voltage signal line (not shown in the figure) is used to provide the second reference voltage signal Vrefn2 to the pixel circuit 150.

[0088] Exemplarily, the routing line GATO2 can be connected to the first reference voltage signal line ref1, or can be connected to the second reference voltage signal line, to provide a reference voltage signal for the pixel circuit 150. The routing line GATO2 can also be connected to the power supply voltage signal line to provide the first power supply voltage ELVDD or the second power supply voltage ELVSS for the pixel circuit 150.

[0089] Exemplarily, referring to Figure 6 and Figure 7 , a second conductive layer M1 and a third conductive layer M2 are further included between the first active layer P-si and the first conductive layer 120. Two plates of the storage capacitor Cst are respectively located in the second conductive layer M1 and the third conductive layer M2. The third conductive layer M2 includes a second gate line SN1-1 and a third gate line SN2-1. Exemplarily, the first transistor T4 is a double-gate transistor, and the first transistor T4 further includes a second gate, and at least part of the second gate line SN1-1 is multiplexed as the second gate. A first insulating layer ( Figure 6 marked as GI, CI, and buffer in

[0090] is provided between the first active layer P-si and the second conductive layer M1, between the second conductive layer M1 and the third conductive layer M2, and between the third conductive layer M2 and the second active layer IGZO, for maintaining the electrical characteristics of the capacitor and the transistor. A fourth conductive layer M3, a planarization layer PIN, a first electrode Anode, a pixel definition layer PDL, and a support layer SPC are further provided on a side of the interlayer insulating layer 130 away from the substrate 110. The fourth conductive layer M3 includes a first source 11, a first drain 12, a second source 21, and a second drain 22.

[0091] The first reference voltage signal line ref1 can be located in the second conductive layer M1. The second scan signal line SP1 can be located in the second conductive layer M1. The fifth scan signal line SP2 can be located in the second conductive layer M1.

[0092] In one embodiment, the material of the routing line GATO2 includes molybdenum and titanium; and / or, the first transistor T4 includes a metal oxide transistor; optionally, the first transistor T4 includes an indium gallium zinc oxide transistor.

[0093] Specifically, the material of the trace GATO2 includes molybdenum and titanium, both of which have good electrical conductivity and stability. Exemplarily, the trace GATO2 is made of two layers of conductive material layers, namely a molybdenum material layer and a titanium material layer. Titanium does not react with hydrogen, which helps prevent the diffusion of hydrogen during the manufacturing process. The channel region material of the first transistor T4 is indium gallium zinc oxide, which is a transparent oxide semiconductor material widely used in thin film transistors because it has a high electron mobility and good optoelectronic properties.

[0094] In this embodiment, the material of the trace GATO2 and the type of the first transistor T4 are provided. Titanium in the trace GATO2 does not react with hydrogen, and it can effectively prevent hydrogen atoms from diffusing through the trace GATO2 to other layers during the manufacturing process, which helps prevent the degradation of transistor performance caused by hydrogen, such as channel conductivity. By using molybdenum, titanium, and stable indium gallium zinc oxide materials, defects in the manufacturing process can be reduced, the production yield can be improved, and the cost can be lowered. Further, the difference in the graphic density between the edge pixel circuit 150 and the in-panel pixel circuit 150 is avoided, the display consistency of the pixels in the display panel 100 is improved, and the display quality of the entire display panel 100 is enhanced.

[0095] Figure 12 The partial layout of the display panel provided by another embodiment of the present application is shown. As Figure 12As shown, the display panel 100 further includes a plurality of gate driving circuits adjacent to the first edge 103, located in the non-display area 102. The plurality of gate driving circuits include at least one effective driving circuit 151 and at least one dummy driving circuit 152 arranged adjacent to each other. The display panel 100 includes at least one connection hole 1313, located on the side of the effective driving circuit 151 close to the display area 101. The display panel 100 includes at least one second dummy hole 1314, located on the side of the dummy driving circuit 152 close to the display area 101. The distribution pattern of the connection holes 1313 is the same as that of the second dummy holes 1314; optionally, the number of connection holes 1313 corresponding to the same effective driving circuit 151 is equal to the number of second dummy holes 1314 corresponding to the same dummy driving circuit 152; optionally, the relative positions of the plurality of connection holes 1313 corresponding to the same effective driving circuit 151 are the same as the relative positions of the plurality of second dummy holes 1314 corresponding to the same dummy driving circuit 152; optionally, the effective driving circuit 151 is electrically connected to the pixel circuit 150 through the connection hole 1313; optionally, the dummy driving circuit 152 and the pixel circuit 150 are insulated; optionally, the display panel 100 includes at least one connection line 161, located on the side of the effective driving circuit 151 close to the display area 101. The connection line 161 connects the connection hole 1313. The display panel 100 includes at least one dummy connection line 162, located on the side of the dummy driving circuit 152 close to the display area 101. The dummy connection line 162 connects the second dummy hole 1314. The shape of the connection line 161 is the same as that of the dummy connection line 162. Exemplarily, the interlayer insulating layer 130 is provided with a plurality of second dummy holes 1314 penetrating through the interlayer insulating layer 130.

[0096] Specifically, the gate driving circuits are arranged in the non-display area 102 along the extending direction of the first edge 103, for driving the transistor gates in the display area 101 to control the display of pixels. The effective driving circuit 151 refers to the circuit part in the gate driving circuit that actually drives the pixels. The dummy driving circuit 152 refers to the circuit part in the gate driving circuit that is set to simulate or assist the effective driving circuit 151 and does not directly participate in the driving of the pixels. The setting of the dummy driving circuit 152 can be used to monitor and compensate the performance of the effective driving circuit 151, thereby improving the reliability and stability of the overall circuit.

[0097] A connection hole 1313 is provided on a side of the active driving circuit 151 away from the display area 101. A connection line 161 between the active driving circuit 151 and the pixel circuit 150 is electrically connected through the connection hole 1313, ensuring signal transmission and control of the pixels. A second dummy hole 1314 is provided on a side of the virtual driving circuit 152 away from the display area 101. The display panel 100 is further provided with a dummy connection line 162 connected to the second dummy hole 1314 for simulating or assisting a circuit portion of the active driving circuit 151. The distribution pattern of the connection holes 1313 is the same as that of the second dummy holes 1314, and the shape of the connection line 161 is also the same as that of the dummy connection line 162, having the same influence on the pixel circuit 150 close to the active driving circuit 151 and the virtual driving circuit 152.

[0098] In this embodiment, by respectively providing the connection hole 1313 and the second dummy hole 1314 on sides of the active driving circuit 151 and the virtual driving circuit 152 away from the display area 101, and their distribution patterns being the same, the uniformity of the pattern of the interlayer insulating layer 130 in the region where the gate driving circuit is located is ensured. By providing the connection line 161 connected to the connection hole 1313, electrical connection between the active driving circuit 151 and the pixel circuit 150 is achieved, which can reduce the impedance and delay of signal transmission and improve the response speed of the display panel 100; by providing the dummy connection line 162 connected to the second dummy hole 1314 and the shape of the connection line 161 being the same as that of the dummy connection line 162, differential influence on the pixel circuit 150 around the gate driving circuit is avoided, thereby improving the performance consistency of the pixel circuit 150 close to the first edge 103.

[0099] In one embodiment, referring to Figure 12 , the active driving circuit 151 includes a first output terminal 1511, the virtual driving circuit 152 includes a second output terminal 1521, the structures of the first output terminal 1511 and the second output terminal 1521 are the same, the first output terminal 1511 is electrically connected to the pixel circuit 150, and the second output terminal 1521 is suspended.

[0100] Specifically, the first output terminal 1511 of the effective driving circuit 151 is directly electrically connected to the pixel circuit 150, ensuring that signals can be correctly transmitted to the pixel circuit 150 to control its display state. The physical structure and design of the second output terminal 1521 of the virtual driving circuit 152 are the same as those of the first output terminal 1511 of the effective driving circuit 151, but the second output terminal 1521 is suspended and not electrically connected to any circuit elements. With this arrangement, the layout of the virtual driving circuit 152 and the effective driving circuit 151 is the same, further improving the uniformity of the pattern of the interlayer insulating layer 130 in the area where the gate driving circuit is located, thereby improving the performance consistency of the pixel circuit 150 near the first edge 103. Moreover, the same process steps and molds can be used during manufacturing, simplifying the production process and reducing costs.

[0101] Figure 13 The following shows a cross-sectional structural schematic diagram along the section line A-A' provided by another embodiment of the present application. As Figure 1 shown, the display panel 100 includes a display area 101 and a non-display area 102. The edge of the non-display area 102 close to the display area 101 includes a first edge 103. The display panel 100 includes: a substrate 110, a first conductive layer 120, and a plurality of pixel circuits 150. Figure 13

[0102] The first conductive layer 120 is located on one side of the substrate 110. The first conductive layer 120 includes a first gate line GATO1. A plurality of pixel circuits 150 adjacent to the first edge 103 are located on one side of the substrate 110. The pixel circuits 150 are located in the display area 101. The pixel circuit 150 includes a first transistor T4 near the first edge 103. The first transistor T4 includes a first gate, and at least a part of the first gate line GATO1 is multiplexed as the first gate. The interlayer insulating layer 130 is located on the side of the first conductive layer 120 facing away from the substrate 110. The interlayer insulating layer 130 is provided with a first dummy hole 131 penetrating through the interlayer insulating layer 130. The orthographic projection of the first dummy hole 131 on the substrate 110 is located on the side of the orthographic projection of the first gate line GATO1 on the substrate 110 close to the non-display area 102. With this arrangement, a plurality of first dummy holes 131 are provided on the interlayer insulating layer 130 as release channels, allowing hydrogen to escape from the interlayer insulating layer 130 without accumulating in the underlying layers, which can effectively reduce the risk of channel conductivity of oxide transistors, improve the reliability and stability of the transistors, and thus improve the performance and lifespan of the entire display panel 100.

[0103] This embodiment can be combined with some or all of the features in the above embodiments, which will not be elaborated here.

[0104] Figure 12 An embodiment of the present application also provides a display panel 100, specifically as Figure 12As shown, the display panel 100 includes a display area 101 and a non-display area 102. The edge of the non-display area 102 adjacent to the display area 101 includes a first edge 103. The display panel 100 includes: a plurality of gate driving circuits adjacent to the first edge 103, located in the non-display area 102; the gate driving circuit includes at least one effective driving circuit 151 and at least one dummy driving circuit 152 arranged adjacent to each other, at least one connection hole 1313, located on the side of the effective driving circuit 151 close to the display area 101, at least one second dummy hole 1314, located on the side of the dummy driving circuit 152 close to the display area 101, and the distribution rule of the connection holes 1313 is the same as that of the second dummy holes 1314. With such a setting, the differential influence on the pixel circuit 150 around the gate driving circuit is avoided, thereby improving the performance consistency of the pixel circuit 150 close to the first edge 103.

[0105] This embodiment can be combined with some or all of the features in the above embodiments, and will not be elaborated here.

[0106] The embodiment of the present application also provides a display device, which includes the display panel 100 mentioned in the above embodiment. Its technical principle and the effects produced are similar and will not be elaborated here.

[0107] It should be understood that various forms of the processes shown above can be used, with steps reordered, added or deleted. For example, the steps described in the present application can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present application can be achieved, and no limitation is made herein.

[0108] The above specific implementation manners do not constitute a limitation to the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area, wherein an edge of the non-display area close to the display area includes a first edge, and the display panel includes: substrate; A first conductive layer, located on one side of the substrate, the first conductive layer comprising a first gate line and a routing line; the routing line is located on one side of the first gate line close to the first edge; A plurality of pixel circuits adjacent to the first edge are located on one side of the substrate, the pixel circuits are located in the display area, the pixel circuits include a first transistor close to the first edge, the first transistor includes a first gate, and at least part of the first gate line is reused as the first gate.

2. The display panel according to claim 1, characterized in that: It also includes an interlayer insulating layer, which is located on the side of the first conductive layer away from the substrate, and the interlayer insulating layer is provided with a plurality of first dummy holes penetrating the interlayer insulating layer, and the orthographic projection of the first dummy holes on the substrate is located on the side where the orthographic projection of the routing line on the substrate is away from the orthographic projection of the first gate line on the substrate.

3. The display panel according to claim 2, characterized in that: A distance between an orthographic projection of the first dummy hole close to the first gate line on the substrate and an orthographic projection of the first gate line on the substrate is less than or equal to 20 um; And / or, on a side of each of the pixel circuits adjacent to the first edge close to the non-display area, the number of the first dummy holes is greater than or equal to 5.

4. The display panel according to claim 2, characterized in that: Also includes: A first active layer, located between the first conductive layer and the substrate; At least one first insulating layer, located between the first active layer and the first conductive layer; a second active layer, located between the first insulating layer and the first conductive layer; a gate insulating layer, located between the second active layer and the first conductive layer; The plurality of first dummy holes include a first hole, the first hole penetrating the interlayer insulating layer, the gate insulating layer and the first insulating layer; And / or, the plurality of first dummy holes include a second hole, and the second hole penetrates the interlayer insulating layer and the gate insulating layer; Preferably, the second active layer includes an active portion of the first transistor; Preferably, the material of the first active layer includes polysilicon; Preferably, the material of the second active layer includes metal oxide; Preferably, the material of the second active layer includes indium gallium zinc oxide; Preferably, the material of the interlayer insulating layer includes inorganic material.

5. The display panel according to claim 1, characterized in that: It also includes a plurality of gate driving circuits adjacent to the first edge and located in the non-display area; the plurality of gate driving circuits include at least one effective driving circuit and at least one virtual driving circuit that are adjacently arranged, The display panel includes at least one connection hole located on a side of the effective driving circuit close to the display area. The display panel includes at least one second dummy hole located on a side of the dummy driving circuit close to the display area, and the distribution pattern of the connecting hole is the same as the distribution pattern of the second dummy hole; Preferably, the number of the connection holes corresponding to the same effective driving circuit is equal to the number of the second dummy holes corresponding to the same virtual driving circuit; Preferably, the relative positions of the plurality of connection holes corresponding to the same effective driving circuit are the same as the relative positions of the plurality of second dummy holes corresponding to the same dummy driving circuit; Preferably, the effective driving circuit is electrically connected to the pixel circuit through the connecting hole; Preferably, the virtual driving circuit and the pixel circuit are insulated from each other; Preferably, the display panel includes at least one connecting line located on a side of the effective driving circuit close to the display area, and the connecting line is connected to the connecting hole. The display panel includes at least one dummy line located on a side of the dummy driving circuit close to the display area, the dummy line is connected to the second dummy hole, and the shape of the connection line is the same as that of the dummy line; Preferably, the non-display area is arranged around at least a portion of the display area.

6. The display panel according to claim 5, characterized in that: The effective driving circuit includes a first output terminal, the virtual driving circuit includes a second output terminal, the first output terminal and the second output terminal have the same structure, the first output terminal is electrically connected to the pixel circuit, and the second output terminal is suspended; And / or, the display panel further includes an interlayer insulating layer located on a side of the first conductive layer away from the substrate, and the interlayer insulating layer is provided with a plurality of the second dummy holes penetrating the interlayer insulating layer.

7. The display panel according to claim 1, characterized in that: The routing line and the first gate line extend along a first direction; And / or, the first transistor further includes a second gate and an active portion, the first gate and the second gate are located on opposite sides of the active portion along a thickness direction of the substrate, and the second gate is located between the active portion and the substrate; And / or, the display panel comprises a second gate line, and at least a part of the second gate line is reused as the second gate; and / or, the first edge comprises an arc-shaped edge; And / or, a plurality of the pixel circuits adjacent to the first edge are arranged along an extension direction of the first edge; and / or, a plurality of the pixel circuits adjacent to the first edge are arranged in a staircase shape; And / or, the wiring is located in the display area; And / or, the display panel includes a first reference voltage signal line, the pixel circuit includes a driving transistor, the first transistor is connected between the first reference voltage signal line and the gate of the driving transistor, and the orthographic projection of the first reference voltage signal line on the substrate is located between the orthographic projection of the routing line on the substrate and the orthographic projection of the first gate line on the substrate; Alternatively, the orthographic projection of the first reference voltage signal line on the substrate overlaps with the orthographic projection of the routing line on the substrate; Alternatively, the orthographic projection of the first part of the first reference voltage signal line on the substrate is located between the orthographic projection of the routing line on the substrate and the orthographic projection of the first gate line on the substrate; The orthographic projection of the second portion of the first reference voltage signal line on the substrate overlaps with the orthographic projection of the routing line on the substrate; And / or, the first transistor is a first reset transistor; And / or, the material of the wiring includes molybdenum and titanium; and / or, the first transistor comprises a metal oxide transistor; Preferably, the first transistor comprises an indium gallium zinc oxide transistor; Preferably, the wiring is connected to a DC potential or a power supply potential. Preferably, the film layer where the first reference voltage signal line is located is located between the substrate and the film layer where the first gate line is located; Preferably, the wiring is a reference voltage signal line; Preferably, the pixel circuit includes a second reset transistor, the display panel also includes a light emitting device, the second reset transistor is connected between a second reference voltage signal line and a first end of the light emitting device, and the wiring is connected to the second reference voltage signal line.

8. A display panel, characterized in that: The display panel includes a display area and a non-display area, wherein an edge of the non-display area close to the display area includes a first edge, and the display panel includes: substrate; A first conductive layer, located on one side of the substrate, wherein the first conductive layer includes a first gate line; A plurality of pixel circuits adjacent to the first edge are located on one side of the substrate, the pixel circuits are located in the display area, the pixel circuits include a first transistor close to the first edge, the first transistor includes a first gate, and at least part of the first gate line is reused as the first gate; The interlayer insulating layer is located on the side of the first conductive layer away from the substrate, and the interlayer insulating layer is provided with a first dummy hole penetrating the interlayer insulating layer. The orthographic projection of the first dummy hole on the substrate is located on the side of the orthographic projection of the first gate line on the substrate close to the non-display area.

9. A display panel, characterized in that: The display panel includes a display area and a non-display area, wherein an edge of the non-display area close to the display area includes a first edge, and the display panel includes: A plurality of gate driving circuits adjacent to the first edge are located in the non-display area; the gate driving circuits include at least one effective driving circuit and at least one virtual driving circuit that are adjacently arranged, at least one connection hole, located on a side of the effective driving circuit close to the display area, At least one second dummy hole is located at a side of the dummy driving circuit close to the display area, and a distribution pattern of the connecting holes is the same as a distribution pattern of the second dummy holes.

10. A display device, characterized in that: include: The display panel according to any one of claims 1 to 9.

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