Display device

Abstract

A display device according to an embodiment of the present specification includes: a substrate including a display area, an optical area disposed in the display area and including a through hole, and a non-display area configured to surround the display area; a plurality of insulating layers disposed on the substrate; at least one dam disposed on the plurality of insulating layers; and at least one anti-connection portion disposed on the plurality of insulating layers and disposed closer to the through hole than the at least one dam, in which a first trench is disposed in some of the plurality of insulating layers overlapping the at least one anti-connection portion in the optical region. Accordingly, crack propagation due to external interference in the optical region can be suppressed.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0187616, filed with the Korean Intellectual Property Office on December 20, 2023, the disclosure of which is incorporated herein by reference. Technical field

[0003] This specification relates to a display device, and more particularly to a display device capable of blocking a crack propagation path in an area where a camera device or a sensor is provided. Background art

[0004] As the information age has arrived, display devices for visually displaying electrical information signals are rapidly developing. Various studies are continuously being conducted to develop various display devices that are thin, light, consume low power, and have improved performance.

[0005] As representative display devices, there may be a liquid crystal display (LCD) device, a field emission display (FED) device, an electro - wetting display (EWD) device, an organic light - emitting display (OLED) device, etc.

[0006] An electroluminescent display device, which is a representative organic light - emitting display device, refers to a display device that emits light autonomously. Different from a liquid crystal display device, an electroluminescent display device does not require a separate light source and can thus be manufactured into a thin and light display device. In addition, an electroluminescent display device is also advantageous in terms of power consumption because it operates at a low voltage. Moreover, since an electroluminescent display device is also excellent in terms of color, response speed, viewing angle, and contrast ratio (CR) realization, it is expected to be adopted in various fields. Summary of the invention

[0007] An object to be achieved by one embodiment of this specification is to provide a display device capable of suppressing the propagation of cracks caused by external interference in an area where a camera device or a sensor is provided.

[0008] Another object to be achieved by another embodiment of this specification is to provide a display device capable of ensuring product yield and reliability.

[0009] The objects of the present disclosure are not limited to the above - mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0010] A display device according to an embodiment of the present specification includes: a substrate including a display area, an optical area disposed in the display area and including a through hole, and a non-display area configured to surround the display area; a plurality of insulating layers disposed on the substrate; at least one dam disposed on the plurality of insulations; and at least one anti-connection portion disposed on the plurality of insulations and closer to the through hole than the at least one dam, wherein a first trench is provided in some of the plurality of insulating layers overlapping the at least one anti-connection portion in the optical area.

[0011] Other detailed matters of the exemplary embodiments are included in the detailed description and the drawings.

[0012] According to the display device based on the embodiment of the present specification, a plurality of anti-connection portions are provided on the outer peripheral portion of the through hole, thereby suppressing the penetration of moisture and oxygen introduced from the through hole. The suppression portion can block the movement path of moisture and oxygen by disconnecting the organic common layer disposed on the front surface of the display panel, that is, the light-emitting layer of the light-emitting element.

[0013] According to the display device based on the embodiment of the present specification, a plurality of dams can be provided near the plurality of anti-connection portions to suppress the overflow of the organic insulating layer of the encapsulation layer into the camera device hole. The plurality of dams can suppress the contamination of the camera device hole area that may occur when the organic insulating layer overflows into the camera device hole, and suppress the interference with the camera device to be disposed in the through hole.

[0014] According to the display device based on the embodiment of the present specification, a trench is provided by partially etching the plurality of inorganic insulating layers overlapping the plurality of anti-connection portions, so that even if the through hole breaks, the path through which the crack propagates can be blocked, and the crack propagation can be suppressed.

[0015] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a block diagram of a display device according to an embodiment of the present specification;

[0018] Figure 2 is along Figure 1 a cross-sectional view taken along line II-II' in

[0019] Figure 3 is Figure 1 an enlarged top plan view of area A in

[0020] Figure 4 is Figure 3 an enlarged top plan view of region B in

[0021] Figure 5 is a sectional view taken along line V-V' in Figure 4 ;

[0022] Figure 6A is an enlarged sectional view of region C in Figure 5 according to an embodiment of the present specification;

[0023] Figure 6B is a sectional view of a display device according to another embodiment of the present specification;

[0024] Figure 6C is a sectional view of a display device according to still another embodiment of the present specification;

[0025] Figure 6D is a sectional view of a display device according to still another embodiment of the present specification;

[0026] Figure 6E is a sectional view of a display device according to still another embodiment of the present specification;

[0027] Figure 7A is a sectional view of a display device according to another embodiment of the present specification;

[0028] Figure 7B is a sectional view of a display device according to still another embodiment of the present specification;

[0029] Figure 7C is a sectional view of a display device according to still another embodiment of the present specification; and

[0030] Figure 7D is a sectional view of a display device according to still another embodiment of the present specification. Detailed Embodiments

[0031] Advantages and features of the present disclosure and methods for achieving these advantages and features will be clear by referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0032] The shapes, dimensions, ratios, angles, numbers, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, like reference numerals generally denote like elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising", "having", and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise explicitly stated.

[0033] Even if not explicitly stated, components are interpreted to include a normal error range.

[0034] When terms such as "on", "above", "below", and "next to" are used to describe the positional relationship between two parts, unless these terms are used together with the terms "immediately" or "directly", one or more parts may be located between these two parts.

[0035] When an element or layer is disposed "on" another element or layer, another layer or another element may be directly inserted on or between other elements.

[0036] Although terms such as "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0037] Throughout the specification, like reference numerals generally denote like elements.

[0038] For ease of description, the dimensions and thicknesses of each component shown in the accompanying drawings are shown, and the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0039] The features of the various embodiments of the present disclosure may be partially or completely adhered to or combined with each other and may be interlocked and operated in technically different ways, and the embodiments may be executed independently of each other or in association with each other.

[0040] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 is a block diagram of a display device according to an embodiment of the present specification.

[0042] Refer to Figure 1, the display device 100 according to the embodiment of the present specification may include an image processing unit 151, a timing controller 152, a data driver unit 153, a gate driver unit 154, and a display panel DP.

[0043] In this case, the image processing unit 151 may output a data signal DATA, a data enable signal DE, etc. supplied from the outside. In addition to the data enable signal DE, the image processing unit 151 may also output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0044] In addition to the data enable signal DE or a driving signal including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, the timing controller 152 also receives the data signal DATA from the image processing unit 151. Based on the driving signal, the timing controller 152 may output a gate timing control signal GDC for controlling the operation timing of the gate driver unit 154 and output a data timing control signal DDC for controlling the operation timing of the data driver unit 153.

[0045] In addition, in response to the data timing control signal DDC supplied from the timing controller 152, the data driver unit 153 may sample and latch the data signal DATA supplied from the timing controller 152, convert the data signal DATA into a gamma reference voltage, and output the gamma reference voltage. The data driver unit 153 may output the data signal DATA through data lines DL1 to DLn.

[0046] In addition, the gate driver unit 154 may output a gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 152. The gate driver unit 154 may output the gate signal through gate lines GL1 to GLm.

[0047] The display panel DP may display an image when a pixel P emits light in response to the data signal DATA and the gate signal supplied from the data driver unit 153 and the gate driver unit 154. The detailed structure of the pixel P will be described in detail with reference to Figure 2 for a detailed description.

[0048] The display panel DP may include a display area DA, an optical area OA provided in the display area DA and including a through hole TH, and a non-display area NDA configured to surround the display area DA.

[0049] The display area DA is an area where the display panel DP displays an image.

[0050] In the display area DA, a plurality of pixels P and a circuit for operating the plurality of pixels P can be provided. The plurality of pixels P are the smallest units that make up the display area DA. A display element can be provided in each of the plurality of pixels P. For example, an organic light-emitting element including an anode, a light-emitting layer, and a cathode can be provided in each of the plurality of pixels P. However, the present disclosure is not limited thereto. In addition, the circuit for operating the plurality of pixels P can include driving elements, lines, etc. For example, the circuit can include thin-film transistors, storage capacitors, gate lines, data lines, etc. However, the present disclosure is not limited thereto.

[0051] The optical area OA is an area provided in the display area DA, and the through hole TH can be provided in the optical area OA. The through hole TH can be provided in the display area DA of the display panel DP, thereby reducing the border area as the non-display area NDA and maximizing the display area DA. A design product with a maximized display area DA maximizes the user's screen immersion, thereby improving the aesthetic appearance.

[0052] The through hole TH can be formed to correspond to optoelectronic devices such as a camera device or an optical sensor.

[0053] Figure 1 Two through holes TH are shown. However, the present disclosure is not limited thereto. The number of through holes TH can be set differently. For example, one or two holes can be provided in the display area DA. A camera device can be provided in the first hole, and a distance detection sensor, a face recognition sensor, or a wide-angle camera device can be provided in the second hole.

[0054] The non-display area NDA is an area where no image is displayed.

[0055] The non-display area NDA can be bent so that the non-display area NDA is not visible from the front surface. The non-display area NDA can be covered by a housing (not shown). The non-display area NDA is called a border area.

[0056] Figure 1 It is shown that the non-display area NDA surrounds the display area DA having a quadrilateral shape. However, the shapes and arrangements of the display area DA and the non-display area NDA are not limited to Figure 1 the example shown. That is, the display area DA and the non-display area NDA can be adapted to the design of the electronic device equipped with the display device 100. For example, the exemplary shape of the display area DA can also be a pentagonal shape, a hexagonal shape, a circular shape, an oval shape, etc.

[0057] In the non-display area NDA, various lines and circuits for operating the organic light-emitting elements in the display area DA can be provided. For example, the non-display area NDA may include link lines for transmitting signals to a plurality of sub-pixels and circuits in the display area DA. The non-display area NDA may include in-panel gate (GIP) lines or driving ICs such as a gate driving unit 154 and a data driving unit 153. However, the present disclosure is not limited thereto.

[0058] The display device 100 may further include various additional elements configured to generate various signals or operate pixels in the display area DA. The additional elements for operating the pixels may include an inverter circuit, a multiplexer, an electrostatic discharge (ESD) circuit, etc. The display device 100 may further include additional elements related to functions other than the function of operating the pixels. For example, the display device 100 may further include additional elements providing a touch detection function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure detection function, a haptic feedback function, etc. The above additional elements may be located in the non-display area NDA and / or an external circuit connected to the connection interface.

[0059] Hereinafter, with reference to Figure 2 the cross-sectional structure of the display area DA of the display device 100 will be described in more detail.

[0060] Figure 2 is a cross-sectional view showing the cross-sectional structure of one pixel provided in the display area according to an embodiment of the present specification.

[0061] The display device 100 according to an embodiment of the present specification may include a substrate 110, a first buffer layer 111, a first thin film transistor TR1, a second thin film transistor TR2, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, a second interlayer insulating layer 113b, a connection electrode CE, a first planarization layer 115a, a second planarization layer 115b, an auxiliary electrode 145, a bank 116a, a spacer 116b, an anode 121, a light-emitting layer 122, a cathode 123, a packaging layer 117, and a touch detection unit.

[0062] The substrate 110 is for supporting and protecting the components provided above the substrate 110 of the flexible display device.

[0063] The substrate 110 is a component for supporting various constituent elements included in the display device 100 and can be made of an insulating material. The substrate 110 may include a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c. The interlayer insulating film 110c may be disposed between the first substrate 110a and the second substrate 110b. As described above, the substrate 110 is composed of the first substrate 110a, the second substrate 110b, and the interlayer insulating film 110c, which can inhibit moisture penetration. For example, the first substrate 110a and the second substrate 110b may each be a polyimide (PI) substrate, and the interlayer insulating film 110c may be configured as a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer including the above-mentioned layers.

[0064] A light blocking layer 125 may be disposed on the substrate 110.

[0065] The first buffer layer 111 may be disposed on the substrate 110 while covering the light blocking layer 125. Specifically, a multi-buffer layer 111a may be disposed on the substrate 110 while covering the light blocking layer 125, and an active buffer layer 111b may be disposed on the multi-buffer layer 111a.

[0066] The multi-buffer layer 111a may delay the diffusion of moisture or oxygen that has penetrated into the substrate 110 and includes at least any one of silicon nitride (SiNx) and silicon oxide (SiOx).

[0067] The active buffer layer 111b may protect the first active layer A1 and inhibit various types of defects introduced from the substrate 110. For example, the active buffer layer 111b may include at least any one of a-Si, silicon nitride (SiNx), and silicon oxide (SiOx).

[0068] A first thin film transistor TR1 may be disposed on the first buffer layer 111. The first thin film transistor TR1 includes a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. In this case, according to the design of the pixel circuit, the first source electrode S1 may be the first drain electrode, and the first drain electrode D1 may be the first source electrode.

[0069] The first active layer A1 may be disposed on the first buffer layer 111 to overlap with the light blocking layer 125. The first active layer A1 may include amorphous silicon or polycrystalline silicon (polycrystalline silicon). For example, the first active layer A1 may include low-temperature polycrystalline silicon (LTPS). For example, since the polycrystalline silicon material has a high mobility (100 cm 2 / Vs or greater), low power consumption, and excellent reliability. Therefore, the polysilicon material can be applied to a gate driver and / or a multiplexer (MUX) that drive components for operating thin film transistors for display elements. In the display device 100 according to an embodiment of the present specification, the polysilicon material can be applied to the first active layer A1 of the thin film driving transistor. However, the present disclosure is not limited thereto. For example, according to the characteristics of the display device 100, the polysilicon material can also be applied to the second active layer A2 of the switching thin film transistor. The first active layer A1 can be formed by depositing an amorphous silicon (a-Si) material on the first buffer layer 111, forming polysilicon by performing a dehydration process and a crystallization process, and then patterning the polysilicon. In this case, the first active layer A1 can include a first channel region where a channel is formed when the first thin film transistor TR1 operates and a first source region and a first drain region provided on two opposite sides of the first channel region. The first source region refers to the portion of the first active layer A1 connected to the first source electrode S1, and the first drain region refers to the portion of the first active layer Al connected to the first drain electrode D1. For example, the first source region and the first drain region can be configured by doping the first active layer A1 with ions (impurities). The first source region and the first drain region can be formed by doping the polysilicon material with ions. The first channel region can mean the portion where the polysilicon material remains without being ion-doped.

[0070] A first gate insulating layer 112a can be provided on the first active layer A1. The first gate insulating layer 112a can be configured as a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer including the above-mentioned layers. The first gate insulating layer 112a can have contact holes through which the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 are respectively connected to the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1.

[0071] A first gate electrode G1 of the first thin film transistor TR1 and a first capacitor electrode C1 of the storage capacitor Cst can be provided on the first gate insulating layer 112a.

[0072] In this case, the first gate electrode G1 and the first capacitor electrode C1 can each be configured as a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof. The first gate electrode G1 can be formed on the first gate insulating layer 112a to overlap with the first channel region of the first active layer A1 of the first thin film transistor TR1.

[0073] Based on the operating characteristics of the display device 100 and the structure, type, etc. of the thin film transistor, the first capacitor electrode C1 may not be included. The first gate electrode G1 and the first capacitor electrode C1 may be formed by the same process. In addition, the first gate electrode G1 and the first capacitor electrode C1 may be made of the same material and formed on the same layer.

[0074] A first interlayer insulating layer 113a may be provided over the first gate insulating layer 112a, the first gate electrode G1, and the first capacitor electrode C1. The first interlayer insulating layer 113a may be configured as a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer including the layers mentioned above. In addition, the first interlayer insulating layer 113a may have contact holes through which the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1 are exposed.

[0075] A second capacitor electrode C2 of the storage capacitor Cst may be provided over the first interlayer insulating layer 113a. The second capacitor electrode C2 may be configured as a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys. The second capacitor electrode C2 may be formed to overlap the first capacitor electrode C1 over the first interlayer insulating layer 113a. In addition, the second capacitor electrode C2 may be made of the same material as the first capacitor electrode C1. Based on the operating characteristics of the display device 100 and the structure, type, etc. of the thin film transistor, the second capacitor electrode C2 may not be included.

[0076] A second buffer layer 114 may be provided over the first interlayer insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 may be configured as a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer including the layers mentioned above. The second buffer layer 114 may have contact holes through which the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1 are exposed. In addition, the second buffer layer 114 may have contact holes through which the second capacitor electrode C2 of the storage capacitor Cst is exposed.

[0077] The second buffer layer 114 may be configured as a multilayer. However, the present disclosure is not limited thereto.

[0078] The second active layer A2 of the second thin film transistor TR2 can be disposed on the second buffer layer 114. In this case, the second thin film transistor TR2 can include a second active layer A2, a second gate insulating layer 112b, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. In this case, according to the design of the pixel circuit, the second source electrode S2 can be the drain electrode, and the second drain electrode D2 can be the source electrode.

[0079] In addition, the second active layer A2 can include a second channel region where a channel is formed when the second thin film transistor TR2 operates, and a second source region and a second drain region provided on two opposite sides of the second channel region. The second source region can refer to the portion of the second active layer A2 connected to the second source electrode S2, and the second drain region can refer to the portion of the second active layer A2 connected to the second drain electrode D2.

[0080] The second active layer A2 can be made of an oxide semiconductor. The oxide semiconductor material is a material having a larger bandgap than the silicon material, and since electrons cannot cross the bandgap in the off state, the oxide semiconductor material has a low off-current. Therefore, a thin film transistor including an active layer made of an oxide semiconductor can be applied to a switching thin film transistor that maintains a short on-time and a long off-time. However, the present disclosure is not limited thereto. According to the characteristics of the display device 100, the oxide semiconductor can also be applied to the thin film driving transistor. In addition, since the oxide semiconductor material has a low off-current and can reduce the size of the parasitic capacitance, the oxide semiconductor material is suitable for high-resolution display elements. For example, the second active layer A2 can be made of a metal oxide, such as various metal oxides such as indium gallium zinc oxide (IGZO). In this case, the description has been made on the assumption that the second active layer A2 of the second thin film transistor TR2 is made of IGZO among various metal oxides. However, the present disclosure is not limited thereto. Instead of IGZO, the second active layer A2 of the second thin film transistor TR2 can be made of another metal oxide, such as indium zinc oxide (IZO), indium gallium tin oxide (IGTO), or indium gallium oxide (IGO).

[0081] The second active layer A2 can be formed by depositing a metal oxide on the second buffer layer 114, performing a heat treatment process for stabilization, and then patterning the metal oxide.

[0082] The second gate insulating layer 112b can be disposed on the entire substrate 110 including the second active layer A2. For example, the second gate insulating layer 112b can be configured as a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx), or a multi-layer including the above-mentioned layers.

[0083] The second gate electrode G2 may be disposed on the second gate insulating layer 112b.

[0084] The second gate electrode G2 may be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys.

[0085] For example, the second gate electrode G2 is formed by: forming a metal material on the second gate insulating layer 112b, forming a photoresist pattern on the metal material, and then wet-etching the metal material using the photoresist pattern as a mask. A material that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or their alloys that make up the metal material and does not etch the insulating material can be used as the wet etching solution for etching the metal material.

[0086] A second interlayer insulating layer 113b may be disposed on the second gate insulating layer 112b and the second gate electrode G2. The second interlayer insulating layer 113b may have contact holes through which the first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2 are exposed. For example, the second interlayer insulating layer 113b may have contact holes through which the first source region and the first drain region of the first active layer A1 of the first thin film transistor TR1 are exposed. The second interlayer insulating layer 113b may have contact holes through which the second source region and the second drain region of the second active layer A2 of the second thin film transistor TR2 are exposed.

[0087] The second interlayer insulating layer 113b may be configured as a single layer made of silicon nitride (SiNx) or silicon oxide (SiOx) or a multi-layer including the layers mentioned above.

[0088] A connection electrode CE, a first source electrode S1 and a first drain electrode D1 of the first thin film transistor TR1, and a second source electrode S2 and a second drain electrode D2 of the second thin film transistor TR2 may be disposed on the second interlayer insulating layer 113b.

[0089] The connection electrode CE may be electrically connected to the second drain electrode D2 of the second thin film transistor TR2. In addition, the connection electrode CE may be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through a contact hole formed in the second buffer layer 114 and the second interlayer insulating layer 113b. That is, the connection electrode CE may be used to electrically connect the second capacitor electrode C2 of the storage capacitor Cst and the second drain electrode D2 of the second thin film transistor TR2.

[0090] In this case, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 can be connected to the first active layer A1 of the first thin film transistor TR1 through contact holes formed in the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, and the second interlayer insulating layer 113b.

[0091] The second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can be connected to the second active layer A2 through contact holes formed in the second interlayer insulating layer 113b.

[0092] The connection electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can be formed by the same process and made of the same material.

[0093] For example, the connection electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can each be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or their alloys. For example, the connection electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 can each have a three-layer structure including titanium (Ti) / aluminum (Al) / titanium (Ti). However, the present disclosure is not limited thereto.

[0094] The connection electrode CE can be integrally connected to the second drain electrode D2 of the second thin film transistor TR2. However, the present disclosure is not limited thereto.

[0095] A first planarization layer 115a can be provided above the connection electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2, and the second interlayer insulating layer 113b.

[0096] The first planarization layer 115a can be an organic layer for planarizing and protecting the upper portions of the first thin film transistor TR1 and the second thin film transistor TR2. For example, the first planarization layer 115a can be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0097] An auxiliary electrode 145 may be provided on the first planarization layer 115a. The auxiliary electrode 145 may be connected to the second drain electrode D2 of the second thin film transistor TR2 through a contact hole in the first planarization layer 115a. The auxiliary electrode 145 may be used to electrically connect the second thin film transistor TR2 and the anode 121. In addition, the auxiliary electrode 145 may be configured as a single layer or a multi-layer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and their alloys. The auxiliary electrode 145 may be made of the same material as the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2.

[0098] A second planarization layer 115b may be provided above the auxiliary electrode 145 and the first planarization layer 115a. For example, the second planarization layer 115b may be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0099] The light emitting element 120 may be provided on the second planarization layer 115b.

[0100] The anode 121 may be provided on the second planarization layer 115b. In this case, the anode 121 may be electrically connected to the auxiliary electrode 145 through a contact hole provided in the second planarization layer 115b. The anode 121 may be made of a metal material.

[0101] In the case where the display device 100 is a top emission type display device, in which light emitted from the light emitting element 120 propagates toward the upper side of the substrate 110 on which the light emitting element 120 is provided, the anode 121 may further include a transparent conductive layer and a reflective layer provided on the transparent conductive layer. For example, the transparent conductive layer may be made of a transparent conductive oxide such as ITO or IZO. For example, the reflective layer may be made of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or their alloys.

[0102] The bank 116 may be provided while covering the anode 121. A portion of the bank 116 corresponding to the light emitting region of the sub-pixel may be open. A portion of the anode 121 may be exposed through the opening portion (hereinafter referred to as the opening region) of the bank 116. In this case, the bank 116 may be made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as benzocyclobutenyl resin, acrylic resin, or imide-based resin. However, the present disclosure is not limited thereto. A spacer 116b may also be provided on the bank 116a.

[0103] The light-emitting layer 122 may be provided in the opening area of the bank 116 and in the area around the opening area. Accordingly, the light-emitting layer 122 may be provided on the anode 121, and the anode 121 may be exposed through the opening area of the bank 116.

[0104] The cathode 123 may be provided on the light-emitting layer 122.

[0105] The light-emitting element 120 may be formed of the anode 121, the light-emitting layer 122, and the cathode 123. The light-emitting layer 122 may include a plurality of organic films.

[0106] The encapsulation layer 117 may be positioned on the light-emitting element 120.

[0107] The encapsulation layer 117 may have a single-layer structure or a multi-layer structure. For example, the encapsulation layer 117 may include a first encapsulation layer 117a, a second encapsulation layer 117b, and a third encapsulation layer 117c.

[0108] In this case, the first encapsulation layer 117a and the third encapsulation layer 117c may each be made of an inorganic film, and the second encapsulation layer 117b may be made of an organic film. Among the first encapsulation layer 117a, the second encapsulation layer 117b, and the third encapsulation layer 117c, the second encapsulation layer 117b may be the thickest and may serve as a planarization layer.

[0109] The first encapsulation layer 117a may be provided on the cathode 123 and closest to the light-emitting element 120. The first encapsulation layer 117a may be made of an inorganic insulating material that can be deposited at a low temperature. For example, the first encapsulation layer 117a may be made of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al2O3), or the like. Since the first encapsulation layer 117a is deposited in a low-temperature environment, damage to the light-emitting layer 122 made of an organic material that is vulnerable to a high-temperature environment during the deposition process can be suppressed.

[0110] The second encapsulation layer 117b may have an area smaller than that of the first encapsulation layer 117a. In this case, the second encapsulation layer 117b may be formed to expose two opposite ends of the first encapsulation layer 117a. The second encapsulation layer 117b may serve as a buffer for reducing stress between layers when the flexible display device is bent. The second encapsulation layer 117b may be used to improve planarization performance.

[0111] For example, the second encapsulation layer 117b may be made of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbide (SiOC). For example, the second encapsulation layer 117b may also be formed by an inkjet method. However, the present disclosure is not limited thereto.

[0112] The third encapsulation layer 117c may be formed on the upper portion of the substrate 110 having the second encapsulation layer 117b to cover the top surface and the side surfaces of each of the second encapsulation layer 117b and the first encapsulation layer 117a. In this case, the third encapsulation layer 117c may minimize or block the penetration of external moisture or oxygen into the first encapsulation layer 117a and the second encapsulation layer 117b. For example, the third encapsulation layer 117c may be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0113] A touch detection layer may be provided on the encapsulation layer 117.

[0114] For example, a touch buffer layer 118a may be provided on the third encapsulation layer 117c, and a touch electrode TE may be provided on the touch buffer layer 118a.

[0115] The touch electrode TE may include a touch sensor metal TS and a bridge metal BM provided on different layers. A touch interlayer insulating layer 118b may be provided between the touch sensor metal TS and the bridge metal BM.

[0116] The touch buffer layer 118a and the touch interlayer insulating layer 118b may be provided to remove the level difference at the points where the touch electrode TE is provided and to achieve appropriate electrical insulation.

[0117] Meanwhile, although not shown, a polarization layer may be provided on the touch detection layer.

[0118] The polarization layer suppresses the reflection of external light in the display area DA of the substrate 110. When the display device 100 is used externally, external natural light may be introduced and reflected by the reflection layer included in the anode 121 of the light-emitting element 120, or reflected by an electrode made of metal and provided under the light-emitting element 120. The light beam reflected as described above may prevent the image on the display device 100 from being visually recognized. The polarization layer may polarize the light introduced from the outside in a specific direction, thereby suppressing the reflected light from being released to the outside of the display device 100 again.

[0119] Although not shown, a cover glass may be bonded to the polarization layer through a bonding layer. The bonding layer may be used to bond the components of the display device 100. For example, the bonding layer may be formed by using an adhesive for an optically transparent display such as a pressure-sensitive adhesive, an optically transparent adhesive (Optical Clear Adhesive (OCR)), or an optically transparent resin (Optical Clear Resin (OCR)). However, the present disclosure is not limited thereto.

[0120] The cover glass may protect the components of the display device 100 from external impact and suppress damage such as scratches.

[0121] Figure 3 is an enlarged top plan view showing a region A corresponding to the optical region in Figure 1 .

[0122] Referring to Figure 3 , a through hole TH for setting an optoelectronic device can be provided at the center of the optical region OA, and a camera device module or a sensor can be provided in the through hole TH. The optical region OA can include all regions in which a dam structure 300, an anti-connection part 200, etc. adjacent to the circular or elliptical through hole TH are provided. The through hole TH can be removed by laser in the panel finishing step. The non-display region NDA can be located between the through hole TH and the display region DA, and a high-potential power line PL, a gate line SL, etc. can be provided in the non-display region NDA. The anti-connection part 200 and the dam structure 300 can be provided around the through hole TH. Referring to Figure 3 , the anti-connection part 200 can include a first suppression part 210 and a second suppression part 220, and the dam structure 300 can include a first dam 301 and a second dam 302. The first suppression part 210, the first dam 301, the second suppression part 220, and the second dam 302 can be provided in sequence based on the through hole TH. Generally, the dam structure can be used to maintain the bonding force between the upper substrate and the lower substrate constituting the display panel DP by suppressing the downward flow of a second encapsulation layer 117b, which is a part of the encapsulation part 117 on the outer peripheral part of the display panel DP, to the end of the outer peripheral part of the display panel 100. The dam structure 300 in the optical region OA can also have a plurality of structures, such as the first dam 301 and the second dam 302, to suppress the second encapsulation layer 117b of the encapsulation layer 117 for protecting the light-emitting element 150 from entering or leaking into the optical region OA. The anti-connection part 200 can be formed to suppress the penetration of moisture or oxygen by disconnecting the light-emitting layer 122. Two dams are provided in this specification. However, the present disclosure is not limited thereto. Additional dams can be provided according to the layout of the space. Referring to Figure 3, the first suppression part 210 can be arranged close to the through hole TH, and then the first dam 301, the second suppression part 220, and the second dam 302 can be sequentially arranged. The first suppression part 210 and the second suppression part 220 can be arranged to protect the light-emitting element 120 in the display area from moisture or oxygen that may be introduced from the through hole TH. The light-emitting layer 122 of the light-emitting element 120 can be deposited on the front surface of the display panel 100 and can also be uniformly deposited in the optical area OA. Due to the nature of the organic material, the light-emitting layer 122 has high reactivity and dispersibility with respect to moisture and oxygen, such that moisture and oxygen can be transmitted to the light-emitting element 120 in the display area DA. The first suppression part 210 and the second suppression part 220 can partially disconnect the light-emitting layer 122 to suppress this problem. In this specification, two suppression parts are shown. However, the present disclosure is not limited thereto.

[0123] The light-emitting element 120 and the pixel circuit in the corresponding area are removed to set the optical area OA. However, the light-emitting element 120 and the pixel circuit provided on the upper side, lower side, left side, and right side based on the optical area OA need to be electrically connected. For this purpose, a high-potential power line PL, a gate line SL, etc. can be arranged in the non-display area NDA adjacent to the optical area OA to be connected on the upper side, lower side, left side, and right side while bypassing the optical area OA.

[0124] Figure 4 is Figure 3 An enlarged top plan view of area B in

[0125] Referring to Figure 4 , the first suppression part 210 can be arranged close to the through hole TH, the first dam 301 can be arranged between the first suppression part 210 and the second suppression part 220, and the second dam 302 can be arranged on the right side of the second suppression part 220. The first suppression part 210 can include a first structure 211, a second structure 212, a third structure 213, and a fourth structure 214, and the second suppression part 220 can include a fifth structure 221, a sixth structure 222, a seventh structure 223, and an eighth structure 224. Referring to Figure 3 and Figure 4 , the first suppression part 210, the first dam 301, the second suppression part 220, and the second dam 302 can be arranged in a closed-loop shape based on the through hole TH. When any one of the first suppression part 210, the first dam 301, the second suppression part 220, and the second dam 302 is penetrated, moisture and oxygen can penetrate from the outside into the display area DA, or the second encapsulation layer 117b can flow through the optical area OA and flow from the inside to the through hole TH. Therefore, the first suppression part 210, the first dam 301, the second suppression part 220, and the second dam 302 are arranged in a closed-loop shape. Referring to Figure 4, the first suppression part 210 and the second suppression part 220 may each have four structures. However, the present disclosure is not limited thereto. For example, the first suppression part 210 and the second suppression part 220 may each have three or fewer or five or more structures. However, the present disclosure is not limited thereto.

[0126] Figure 5 is a cross-sectional view of an optical region taken along Figure 4 the line V-V' in

[0127] The first suppression part 210 and the second suppression part 220 surround the through hole TH in a closed-loop shape. The first dam 301 may be disposed between the first suppression part 210 and the second suppression part 220, and the second dam 302 may be disposed in a closed-loop shape on another side surface of the second suppression part 220. Referring to Figure 5 , the through hole TH may be disposed close to the first suppression part 210.

[0128] Referring to Figure 4 , the first suppression part 210 may include a first structure 211 to a fourth structure 214. The first to fourth structures 211, 212, 213, and 214 may each be formed into a two-stage structure including an upper part and a lower part for disconnecting the light-emitting layer 122, and an undercut structure may be defined on a side surface of the upper part, and the undercut structure may become a moisture penetration path for moisture from the region where the through hole TH is provided. Specifically, the upper part of each of the first to fourth structures 211, 212, 213, and 214 is provided with a trapezoidal cross-section having a tapered shape, and the lower part of each of the first to fourth structures 211, 212, 213, and 214 is provided with a rectangular cross-section having an inverted tapered or approximately vertical side surface and having a predetermined height, so that a width difference may occur between the bottom surface of the upper part and the top surface of the lower part at the point where the upper part and the lower part meet. Since the top surface of the lower part may be formed to be narrower than the bottom surface of the upper part, an undercut structure may be formed, and a part of the bottom surface of the upper part may be exposed through the undercut structure. Therefore, the light-emitting layer 122 deposited on the front surface of the display panel DP may be disconnected by the undercut structure on the side surface of the upper part of the first to fourth structures 211, 212, 213, and 214.

[0129] The first to fourth structures 211, 212, 213, and 214 constituting the first suppression part 210 may be made of organic materials and inorganic materials. For example, the upper part of each of the first to fourth structures 211, 212, 213, and 214 may be made of the same material as the first planarization layer 115a or the second planarization layer 115b. However, the present disclosure is not limited thereto. In addition, the lower part of each of the first to fourth structures 211, 212, 213, and 214 may be made of the same material as the second interlayer insulating layer 113b. However, the present disclosure is not limited thereto.

[0130] The second suppression part 220 may include fifth to eighth structures 221, 222, 223, and 224. Similar to the first to fourth structures 211, 212, 213, and 214, the fifth to eighth structures 221, 222, 223, and 224 constituting the second suppression part 220 may each have a two-stage structure including an upper part and a lower part. The second encapsulation layer 117b provided on the second suppression part 220 may make it difficult for moisture or oxygen to penetrate the upper part. Similar to the first suppression part 210, the second suppression part 220 may have an undercut structure formed in the side surface of the upper part to block the path through which moisture or oxygen mainly penetrates into the through hole TH or the side surface where the first suppression part 210 is provided. The arrangement of the first suppression part 210 and the second suppression part 220 may suppress moisture or oxygen from penetrating from the optical region OA to the light-emitting element 120 in the display region DA through the light-emitting layer 122.

[0131] The fifth to eighth structures 221, 222, 223, and 224 constituting the second suppression part 220 may also be made of organic materials and inorganic materials. For example, the upper part of each of the fifth to eighth structures 221, 222, 223, and 224 may be made of the same material as the first planarization layer 115a or the second planarization layer 115b. However, the present disclosure is not limited thereto. The lower part of each of the fifth to eighth structures 221, 222, 223, and 224 may be made of the same material as the second interlayer insulating layer 113b. However, the present disclosure is not limited thereto.

[0132] As Figure 5 shown, the first dam 301 and the second dam 302 may be formed by stacking the second planarization layer 115b, the bank 116a, and the spacer 116b. However, the present disclosure is not limited thereto. The first dam 301 and the second dam 302 may further include the first planarization layer 115a and may further include other layers.

[0133] Referring to Figure 3, the optical region OA can vary according to the size of the imaging device to be applied to the product. The corresponding region is shown as a blank space, but some insulating films or wiring structures can be provided in this region. However, the separate description of the dummy region is omitted because the dummy region does not remain in the finished product when the via hole TH is removed by laser. The laser beam can be emitted in a circular or elliptical shape according to the shape of the optical region OA. All regions on the substrate including the substrate 110 can be removed by the emitted laser beam. There may be a difference between the actual optical region OA and the laser irradiation region. For example, the laser irradiation region of the optical region OA can be a region formed inward by about 100 μm. It is necessary to define the difference between the laser irradiation region and the optical region OA so that the insulating layer of the optical region OA is not damaged during laser irradiation. A picosecond laser or a femtosecond laser can be used as the laser. However, the present disclosure is not limited thereto. A laser refers to a device that amplifies light generated by applying energy to a specific material and uses the induced and emitted light. The laser beam has the same characteristics as radio waves and has the directivity of monochromatic light. Therefore, lasers are used for communication, medical, or industrial purposes. By using lasers, patterns can be easily formed on desired parts or specific positions can be easily removed. Lasers utilize energy to form or remove patterns. When the energy of the laser is emitted onto an object, the thermal energy melts the object to form a pattern. The longer the time the laser beam is applied, the more thermal effects that may occur and transfer to the adjacent regions where the pattern is formed. This thermal effect is the accumulation of heat around the laser irradiation region of the object, and this heat may cause the surrounding region larger than the set pattern to burn or deform. Due to these characteristics of the laser, when the region irradiated by the laser overlaps with or is adjacent to the insulating film, the thermal energy of the laser may deform the insulating film. The deformation of the insulating film may cause cracks, and the cracks may propagate through the insulating film, which may lead to the separation of the insulating film and subsequent penetration of moisture and oxygen. For example, in order to suppress the deformation or separation of the insulating films (e.g., the multi-buffer layer 111a, the active buffer layer 111b, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b), all the insulating films can be removed at a distance of about 100 μm from the laser irradiation position.

[0134] The problem lies in that: cracks that occur when the substrate 110 is cut by a laser propagate through the inorganic insulating layer. Moisture or oxygen is characterized by reacting with the light-emitting layer 122 of the light-emitting element 120 and transferring to the light-emitting layer 122 of the light-emitting element 120, and the cracks can transfer through the hard inorganic insulating layer that does not have flexibility. Alternatively, when a camera device or a sensor is assembled into the through-hole TH formed by a laser, cracks may occur due to interference. The cracks that occur as described above may also propagate through the inorganic insulating layer. When cracks that occur in the through-hole TH propagate through the inorganic insulating layer, line defects or growing dark spot (GDS) defects may occur.

[0135] Therefore, in the display device 100 according to an embodiment of the present specification, first trenches T1 may be provided in some of the plurality of insulating layers provided in the optical region OA, so as to form a stepped structure on the plurality of insulating layers, which can block the crack propagation path.

[0136] Figure 6A is according to an embodiment of the present specification Figure 5 An enlarged cross-sectional view of region C in

[0137] Referring to Figure 5 and Figure 6A , according to an embodiment of the present specification, first trenches T1 may be provided in some of the plurality of insulating layers that overlap with at least one anti-connection portion 200 in the optical region OA. For example, the plurality of insulating layers may be at least one of a first buffer layer 111, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, and a second interlayer insulating layer 113b provided on the substrate 110, and the first trenches T1 may be provided in some of the plurality of insulating layers provided on the upper side.

[0138] Specifically, referring together to Figure 3 and Figure 6A , the first trenches T1 may be provided by etching at least partially the plurality of insulating layers that overlap with at least one anti-connection portion 200 provided in the optical region OA, that is, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0139] A stepped structure may be formed on the plurality of insulating layers by the first trenches T1. Therefore, even if the through-hole TH breaks, the propagation of cracks can be suppressed because the inorganic insulating layer through which the cracks can propagate is removed from the region where the first trenches T1 are formed.

[0140] In addition, according to an embodiment of the present specification, at least any one of the first planarization layer 115a and the second planarization layer 115b may be disposed in the first trench T1 to fill the first trench T1.

[0141] According to an embodiment of the present specification, the first trench T1 may be formed by at least partially removing a plurality of inorganic insulating layers through which cracks may propagate, and the inside of the first trench T1 is filled with an organic material. Therefore, even if the through hole TH breaks, the crack does not further propagate in the first trench T1.

[0142] Figure 5 and Figure 6A The first trench disposed in the optical region OA is shown. However, the first trench in the optical region OA according to the embodiment of the present specification is not limited thereto.

[0143] Figure 6B is a cross-sectional view of a display device according to another embodiment of the present specification. Figure 6C is a cross-sectional view of a display device according to still another embodiment of the present specification. Figure 6D is a cross-sectional view of a display device according to still another embodiment of the present specification. Figure 6E is a cross-sectional view of a display device according to still another embodiment of the present specification.

[0144] As Figure 6B shown, the display device 1000 according to another embodiment of the present specification may further include: a first trench T1 configured to overlap at least one anti-connection portion 200 provided in the optical region OA; and a second trench T2 provided in some of the plurality of insulating layers overlapping the dam structure 300 provided in the optical region OA.

[0145] Specifically, as Figure 6B shown, the optical region OA may include a first trench T1 formed by at least partially etching the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b overlapping at least one anti-connection portion 200, and a second trench T2 formed by at least partially etching the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112a, and the second interlayer insulating layer 113b overlapping the dam structure 300.

[0146] Accordingly, in the display device 1000 according to another embodiment of the present specification, the first trench T1 and the second trench T2 are provided in the optical region OA. Accordingly, even when a crack occurs during the formation of the through hole TH in the optical region OA or when the optoelectronic device is assembled into the through hole TH, the crack propagation path is blocked by the first trench T1 and the second trench T2, which can suppress defects caused by crack propagation.

[0147] For example, after forming a plurality of insulating layers, the depths of the first trench T1 and the second trench T2 formed in some of the plurality of insulating layers can be adjusted by using a mask process. In this case, the first trench T1 and the second trench T2 can be formed by the same mask process.

[0148] If necessary, the depths of the first trench T1 and the second trench T2 can be adjusted by changing the conditions of the mask process.

[0149] Figure 6C is a cross-sectional view of a display device according to still another embodiment of the present specification.

[0150] As Figure 6C shown, in the display device 1100 according to still another embodiment of the present specification, the first trench T1 and the second trench T2 can overlap with at least one anti-connection part 200 and the dam structure 300, and are at least partially provided on the gate metal GM, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b that are provided on the same layer as the gate electrode G1 of the first thin film transistor.

[0151] Figure 6D is a cross-sectional view of a display device according to still another embodiment of the present specification. Figure 6E is a cross-sectional view of a display device according to still another embodiment of the present specification.

[0152] As Figure 6D shown, in the display device 1200 according to still another embodiment of the present specification, the first trench T1 and the second trench T2 can overlap with at least one anti-connection part 200 and the dam structure 300, and are at least partially provided on the light blocking layer 125, the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0153] Figure 6E is a cross-sectional view of a display device according to still another embodiment of the present specification.

[0154] As Figure 6EAs shown, in a display device 1300 according to another embodiment of the present specification, the first trench T1 and the second trench T2 may overlap with at least one anti-connection part 200 and a dam structure 300, and are at least partially disposed on the first buffer layer 111, the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, the second gate insulating layer 112b, and the second interlayer insulating layer 113b.

[0155] Therefore, according to another embodiment of the present specification, the first trench T1 and the second trench T2 are disposed in the optical region OA. Thus, even when a crack occurs during the formation of a via TH in the optical region OA or when an optoelectronic device is assembled to the via TH, the crack propagation path is blocked by the first trench T1 and the second trench T2, which can suppress defects caused by crack propagation.

[0156] Furthermore, according to another embodiment of the present specification, the first trench T1 and the second trench T2 are disposed in the optical region OA to overlap with at least one anti-connection part 200 and a dam structure 300, such that a separate space for suppressing crack propagation is not required, and the non-display region NDA adjacent to the optical region OA can be minimized.

[0157] Hereinafter, a more detailed description of the optical region OA of a display device according to another embodiment of the present specification will be described with reference to FIG. 7.

[0158] Figure 7A is a cross-sectional view of a display device according to another embodiment of the present specification. Figure 7B is a cross-sectional view of a display device according to another embodiment of the present specification. Figure 7C is a cross-sectional view of a display device according to another embodiment of the present specification. Figure 7D is a cross-sectional view of a display device according to another embodiment of the present specification. Except for the first metal layer and the second metal layer, Figures 7A to 7D the cross-sectional view in Figures 6A to 6E is substantially the same in structure as the cross-sectional view in

[0159] Therefore, for ease of description, repeated descriptions except for the first metal layer and the second metal layer will be omitted.

[0160] For example, the first metal layer 410 may be disposed in the first trench T1 and the second trench T2 and adjacent to the surfaces of some of the plurality of insulating layers.

[0161] As Figure 7AAs shown in [Fig.], the first metal layer 410 may be disposed in the first trench T1 and the second trench T2 and adjacent to the surfaces of the plurality of insulating layers. For example, the first metal layer 410 may be made of the same material as the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1.

[0162] In the display device 1400 according to another embodiment of the present specification, the crack propagation path may be blocked by the stepped structure of the plurality of insulating layers formed by the first trench T1 and the second trench T2, and the crack propagation may be further blocked by the first metal layer 410 disposed in the first trench T1 and the second trench T2 and adjacent to the surfaces of the plurality of insulating layers. Therefore, even if a crack occurs when forming the through hole TH in the optical region OA or assembling the optoelectronic device to the through hole TH, the crack propagation path may be completely blocked by the first trench T1, the second trench T2, and the first metal layer 410, which may suppress the defects caused by the crack propagation.

[0163] Figure 7A The structure of the first metal layer 410 disposed in the first trench T1 and the second trench T2 and along the surfaces of some of the plurality of insulating layers in the optical region OA is shown. However, the structure of the optical region OA according to the embodiment of the present specification is not limited thereto.

[0164] Figure 7B is a cross-sectional view of a display device according to another embodiment of the present specification.

[0165] The display device 1500 according to another embodiment of the present specification may further include a second metal layer 520 disposed below the first trench T1 and the second trench T2 in the optical region OA.

[0166] For example, as Figure 7B shown, the first metal layer 510 may be disposed in the first trench T1 and the second trench T2 and adjacent to the side surfaces of some of the plurality of insulating layers. The first metal layer 510 and the second metal layer 520 may be adjacent to each other. For example, the first metal layer 510 may be disposed on the same layer as the first source electrode S1 and the first drain electrode D1 and made of the same material as the first source electrode S1 and the first drain electrode D1, and the second metal layer 520 may be disposed on the same layer as the first gate electrode G1 and made of the same material as the first gate electrode G1.

[0167] In a display device 1500 according to another embodiment of the present specification, a crack propagation path can be blocked by a stepped structure of a plurality of insulating layers formed by a first trench T1 and a second trench T2, and the crack propagation path can be further blocked by a first metal layer 510 disposed in the first trench T1 and the second trench T2 and a second metal layer 520 disposed under the first trench T1 and the second trench T2. Accordingly, even when a crack occurs when forming a through hole TH in the optical region OA or assembling an optoelectronic device to the through hole TH, the crack propagation path can be completely blocked by the first trench T1, the second trench T2, the first metal layer 510, and the second metal layer 520, which can suppress defects caused by crack propagation.

[0168] According to another embodiment of the present specification, the depths of the first trench T1 and the second trench T2 in some of the plurality of insulating layers can be adjusted. In this case, the materials for forming the first metal layer 510 and the second metal layer 520 can vary according to the depths of the first trench T1 and the second trench T2.

[0169] Figure 7C is a cross-sectional view of a display device according to still another embodiment of the present specification. As Figure 7C shown, in a display device 1600 according to still another embodiment of the present specification, the first metal layer 610 can be made of the same material as the first source electrode S1 and the first drain electrode D1, and the second metal layer 620 can be made of the same material as the light blocking layer 125.

[0170] Figure 7D is a cross-sectional view of a display device according to still another embodiment of the present specification. As Figure 7D shown, in a display device 1700 according to still another embodiment of the present specification, the second metal layer 720 can be disposed in the first trench T1 and the second trench T2 and adjacent to the surface of the plurality of insulating layers, and the first metal layer 710 can be disposed in the first trench T1 and the first trench T2 and adjacent to the surface of the second metal layer 720. For example, the first metal layer 710 can be disposed on the same layer as the second source electrode S2 and the second drain electrode D2 and made of the same material as the second source electrode S2 and the second drain electrode D2, and the second metal layer 720 can be disposed on the same layer as the first source electrode S1 and the first drain electrode D1 and made of the same material as the first source electrode S1 and the first drain electrode D1.

[0171] Accordingly, according to another embodiment of the present specification, the first trench T1 and the second trench T2 are provided in the optical region OA. Thus, even if cracks occur when forming the through hole TH in the optical region OA or assembling the optoelectronic device into the through hole TH, the crack propagation path is blocked by the first trench T1 and the second trench T2, which can suppress defects caused by crack propagation. In addition, the first trench T1 and the second trench T2 are provided in the optical region OA to overlap with at least one anti-connection portion 200 and the dam structure 300, so that a separate space for suppressing crack propagation is not required, and the non-display region NDA adjacent to the optical region OA can be minimized.

[0172] In addition, according to another embodiment of the present specification, the first metal layers 410, 510, 610, and 710 may be provided in the first trench T1 and the second trench T2, and the second metal layers 420, 520, 620, and 720 may be provided adjacent to the first metal layers 410, 510, 610, and 710, so that crack propagation can be further blocked. Thus, even if cracks occur when forming the through hole TH in the optical region OA or assembling the optoelectronic device into the through hole TH, the crack propagation path can be completely blocked by the first trench T1, the second trench T2, the first metal layers 410, 510, 610, and 710, and the second metal layers 420, 520, 620, and 720, which can suppress defects caused by crack propagation.

[0173] Exemplary embodiments of the present disclosure may also be described as follows:

[0174] According to one aspect of the present disclosure, a display device includes: a substrate including a display region, an optical region provided in the display region and including a through hole, and a non-display region configured to surround the display region; a plurality of insulating layers provided on the substrate; at least one dam provided on the plurality of insulating layers; and at least one anti-connection portion provided on the plurality of insulating layers and provided closer to the through hole than at least one dam, wherein a first trench is provided in some of the plurality of insulating layers that overlap with at least one anti-connection portion in the optical region.

[0175] The plurality of insulating layers may include at least one of a first buffer layer, a first gate insulating layer, a first interlayer insulating layer, a second buffer layer, a second gate insulating layer, and a second interlayer insulating layer provided on the substrate, and the first trench is provided in some of the plurality of insulating layers provided on the upper side.

[0176] The display device may further include a second trench provided in some of the plurality of insulating layers that overlap with at least one dam in the optical region.

[0177] The display device may further include: a first thin film transistor disposed on a substrate in a display area and including a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; at least one insulating layer disposed on the first gate electrode; a second thin film transistor disposed on the at least one insulating layer and including a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; a first planarization layer disposed above the first source electrode and the first drain electrode of the first thin film transistor, and the second source electrode and the second drain electrode of the second thin film transistor, and a second planarization layer disposed above the first planarization layer, wherein at least any one of the first planarization layer and the second planarization layer is disposed in a first trench to fill the first trench.

[0178] The display device may further include a first metal layer disposed in each of the first trench and the second trench and disposed along a surface of some of the plurality of insulating layers.

[0179] The first metal layer is disposed in each of the first trench and the second trench and may be adjacent to the surface of the plurality of insulating layers.

[0180] The display device may further include: a first thin film transistor disposed on a substrate in a display area and including a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; at least one insulating layer disposed on the first gate electrode; and a second thin film transistor disposed on the at least one insulating layer and including a second active layer, a second gate electrode, a second source electrode, and a second drain electrode.

[0181] The first metal layer may be made of the same material as the first source electrode and the first drain electrode.

[0182] The display device may further include a second metal layer disposed below each of the first trench and the second trench.

[0183] The first metal layer is disposed in each of the first trench and the second trench and is adjacent to side surfaces of some of the plurality of insulating layers, and the first metal layer and the second metal layer may be adjacent to each other.

[0184] The first metal layer is disposed on the same layer as the first source electrode and the first drain electrode and is made of the same material as the first source electrode and the first drain electrode, and the second metal layer may be disposed on the same layer as the first gate electrode and is made of the same material as the first gate electrode.

[0185] The display device may further include a light blocking layer disposed below the first active layer to overlap with the first gate electrode, the first metal layer may be made of the same material as the first source electrode and the first drain electrode, and the second metal layer may be made of the same material as the light blocking layer.

[0186] The second metal layer is disposed in each of the first trench and the second trench, and is adjacent to the surfaces of the plurality of insulating layers and the surfaces of the first metal layer that are disposed in each of the first trench and the second trench and may be adjacent to the surfaces of the second metal layer.

[0187] The first metal layer is disposed on the same layer as the second source electrode and the second drain electrode and is made of the same material as the second source electrode and the second drain electrode, and the second metal layer may be disposed on the same layer as the first source electrode and the first drain electrode and is made of the same material as the first source electrode and the first drain electrode.

[0188] The display device may further include an optoelectronic device disposed to overlap the optical region.

[0189] A via hole is formed corresponding to the optoelectronic device.

[0190] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The protection scope of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: a substrate including a display area, an optical area disposed in the display area and including a through hole, and a non-display area configured to surround the display area; a plurality of insulating layers disposed on the substrate; at least one dam disposed on the plurality of insulating layers; as well as at least one connection prevention portion disposed on the plurality of insulating layers and disposed closer to the through hole than the at least one dam, Wherein, a first groove is provided in some of the plurality of insulating layers overlapping the at least one connection preventing portion in the optical region.

2. The display device according to claim 1, wherein: The plurality of insulating layers include at least one of a first buffer layer, a first gate insulating layer, a first interlayer insulating layer, a second buffer layer, a second gate insulating layer, and a second interlayer insulating layer disposed on the substrate, and The first trench is disposed in some of the plurality of insulating layers disposed on the upper side.

3. The display device according to claim 1, further comprising: Second trenches are provided in some of the plurality of insulating layers overlapping the at least one dam in the optical region.

4. The display device according to claim 2, further comprising: a first thin film transistor, the first thin film transistor being disposed on the substrate in the display area and comprising a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; at least one insulating layer disposed on the first gate electrode; a second thin film transistor disposed on the at least one insulating layer and including a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; a first planarization layer, the first planarization layer being disposed above the first source electrode and the first drain electrode of the first thin film transistor, the second source electrode and the second drain electrode of the second thin film transistor, and a second planarization layer disposed above the first planarization layer, At least any one of the first planarization layer and the second planarization layer is disposed in the first trench to fill the first trench.

5. The display device according to claim 3, further comprising: A first metal layer is disposed in each of the first trench and the second trench and along surfaces of some of the plurality of insulating layers.

6. The display device according to claim 5, wherein: The first metal layer is disposed in each of the first trench and the second trench and is adjacent to surfaces of the plurality of insulating layers.

7. The display device according to claim 6, further comprising: a first thin film transistor, the first thin film transistor being disposed on the substrate in the display area and comprising a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; at least one insulating layer disposed on the first gate electrode; as well as A second thin film transistor is disposed on the at least one insulating layer and includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode.

8. The display device according to claim 7, wherein: The first metal layer is made of the same material as the first source electrode and the first drain electrode.

9. The display device according to claim 7, further comprising: A second metal layer is disposed under each of the first trench and the second trench.

10. The display device according to claim 9, wherein: The first metal layer is disposed in each of the first trench and the second trench and adjoins side surfaces of some of the plurality of insulating layers, and the first metal layer and the second metal layer adjoin each other.

11. The display device according to claim 10, wherein: The first metal layer is disposed on the same layer as the first source electrode and the first drain electrode and is made of the same material as the first source electrode and the first drain electrode, and the second metal layer is disposed on the same layer as the first gate electrode and is made of the same material as the first gate electrode.

12. The display device according to claim 10, further comprising: a light blocking layer disposed under the first active layer to overlap the first gate electrode, wherein the first metal layer is made of the same material as the first source electrode and the first drain electrode, and Wherein, the second metal layer is made of the same material as the light blocking layer.

13. The display device according to claim 10, wherein: The second metal layer is disposed in each of the first and second trenches and is adjacent to surfaces of the plurality of insulating layers and a surface of the first metal layer disposed in each of the first and second trenches and adjacent to a surface of the second metal layer.

14. The display device according to claim 13, wherein: The first metal layer is arranged on the same layer as the second source electrode and the second drain electrode and is made of the same material as the second source electrode and the second drain electrode, and the second metal layer is arranged on the same layer as the first source electrode and the first drain electrode and is made of the same material as the first source electrode and the first drain electrode.

15. The display device according to claim 1, further comprising: Optical electronics are disposed to overlap the optical region.

16. The display device according to claim 15, wherein: The through hole is formed to correspond to the optical electronic device.

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