Gamma voltage generation circuit and display device including same

Abstract

The invention relates to a gamma voltage generation circuit and a display device including the same. The gamma voltage generating circuit includes: a plurality of tap nodes; a plurality of resistor strings, the plurality of resistor strings being connected between two of the plurality of tap nodes; and a plurality of gamma buffers configured to generate a plurality of tap gamma voltages to be output to the plurality of tap nodes based on voltage division results of the plurality of resistor strings, each of the plurality of resistor strings includes a first connection portion coupled to a tapped gamma output of a first gray level and a second connection portion coupled to a tapped gamma output of a second gray level lower than the first gray level, and the second connection portions of the plurality of resistor strings are distributed and connected to output terminals of two or more gamma buffers.

Description

Technical Field

[0001] The present disclosure relates to a gamma voltage generation circuit and a display device including the gamma voltage generation circuit. Background Art

[0002] A display device supplies a data voltage to pixels (e.g., pixels having the same or different sizes) for each gray level to display an input image. The data voltage is output from a digital-to-analog converter based on a gamma compensation voltage generated by a gamma voltage generation circuit.

[0003] In a display device having a high resolution and a high frequency, since the time margin of gamma output is small, the time for the gamma output to stabilize to a target voltage is preferably short. For this purpose, it is preferable to reduce the time during which the gamma output is unstable in a transient state, that is, the output response time of the gamma voltage generation circuit is preferably short.

[0004] The descriptions provided in the background art section should not be considered as prior art merely because they are mentioned in or related to the background art section. The background art section may include information describing one or more aspects of the subject technology. Summary of the Invention

[0005] A method of reducing the level of an internal load resistor of the gamma voltage generation circuit may be considered to improve the output response time of the gamma voltage generation circuit, but there may be a problem that a specific gamma buffer is abnormally driven due to overcurrent. For this reason, since it is difficult to reduce the load resistor level, it is necessary to use a large-capacity gamma buffer having good driving ability. However, a gamma buffer having a large size causes an increase in the circuit size of the gamma voltage generation circuit.

[0006] To overcome the problems of the above prior art, the present disclosure may provide a gamma voltage generation circuit and a display device including the gamma voltage generation circuit, which can achieve a fast response time without a problem of abnormal operation caused by overcurrent even without increasing the size of the gamma buffer.

[0007] To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a gamma voltage generation circuit includes: a plurality of tap nodes; a plurality of resistor strings connected between two of the plurality of tap nodes; and a plurality of gamma buffers configured to generate a plurality of tap gamma voltages based on the voltage division results of the plurality of resistor strings for output to the plurality of tap nodes, wherein each of the plurality of resistor strings includes a first connection portion coupled to the tap gamma output of a first gray level and a second connection portion coupled to the tap gamma output of a second gray level lower than the first gray level, and the second connection portions of the plurality of resistor strings are distributed and connected to the output terminals of two or more gamma buffers.

[0008] It should be understood that the foregoing general description and the following detailed description are both exemplary and explanatory and are intended to provide further explanation of the claimed inventive concept. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. In the drawings:

[0010] Figure 1 is a diagram illustrating a display device according to the present embodiment;

[0011] Figure 2 is a diagram illustrating a data driving circuit of the display device according to the present embodiment;

[0012] Figure 3 shows Figure 2 the operation timing of the data driving circuit;

[0013] Figure 4 is a diagram illustrating a gamma voltage generation circuit according to a comparative example;

[0014] Figure 5 is a diagram illustrating the flow of internal current when the internal resistance load decreases in the gamma voltage generation circuit according to the comparative example;

[0015] Figure 6 and Figure 7 is a diagram showing the gamma voltage determination order and the output stabilization time based on the gamma voltage determination order in the gamma voltage generation circuit according to the comparative example;

[0016] Figure 8 and Figure 9 is a diagram illustrating a gamma voltage generation circuit according to a first exemplary embodiment;

[0017] Figure 10 is a diagram illustrating the flow of an internal current when an internal resistance load decreases in a gamma voltage generation circuit according to a first exemplary embodiment;

[0018] Figure 11 and Figure 12 is a diagram showing the gamma voltage determination order and the output stabilization time based on the gamma voltage determination order in a gamma voltage generation circuit according to a first exemplary embodiment;

[0019] Figure 13 is a diagram illustrating an example in which the output stabilization time is reduced more in a first exemplary embodiment than in a comparative example;

[0020] Figure 14 is a diagram illustrating a gamma voltage generation circuit according to a second exemplary embodiment;

[0021] Figure 15 is a diagram illustrating a gamma voltage generation circuit according to a third exemplary embodiment; and

[0022] Figure 16 is a diagram illustrating a gamma voltage generation circuit according to a fourth exemplary embodiment.

[0023] Throughout the drawings and the detailed description, unless otherwise specified, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative dimensions and descriptions of these elements may be exaggerated. Detailed Description

[0024] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification, when adding reference numerals to the elements in each drawing, it should be noted that the same reference numerals that have been used to denote the same elements in other drawings are used for the elements wherever possible. In the following description, when the detailed description of related known functions or configurations is determined to unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as known in the art, except for the steps and / or operations that must occur in a specific order. The names of the respective elements used in the following description may be selected merely for convenience in writing the specification and may therefore be different from the names used in actual products.

[0025] The advantages, features, and methods of implementation of the present disclosure will be clarified by the embodiments described with reference to the following accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the scope of protection of the present disclosure is defined by the claims and their equivalents.

[0026] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, and quantities of the elements used to describe the embodiments of the present disclosure in the accompanying drawings are merely examples, and thus, the present disclosure is not limited to the details shown. Any implementation described herein as an "example" is not necessarily to be construed as superior or better than other implementations.

[0027] When the terms "comprising", "having", and "including" described in the present disclosure can be used, another part can be added unless a more restrictive term such as "only" is used. Unless otherwise mentioned, terms in the singular form can include the plural form.

[0028] The term "exemplary" is used to mean serving as an example or illustration. An aspect is an exemplary aspect. "Embodiment", "example", "aspect", etc. should not be construed as superior or better than other implementations. Embodiments, examples, example embodiments, aspects, etc. can refer to one or more embodiments, one or more examples, one or more example embodiments, one or more aspects, etc., unless otherwise stated. In addition, the term "may" encompasses all meanings of the term "can".

[0029] In the description of the various embodiments of the present disclosure, when describing the positional relationship, for example, when the positional relationship between two parts is described as, for example, "on", "above", "below", and "next to", etc., one or more other parts can be located between the two parts unless a more restrictive term such as "right" or "directly" is used. For example, when an element or layer is disposed "on" another element or layer, a third layer or element can be interposed therebetween.

[0030] Spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used to describe the correlation between various elements (e.g., layers, films, regions, components, parts, etc.) shown in the figures. The spatial relative terms should be understood to include terms for different orientations of the elements in use or operation in addition to the orientation depicted in the figures. For example, if the elements shown in the figures are flipped, an element described as "below" or "beneath" other elements will be oriented "above" the other elements. Thus, the term "below", as an example term, may include all directions of "above" and "below". Similarly, the exemplary terms "above" or "upper" may include both directions of "above" and "below".

[0031] The term "at least one / one" should be understood to include any and all combinations of one or more of the related listed items. For example, the meaning of "at least one / one of the first item, the second item, and the third item" encompasses combinations of all three listed elements, combinations of any two of the three elements, and each individual element - the first element, the second element, and the third element.

[0032] The features of the various embodiments of the present disclosure may be interconnected or combined partially or wholly, and may interoperate with each other and be technically driven in various ways as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be executed independently of each other, or may be executed together in a mutually dependent relationship.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this specification. For example, the term "part" or "unit" may apply to, for example, a separate circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described function, as should be understood by one of ordinary skill in the art.

[0034] Figure 1 is a diagram illustrating the display device 10 according to this exemplary embodiment.

[0035] Refer to Figure 1, the display device 10 may include: a display panel 100 including a plurality of pixels P; a controller 200; a gate driving circuit 300 that supplies a gate signal to each of the plurality of pixels P; a data driving circuit 400 that supplies a data signal (or data voltage) to each of the plurality of pixels P; and a power supply circuit 500 that supplies power required for driving. The gate driving circuit 300 and the data driving circuit 400 may be included in the display panel driving circuit. The embodiments are not limited thereto. As an example, one or more additional components may also be included.

[0036] The display panel 100 may include a display area provided with pixels P and a non-display area extending from the display area. As an example, the non-display area may partially or completely surround the display area. As an example, the gate driving circuit 300 and / or the data driving circuit 400 may be provided in the non-display area or connected to the non-display area.

[0037] In the display panel 100, a plurality of gate lines GL and a plurality of data lines DL may cross each other, and each of the plurality of pixels P may be connected to the gate line GL and the data line DL. Specifically, one pixel P may be supplied with a gate signal from the gate driving circuit 300 through the gate line GL, may be supplied with a data signal from the data driving circuit 400 through the data line DL, and may be supplied with a high-level driving voltage EVDD and a low-level driving voltage EVSS from the power supply circuit 500. The embodiments are not limited thereto. As an example, one or more additional signal lines may also be included.

[0038] The gate line GL may transmit a scan signal SC and a light emission control signal EM to the plurality of pixels P, and the data line DL may transmit a data voltage Vdata to the plurality of pixels P. According to various exemplary embodiments, the gate line GL may include a plurality of scan lines SCL for supplying the scan signal SC and a plurality of light emission control signal lines EML for supplying the light emission control signal EM. The plurality of pixels P may be supplied with the high-level driving voltage EVDD through a first power line VL1 and may be supplied with the low-level driving voltage EVSS through a second power line VL2.

[0039] Each pixel P may include a light emitting device and a pixel circuit that controls the driving of the light emitting device. The light emitting device may include an anode electrode, a cathode electrode, and a light emitting layer located between the anode electrode and the cathode electrode.

[0040] The pixel circuit may include a plurality of switching elements, driving elements, and capacitors. The switching elements and the driving elements may both be configured as thin film transistors (TFTs). The driving elements may control the amount of current supplied to the light emitting device based on the data voltage Vdata to adjust the light emission amount of the light emitting device. The plurality of switching elements may be turned on or off based on the scan signal SC supplied through a plurality of scan lines SCL and the light emission control signal EML supplied through the light emission control signal line EML.

[0041] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device, where an image is displayed on the screen and the real content of the background is visible. The display panel 100 may be implemented as a flexible display panel or a non-flexible display panel. The flexible display panel may be implemented as an organic light emitting diode (OLED) panel including a plastic substrate, but is not limited thereto.

[0042] Each pixel P may be divided into a red pixel, a green pixel, and a blue pixel to implement colors. Each pixel P may also include a white pixel. The embodiments are not limited thereto. As an example, pixels having other colors such as cyan, magenta, yellow, etc. may be alternatively or additionally included.

[0043] As an example, a touch sensor may be disposed on the display panel 100. Touch input may be sensed by using a separate touch sensor, or may be sensed by the pixel P. The touch sensor may be arranged on the screen of the display panel 100 as an on-cell type or an add-on type, or may be implemented as an in-cell type touch sensor embedded in the display panel 100. As an example, the touch sensor may be omitted according to the design.

[0044] The controller 200 may process the image data RGB input from a host system (not shown) based on, for example, the size and resolution of the display panel 100 to supply the processed image data RGB to the data driving circuit 400. The controller 200 may generate a gate control signal GCS and a data control signal DCS by using, for example, a synchronization signal (e.g., a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync, etc.) input from the host system. The controller 200 may supply the gate control signal GCS to the gate driving circuit 300 to control the operation timing of the gate driving circuit 300. The controller 200 may supply the data control signal DCS to the data driving circuit 400 to control the operation timing of the data driving circuit 400. The controller 200 may synchronize the operation timing of the gate driving circuit 300 with the operation timing of the data driving circuit 400 by using the gate control signal GCS and the data control signal DCS.

[0045] The host system is one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, a household appliance, a laptop computer, a building and an automotive display system, etc.

[0046] The controller 200 may be equipped with various processors (e.g., a microprocessor, a mobile processor, an application processor, etc. and combinations thereof) based on the device on which the controller is installed.

[0047] As an example, the controller 200 may drive the pixel P at various refresh rates. The controller 200 may drive the pixel P in a variable refresh rate (VRR) mode. As an example, the controller 200 may variably drive the pixel P at a refresh rate between a first refresh rate and a second refresh rate. The embodiments are not limited thereto. As an example, the controller 200 may variably drive the pixel P at one of three or more refresh rates. As an example, the controller 200 may drive the pixel P at a single refresh rate. The controller 200 may simply change the speed of a clock signal, or may generate a synchronization signal to cause horizontal blanking or vertical blanking to occur, or may drive the gate driving circuit 300 in a mask type to drive the pixel P at various refresh rates, but is not limited thereto.

[0048] The logic voltage level of the gate control signal GCS output from the controller 200 may be level-converted into a gate low voltage VGL and a gate high voltage VGH by using a level converter (not shown), and then may be supplied to the gate driving circuit 300. As an example, the level converter may convert the low logic level voltage of the gate control signal GCS into a gate low voltage VGL level, and may convert the high logic level voltage of the gate control signal GCS into a gate high voltage VGH level. The gate control signal GCS may include a start pulse and a shift clock, but is not limited thereto.

[0049] The gate driving circuit 300 may supply a gate signal to the gate lines GL based on the gate control signal GCS supplied from the controller 200. As an example, the gate driving circuit 300 may be disposed on one or both sides of the display panel 100 in a gate-in-panel (GIP) type, but is not limited thereto. As an example, the gate driving circuit 300 may be separately provided (e.g., on a separate panel), and then connected to the display panel 100 by a tape automated bonding (TAB) method, a chip-on-glass (COG) method, a chip-on-board (COP) method, or a chip-on-film (COF) method, but is not limited thereto.

[0050] The gate driving circuit 300 may output gate signals to a plurality of gate lines GL based on the control of the controller 200 (e.g., sequentially). The gate driving circuit 300 may shift the gate signals by using a shift register to sequentially supply corresponding signals to the gate lines GL.

[0051] In the organic light emitting display device, the gate signals may include a scan signal SC and an emission control signal EM. The scan signal SC may include a scan pulse that swings between a gate low voltage VGL and a gate high voltage VGH. The emission control signal EM may include an emission control signal pulse that swings between the gate low voltage VGL and the gate high voltage VGH. The scan signal SC may select pixels P of a row to which a data voltage Vdata is to be written. The emission control signal EM may define the emission time of each pixel P.

[0052] The gate driving circuit 300 may include an emission control signal driving circuit 310 and one or more scan driving circuits 320.

[0053] The emission control signal driving circuit 310 may output an emission control signal pulse in response to a start pulse and a shift clock from the controller 200, and may sequentially shift the emission control signal pulse based on the shift clock.

[0054] One or more scan driving circuits 320 may output a scan pulse in response to a start pulse and a shift clock from the controller 200, and may shift the scan pulse based on the shift clock.

[0055] The data driving circuit 400 may convert image data RGB into a data voltage Vdata based on a data control signal DCS supplied from the controller 200, and may supply the data voltage Vdata to the pixels P through data lines DL. The data driving circuit 400 may include a gamma voltage generation circuit. As an example, the data driving circuit 400 may include a gamma voltage generation circuit that is supplied with a first reference voltage VREF1 and a second reference voltage VREF2 to output a gamma compensation voltage.

[0056] In Figure 1 , it is illustrated that the data driving circuit 400 is provided on one side of the display panel 100, but the number and arrangement position of the data driving circuit 400 are not limited thereto. As an example, the data driving circuit 400 may be configured as a plurality of integrated circuits (ICs), and may be provided on one side or more sides of the display panel 100.

[0057] The power supply circuit 500 can generate direct current (DC) power required to drive the display panel driving circuit and the pixel array of the display panel 100, for example, by using a DC-DC converter. As an example, the DC-DC converter may include, but is not limited to, a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply circuit 500 can receive a DC input voltage applied from a host system (not shown) to generate DC voltages such as a gate low voltage VGL, a gate high voltage VGH, a high-level driving voltage EVDD, a low-level driving voltage EVSS, and a first reference voltage VREF1 and a second reference voltage VREF2. The gate low voltage VGL and the gate high voltage VGH can be supplied to a level converter (not shown) and the gate driving circuit 300. The high-level driving voltage EVDD and the low-level driving voltage EVSS can be jointly supplied to the pixel P. The first reference voltage VREF1 and the second reference voltage VREF2 can be supplied to the data driving circuit 400.

[0058] Figure 2 FIG. is an illustration of a data driving circuit of a display device according to the present embodiment. Figure 3 FIG. shows Figure 2 the operation timing of the data driving circuit.

[0059] Referring to Figure 2 , the data driving circuit 400 of the display device 10 may include a plurality of source ICs SICs. Each source IC SIC may include a shift register unit 402, a latch unit 404, an R / G / B switching unit 406, a gamma voltage generation circuit 408, a digital-to-analog converter (DAC) 410, and an output buffer unit (OBUF) 412.

[0060] The shift register unit 402 can convert digital image data RGB received from the controller ( Figure 1 200) into parallel data to supply the parallel data to the latch unit 404. The shift register unit 402 can shift the source start pulse SSP according to the source sampling clock SSC to generate a sampling clock (e.g., sequentially).

[0061] The latch unit 404 can sample the digital image data RGB for the sampling clocks sequentially input from the shift register unit 402 and can output the latched data items. As an example, the latch unit 404 can output the latched data items simultaneously with the latch units of other source ICs in response to the source output enable signal SOE, but is not limited thereto. As an example, the latch unit 404 can output the latched data items simultaneously with the latch units of other source ICs in response to the low logic voltage of the source output enable signal SOE or the high logic voltage of the source output enable signal SOE, but is not limited thereto. As an example, the latch unit 404 can output the latched data items independently of the latch units of other source ICs.

[0062] The R / G / B switching unit 406 can perform switching of the image data RGB sampled and latched by the latch unit 404 for each R / G / B to divide the data.

[0063] The DAC 410 can be supplied with the gamma compensation voltage VGAM[255:0] from the gamma voltage generation circuit 408, and can map the image data RGB input from the R / G / B switching unit 406 to the gamma compensation voltage VGAM[255:0] to generate the buffer input voltage Vin, and then can output the buffer input voltage Vin to the output buffer unit (OBUF) 412. As an example, the buffer input voltage Vin can be substantially the same as the analog data voltage Vdata. When 8-bit digital image data RGB is supplied, the digital image data RGB can be represented as 256 data items having gray levels G0 to G255 from 0 to 255. In this case, as an example, the DAC 410 can receive the gamma compensation voltages VGAM[0] to VGAM

[255] from 0 to 255 from the gamma voltage generation circuit 408, and can output one gamma compensation voltage VGAM corresponding to the data value of the digital image data RGB among the gamma compensation voltages VGAM[0] to VGAM

[255] as the buffer input voltage Vin.

[0064] The output buffer unit (OBUF) 412 outputs the result Vout obtained by buffering the buffer input voltage Vin via the output buffer as the data voltage Vdata to the data line. As an example, the output buffer unit (OBUF) 412 can output the result Vout to the data line in response to the low logic voltage or the high logic voltage of the source output enable signal SOE, but is not limited thereto.

[0065] The gamma voltage generation circuit 408 can output gamma compensation voltages VGAM[0] to VGAM

[255] corresponding to R, G, and B from 0 to 255 (e.g., in sequence). Whenever R, G, and B change, the gamma voltage generation circuit 408 may require time to stabilize the output voltage to the target level. Even without increasing the size of the gamma buffer, the gamma voltage generation circuit 408 can be implemented as Figures 8 to 16 to reduce the output stabilization time, that is, to achieve a short response time, without the limitation of abnormal operation due to overcurrent.

[0066] Figure 4 is a diagram illustrating a gamma voltage generation circuit according to a comparative example. Figure 5 is a diagram illustrating the flow of internal current when the internal resistor load decreases in the gamma voltage generation circuit according to the comparative example. Figure 6 and Figure 7 are diagrams showing the gamma voltage determination order and the output stabilization time based on the gamma voltage determination order in the gamma voltage generation circuit according to the comparative example.

[0067] The gamma compensation voltages VGAM[0] to VGAM

[255] from 0 to 255 output from the gamma voltage generation circuit can change over time based on the output order of R, G, and B. As Figure 4 shown, the gamma voltage generation circuit can generate gamma compensation voltages VGAM[0] to VGAM

[255] from 0 to 255 determined based on a first input voltage VIN255 and a second input voltage VIN0. Each of the first input voltage VIN255 and the second input voltage VIN0 can be one of the voltage division results of a main resistor string Main-RString connected to a first reference voltage VREF1 and a second reference voltage VREF2, but is not limited thereto. As an example, the first input voltage VIN255 and the second input voltage VIN0 can be adjustable based on the adjustment of the main resistor string Main-RString.

[0068] The gamma voltage generation circuit can include a plurality of tap nodes TAB, a plurality of resistor strings RString connected between two tap nodes TAB, a multiplexer MUX that selectively outputs the voltage division result of the resistor string, and a gamma buffer GAM BUF that buffers the multiplexer output to apply the multiplexer output to the tap node TAB.

[0069] Some of the gamma compensation voltages VGAM[0] to VGAM

[255] from 0 to 255 can be multiple tapped gamma voltages VGAM[0], [5],

[10] , …,

[190] , and

[255] output through tap nodes. The number of the tapped gamma voltages VGAM[0], [5],

[10] , …,

[190] , and

[255] can be 10, but is not limited thereto. As an example, the number of the tapped gamma voltages can be less than 10 or greater than 10. The tapped gamma voltages can be referred to as gamma reference voltages. In addition, other gamma compensation voltages except the tapped gamma voltages can be voltages obtained by dividing the voltage by tap resistors RTAB connected between adjacent tap nodes TAB.

[0070] The first input voltage VIN255 can be buffered by the top gamma buffer GAM BUF, and then can be applied to the top tap node TAB, and thus can be the tapped gamma voltage VGAM

[255] with the highest gray level. The second input voltage VIN0 can be buffered by the bottom gamma buffer GAM BUF, then can be applied to the bottom tap node TAB, and thus can be the tapped gamma voltage VGAM[0] with the lowest gray level.

[0071] When the levels of the first input voltage VIN255 and the second input voltage VIN0 are shifted, the levels of the gamma compensation voltages VGAM[0] to VGAM

[255] from 0 to 255 can be shifted.

[0072] In a display device with high resolution and high frequency, since the time margin for gamma output is small, the time for the gamma output to stabilize to the target voltage is preferably short. For this purpose, the output response time of the gamma voltage generation circuit is preferably short.

[0073] A method of reducing the internal load resistance level of the gamma voltage generation circuit can be considered to improve the output response time of the gamma voltage generation circuit. Figure 5 Illustrates the flow of the internal current of the gamma voltage generation circuit when the internal resistance load of the resistor string is reduced. When the load resistance level of the resistor string is reduced, the levels of the currents I1, I2, ……, and I9 flowing in the resistor string can increase, and the increased currents I1, I2, ……, and I9 may concentrate at the output terminal of the bottom gamma buffer GAM BUF. Therefore, when the sum of the concentrated currents is greater than the available level defined in the gamma buffer, the bottom gamma buffer GAM BUF may operate abnormally.

[0074] Because in a device with Figure 4There are limitations in reducing the load resistance level of the gamma string in the gamma voltage generation circuit of the shown structure, so the gamma output stabilization time may increase. For example, in the gamma voltage generation circuit according to the comparative example, the tapped gamma voltage can be charged in the tapped nodes in the order of ①_②_③_…_⑧_⑨ in Figure 6 and the tapped gamma voltage can be stabilized in the same order when the R_G_B output changes. As a result, since the charging order of the tapped gamma voltage in the gamma voltage generation circuit according to the comparative example is sequentially determined in this order from the voltage at the upper end to the voltage at the lower end, there may be a limitation that the output stabilization time Y of the gamma voltage generation circuit increases as shown in Figure 7 .

[0075] To reduce the output stabilization time of the gamma voltage generation circuit, it may be necessary to use a large-capacity gamma buffer with good driving ability. However, there may be limitations in increasing the circuit size of the gamma voltage generation circuit.

[0076] Figure 8 And Figure 9 are diagrams illustrating the gamma voltage generation circuit 408-1 according to the first exemplary embodiment. Figure 10 is a diagram illustrating the flow of the internal current when the internal resistance load decreases in the gamma voltage generation circuit 408-1 according to the first exemplary embodiment. Figure 11 And Figure 12 are diagrams showing the gamma voltage determination order and the output stabilization time based on the gamma voltage determination order in the gamma voltage generation circuit 408-1 according to the first exemplary embodiment. Figure 13 is a diagram showing an example in which the output stabilization time is reduced more in the first exemplary embodiment compared to the comparative example.

[0077] Referring to Figure 8 and Figure 9 , compared with the above comparative example, the gamma voltage generation circuit 408-1 according to the first exemplary embodiment may have a main difference in the connection structure between the plurality of resistor strings R Sring 1 to 8.

[0078] Each of the plurality of resistor strings R String 1 to 8 may include a first connection portion connected to the tapped gamma output of the first gray level and a second connection portion connected to the tapped gamma output of a second gray level lower than the first gray level, and the second connection portions of the plurality of resistor strings R String 1 to 8 may be distributed and connected to the output terminals of two or more gamma buffers (e.g., three or more gamma buffers, four or more gamma buffers, etc.). As an example, the second connection portions of two or more of the plurality of resistor strings R String 1 to 8 may be connected to the output terminal of one gamma buffer. As an example, the second connection portions of the plurality of resistor strings R String 1 to 8 may be distributed and connected to the output terminals of different gamma buffers. As an example, the first connection portions of the plurality of resistor strings R String 1 to 8 may be distributed and connected to the output terminals of two or more gamma buffers, but not limited thereto. As an example, the first connection portions of two or more of the plurality of resistor strings R String 1 to 8 may be connected to the output terminal of one gamma buffer. As an example, the first connection portions of the plurality of resistor strings R String 1 to 8 may be distributed and connected to the output terminals of different gamma buffers, but not limited thereto.

[0079] Based on the connection configuration of the resistor strings R String 1 to 8, the currents I1 to I8 flowing in the resistor strings R String 1 to 8 may not be concentrated at the output terminal of one gamma buffer and may be distributed to the output terminals of two or more gamma buffers, as Figure 10 shown.

[0080] Therefore, even when the levels of the currents I1 to I8 flowing in the resistor strings R String 1 to 8 increase due to a decrease in the load resistance level of the resistor strings R String 1 to 8, the increased currents I1 to I8 may not be concentrated only at the output terminal of the bottom gamma buffer GB0 but may be distributed to the output terminals of other gamma buffers, thereby reducing or preventing abnormal operation of the gamma buffers caused by overcurrent.

[0081] The gamma voltage generation circuit 408-1 according to the first exemplary embodiment can reduce the load resistance level of the resistor strings RString1 to 8 without being restricted by abnormal operations due to overcurrent, and thus it may not be necessary to use a large-capacity gamma buffer that increases the circuit size. On the other hand, since the load resistance level of the resistor strings R String 1 to 8 is reduced, the size of the gamma buffer can be reduced. As a result, the gamma voltage generation circuit 408-1 according to the first exemplary embodiment can achieve a short response time in small-sized products that require high resolution and high frequency, such as augmented reality (AR) or virtual reality (VR), and can effectively improve the performance of the display device. The embodiment is not limited thereto. As an example, the gamma voltage generation circuit 408-1 according to the first exemplary embodiment can also achieve a short response time in large-sized products such as TVs, personal computers, and signage.

[0082] Reference Figure 8 and Figure 9 , the gamma voltage generation circuit 408-1 according to the first exemplary embodiment may include a plurality of tap nodes TAB0, TAB5, TAB10, TAB21, TAB40, TAB65, TAB99, TAB144, TAB190, and TAB255, a plurality of resistor strings R String 1 to 8 connected between two tap nodes, and a plurality of gamma buffers GB0, GB5, GB10, GB21, GB40, GB65, GB99, GB144, GB190, and GB255 that generate a plurality of tap gamma voltages VGAM[0], VGAM[5], VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] , VGAM

[144] , VGAM

[190] , and VGAM

[255] based on the voltage division results of the plurality of resistor strings R String 1 to 8 and output them to the plurality of tap nodes respectively. The embodiment is not limited thereto. As an example, the number of tap nodes, resistor strings, and tap gamma voltages can be changed in various ways. As an example, the number of resistor strings can be 2 less than the number of tap nodes, but it is not limited thereto.

[0083] Some of the gamma compensation voltages VGAM[0] to VGAM

[255] from 0 to 255 can be multiple tapped gamma voltages VGAM[0], VGAM[5], VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] , VGAM

[144] , VGAM

[190] , and VGAM

[255] output via tap nodes. The number of the tapped gamma voltages VGAM[0], VGAM[5], VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] , VGAM

[144] , VGAM

[190] , and VGAM

[255] can be 10, or less than 10 or greater than 10, but not limited thereto. The tapped gamma voltages can be referred to as gamma reference voltages. In addition, other gamma compensation voltages other than the tapped gamma voltages can be voltages obtained by dividing the voltage by tap resistors RTAB connected between adjacent tap nodes TAB.

[0084] The first input voltage VIN255 can be buffered by the top gamma buffer GB255 and then can be applied to the top tap node TAB255, and thus can be the tapped gamma voltage VGAM

[255] with the highest gray level. The second input voltage VIN0 can be buffered by the bottom gamma buffer GB0 and then can be applied to the bottom tap node TAB0, and thus can be the tapped gamma voltage VGAM[0] with the lowest gray level.

[0085] When the levels of the first input voltage VIN255 and the second input voltage VIN0 are shifted, the levels of the gamma compensation voltages VGAM[0] to VGAM

[255] from 0 to 255 can be shifted, but not limited thereto.

[0086] The first resistor string R String 1 can include a first connection part connected to the tapped gamma output VGAM

[255] of the 255 gray level and a second connection part connected to the tapped gamma output VGAM[0] of the 0 gray level. One of the voltage division results of the first resistor string R String 1 can be the tapped gamma output VGAM

[190] of the 190 gray level, and can be charged in the tap node TAB190 through the multiplexer MUX and the gamma buffer GB190.

[0087] The second resistor string R String 2 may include a first connection portion connected to the tapped gamma output VGAM

[190] of the 190 gray level and a second connection portion connected to the tapped gamma output VGAM[0] of the 0 gray level. One of the voltage division results of the second resistor string R String 2 may be the tapped gamma output VGAM[5] of the 5 gray level, and may be charged at the tap node TAB5 through the multiplexer MUX and the gamma buffer GB5.

[0088] The third resistor string R String 3 may include a first connection portion connected to the tapped gamma output VGAM

[190] of the 190 gray level and a second connection portion connected to the tapped gamma output VGAM[5] of the 5 gray level. One of the voltage division results of the third resistor string R String 3 may be the tapped gamma output VGAM

[144] of the 144 gray level, and may be charged at the tap node TAB144 through the multiplexer MUX and the gamma buffer GB144.

[0089] The fourth resistor string R String 4 may include a first connection portion connected to the tapped gamma output VGAM

[144] of the 144 gray level and a second connection portion connected to the tapped gamma output VGAM[5] of the 5 gray level. One of the voltage division results of the fourth resistor string R String 4 may be the tapped gamma output VGAM

[10] of the 10 gray level, and may be charged at the tap node TAB10 through the multiplexer MUX and the gamma buffer GB10.

[0090] The fifth resistor string R String 5 may include a first connection portion connected to the tapped gamma output VGAM

[144] of the 144 gray level and a second connection portion connected to the tapped gamma output VGAM

[10] of the 10 gray level. One of the voltage division results of the fifth resistor string R String 5 may be the tapped gamma output VGAM

[99] of the 99 gray level, and may be charged at the tap node TAB99 through the multiplexer MUX and the gamma buffer GB99.

[0091] The sixth resistor string R String 6 may include a first connection portion connected to the tapped gamma output VGAM

[99] of the 99 gray level and a second connection portion connected to the tapped gamma output VGAM

[10] of the 10 gray level. One of the voltage division results of the sixth resistor string R String 6 may be the tapped gamma output VGAM

[21] of the 21 gray level, and may be charged at the tap node TAB21 through the multiplexer MUX and the gamma buffer GB21.

[0092] The seventh resistor string R String 7 may include a first connection portion connected to the tapped gamma output VGAM

[99] of 99 gray levels and a second connection portion connected to the tapped gamma output VGAM

[21] of 21 gray levels. One of the voltage division results of the seventh resistor string R String 7 may be the tapped gamma output VGAM

[65] of 65 gray levels, and may be charged in the tap node TAB65 through the multiplexer MUX and the gamma buffer GB65.

[0093] The eighth resistor string R String 8 may include a first connection portion connected to the tapped gamma output VGAM

[65] of 65 gray levels and a second connection portion connected to the tapped gamma output VGAM

[21] of 21 gray levels. One of the voltage division results of the eighth resistor string R String 8 may be the tapped gamma output VGAM

[40] of 40 gray levels, and may be charged in the tap node TAB40 through the multiplexer MUX and the gamma buffer GB40.

[0094] The multiple tapped gamma voltages VGAM[0], VGAM[5], VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] , VGAM

[144] , VGAM

[190] and VGAM

[255] may include the tapped gamma voltage VGAM

[255] of the highest gray level, the tapped gamma voltage VGAM[0] of the lowest gray level, and the tapped gamma voltages VGAM[5], VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] , VGAM

[144] and VGAM

[190] of other gray levels between the highest gray level and the lowest gray level. In addition, the tapped gamma voltages VGAM[5], VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] , VGAM

[144] and VGAM

[190] of other gray levels may include the tapped gamma voltage VGAM

[190] of the second highest gray level, the tapped gamma voltage VGAM[5] of the second lowest gray level, and the tapped gamma voltages VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] and VGAM

[144] of the intermediate gray levels between the second highest gray level and the second lowest gray level.

[0095] In this case, according to the charging order of the multiple tapped gamma voltages on the multiple tap nodes, as Figure 11As shown, the tap gamma voltage VGAM

[255] of the highest gray level and the tap gamma voltage VGAM[0] of the lowest gray level can be the first in sequence, and at least one tap gamma voltage VGAM (e.g., VGAM

[40] ) among the tap gamma voltages VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] , and VGAM

[144] of the intermediate gray levels can be the last in sequence.

[0096] Based on such a connection configuration, the number of resistor strings R String 1 to 8 can be equal to the number of tap gamma voltages VGAM[5], VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] , VGAM

[144] , and VGAM

[190] of other gray levels. In addition, the input ends of each of the other gamma buffers GB5, GB10, GB21, GB40, GB65, GB99, GB144, and GB190 that generate the tap gamma voltages VGAM[5], VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] , VGAM

[144] , and VGAM

[190] of other gray levels can be connected to a corresponding resistor string through a multiplexer MUX. The implementation is not limited to this. As an example, as long as the second connection portions of the plurality of resistor strings R String 1 to 8 can be distributed and connected to the output ends of two or more gamma buffers, the connection configuration can vary in various ways.

[0097] The currents I1 to I8 flowing in the plurality of resistor strings R String 1 to 8 may not be concentrated at the output end of one gamma buffer, but may be distributed to the output ends of two or more gamma buffers, as Figure 10As shown. For example, when it is assumed that currents I1 to I8 flow in a plurality of resistor strings R String 1 to 8, "I1 + I2" may flow at the output terminal of gamma buffer GB0, "I3 + I4" may flow at the output terminal of gamma buffer GB5, "I5 + I6" may flow at the output terminal of gamma buffer GB10, and "I7 + I8" may flow at the output terminal of gamma buffer GB21. Although the figure shows that the second connection portions of every two resistor strings (e.g., adjacent or non-adjacent to each other) among the plurality of resistor strings R String 1 to 8 are connected to the output terminal of one gamma buffer, the embodiment is not limited thereto. As an example, the output terminal of each of the plurality of gamma buffers may be connected to different numbers of second connection portions of the plurality of resistor strings R String 1 to 8. As an example, the output terminal of one of the plurality of gamma buffers may be connected to one second connection portion of the plurality of resistor strings R String 1 to 8, or three or more second connection portions of the plurality of resistor strings R String 1 to 8, but is not limited thereto.

[0098] As described above, even when the levels of the currents I1 to I8 flowing in the resistor strings R String 1 to 8 increase due to a decrease in the load resistance level of the resistor strings R String 1 to 8, the increased currents I1 to I8 may not be concentrated only at the output terminal of the bottommost gamma buffer GB0, but may be distributed to the output terminals of other gamma buffers. Therefore, abnormal operation of the gamma buffer caused by overcurrent can be reduced or prevented. For example, in the gamma voltage generation circuit according to the first exemplary embodiment, the tapped gamma voltage may be charged at the tap nodes in the order of ①_②_③_…_⑧_⑨ in Figure 11 and Figure 12 . Since the charging order of the tapped gamma voltage is determined in a zigzag form as the voltage at the upper end is alternately provided to the voltage at the lower end, the output stabilization time X of the gamma voltage generation circuit can be reduced.

[0099] Referring to Figure 13 , it can be seen that the output stabilization time X according to the first exemplary embodiment is reduced by about 30% compared to the output stabilization time Y of the comparative example.

[0100] Figure 14 FIG. is an illustration of a gamma voltage generation circuit 408-2 according to a second exemplary embodiment.

[0101] Referring to Figure 14, the gamma voltage generation circuit 408-2 according to the second exemplary embodiment can more easily reduce the circuit size than the gamma voltage generation circuit 408-1 according to the first exemplary embodiment. In the gamma voltage generation circuit 408-2 according to the second exemplary embodiment, two gamma buffers can be commonly connected to a resistor string to miniaturize the circuit.

[0102] In the gamma voltage generation circuit 408-2 according to the second exemplary embodiment, the number of resistor strings R String 1 to 4 can be less than the number of tap gamma voltages VGAM[5], VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] , VGAM

[144] , and VGAM

[190] of other gray levels. As an example, at least two of the gamma buffers can be commonly connected to one resistor string.

[0103] Among the other gamma buffers GB5, GB10, GB21, GB40, GB65, GB99, GB144, and GB190, the gamma buffers GB5 and GB190 can be commonly connected to the first resistor string R String 1, and the gamma buffers GB10 and GB144 can be commonly connected to the second resistor string R String 2 through the multiplexer MUX.

[0104] In addition, the gamma voltage generation circuit 408-2 according to the second exemplary embodiment can include all the basic elements of the gamma voltage generation circuit 408-1 according to the first exemplary embodiment, thereby achieving all the technical effects of the gamma voltage generation circuit 408-1 according to the first exemplary embodiment.

[0105] Figure 15 FIG. is a diagram showing a gamma voltage generation circuit 408-3 according to a third exemplary embodiment.

[0106] Referring to Figure 15 , the gamma voltage generation circuit 408-3 according to the third exemplary embodiment can more easily reduce the circuit size than the gamma voltage generation circuit 408-1 according to the first exemplary embodiment. In the gamma voltage generation circuit 408-3 according to the third exemplary embodiment, four gamma buffers can be commonly connected to a resistor string to miniaturize the circuit.

[0107] In the gamma voltage generation circuit 408-3 according to the third exemplary embodiment, the number of resistor strings R String 1 and 2 can be less than the number of tap gamma voltages VGAM[5], VGAM

[10] , VGAM

[21] , VGAM

[40] , VGAM

[65] , VGAM

[99] , VGAM

[144] , and VGAM

[190] for other gray levels.

[0108] Among the other gamma buffers GB5, GB10, GB21, GB40, GB65, GB99, GB144, and GB190, the gamma buffers GB5, GB21, GB98, and GB190 can be commonly connected to the first resistor string R String1, and the gamma buffers GB10, GB40, GB65, and GB144 can be commonly connected to the second resistor string R String 2 through the multiplexer MUX.

[0109] In addition, the gamma voltage generation circuit 408-3 according to the third exemplary embodiment can include all the basic elements of the gamma voltage generation circuit 408-1 according to the first exemplary embodiment, thereby achieving all the technical effects of the gamma voltage generation circuit 408-1 according to the first exemplary embodiment.

[0110] Figure 16 FIG. is a diagram showing a gamma voltage generation circuit 408-4 according to a fourth exemplary embodiment.

[0111] Referring to Figure 16 , compared with the gamma voltage generation circuit 408-1 according to the first exemplary embodiment, the gamma voltage generation circuit 408-4 according to the fourth exemplary embodiment can have a main difference in the connection configuration between the resistor strings R String. The gamma voltage generation circuit 408-4 according to the fourth exemplary embodiment can be implemented by modifying the connection arrangement structure of the gamma buffers based on the gray level periods / cycles that need to be adjusted in detail.

[0112] In addition, the gamma voltage generation circuit 408-4 according to the fourth exemplary embodiment can include all the basic elements of the gamma voltage generation circuit 408-1 according to the first exemplary embodiment, thereby achieving all the technical effects of the gamma voltage generation circuit 408-1 according to the first exemplary embodiment.

[0113] This embodiment can achieve the following effects:

[0114] Even without increasing the size of the gamma buffer, the gamma voltage generation circuit according to the present invention can achieve a short response time without being limited by abnormal operations due to overcurrent.

[0115] The effects according to the present disclosure are not limited to the above examples, and the specification may include various other effects.

[0116] Although the present disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0117] Cross - reference to related applications

[0118] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0189480, filed on December 22, 2023, the entire contents of which are incorporated herein by reference for all purposes as if fully set forth herein.

Claims

1. A gamma voltage generating circuit, the gamma voltage generating circuit comprising: Multiple tap nodes; a plurality of resistor strings, each of the plurality of resistor strings being connected between two tap nodes among the plurality of tap nodes; as well as a plurality of gamma buffers configured to respectively generate a plurality of tap gamma voltages based on the results of voltage division by the plurality of resistor strings to respectively output the plurality of tap gamma voltages to the plurality of tap nodes, wherein each of the plurality of resistor strings comprises a first connection portion connected to a tapped gamma output of a first grayscale level and a second connection portion connected to a tapped gamma output of a second grayscale level lower than the first grayscale level, and The second connection portions of the plurality of resistor strings are distributed and connected to output terminals of two or more gamma buffers among the plurality of gamma buffers.

2. The gamma voltage generating circuit according to claim 1, wherein: Currents flowing in the plurality of resistor strings are not concentrated on an output terminal of one gamma buffer but are distributed to output terminals of the two or more gamma buffers.

3. The gamma voltage generating circuit according to claim 1, wherein: The plurality of tap gamma voltages include a tap gamma voltage of a highest grayscale level, a tap gamma voltage of a lowest grayscale level, and tap gamma voltages of other grayscale levels between the highest grayscale level and the lowest grayscale level, The tap gamma voltages of the other gray levels include a tap gamma voltage of a second high gray level, a tap gamma voltage of a second low gray level, and a tap gamma voltage of an intermediate gray level between the second high gray level and the second low gray level, and In a charging order of the plurality of tap gamma voltages on the plurality of tap nodes, the highest grayscale tap gamma voltage and the lowest grayscale tap gamma voltage are sequentially first, and at least one of the middle grayscale tap gamma voltages is sequentially last.

4. The gamma voltage generating circuit according to claim 3, wherein: The number of the resistor strings is equal to the number of the tapped gamma voltages of the other gray levels.

5. The gamma voltage generating circuit according to claim 4, wherein: An input terminal of each of the gamma buffers generating the tapped gamma voltages of the other gray levels is connected to one resistor string among the plurality of resistor strings through a multiplexer.

6. The gamma voltage generating circuit according to claim 5, wherein: The multiplexer selectively outputs the voltage division result of the one resistor string to output a corresponding one of the tapped gamma voltages of the other gray levels.

7. The gamma voltage generating circuit according to claim 3, wherein: The number of the resistor strings is smaller than the number of the tapped gamma voltages of the other gray levels.

8. The gamma voltage generating circuit according to claim 7, wherein: A plurality of gamma buffers among the gamma buffers generating the tapped gamma voltages of the other gray levels are commonly connected to one resistor string through corresponding multiplexers.

9. The gamma voltage generating circuit according to claim 1, further comprising a main resistor string connected to the first reference voltage and the second reference voltage, in, The plurality of tapped gamma voltages are determined based on a first input voltage and a second input voltage, each of which is one of voltage division results of the main resistor string.

10. The gamma voltage generating circuit according to claim 1, wherein: The other gamma compensation voltages except the plurality of tap gamma voltages are voltages obtained by voltage division by tap resistors connected between adjacent tap nodes of the plurality of tap nodes.

11. The gamma voltage generating circuit according to claim 1, wherein: The second connection portions of two or more resistor strings among the plurality of resistor strings are connected to an output terminal of one gamma buffer among the plurality of gamma buffers.

12. The gamma voltage generating circuit according to claim 1, wherein: The first connection portions of the plurality of resistor strings are distributed and connected to output terminals of two or more gamma buffers among the plurality of gamma buffers.

13. The gamma voltage generating circuit according to claim 1, wherein: The second connection portions of each two resistor strings among the plurality of resistor strings are commonly connected to an output terminal of one gamma buffer among the plurality of gamma buffers.

14. A display device, comprising: A display panel, the display panel comprising a plurality of pixels; The gamma voltage generating circuit according to any one of claims 1 to 13, the gamma voltage generating circuit being configured to output a gamma compensation voltage including the plurality of tapped gamma voltages; as well as A digital-to-analog converter is configured to map input image data to the gamma compensation voltage to output data voltages to be input to the plurality of pixels. 15 . The display device according to claim 14 , further comprising a power supply circuit configured to generate a first reference voltage and a second reference voltage to be supplied to the gamma voltage generating circuit.

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