Pixel and display device including same

Abstract

The invention relates to a pixel and a display device including the same. A display device according to one or more embodiments includes a first pixel in a display area, and the first pixel includes: a first pixel electrode; a first common electrode spaced apart from the first pixel electrode; a first light emitting element connected between the first pixel electrode and the first common electrode; and a second light emitting element connected in parallel with the first light emitting element between the first pixel electrode and the first common electrode, and having a threshold voltage lower than a threshold voltage of the first light emitting element.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0188387, filed with the Korean Intellectual Property Office on December 21, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to pixels and a display device including the pixels. Background art

[0004] With the development of an information - oriented society, there is an increasing demand for display devices for displaying images in various ways. Along with this trend, various types of display devices including light - emitting display devices are being developed.

[0005] A light - emitting display device may use a light - emitting element such as an organic light - emitting diode or a micro - light - emitting diode (hereinafter referred to as "micro - light - emitting element") as a light source of a pixel. In order to reduce the power consumption of the light - emitting display device, a high - efficiency light - emitting element may be used. However, by using a high - efficiency light - emitting element, it may be difficult to precisely control the brightness of low gray levels. Therefore, the image quality of the display device may deteriorate. Summary of the invention

[0006] Aspects of the present disclosure provide a pixel and a display device including the pixel that can improve image quality while reducing power consumption.

[0007] However, the aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to an aspect of the present disclosure, there is provided a display device including a first pixel in a display area, and the first pixel includes: a first pixel electrode; a first common electrode spaced apart from the first pixel electrode; a first light - emitting element connected between the first pixel electrode and the first common electrode; and a second light - emitting element connected in parallel with the first light - emitting element between the first pixel electrode and the first common electrode and having a threshold voltage lower than that of the first light - emitting element.

[0009] The size of the first light - emitting element may be different from the size of the second light - emitting element.

[0010] The size of the first light - emitting element may be larger than the size of the second light - emitting element.

[0011] The luminous efficiency of the first light - emitting element may be higher than that of the second light - emitting element.

[0012] The first pixel electrode and the first common electrode may not overlap with each other in the thickness direction of the first light-emitting element and the second light-emitting element, wherein a part of the first light-emitting element and a part of the second light-emitting element are above the first pixel electrode, and wherein another part of the first light-emitting element and another part of the second light-emitting element are above the first common electrode.

[0013] The first pixel electrode and the first common electrode may overlap with each other in the thickness direction of the first light-emitting element and the second light-emitting element, wherein the first light-emitting element and the second light-emitting element are above the first pixel electrode, and wherein the first common electrode is above the first light-emitting element and the second light-emitting element.

[0014] The first pixel electrode may include a first sub-pixel electrode and a second sub-pixel electrode that are separated from each other and electrically connected to each other.

[0015] The first light-emitting element and the second light-emitting element may be respectively above the first sub-pixel electrode and the second sub-pixel electrode.

[0016] The first common electrode may include a first sub-common electrode and a second sub-common electrode that are separated from each other and electrically connected to each other.

[0017] The first light-emitting element may include a first portion above the first sub-pixel electrode and a second portion extending from the first portion and above the first sub-common electrode, wherein the second light-emitting element includes a first portion above the second sub-pixel electrode and a second portion extending from the first portion of the second light-emitting element and above the second sub-common electrode.

[0018] The first light-emitting element and the second light-emitting element may include: a first contact electrode above the first pixel electrode; a first semiconductor layer above the first contact electrode; a light-emitting layer above the first semiconductor layer; and a second semiconductor layer above the light-emitting layer and electrically connected to the first common electrode.

[0019] The first light-emitting element and the second light-emitting element may further include a second contact electrode between the second semiconductor layer and the first common electrode.

[0020] The first pixel may further include a third light-emitting element connected in series with the second light-emitting element between the first pixel electrode and the first common electrode, wherein the threshold voltage of the third light-emitting element is lower than the threshold voltage of the first light-emitting element.

[0021] The threshold voltage of the third light-emitting element may be equal to the threshold voltage of the second light-emitting element.

[0022] The first pixel may further include a fourth light-emitting element connected in series with the first light-emitting element between the first pixel electrode and the first common electrode, wherein the threshold voltage of the fourth light-emitting element is higher than the threshold voltage of the second light-emitting element.

[0023] The threshold voltage of the fourth light-emitting element may be equal to the threshold voltage of the first light-emitting element.

[0024] The display device may further include a second pixel in the display area and including more light-emitting elements than the first pixel, wherein two of the light-emitting elements of the second pixel are connected in parallel and have different respective threshold voltages.

[0025] The first pixel and the second pixel may be configured to emit light of different colors.

[0026] According to an aspect of the present disclosure, there is provided a pixel including: a pixel electrode; a common electrode spaced apart from the pixel electrode; a first light-emitting element connected between the pixel electrode and the common electrode; and a second light-emitting element connected in parallel with the first light-emitting element between the pixel electrode and the common electrode and having a threshold voltage lower than the threshold voltage of the first light-emitting element.

[0027] The pixel may further include a third light-emitting element connected in series with the second light-emitting element between the pixel electrode and the common electrode, wherein the threshold voltage of the third light-emitting element is lower than the threshold voltage of the first light-emitting element.

[0028] The pixel according to an embodiment includes a first light-emitting element and a second light-emitting element connected in parallel between the pixel electrode and the common electrode and having different threshold voltages. The display device according to an embodiment includes the pixel.

[0029] According to an embodiment, the brightness of the pixel according to the low gray-level data signal can be appropriately controlled while reducing the power consumption of the display device. Accordingly, the low gray-level representation performance of the pixel can be improved, and the image quality of the display device can be improved.

[0030] However, aspects according to embodiments of the present disclosure are not limited to the aspects described above, and various other aspects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects of the present disclosure will become more apparent by referring to the embodiments of the present disclosure described in detail with reference to the accompanying drawings, in which:

[0032] Figure 1 is a perspective view showing a display device according to one or more embodiments;

[0033] Figure 2 is a plan view showing a display panel according to one or more embodiments;

[0034] Figure 3 is a block diagram showing a display device according to one or more embodiments;

[0035] Figure 4 is a circuit diagram showing a sub-pixel according to one or more embodiments;

[0036] Figure 5 is a circuit diagram showing a sub-pixel according to one or more embodiments;

[0037] Figure 6 is a circuit diagram showing a sub-pixel according to one or more embodiments;

[0038] Figure 7 is a circuit diagram showing a sub-pixel according to one or more embodiments;

[0039] Figure 8 is a plan view showing a sub-pixel according to one or more embodiments;

[0040] Figure 9 is a plan view showing a sub-pixel according to one or more embodiments;

[0041] Figure 10 is a plan view showing a sub-pixel according to one or more embodiments;

[0042] Figure 11 is a plan view showing a sub-pixel according to one or more embodiments;

[0043] Figure 12 is a plan view showing a sub-pixel according to one or more embodiments;

[0044] Figure 13 is a cross-sectional view showing a display panel according to one or more embodiments;

[0045] Figure 14 is a detailed illustration of Figure 13 a cross-sectional view of region A1;

[0046] Figure 15 is a plan view showing a sub-pixel according to one or more embodiments;

[0047] Figure 16 is a cross-sectional view showing a display panel according to one or more embodiments;

[0048] Figure 17 is a diagram showing a virtual reality device including a display device according to one or more embodiments;

[0049] Figure 18 is a diagram showing a smart device including a display device according to one or more embodiments;

[0050] Figure 19 is a diagram showing an instrument panel and a center instrument panel of a vehicle including a display device according to one or more embodiments; and

[0051] Figure 20 is a diagram showing a transparent display device including a display device according to one or more embodiments. DETAILED DESCRIPTION

[0052] Aspects of some embodiments of the present disclosure and methods of implementing the same can be more easily understood by referring to the detailed description of the embodiments and the drawings. The embodiments are provided as examples so that the present disclosure will be thorough and complete, and aspects of the present disclosure will be fully conveyed to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, not relevant to the description of the embodiments, or not necessary for those of ordinary skill in the art to fully understand aspects of the present disclosure may be omitted. Unless otherwise stated, throughout the drawings and the written description, the same reference numerals, characters, or combinations thereof represent the same elements, and thus, their repeated description may be omitted.

[0053] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as limited to the embodiments shown herein. When describing embodiments, the use of "able to", "may", or "may not" corresponds to one or more embodiments of the present disclosure.

[0054] Based on the overall content of the present disclosure, those of ordinary skill in the art will understand that the present disclosure covers all modifications, equivalents, and substitutions within the spirit and technical scope of the present disclosure. Each of the features of the embodiments of the present disclosure may be partially or wholly combined with each other, and various interlocks and drives are possible technically, and each embodiment may be implemented independently of each other, or may be implemented in association with each other, unless otherwise stated or implied.

[0055] In the drawings, for clarity and / or descriptive purposes, the relative dimensions of elements, layers, and regions may be exaggerated. Additionally, the use of cross-hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Thus, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements, unless otherwise stated.

[0056] In this document, various embodiments are described with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Additionally, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments in accordance with the concepts of the present disclosure. Accordingly, the embodiments disclosed herein should not be construed as being limited to the shapes of the elements, layers, or regions shown, but include deviations in shapes due to, for example, manufacturing.

[0057] For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or a gradient of implantation concentration, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed.

[0058] For ease of explanation, spatially relative terms such as "below", "beneath", "lower", "bottom", "under", "above", "upper", "top" etc. may be used herein to describe the relationship of one element or feature to another (or others) as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below", "beneath", or "under" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can include both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being disposed "on" a second part, this means that the first part is disposed at the upper or lower side of the second part, and is not limited to the upper side based on the direction of gravity.

[0059] In addition, the phrase "in a plan view" means observing an object portion from above, and the phrase "in a schematic cross-sectional view" means observing a schematic cross-section taken by vertically cutting the object portion from the side. The term "overlap" or "overlapping" means that a first object can be above or below a second object, or on one side of the second object, and vice versa. Additionally, the term "overlap" can include laminating, facing or being oriented towards, extending over, covering or partially covering, or any other suitable term as would be understood and appreciated by a person of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separate from", "arranged side by side with", "offset from", and any other suitable equivalents as would be understood and appreciated by a person of ordinary skill in the art. The terms "face" and "be oriented towards" can mean that a first object can be directly or indirectly opposite a second object. In cases where a third object is between the first object and the second object, the first object and the second object can be understood as being indirectly opposite each other, although still facing each other.

[0060] It will be understood that when an element, layer, region or component is referred to as being "formed" "on", "over", "connected to" or "(operatively or communicatively) coupled to" another element, layer, region or component, it can be directly formed on, directly over, directly connected to or directly coupled to the other element, layer, region or component, or indirectly formed on, indirectly over, indirectly connected to or indirectly coupled to the other element, layer, region or component such that there can be one or more intervening elements, layers, regions or components. Further, this can generally refer to direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or directly electrically coupled to the other layer, region and / or component, or there can be one or more intervening layers, regions or components. One or more intervening components can include switches, resistors, capacitors, etc. When describing an embodiment, unless explicitly described as a direct connection, the expression of connection means an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or directly coupled to another component or on another component without an intermediate component.

[0061] In addition, in this specification, when forming a part of a layer, film, region, plate, etc. on another part, the forming direction is not limited to the upper direction, but includes forming the part on a side surface or in a lower direction. Conversely, when forming a part of a layer, film, region, plate, etc. "under" another part, this includes not only the case where the part is "directly" "below" the other part, but also the case where there is another part between the part and the other part. On the other hand, other expressions such as "between", "directly between", or "adjacent to" and "directly adjacent to" that describe the relationship between components can be similarly interpreted. It will be understood that when an element or layer is said to be "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0062] For the purposes of this disclosure, expressions such as "at least one of...", "any one of...", or "one or more of..." when following a list of elements modify the entire list of elements, rather than individual elements in the list. For example, "at least one of X, Y, and Z", and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as for example XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, an expression such as "A and / or B" can include A, B, or A and B. Similarly, expressions such as "at least one of...", "a plurality of", "one of...", and other prepositional phrases when following a list of elements modify the entire list of elements, rather than individual elements in the list.

[0063] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position, or priority, and are only used to distinguish one element, member, component, region, zone, layer, section, or part from another element, member, component, region, zone, layer, section, or part. Thus, the first element, first component, first region, first layer, or first section described below may be referred to as the second element, second component, second region, second layer, or second section without departing from the spirit and scope of the present disclosure. Describing an element as a "first" element does not require or imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish different categories or different groups of elements. For the sake of brevity, the terms "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0064] In an example, the DR1 axis, DR2 axis, and / or DR3 axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. This also applies to the first direction, second direction, and / or third direction.

[0065] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, and the plural forms are also intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises", "comprising", "has", "having", "contains", and "containing" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0066] As used herein, the terms "substantially", "about", "approximate" and similar terms are used as terms of approximation and not of degree, and are intended to account for the inherent variations of measured or calculated values that would be recognized by a person of ordinary skill in the art. For example, "substantially" may include a range of ±5% of the corresponding value. Given the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximate" as used herein includes the recited value and means within an acceptable variation of the particular value as determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the recited value. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0067] In some embodiments, well-known structures and devices may be described in the drawings with respect to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that these functional blocks, units, and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wire connections, and other electronic circuits. These may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Functional blocks, units, and / or modules implemented by a microprocessor or other similar hardware may be programmed and controlled with software to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Additionally, each functional block, unit, and / or module may be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs functions different from those of the dedicated hardware. Further, in some embodiments, a functional block, unit, and / or module may be physically divided into two or more interacting separate functional blocks, units, and / or modules without departing from the scope of the present disclosure. Additionally, in some embodiments, functional blocks, units, and / or modules may be physically combined into more complex functional blocks, units, and / or modules without departing from the scope of the present disclosure.

[0068] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0069] Figure 1is a perspective view showing a display device according to one or more embodiments.

[0070] Reference Figure 1 , the display device 10 is a device for displaying moving images or still images. The display device 10 can be used as various devices such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IoT) device, and a display screen of a portable electronic device such as a mobile phone, a smartphone, a tablet personal computer (PC), a smartwatch, a watch phone, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC).

[0071] The display device 10 can be a light-emitting display device, such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro light-emitting display using a micron or nano light-emitting diode (LED). In the following description, it is assumed that the display device 10 is a micro light-emitting display device, but the embodiments are not limited thereto. On the other hand, for simplicity of description, hereinafter, an ultra-small light-emitting diode is referred to as a light-emitting element. However, the type of light-emitting element that can be applied to the embodiments is not limited to a micro light-emitting diode.

[0072] The display device 10 includes a display panel 100, a display driving circuit 250, a circuit board 300, and a power supply circuit 500.

[0073] The display panel 100 may have a rectangular or square planar shape having sides extending in a first direction DR1 and sides extending in a second direction DR2 intersecting the first direction DR1. The corners where the sides in the first direction DR1 and the sides in the second direction DR2 intersect may be rounded to have a curvature (e.g., a predetermined curvature), or may be right-angled. The planar shape of the display panel 100 is not limited to a quadrilateral shape. For example, the display panel 100 may have different planar shapes, such as other polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. In one or more embodiments, the display panel 100 may be formed flexibly so that it can be curved, bent, folded, or curled.

[0074] The substrate SUB of the display panel 100 (see Figure 13 ) may include a main region MA and a sub-region SBA.

[0075] The main area MA may include a display area DA for displaying an image, and a non-display area NDA that is a peripheral area of the display area DA. The display area DA may include pixels for displaying an image. In one or more embodiments, each pixel may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light.

[0076] The sub-area SBA may protrude from one side of the main area MA in the second direction DR2. Although the sub-area SBA is shown as being unfolded in Figure 1 , the sub-area SBA may be bent and disposed on the bottom surface (e.g., below) of the display panel 100. When the sub-area SBA is bent, the main area MA and the sub-area SBA may overlap in a third direction DR3, which is the thickness direction of the display panel 100. The display driving circuit 250 may be disposed in the sub-area SBA.

[0077] The display driving circuit 250 may generate signals and voltages for driving the display panel 100. The display driving circuit 250 may be formed as an integrated circuit (IC), and may be attached to the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but the present disclosure is not limited thereto. For example, the display driving circuit 250 may be attached to the circuit board 300 by a chip on film (COF) method.

[0078] The circuit board 300 may be attached to the sub-area SBA of the display panel 100. As an example, the circuit board 300 may be attached to a pad of the display panel 100 located at one end of the sub-area SBA. Accordingly, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0079] The power supply circuit 500 may generate a panel driving voltage according to a power voltage provided from the outside. The power supply circuit 500 may be formed as an integrated circuit (IC), and may be attached to the circuit board 300 by a COF method.

[0080] Figure 2 is a plan view showing a display panel according to one or more embodiments. In Figure 2 , the sub-area SBA is shown in an unfolded state without being bent.

[0081] Refer to Figure 1 and Figure 2 , the display panel 100 may include a main area MA and a sub-area SBA.

[0082] The main area MA may include a display area DA for displaying an image and a non-display area NDA that is a peripheral area of the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be located at the center of the main area MA.

[0083] The display area DA may include unit pixels PX for displaying an image, and each of the unit pixels PX may include a plurality of sub-pixels SPX (or pixels). The unit pixel PX may be defined as the smallest unit sub-pixel group capable of representing a white gray level.

[0084] The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be positioned to surround the display area DA (e.g., in a plan view). The non-display area NDA may be an edge area of the display panel 100.

[0085] The first scan driver SDC1 and the second scan driver SDC2 may be located in the non-display area NDA. The first scan driver SDC1 may be located at one side (e.g., the left side) of the display panel 100, while the second scan driver SDC2 may be located at the other side (e.g., the right side) of the display panel 100, but the present disclosure is not limited thereto. Each of the first scan driver SDC1 and the second scan driver SDC2 may be electrically connected to the display driving circuit 250 through a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 may receive a scan control signal input from the display driving circuit 250, may generate a scan signal in response to the scan control signal, and may output the generated scan signal to the scan line.

[0086] The sub-area SBA may protrude from one side of the main area MA in the second direction DR2. The length of the sub-area SBA in the second direction DR2 may be less than the length of the main area MA in the second direction DR2. The length of the sub-area SBA in the first direction DR1 may be substantially equal to or less than the length of the main area MA in the first direction DR1. The sub-area SBA may be bent, and thus a part of the sub-area SBA may be located below the main area MA. For example, the sub-area SBA may overlap the main area MA in the third direction DR3.

[0087] The sub-area SBA may include a connection area CA, a pad area PA, and a bending area BA.

[0088] The connection area CA is an area that protrudes from one side of the main area MA in the second direction DR2. One side of the connection area CA may be in contact with the non-display area NDA of the main area MA, while the other side of the connection area CA may be in contact with the bending area BA.

[0089] The pad region PA is the region on which the pad PD and the display driving circuit 250 are located. The display driving circuit 250 can be attached to the driving pads of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 can be attached to the pad PD of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad region PA can be in contact with the bending region BA.

[0090] The bending region BA is a region that can be bent. When the bending region BA is bent, the pad region PA can be located under the connection region CA and the main region MA. The bending region BA can be located between the connection region CA and the pad region PA. One side of the bending region BA can be in contact with the connection region CA, and the other side of the bending region BA can be in contact with the pad region PA.

[0091] Figure 3 is a block diagram showing a display device according to one or more embodiments.

[0092] Reference Figures 1 to 3 , including the unit pixel PX of each in the sub-pixel SPX and the scan line SL, emission control line EL, and data line DL connected to the sub-pixel SPX, can be located in the display area DA.

[0093] The sub-pixels SPX can be arranged in a matrix form in a first direction DR1 and a second direction DR2. The scan lines SL and the emission control lines EL can extend in the first direction DR1 and can be arranged in the second direction DR2. The data lines DL can extend in the second direction DR2 and can be arranged in the first direction DR1. The scan line SL can include a write scan line GWL, a control scan line GCL, an initialization scan line GIL, and a bias scan line GBL located in each pixel row.

[0094] Each of the sub-pixels SPX can be connected to one write scan line GWL, one control scan line GCL, one initialization scan line GIL, one bias scan line GBL, one emission control line EL, and one data line DL. For example, each of the sub-pixels SPX can be connected to the write scan line GWL, control scan line GCL, initialization scan line GIL, bias scan line GBL, and emission control line EL located in each pixel row and the data line DL located in each pixel column.

[0095] Each of the sub-pixels SPX can receive the data signal (e.g., data voltage) of the data line DL according to the write scan signal provided through the write scan line GWL, and can operate the light-emitting element according to the data signal.

[0096] The first scan driver SDC1, the second scan driver SDC2, and the display driving circuit 250 may be located in the non-display area NDA.

[0097] Each of the first scan driver SDC1 and the second scan driver SDC2 may include a write scan signal output unit 611, a control scan signal output unit 612, an initialization scan signal output unit 613, a bias scan signal output unit 614, and a transmit signal output unit 615. Each of the write scan signal output unit 611, the control scan signal output unit 612, the initialization scan signal output unit 613, the bias scan signal output unit 614, and the transmit signal output unit 615 may receive a scan timing control signal SCS from the timing control circuit 251. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS of the timing control circuit 251, and may output them sequentially to the write scan lines GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS, and may output them sequentially to the control scan lines GCL. The initialization scan signal output unit 613 may generate initialization scan signals in response to the scan timing control signal SCS, and may output them sequentially to the initialization scan lines GIL. The bias scan signal output unit 614 may generate bias scan signals according to the scan timing control signal SCS, and may output them sequentially to the bias scan lines GBL. The transmit signal output unit 615 may generate transmit control signals according to the scan timing control signal SCS, and may output them sequentially to the transmit control lines EL.

[0098] The display driving circuit 250 may include a timing control circuit 251 and a data driving circuit 252.

[0099] The timing control circuit 251 may receive video data DATA (e.g., digital video data) and timing signals from the outside. The timing control circuit 251 may generate a scan timing control signal SCS and a data timing control signal DCS for controlling the display panel 100 in response to the timing signals. The timing control circuit 251 may output the scan timing control signal SCS to the first scan driver SDC1 and the second scan driver SDC2. The timing control circuit 251 may output the video data DATA and the data timing control signal DCS to the data driving circuit 252.

[0100] The data driving circuit 252 can receive video data DATA and a data timing control signal DCS from the timing control circuit 251. The data driving circuit 252 can supply corresponding data signals (e.g., analog data voltages) to the sub-pixels SPX. For example, the data driving circuit 252 can convert the video data DATA into analog data voltages in response to the data timing control signal DCS, and can output them to the data lines DL. The sub-pixels SPX can be selected by write scan signals of the first scan driver SDC1 and the second scan driver SDC2, and the data signals can be supplied to the selected sub-pixels SPX.

[0101] The power supply circuit 500 can generate a plurality of panel driving voltages based on an external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VDD, a second driving voltage VSS, and a third driving voltage VINT, and can supply them to the display panel 100.

[0102] Figure 4 is a circuit diagram showing a sub-pixel according to one or more embodiments. Figure 5 is a circuit diagram showing a sub-pixel according to one or more embodiments. Compared with Figure 4 compared with Figure 5 shows one or more embodiments in which the types of some of the transistors are changed.

[0103] Reference Figure 4 and Figure 5 , according to one or more embodiments, the sub-pixel SPX can be connected between a first power line VDL and a second power line VSL, and can include a light emitting unit EMP including a light emitting element LE. The sub-pixel SPX can also include a pixel circuit PXC connected to the light emitting unit EMP. In one or more embodiments, the pixel circuit PXC can be connected between the first power line VDL and the light emitting unit EMP.

[0104] The pixel circuit PXC can be connected to the scan line SL, the emission control line EL, and the data line DL. For example, the pixel circuit PXC can be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission control line EL, and the data line DL.

[0105] The pixel circuit PXC can include a driving transistor DT, at least one switching transistor ST, and a capacitor C1. In one or more embodiments, the pixel circuit PXC can include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6 as the switching transistor ST. The configuration of the pixel circuit PXC is not limited to Figure 4 and Figure 5Embodiments thereof can be varied in various ways.

[0106] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT can control the drain-source current (hereinafter referred to as "driving current") flowing between the first electrode and the second electrode according to a data signal (e.g., an analog data voltage) applied to the gate electrode.

[0107] The first transistor ST1 can be connected between the second electrode and the gate electrode of the driving transistor DT, and the gate electrode of the first transistor ST1 can be connected to the control scan line GCL. According to the control scan signal provided to the control scan line GCL, the first transistor ST1 can operate as a switch.

[0108] The second transistor ST2 can be connected between the data line DL and the first electrode of the driving transistor DT, and the gate electrode of the second transistor ST2 can be connected to the write scan line GWL. According to the write scan signal provided to the write scan line GWL, the second transistor ST2 can operate as a switch.

[0109] The third transistor ST3 can be connected between the gate electrode of the driving transistor DT and the initialization voltage line VIL, and the gate electrode of the third transistor ST3 can be connected to the initialization scan line GIL. According to the initialization scan signal provided to the initialization scan line GIL, the third transistor ST3 can operate as a switch. The third driving voltage VINT can be applied to the initialization voltage line VIL.

[0110] The fourth transistor ST4 can be connected between the first node N1 and the initialization voltage line VIL, and the gate electrode of the fourth transistor ST4 can be connected to the bias scan line GBL. The first node N1 can be the node to which the pixel circuit PXC and the light-emitting unit EMP are connected. As an example, the first node N1 can be the node at which the pixel electrode PXE (e.g., an anode electrode) of the fourth transistor ST4, the sixth transistor ST6, and the light-emitting unit EMP are connected to each other. According to the bias scan signal provided to the bias scan line GBL, the fourth transistor ST4 can operate as a switch.

[0111] The fifth transistor ST5 can be connected between the first power line VDL and the first electrode of the driving transistor DT, and the gate electrode of the fifth transistor ST5 can be connected to the emission control line EL. According to the emission control signal provided to the emission control line EL, the fifth transistor ST5 can operate as a switch. The first driving voltage VDD can be applied to the first power line VDL.

[0112] The sixth transistor ST6 can be connected between the second electrode of the driving transistor DT and the first node N1, and the gate electrode of the sixth transistor ST6 can be connected to the emission control line EL. According to the emission control signal provided to the emission control line EL, the sixth transistor ST6 can operate as a switch.

[0113] In one or more embodiments, as Figure 4 shown, the driving transistor DT and the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed of p-type transistors. For example, each of the driving transistor DT and the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed of a p-type MOSFET including an active layer formed of polysilicon.

[0114] In one or more embodiments, as Figure 5 shown, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed of p-type transistors, and the first transistor ST1 and the third transistor ST3 can be formed of n-type transistors. As an example, each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed of a p-type MOSFET including an active layer formed of polysilicon, and each of the first transistor ST1 and the third transistor ST3 can be formed as an n-type MOSFET including an active layer formed of an oxide semiconductor. In one or more embodiments, the transistor including an active layer formed of polysilicon and the transistor including an active layer formed of an oxide semiconductor can be located on different layers in the display panel 100.

[0115] Alternatively, although not shown in Figure 4 and Figure 5 the driving transistor DT and the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed of n-type transistors. As an example, each of the driving transistor DT and the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed of an n-type MOSFET including an active layer formed of an oxide semiconductor.

[0116] Depending on the type of transistor, the levels of the gate-on voltage and the gate-off voltage of the signal (e.g., each of the scan signal, the data signal, and the emission control signal) applied to the gate electrode of each transistor can be appropriately set or changed. For example, the gate-on voltage of a p-type transistor can be a low-level voltage (e.g., a gate low voltage), and the gate-on voltage of an n-type transistor can be a high-level voltage (e.g., a gate high voltage).

[0117] The capacitor C1 can be connected between the first power line VDL and the gate electrode of the driving transistor DT. The capacitor C1 can be charged with a voltage corresponding to the data signal.

[0118] The light-emitting unit EMP can include a plurality of light-emitting elements LE, and the plurality of light-emitting elements LE includes a first light-emitting element LE1 and a second light-emitting element LE2. The light-emitting element LE can be connected between the pixel circuit PXC (or the first node N1) and the second power line VSL. For example, the first contact electrode (or the first semiconductor layer) of the light-emitting element LE can be connected to the pixel circuit PXC through the pixel electrode PXE, and the second contact electrode (or the second semiconductor layer) of the light-emitting element LE can be connected to the second power line VSL through the common electrode CE (e.g., the cathode electrode). The second driving voltage VSS can be applied to the second power line VSL. The second driving voltage VSS can be a voltage having a level lower than that of the first driving voltage VDD. In one or more embodiments, each light-emitting element LE can be a micro light-emitting diode. The light-emitting unit EMP can emit light with a brightness corresponding to the driving current provided from the pixel circuit PXC.

[0119] In an embodiment, the first light-emitting element LE1 and the second light-emitting element LE2 can be connected in parallel between the pixel electrode PXE and the common electrode CE. In addition, the first light-emitting element LE1 and the second light-emitting element LE2 can be elements having different characteristics, and the threshold voltage of the first light-emitting element LE1 and the threshold voltage of the second light-emitting element LE2 can be different. For example, the threshold voltage of the second light-emitting element LE2 can be lower than the threshold voltage of the first light-emitting element LE1.

[0120] In an embodiment, the pixel circuit PXC can substantially not generate a driving current in response to the data signal corresponding to video data DATA corresponding to a black gray level (e.g., 0 gray level). In this case, the first light-emitting element LE1 and the second light-emitting element LE2 can not operate, and thus, the sub-pixel SPX can not emit light.

[0121] The pixel circuit PXC can generate a relatively small driving current in response to a data signal (hereinafter referred to as "low gray-level data signal") corresponding to video data DATA within a low gray-level range (e.g., 1 to 150 gray levels), and the low gray-level range is equal to or lower than a reference value (e.g., a predetermined reference value). In an embodiment, during a period when the sub-pixel SPX is driven by the low gray-level data signal, a voltage lower than the threshold voltage of the first light-emitting element LE1 and equal to or higher than the threshold voltage of the second light-emitting element LE2 can be applied between the pixel electrode PXE and the common electrode CE. Therefore, the first light-emitting element LE1 can remain in the off state, and the second light-emitting element LE2 can emit light. Due to the operation (e.g., light emission) of the second light-emitting element LE2, the sub-pixel SPX can emit light with a low brightness corresponding to the low gray-level data signal.

[0122] In an embodiment, the second light-emitting element LE2 can be an element having a lower luminous efficiency than the first light-emitting element LE1. Therefore, in the second light-emitting element LE2, the change in the current density according to the change in the input signal (e.g., the low gray-level data signal) may not occur suddenly, but may occur relatively gradually. When only the second light-emitting element LE2 is used to drive the sub-pixel SPX with a low brightness corresponding to the low gray-level data signal while turning off the first light-emitting element LE1, the brightness of the sub-pixel SPX can be controlled more precisely or appropriately corresponding to each gray level of the low gray-level data signal. Therefore, the low gray-level representation performance of the sub-pixel SPX can be improved, and the image quality of the display device 10 can be improved.

[0123] The pixel circuit PXC can generate a relatively large driving current in response to a data signal (hereinafter referred to as "high gray-level data signal") corresponding to video data DATA within a high gray-level range (e.g., 151 or more gray levels, or 151 to 255 gray levels), and the high gray-level range is higher than the reference value. In an embodiment, during a period when the sub-pixel SPX is driven by the high gray-level data signal, a voltage equal to or higher than the threshold voltage of the first light-emitting element LE1 can be applied between the pixel electrode PXE and the common electrode CE. Therefore, both the first light-emitting element LE1 and the second light-emitting element LE2 can emit light to represent a high-brightness gray level corresponding to the data signal.

[0124] In an embodiment, the first light-emitting element LE1 may be an element having a higher luminous efficiency than the second light-emitting element LE2. Both the first light-emitting element LE1 and the second light-emitting element LE2 may emit light corresponding to a high gray-scale data signal, so that while appropriately restricting the driving current flowing through the sub-pixel SPX, the brightness corresponding to each gray-scale of the high gray-scale data signal of the sub-pixel SPX can be sufficiently or appropriately ensured. Therefore, the power consumption of the display device 10 can be reduced or improved.

[0125] Figure 6 is a circuit diagram of a sub-pixel according to one or more embodiments. Figure 7 is a circuit diagram of a sub-pixel according to one or more embodiments. Compared with Figure 5 compared with Figure 6 and Figure 7 show different modified embodiments regarding the light-emitting unit EMP.

[0126] Referring to Figure 6 , the light-emitting unit EMP may further include a third light-emitting element LE3 connected in series with the second light-emitting element LE2. For example, the third light-emitting element LE3 may be connected between the second light-emitting element LE2 and the common electrode CE.

[0127] The threshold voltage of the third light-emitting element LE3 may be lower than the threshold voltage of the first light-emitting element LE1. In one or more embodiments, the threshold voltage of the second light-emitting element LE2 and the threshold voltage of the third light-emitting element LE3 may be substantially the same or similar, and the second light-emitting element LE2 and the third light-emitting element LE3 may emit light substantially simultaneously. The third light-emitting element LE3 allows the light-emitting unit EMP to emit light with appropriate or sufficient brightness, so that each gray-scale can be represented even at a low driving current. Therefore, the brightness of the sub-pixel SPX can be supplemented or improved, and the light efficiency of the sub-pixel SPX can be increased.

[0128] Referring to Figure 7 , the light-emitting unit EMP may further include a fourth light-emitting element LE4 connected in series with the first light-emitting element LE1. For example, the fourth light-emitting element LE4 may be connected between the first light-emitting element LE1 and the common electrode CE.

[0129] The threshold voltage of the fourth light-emitting element LE4 may be higher than the threshold voltage of the second light-emitting element LE2 and the threshold voltage of the third light-emitting element LE3. In one or more embodiments, the threshold voltage of the first light-emitting element LE1 and the threshold voltage of the fourth light-emitting element LE4 may be substantially the same or similar, and the first light-emitting element LE1 and the fourth light-emitting element LE4 may emit light substantially simultaneously. The fourth light-emitting element LE4 can increase the brightness and light efficiency of the light-emitting unit EMP and the sub-pixel SPX including the light-emitting unit EMP.

[0130] Figure 8 is a plan view showing sub-pixels according to one or more embodiments. For example, Figure 8 schematically shows the light-emitting units EMP of a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 located in a display area DA.

[0131] Reference Figures 1 to 8 , each of the unit pixels PX located in the display area DA may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. In one or more embodiments, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 constituting one unit pixel PX may be arranged in a first direction DR1, but is not limited thereto. For example, the arrangement shape of the sub-pixels SPX may vary according to the embodiment.

[0132] Figure 8 One or more embodiments are disclosed in which one first sub-pixel SPX1, one second sub-pixel SPX2, and one third sub-pixel SPX3 constitute one unit pixel PX, but the embodiments are not limited thereto. For example, the type, number, ratio, etc. of the sub-pixels SPX constituting each of the unit pixels PX may vary according to the embodiment.

[0133] In addition, Figure 8 it is shown that the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 (or the emission regions of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3) have substantially the same size and shape, but the embodiments are not limited thereto. For example, the size or shape of the sub-pixels SPX may vary according to the embodiment. For example, the size of the sub-pixels SPX may be appropriately adjusted according to the light efficiency of the sub-pixels SPX.

[0134] The first sub-pixel SPX1 (also referred to as the "first pixel") may emit first light, the second sub-pixel SPX2 may emit second light, and the third sub-pixel SPX3 (also referred to as the "second pixel") may emit third light. In one or more embodiments, the first light may be light in a blue wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a red wavelength band. In one example, the first light, the second light, and the third light may be blue light with a peak wavelength in the range from about 440 nm to about 480 nm, green light with a peak wavelength in the range from about 510 nm to about 550 nm, and red light with a peak wavelength in the range from about 610 nm to about 650 nm, respectively. The color or wavelength band of the light emitted from each of the sub-pixels SPX may vary according to the embodiment.

[0135] Each sub-pixel SPX may include each of a pixel electrode PXE, a common electrode CE, and a light-emitting element LE. For example, a first sub-pixel SPX1 may include a first pixel electrode PXE1, a first common electrode CE1, a first light-emitting element LE1, and a second light-emitting element LE2. A second sub-pixel SPX2 may include a second pixel electrode PXE2, a second common electrode CE2, a first light-emitting element LE1, and a second light-emitting element LE2. A third sub-pixel SPX3 may include a third pixel electrode PXE3, a third common electrode CE3, a first light-emitting element LE1, and a second light-emitting element LE2.

[0136] The pixel electrode PXE and the common electrode CE of each of the sub-pixels SPX may be spaced apart from each other in each sub-pixel region. For example, the first pixel electrode PXE1 and the first common electrode CE1 may be spaced apart from each other in the emission region of the first sub-pixel SPX1. The second pixel electrode PXE2 and the second common electrode CE2 may be spaced apart from each other in the emission region of the second sub-pixel SPX2. The third pixel electrode PXE3 and the third common electrode CE3 may be spaced apart from each other in the emission region of the third sub-pixel SPX3.

[0137] The corresponding light-emitting element LE may be located on or bonded to the pixel electrode PXE and the common electrode CE (as used herein, "located on" may mean "above"). For example, the pixel electrode PXE and the common electrode CE may be bonding pads bonded to the corresponding light-emitting element LE. In one or more embodiments, the pixel electrode PXE and the common electrode CE may be metal electrodes including a metal suitable for bonding, but are not limited thereto.

[0138] Although Figure 8 One or more embodiments are shown in which each of the pixel electrode PXE and the common electrode CE has a quadrilateral planar shape, but the embodiments are not limited thereto. In addition, although Figure 8 One or more embodiments are shown in which the corresponding pixel electrode PXE and the corresponding common electrode CE are formed to have substantially the same size, but the embodiments are not limited thereto. For example, the shape, size, etc. of the pixel electrode PXE and the common electrode CE located in each of the sub-pixels SPX may be changed according to the embodiment. The sub-pixels SPX may have pixel electrodes PXE and / or common electrodes CE of substantially the same size, or the sizes of the pixel electrodes PXE and / or common electrodes CE may vary for each of the sub-pixels SPX.

[0139] Each of the pixel electrodes PXE can be connected to the pixel circuit PXC of a corresponding sub-pixel SPX through each of the first connection holes CT1. For example, the first pixel electrode PXE1 can be connected to the pixel circuit PXC of the first sub-pixel SPX1, the second pixel electrode PXE2 can be connected to the pixel circuit PXC of the second sub-pixel SPX2, and the third pixel electrode PXE3 can be connected to the pixel circuit PXC of the third sub-pixel SPX3.

[0140] Each of the common electrodes CE can be connected to the second power line VSL, and a second driving voltage VSS is applied to the second power line VSL through each of the second connection holes CT2. For example, each of the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 can be connected to the second power line VSL through the second connection hole CT2. Therefore, the second driving voltage VSS can be applied to the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3.

[0141] Although Figure 8 One or more embodiments are shown in which the common electrodes CE of the sub-pixels SPX are separated respectively, but the embodiments are not limited thereto. For example, the common electrodes CE located in the plurality of sub-pixels SPX positioned in the display area DA can be integrally formed to form one common electrode CE.

[0142] The first light-emitting element LE1 and the second light-emitting element LE2 of each of the sub-pixels SPX can be located between the pixel electrode PXE and the common electrode CE of the corresponding sub-pixel SPX or connected in parallel between the pixel electrode PXE and the common electrode CE of the corresponding sub-pixel SPX. For example, the first light-emitting element LE1 and the second light-emitting element LE2 of the first sub-pixel SPX1 can be connected in parallel between the first pixel electrode PXE1 and the first common electrode CE1. The first light-emitting element LE1 and the second light-emitting element LE2 of the second sub-pixel SPX2 can be connected in parallel between the second pixel electrode PXE2 and the second common electrode CE2. The first light-emitting element LE1 and the second light-emitting element LE2 of the third sub-pixel SPX3 can be connected in parallel between the third pixel electrode PXE3 and the third common electrode CE3.

[0143] In one or more embodiments, each of the light-emitting elements LE can include a first contact electrode CTE1 connected to each of the pixel electrodes PXE. In one or more embodiments, each of the light-emitting elements LE can further include a second contact electrode CTE2 connected to each of the common electrodes CE.

[0144] In an embodiment, the first light-emitting element LE1 and the second light-emitting element LE2 of each of the sub-pixels SPX may be light-emitting elements LE having different characteristics. For example, the threshold voltages of the first light-emitting element LE1 and the second light-emitting element LE2 may be different from each other. In addition, the luminous efficiencies of the first light-emitting element LE1 and the second light-emitting element LE2 may be different from each other. In one or more embodiments, the second light-emitting element LE2 may be an element having a lower threshold voltage and a lower luminous efficiency than the first light-emitting element LE1.

[0145] In one or more embodiments, the first light-emitting element LE1 and the second light-emitting element LE2 of each of the sub-pixels SPX may have different respective sizes (e.g., different areas and / or volumes). For example, the size of the first light-emitting element LE1 may be larger than the size of the second light-emitting element LE2.

[0146] In an embodiment, during a period in which each of the sub-pixels SPX is driven at a low luminance by a data signal corresponding to video data DATA in a low gray level range equal to or lower than a reference value, by passing a low drive current to the second light-emitting element LE2 having a relatively low luminous efficiency, the second light-emitting element LE2 can be made to emit light having a luminance corresponding to each gray level. During a period in which each of the sub-pixels SPX is driven at a high luminance by a data signal corresponding to video data DATA in a high gray level range greater than the reference value, in addition to the second light-emitting element LE2, the drive current can be appropriately limited by causing the first light-emitting element LE1 having a relatively high luminous efficiency to emit light. Therefore, each of the sub-pixels SPX can be appropriately made to emit light at a high luminance corresponding to each gray level while reducing or improving power consumption.

[0147] In one or more embodiments, the light-emitting elements LE located in the sub-pixels SPX may emit light of the same color. As an example, the first light-emitting element LE1 and the second light-emitting element LE2 located in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be first color light-emitting diodes that emit first light (e.g., blue light). In one or more embodiments, at least some of the sub-pixels SPX (e.g., the second sub-pixel SPX2 and the third sub-pixel SPX3) may further include a light conversion layer that converts the light generated from each of the light-emitting elements LE into light of a different wavelength band or a different color.

[0148] In one or more other embodiments, the light-emitting elements LE in the sub-pixels SPX may emit light of different colors. For example, the first light-emitting element LE1 and the second light-emitting element LE2 in the first sub-pixel SPX1 may be first-color light-emitting diodes that emit first light (e.g., blue light). The first light-emitting element LE1 and the second light-emitting element LE2 in the second sub-pixel SPX2 may be second-color light-emitting diodes that emit second light (e.g., green light). The first light-emitting element LE1 and the second light-emitting element LE2 in the third sub-pixel SPX3 may be third-color light-emitting diodes that emit third light (e.g., red light).

[0149] Figure 9 is a plan view showing a sub-pixel according to one or more embodiments. For example, Figure 9 shows a sub-pixel SPX according to one or more embodiments, which is different from one or more embodiments corresponding to Figure 8 in terms of a pixel electrode PXE and a common electrode CE.

[0150] Referring to Figure 9 , each of the pixel electrodes PXE may include a plurality of sub-pixel electrodes formed of separate patterns separated from each other. For example, the first pixel electrode PXE1 of the first sub-pixel SPX1 may include a first sub-pixel electrode PXE11 and a second sub-pixel electrode PXE12. The first sub-pixel electrode PXE11 and the second sub-pixel electrode PXE12 of the first sub-pixel SPX1 may be electrically connected to each other. For example, the first sub-pixel electrode PXE11 and the second sub-pixel electrode PXE12 of the first sub-pixel SPX1 may be commonly connected to the pixel circuit PXC of the first sub-pixel SPX1 through corresponding first connection holes CT1.

[0151] The second pixel electrode PXE2 of the second sub-pixel SPX2 may include a first sub-pixel electrode PXE21 and a second sub-pixel electrode PXE22. The first sub-pixel electrode PXE21 and the second sub-pixel electrode PXE22 of the second sub-pixel SPX2 may be electrically connected to each other. For example, the first sub-pixel electrode PXE21 and the second sub-pixel electrode PXE22 of the second sub-pixel SPX2 may be commonly connected to the pixel circuit PXC of the second sub-pixel SPX2 through corresponding first connection holes CT1.

[0152] The third pixel electrode PXE3 of the third sub-pixel SPX3 may include a first sub-pixel electrode PXE31 and a second sub-pixel electrode PXE32. The first sub-pixel electrode PXE31 and the second sub-pixel electrode PXE32 of the third sub-pixel SPX3 may be electrically connected to each other. For example, the first sub-pixel electrode PXE31 and the second sub-pixel electrode PXE32 of the third sub-pixel SPX3 may be commonly connected to the pixel circuit PXC of the third sub-pixel SPX3 through corresponding first connection holes CT1.

[0153] In one or more embodiments, each of the common electrodes CE may include a plurality of sub-common electrodes formed of separate patterns separated from each other. For example, the first common electrode CE1 of the first sub-pixel SPX1 may include a first sub-common electrode CE11 and a second sub-common electrode CE12. The first sub-common electrode CE11 and the second sub-common electrode CE12 of the first sub-pixel SPX1 may be electrically connected to each other. For example, the first sub-common electrode CE11 and the second sub-common electrode CE12 of the first sub-pixel SPX1 may be commonly connected to the second power line VSL through corresponding second connection holes CT2.

[0154] The second common electrode CE2 of the second sub-pixel SPX2 may include a first sub-common electrode CE21 and a second sub-common electrode CE22. The first sub-common electrode CE21 and the second sub-common electrode CE22 of the second sub-pixel SPX2 may be electrically connected to each other. For example, the first sub-common electrode CE21 and the second sub-common electrode CE22 of the second sub-pixel SPX2 may be commonly connected to the second power line VSL through corresponding second connection holes CT2.

[0155] The third common electrode CE3 of the third sub-pixel SPX3 may include a first sub-common electrode CE31 and a second sub-common electrode CE32. The first sub-common electrode CE31 and the second sub-common electrode CE32 of the third sub-pixel SPX3 may be electrically connected to each other. For example, the first sub-common electrode CE31 and the second sub-common electrode CE32 of the third sub-pixel SPX3 may be commonly connected to the second power line VSL through corresponding second connection holes CT2.

[0156] Each of the first light-emitting elements LE1 may be located on the first sub-pixel electrode and the first common electrode positioned in each of the sub-pixels SPX. For example, the first light-emitting element LE1 of the first sub-pixel SPX1 may include a first portion located on the first sub-pixel electrode PXE11 of the first sub-pixel SPX1 and including a first contact electrode CTE1, and a second portion extending from the first portion and located on the first common electrode CE11 of the first sub-pixel SPX1 and including a second contact electrode CTE2.

[0157] The first light-emitting element LE1 of the second sub-pixel SPX2 may include a first portion located on the first sub-pixel electrode PXE21 of the second sub-pixel SPX2 and including the first contact electrode CTE1, and a second portion extending from the first portion and located on the first sub-common electrode CE21 of the second sub-pixel SPX2 and including the second contact electrode CTE2.

[0158] The first light-emitting element LE1 of the third sub-pixel SPX3 may include a first portion located on the first sub-pixel electrode PXE31 of the third sub-pixel SPX3 and including the first contact electrode CTE1, and a second portion extending from the first portion and located on the first sub-common electrode CE31 of the third sub-pixel SPX3 and including the second contact electrode CTE2.

[0159] Each of the second light-emitting elements LE2 may be located on the second sub-pixel electrode and the second sub-common electrode positioned in each of the sub-pixels SPX. For example, the second light-emitting element LE2 of the first sub-pixel SPX1 may include a first portion located on the second sub-pixel electrode PXE12 of the first sub-pixel SPX1 and including the first contact electrode CTE1, and a second portion extending from the first portion and located on the second sub-common electrode CE12 of the first sub-pixel SPX1 and including the second contact electrode CTE2.

[0160] The second light-emitting element LE2 of the second sub-pixel SPX2 may include a first portion located on the second sub-pixel electrode PXE22 of the second sub-pixel SPX2 and including the first contact electrode CTE1, and a second portion extending from the first portion and located on the second sub-common electrode CE22 of the second sub-pixel SPX2 and including the second contact electrode CTE2.

[0161] The second light-emitting element LE2 of the third sub-pixel SPX3 may include a first portion located on the second sub-pixel electrode PXE32 of the third sub-pixel SPX3 and including the first contact electrode CTE1, and a second portion extending from the first portion and located on the second sub-common electrode CE32 of the third sub-pixel SPX3 and including the second contact electrode CTE2.

[0162] According to an embodiment, each of the pixel electrodes PXE is divided into a plurality of sub-pixel electrodes and / or each of the common electrodes CE is divided into a plurality of sub-common electrodes, so that damage to elements (e.g., peripheral insulating layers or conductive patterns, etc.) located around the pixel electrodes PXE and the common electrodes CE can be reduced or prevented. For example, in a bonding process or the like that connects the light-emitting elements LE to the pixel electrodes PXE and the common electrodes CE respectively, the pressure applied to the peripheries of the pixel electrodes PXE and the common electrodes CE is reduced or alleviated, so that damage to elements located in the peripheries can be reduced or prevented.

[0163] In addition, according to an embodiment, each of the pixel electrodes PXE is divided into a plurality of sub-pixel electrodes and / or each of the common electrodes CE is divided into a plurality of sub-common electrodes, so that a repair process for defective sub-pixels SPX can be performed more conveniently. For example, since each of the pixel electrodes PXE and the common electrodes CE is divided into smaller-sized patterns, in the process of repairing a defective sub-pixel SPX that has occurred therein by using a laser cutting method or the like, scattering of the laser caused by the pixel electrode PXE and / or the common electrode CE located in the corresponding sub-pixel SPX can be reduced or prevented, and the area where the repair can be performed can be expanded.

[0164] Figure 10 is a plan view showing a sub-pixel according to one or more embodiments. For example, Figure 10 shows one or more embodiments of a sub-pixel SPX further including a third light-emitting element LE3, which is similar to the corresponding Figure 6 one or more embodiments.

[0165] Reference Figure 10 , each of the sub-pixels SPX may further include a third light-emitting element LE3 connected in series with the second light-emitting element LE2 between the pixel electrode PXE and the common electrode CE. In addition, each of the sub-pixels SPX may further include a first bridging electrode BRE1 connecting the second light-emitting element LE2 to the third light-emitting element LE3.

[0166] The second light-emitting element LE2 of each of the sub-pixels SPX may be connected between the pixel electrode PXE and the first bridging electrode BRE1 located in the corresponding sub-pixel SPX. For example, the first contact electrode CTE1 of the second light-emitting element LE2 may be connected to the second sub-pixel electrode PXE12, PXE22, or PXE32, and the second contact electrode CTE2 of the second light-emitting element LE2 may be connected to the first bridging electrode BRE1.

[0167] The third light-emitting element LE3 of each of the sub-pixels SPX may be connected between the first bridging electrode BRE1 and the common electrode CE located in the corresponding sub-pixel SPX. For example, the first contact electrode CTE1 of the third light-emitting element LE3 may be connected to the first bridging electrode BRE1, and the second contact electrode CTE2 of the third light-emitting element LE3 may be connected to the second sub-common electrode CE12, CE22, or CE32.

[0168] In one or more embodiments, the second light-emitting element LE2 and the third light-emitting element LE3 of each of the sub-pixels SPX may be elements having substantially the same characteristics. For example, the threshold voltages of the second light-emitting element LE2 and the third light-emitting element LE3 of each of the sub-pixels SPX may be substantially the same or similar. In an embodiment, the threshold voltages of the second light-emitting element LE2 and the third light-emitting element LE3 of each of the sub-pixels SPX may be lower than the threshold voltage of the first light-emitting element LE1. In addition, the luminous efficiencies of the second light-emitting element LE2 and the third light-emitting element LE3 of each of the sub-pixels SPX may be substantially the same or similar. However, the embodiments are not limited thereto. For example, the threshold voltages and / or luminous efficiencies of the second light-emitting element LE2 and the third light-emitting element LE3 may be different.

[0169] In one or more embodiments, the second light-emitting element LE2 and the third light-emitting element LE3 of each of the sub-pixels SPX may have substantially the same size. However, the embodiments are not limited thereto. For example, the second light-emitting element LE2 and the third light-emitting element LE3 may have different sizes.

[0170] By further positioning the third light-emitting element LE3 in the sub-pixel SPX, the luminance of the sub-pixel SPX (e.g., the luminance corresponding to a data signal in a low gray level range) can be supplemented or increased.

[0171] Figure 11 is a plan view showing a sub-pixel according to one or more embodiments. For example, Figure 11 shows one or more embodiments of a sub-pixel SPX further including a fourth light-emitting element LE4, which is similar to the corresponding Figure 7 one or more embodiments.

[0172] Reference Figure 11 shows that each of the sub-pixels SPX may further include a fourth light-emitting element LE4 connected in series with the first light-emitting element LE1 between the pixel electrode PXE and the common electrode CE. In addition, each of the sub-pixels SPX may further include a second bridging electrode BRE2 connecting the first light-emitting element LE1 to the fourth light-emitting element LE4.

[0173] The first light-emitting element LE1 of each of the sub-pixels SPX may be connected between the pixel electrode PXE located in the corresponding sub-pixel SPX and the second bridging electrode BRE2. For example, the first contact electrode CTE1 of the first light-emitting element LE1 may be connected to the first sub-pixel electrode PXE11, PXE21, or PXE31, and the second contact electrode CTE2 of the first light-emitting element LE1 may be connected to the second bridging electrode BRE2.

[0174] The fourth light-emitting element LE4 of each in the sub-pixel SPX can be connected between the second bridging electrode BRE2 and the common electrode CE located in the corresponding sub-pixel SPX. For example, the first contact electrode CTE1 of the fourth light-emitting element LE4 can be connected to the second bridging electrode BRE2, and the second contact electrode CTE2 of the fourth light-emitting element LE4 can be connected to the first sub-common electrodes CE11, CE21, or CE31.

[0175] In one or more embodiments, the first light-emitting element LE1 and the fourth light-emitting element LE4 of each in the sub-pixel SPX can be elements having substantially the same characteristics. For example, the threshold voltages of the first light-emitting element LE1 and the fourth light-emitting element LE4 of each in the sub-pixel SPX can be substantially the same or similar. In an embodiment, the threshold voltages of the first light-emitting element LE1 and the fourth light-emitting element LE4 of each in the sub-pixel SPX can be higher than the threshold voltages of the second light-emitting element LE2 and the third light-emitting element LE3. In addition, the luminous efficiencies of the first light-emitting element LE1 and the fourth light-emitting element LE4 of each in the sub-pixel SPX can be substantially the same or similar. However, the embodiments are not limited thereto. For example, the threshold voltages and / or luminous efficiencies of the first light-emitting element LE1 and the fourth light-emitting element LE4 can be different.

[0176] In one or more embodiments, the first light-emitting element LE1 and the fourth light-emitting element LE4 of each in the sub-pixel SPX can have substantially the same size. However, the embodiments are not limited thereto. For example, the first light-emitting element LE1 and the fourth light-emitting element LE4 can have different sizes.

[0177] By further providing the fourth light-emitting element LE4 in the sub-pixel SPX, the brightness of the sub-pixel SPX (for example, the brightness corresponding to the data signal in the high gray level range) can be supplemented or increased.

[0178] Figure 12 is a plan view showing a sub-pixel according to one or more embodiments. For example, Figure 12 shows one or more embodiments of a unit pixel PX including sub-pixels SPX having different structures.

[0179] Reference Figure 12 , at least two sub-pixels SPX constituting each of the unit pixels PX can have different structures. For example, the first sub-pixel SPX1 and the third sub-pixel SPX3 can have different structures.

[0180] In one or more embodiments, compared to the first sub-pixel SPX1, the third sub-pixel SPX3 may include a greater number of light-emitting elements LE. As an example, the first sub-pixel SPX1 may include two light-emitting elements LE including a first light-emitting element LE1 and a second light-emitting element LE2, and the third sub-pixel SPX3 may include three light-emitting elements LE including a first light-emitting element LE1, a second light-emitting element LE2, and a third light-emitting element LE3.

[0181] In one or more embodiments, the second sub-pixel SPX2 may have a substantially same structure as the first sub-pixel SPX1 or the third sub-pixel SPX3. As an example, similar to the first sub-pixel SPX1, the second sub-pixel SPX2 may include two light-emitting elements LE including a first light-emitting element LE1 and a second light-emitting element LE2. Alternatively, similar to the third sub-pixel SPX3, the second sub-pixel SPX2 may include three light-emitting elements LE including a first light-emitting element LE1, a second light-emitting element LE2, and a third light-emitting element LE3.

[0182] In one or more other embodiments, the second sub-pixel SPX2 may have a structure different from that of the first sub-pixel SPX1 and the third sub-pixel SPX3. As an example, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include different numbers of light-emitting elements LE.

[0183] In one or more embodiments, considering the light efficiency or brightness of the sub-pixel SPX, etc., at least two sub-pixels SPX may be formed in different structures. For example, when the light efficiency or brightness of the third sub-pixel SPX3 among the first sub-pixel SPX1 and the third sub-pixel SPX3 formed in the same structure is low, a greater number of light-emitting elements LE are located in the third sub-pixel SPX3, thereby improving the light efficiency or brightness of the third sub-pixel SPX3.

[0184] Figure 13 is a cross-sectional view showing a display panel according to one or more embodiments. For example, Figure 13 shows Figure 8 one or more embodiments of a cross-section of the display panel 100 taken along the line X1-X1'. Figure 14 is a cross-sectional view showing in detail Figure 13 region A1.

[0185] In addition to Figures 1 to 12 also referring to Figure 13 and Figure 14, the display panel 100 may include a substrate SUB and a thin-film transistor layer TFTL (also referred to as a "panel circuit layer") and a light-emitting element layer LEL located on the substrate SUB (e.g., above). In one or more embodiments, the display panel 100 may further include a light conversion layer, a color filter, etc. located on the light-emitting element layer LEL.

[0186] The substrate SUB may be formed of an insulating material such as glass or a polymer resin. When the substrate SUB is made of a polymer resin, it may be a flexible substrate that can be stretched. The polymer resin may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0187] The barrier layer BR may be located on the substrate SUB. The barrier layer BR may protect the transistors of the thin-film transistor layer TFTL and the light-emitting element layer LEL from moisture that penetrates through the substrate SUB (which may be vulnerable to moisture penetration). The barrier layer BR may be formed as a plurality of inorganic layers stacked alternately. For example, the barrier layer BR may be formed of a multilayer in which one or more inorganic layers among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked alternately.

[0188] The first thin-film transistor TFT1 may be located on the barrier layer BR. The first thin-film transistor TFT1 may be one of the first type of transistors (e.g., p-type transistors) among the transistors provided to each of the sub-pixels SPX. For example, the first thin-film transistor TFT1 may be Figure 5 either the fourth transistor ST4 or the sixth transistor ST6 shown in. The first thin-film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0189] The first active layer ACT1 of the first thin-film transistor TFT1 may be located on the barrier layer BR. The first active layer ACT1 of the first thin-film transistor TFT1 may include polysilicon, single-crystalline silicon, low-temperature polysilicon, or amorphous silicon.

[0190] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region that overlaps with the first gate electrode G1 in a third direction DR3, which is the thickness direction of the substrate SUB. The first source region S1 may be located on one side of the first channel region CHA1, and the first drain region D1 may be located on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions that do not overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 may be regions that have conductivity by doping a silicon semiconductor with ions.

[0191] The first gate insulating layer 131 may be located on the first channel region CHA1, the first source region S1, and the first drain region D1 of the first thin film transistor TFT1. The first gate insulating layer 131 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0192] The first gate metal layer may be located on the first gate insulating layer 131. The first gate metal layer may include the first gate electrode G1 of the first thin film transistor TFT1 and the first capacitor electrode CAE1. The first gate electrode G1 may overlap with the first active layer ACT1 in the third direction DR3. Figure 13 It is shown that the first gate electrode G1 and the first capacitor electrode CAE1 are spaced apart from each other, but the first gate electrode G1 and the first capacitor electrode CAE1 may be connected to each other. The first gate metal layer may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0193] The second gate insulating layer 132 may be located on the first gate electrode G1 and the first capacitor electrode CAE1 of the first thin film transistor TFT1. The second gate insulating layer 132 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0194] The second gate metal layer may be located on the second gate insulating layer 132. The second gate metal layer may include the second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap with the first capacitor electrode CAE1 in the third direction DR3. Since the second gate insulating layer 132 has a dielectric constant (e.g., a predetermined dielectric constant), a capacitor (e.g., Figure 5 capacitor C1 in) may be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the second gate insulating layer 132 located therebetween. The second gate metal layer may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0195] The first interlayer insulating layer 141 may be located on the second capacitor electrode CAE2. The first interlayer insulating layer 141 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0196] The second thin film transistor TFT2 may be located on the first interlayer insulating layer 141. The second thin film transistor TFT2 may be one of the second type transistors (e.g., n-type transistors) among the transistors of the pixel circuit PXC provided to each of the sub-pixels SPX. For example, the second thin film transistor TFT2 may be Figure 5 either the first transistor ST1 or the third transistor ST3 shown in. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2.

[0197] The second active layer ACT2 of the second thin film transistor TFT2 may be located on the first interlayer insulating layer 141. The second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0198] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region overlapping with the second gate electrode G2 in the third direction DR3. The second source region S2 may be located on one side of the second channel region CHA2, while the second drain region D2 may be located on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be regions that do not overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 and the second drain region D2 may be regions having conductivity by ion-doping an oxide semiconductor.

[0199] The third gate insulating layer 133 may be located on the second active layer ACT2 of the second thin film transistor TFT2. The third gate insulating layer 133 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0200] The third gate metal layer may be located on the third gate insulating layer 133. The third gate metal layer may include the second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may overlap with the second active layer ACT2 in the third direction DR3. The third gate metal layer may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0201] The second interlayer insulating layer 142 may be located on the second gate electrode G2 of the second thin film transistor TFT2. The second interlayer insulating layer 142 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0202] The first data metal layer (also referred to as the "first source-drain conductive layer") may be located on the second interlayer insulating layer 142. The first data metal layer may include a first connection electrode PCE1, a second connection electrode BE1, and a third connection electrode BE2. The first connection electrode PCE1 may be connected to the first drain region D1 of the first active layer ACT1 through a first contact hole PCT1 that penetrates the first gate insulating layer 131, the second gate insulating layer 132, the first interlayer insulating layer 141, the third gate insulating layer 133, and the second interlayer insulating layer 142. The second connection electrode BE1 may be connected to the second source region S2 of the second active layer ACT2 through a second contact hole BCT1 that penetrates the third gate insulating layer 133 and the second interlayer insulating layer 142. The third connection electrode BE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third contact hole BCT2 that penetrates the third gate insulating layer 133 and the second interlayer insulating layer 142. The first data metal layer may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. For example, the first data metal layer may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0203] On the first connection electrode PCE1, on the second connection electrode BE1, and on the third connection electrode BE2, a first organic layer 160 may be positioned to flatten the step portions caused by the first thin film transistor TFT1 and the second thin film transistor TFT2. The first organic layer 160 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0204] The second data metal layer (also referred to as the "second source-drain conductive layer") may be located on the first organic layer 160. The second data metal layer may include a fourth connection electrode PCE2. The fourth connection electrode PCE2 may be connected to the first connection electrode PCE1 through a fourth contact hole PCT2 that penetrates the first organic layer 160. The second data metal layer may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. For example, the second data metal layer may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0205] The second organic layer 180 may be located on the fourth connection electrode PCE2. The second organic layer 180 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0206] The light-emitting element layer LEL may be located on the second organic layer 180. The light-emitting element layer LEL may include a pixel electrode PXE, a common electrode CE, a light-emitting element LE, a bank 190, a third organic layer 191, a fourth organic layer 192, and a first capping layer CAP1.

[0207] The pixel electrode PXE and the common electrode CE may be located on the second organic layer 180. The pixel electrode PXE of each of the sub-pixels SPX may be connected to the fourth connection electrode PCE2 of the corresponding sub-pixel SPX through a first connection hole CT1 (see Figure 8 ) that penetrates the second organic layer 180. The common electrode CE of each of the sub-pixels SPX may be connected to the second power line VSL (see Figure 8 ) through a second connection hole CT2 (see Figure 5 ).

[0208] In one or more embodiments, the pixel electrode PXE and the common electrode CE of each of the sub-pixels SPX may not overlap with each other in the thickness direction (e.g., the third direction DR3) of the light-emitting element LE, and may overlap with different portions of the light-emitting element LE. For example, the first pixel electrode PXE1 and the first common electrode CE1 may not overlap with each other in the thickness direction of the first light-emitting element LE1 and the second light-emitting element LE2 in the first sub-pixel SPX1. In addition, a part of the first light-emitting element LE1 and a part of the second light-emitting element LE2 may be located on the first pixel electrode PXE1, and another part of the first light-emitting element LE1 and another part of the second light-emitting element LE2 may be located on the first common electrode CE1.

[0209] The pixel electrode PXE and the common electrode CE may be formed as a single layer or a multi-layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. For example, in order to reduce the resistance of each of the pixel electrode PXE and the common electrode CE, the pixel electrode PXE and the common electrode CE may be formed as a multi-layer made of copper (Cu) having a low sheet resistance or an alloy made of titanium (Ti) or copper (Cu).

[0210] The bank 190 may cover a part of each of the pixel electrode PXE and the common electrode CE. For example, the bank 190 may cover at least one side edge of the pixel electrode PXE and the common electrode CE. The bank 190 may not be located on the remaining portions of the pixel electrode PXE and the common electrode CE. For example, the bank 190 may not be located on the central portions of each of the pixel electrode PXE and the common electrode CE, and not on the edge where the pixel electrode PXE faces the common electrode CE among the edges of the pixel electrode PXE and the common electrode CE.

[0211] The bank 190 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. The bank 190 may include a light-blocking material to reduce or prevent the light of the light-emitting element LE of any one sub-pixel SPX from traveling to an adjacent sub-pixel SPX. For example, the bank 190 may contain an organic black pigment or an inorganic black pigment such as carbon black.

[0212] The corresponding light-emitting element LE may be located on the pixel electrode PXE and the common electrode CE. For example, a part of the first light-emitting element LE1 and the second light-emitting element LE2 provided to the corresponding sub-pixel SPX may be located on the pixel electrode PXE of each of the sub-pixels SPX, and another part of the first light-emitting element LE1 and the second light-emitting element LE2 provided in the corresponding sub-pixel SPX may be located on the common electrode CE of each of the sub-pixels SPX. As an example, the first contact electrode CTE1 of each of the first light-emitting element LE1 and the second light-emitting element LE2 provided in the corresponding sub-pixel SPX may be located on the pixel electrode PXE of each of the sub-pixels SPX, and the second contact electrode CTE2 of each of the first light-emitting element LE1 and the second light-emitting element LE2 provided in the corresponding sub-pixel SPX may be located on the common electrode CE of each of the sub-pixels SPX.

[0213] In Figure 13 and Figure 14 embodiments, each of the light-emitting elements LE may be a flip-chip type micro-LED. The flip-chip type micro-LED may refer to an LED in which the first contact electrode CTE1 and the second contact electrode CTE2 are formed on one surface (e.g., the bottom surface) of the light-emitting element LE.

[0214] In one or more embodiments, each of the light-emitting elements LE may be formed of gallium nitride (GaN) or another inorganic material. In one or more embodiments, each of the light-emitting elements LE may be a micro light-emitting diode having a length in a first direction DR1, a length in a second direction DR2, and a length in a third direction DR3 of several μm to several hundred μm, respectively. For example, in each of the light-emitting elements LE, each of the length in the first direction DR1, the length in the second direction DR2, and the length in the third direction DR3 may be about 100 μm or less.

[0215] Each of the light-emitting elements LE may be formed by growing on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The light-emitting element LE may be directly transferred onto the pixel electrode PXE and the common electrode CE of the display panel 100. Alternatively, the light-emitting element LE may be transferred onto the common electrode CE and the pixel electrode PXE of the display panel 100 by an electrostatic method using an electrostatic head or an imprinting method using an elastic polymer material such as PDMS or silicone as a transfer substrate.

[0216] Reference Figure 14 As shown, each of the light-emitting elements LE may include a first semiconductor layer SEM1, a light-emitting layer EML, a second semiconductor layer SEM2, and a passivation layer INS. In one or more embodiments, each of the light-emitting elements LE may further include at least one contact electrode. For example, each of the light-emitting elements LE may further include a first contact electrode CTE1 connected to the first semiconductor layer SEM1 and a second contact electrode CTE2 connected to the second semiconductor layer SEM2.

[0217] The first contact electrode CTE1 may be located on the pixel electrode PXE of each of the sub-pixels SPX. For example, the first contact electrode CTE1 may be located between the pixel electrode PXE of each of the sub-pixels SPX and the first semiconductor layer SEM1 of the light-emitting element LE. The first contact electrode CTE1 may connect the first semiconductor layer SEM1 of the light-emitting element LE to the pixel electrode PXE of each of the sub-pixels SPX.

[0218] The second contact electrode CTE2 may be located on the common electrode CE of each of the sub-pixels SPX. For example, the second contact electrode CTE2 may be located between the common electrode CE of each of the sub-pixels SPX and the second semiconductor layer SEM2 of the light-emitting element LE. The second contact electrode CTE2 may connect the second semiconductor layer SEM2 of the light-emitting element LE to the common electrode CE of each of the sub-pixels SPX.

[0219] The first contact electrode CTE1 and the second contact electrode CTE2 may include a metal, a metal oxide, or other conductive materials. For example, the first contact electrode CTE1 and the second contact electrode CTE2 may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0220] The first semiconductor layer SEM1 may be located on the first contact electrode CTE1. In one or more embodiments, the first semiconductor layer SEM1 may be made of p-GaN doped with a first conductive type dopant (e.g., a p-type dopant) such as Mg, Zn, Ca, and / or Ba.

[0221] The first semiconductor layer SEM1 may be electrically connected to the pixel electrode PXE of each of the sub-pixels SPX. For example, the first semiconductor layer SEM1 may be electrically connected to the pixel electrode PXE of each of the sub-pixels SPX through the first contact electrode CTE1.

[0222] The light-emitting layer EML may be located on the first semiconductor layer SEM1. For example, the light-emitting layer EML may be located between the first semiconductor layer SEM1 and the second semiconductor layer SEM2. According to the electrical signals applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2, the light-emitting layer EML may emit light through the recombination of electron-hole pairs.

[0223] The light-emitting layer EML may include a material having a single quantum well structure or a multi-quantum well structure. When the light-emitting layer EML includes a material having a multi-quantum well structure, the light-emitting layer EML may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In one or more embodiments, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. Alternatively, the light-emitting layer EML may have a structure in which a semiconductor material having a large bandgap and a semiconductor material having a small bandgap are alternately stacked, and may include other group III-V semiconductor materials according to the wavelength band of the emitted light.

[0224] When the light-emitting layer EML includes InGaN, the color of the emitted light may vary according to the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the light-emitting layer EML may shift to the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the light-emitting layer EML may shift to the blue wavelength band. For example, the light-emitting layer EML of a light-emitting element LE that emits first light (light in the blue wavelength band) may contain about 10 wt% to about 20 wt% of indium (In).

[0225] The second semiconductor layer SEM2 may be located on the light-emitting layer EML. In one or more embodiments, the second semiconductor layer SEM2 may be made of n-GaN doped with a second-conductivity-type dopant (e.g., an n-type dopant) such as Si, Ge, Se, and Sn.

[0226] The second semiconductor layer SEM2 may be electrically connected to the common electrode CE of each of the sub-pixels SPX. For example, the second semiconductor layer SEM2 may be electrically connected to the common electrode CE of each of the sub-pixels SPX through the second contact electrode CTE2.

[0227] In one or more embodiments, the second semiconductor layer SEM2 may have a larger area than the first semiconductor layer SEM1 and the light-emitting layer EML. The second semiconductor layer SEM2 may include a first portion SEM21 overlapping with the first semiconductor layer SEM1 and the light-emitting layer EML, and a second portion SEM22 and a third portion SEM23 extending from the first portion SEM21 and not overlapping with the first semiconductor layer SEM1 and the light-emitting layer EML.

[0228] The second portion SEM22 of the second semiconductor layer SEM2 may be located on the second contact electrode CTE2. The second contact electrode CTE2 may be located between each of the common electrodes CE and the second portion SEM22 of the second semiconductor layer SEM2.

[0229] In one or more embodiments, the second portion SEM22 of the second semiconductor layer SEM2 may have a greater thickness than the rest of the second semiconductor layer SEM2. Thus, the light-emitting element LE can be stably positioned or connected to each of the pixel electrode PXE and the common electrode CE without increasing the thickness of the second contact electrode CTE2. In one or more other embodiments, the second portion SEM22 of the second semiconductor layer SEM2 may have a thickness similar to that of the rest of the second semiconductor layer SEM2, and the second contact electrode CTE2 may have a greater thickness than the first contact electrode CTE1. Thus, the light-emitting element LE can be stably positioned or connected to each of the pixel electrode PXE and the common electrode CE.

[0230] The third portion SEM23 of the second semiconductor layer SEM2 may connect the first portion SEM21 and the second portion SEM22 of the second semiconductor layer SEM2. In one or more embodiments, the third portion SEM23 of the second semiconductor layer SEM2 may have a thickness less than that of the rest of the second semiconductor layer SEM2, but the present disclosure is not limited thereto.

[0231] The passivation layer INS can surround the first semiconductor layer SEM1, the light-emitting layer EML, and the second semiconductor layer SEM2. As an example, the passivation layer INS can surround the outer surfaces of the first semiconductor layer SEM1, the light-emitting layer EML, and the second semiconductor layer SEM2.

[0232] The passivation layer INS can be a layer for protecting the side surfaces of the light-emitting element LE. The passivation layer INS can be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0233] The third organic layer 191 and the fourth organic layer 192 can be located around the light-emitting element LE. For example, the third organic layer 191 can be located on at least a part of the bank 190, the pixel electrode PXE, and the common electrode CE, and the fourth organic layer 192 can be located on the third organic layer 191. The third organic layer 191 and the fourth organic layer 192 can cover the side surfaces of the light-emitting element LE. Each of the third organic layer 191 and the fourth organic layer 192 can be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0234] The third organic layer 191 and the fourth organic layer 192 can be layers for flattening the step portion caused by the light-emitting element LE. When the third organic layer 191 has a height covering most of the side surfaces of the light-emitting element LE, the fourth organic layer 192 can be omitted.

[0235] The first capping layer CAP1 can be located on the light-emitting element LE and the fourth organic layer 192. The first capping layer CAP1 can be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0236] Reference Figure 13, the light blocking layer BM, the light transmissive layer TPL, the first light conversion layer QDL1, and the second light conversion layer QDL2 may be located on the first capping layer CAP1. However, the embodiments are not limited thereto, and a third light conversion layer may be positioned to replace the light transmissive layer TPL. In this case, the third light conversion layer may include a material different from that of the first light conversion layer QDL1 and the second light conversion layer QDL2. For example, the first light conversion layer QDL1 may include quantum dots that convert light in the blue wavelength band into light in the green wavelength band, the second light conversion layer QDL2 may include quantum dots that convert light in the blue wavelength band into light in the red wavelength band, and the third light conversion layer may include blue phosphors. In addition, in addition to quantum dots, each of the first light conversion layer QDL1, the second light conversion layer QDL2, and the third light conversion layer may further include a light dispersant such as titanium dioxide (TiO2). In this case, the number of titanium dioxide (TiO2) particles in the third light conversion layer may be greater than the number of titanium dioxide (TiO2) particles in the first light conversion layer QDL1 or greater than the number of titanium dioxide (TiO2) particles in the second light conversion layer QDL2.

[0237] The light transmissive layer TPL, the first light conversion layer QDL1, and the second light conversion layer QDL2 may be formed in each emission region separated by the light blocking layer BM. For example, the light transmissive layer TPL may be located on the first capping layer CAP1 in the first sub-pixel SPX1, the first light conversion layer QDL1 may be located on the first capping layer CAP1 in the second sub-pixel SPX2, and the second light conversion layer QDL2 may be located on the first capping layer CAP1 in the third sub-pixel SPX3. The light blocking layer BM may overlap the bank 190 in the third direction DR3 and may not overlap the light emitting element LE.

[0238] The light transmissive layer TPL may include a light transmissive organic material. For example, the light transmissive layer TPL may include epoxy resin, acrylic resin, cardo resin, imide resin, etc.

[0239] The first light conversion layer QDL1 can convert a part of the first light (light in the blue wavelength band) incident from the light-emitting element LE into the second light (light in the green wavelength band). The first light conversion layer QDL1 can include a first base resin BRS1 and first wavelength conversion particles WCP1. The first base resin BRS1 can include a light-transmissive organic material. For example, the first base resin BRS1 can contain an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first wavelength conversion particles WCP1 can convert a part of the first light (light in the blue wavelength band) incident from the light-emitting element LE into the second light (light in the green wavelength band). The first wavelength conversion particles WCP1 can be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials. The first light conversion layer QDL1 can further include a light dispersant such as titanium dioxide (TiO2).

[0240] The second light conversion layer QDL2 can convert a part of the first light (light in the blue wavelength band) incident from the light-emitting element LE into the third light (light in the red wavelength band). The second light conversion layer QDL2 can include a second base resin BRS2 and second wavelength conversion particles WCP2. The second base resin BRS2 can contain a light-transmissive organic material. For example, the second base resin BRS2 can contain an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The second wavelength conversion particles WCP2 can convert a part of the first light (light in the blue wavelength band) incident from the light-emitting element LE into the third light (light in the red wavelength band). The second wavelength conversion particles WCP2 can be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials. The second light conversion layer QDL2 can further include a light dispersant such as titanium dioxide (TiO2).

[0241] The light blocking layer BM can include a first light blocking layer BM1 and a second light blocking layer BM2 stacked in sequence. The length of the first light blocking layer BM1 in the first direction DR1 or the length of the first light blocking layer BM1 in the second direction DR2 can be greater than the length of the second light blocking layer BM2 in the first direction DR1 or the length of the second light blocking layer BM2 in the second direction DR2. The length (or height) of the first light blocking layer BM1 in the third direction DR3 can be greater than the length (or height) of the second light blocking layer BM2 in the third direction DR3. The first light blocking layer BM1 and the second light blocking layer BM2 can include an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The first light blocking layer BM1 and the second light blocking layer BM2 can further include a dye or a pigment having a light blocking property. For example, the first light blocking layer BM1 and the second light blocking layer BM2 can contain an organic black pigment or an inorganic black pigment such as carbon black.

[0242] The second capping layer CAP2 may be located on the first capping layer CAP1 and the light blocking layer BM. The second capping layer CAP2 may be located on the side surface and the top surface of the light blocking layer BM. That is, the second capping layer CAP2 may be located on the side surface of the first light blocking layer BM1 and on the side surface and the top surface of the second light blocking layer BM2. The second capping layer CAP2 is used to protect the first wavelength conversion particles WCP1 of the first light conversion layer QDL1 and the second wavelength conversion particles WCP2 of the second light conversion layer QDL2 from moisture penetration, and may thus be positioned to surround the upper, lower, and side surfaces of the first light conversion layer QDL1 and the second light conversion layer QDL2.

[0243] The reflective layer RF may be located between the light blocking layer BM and the light transmissive layer TPL, between the light blocking layer BM and the first light conversion layer QDL1, and between the light blocking layer BM and the second light conversion layer QDL2. The reflective layer RF may be located on the second capping layer CAP2 positioned on the side surfaces of the first light blocking layer BM1 and the second light blocking layer BM2. The reflective layer RF is used to reflect light traveling in the lateral direction from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmissive layer TPL.

[0244] The reflective layer RF may include a metallic material having a high reflectivity, such as aluminum (Al). The thickness of the reflective layer RF may be about 0.1 μm.

[0245] Alternatively, the reflective layer RF may include M (where M is an integer of 2 or greater) pairs of a first layer and a second layer having different respective refractive indices to function as a distributed Bragg reflector (DBR). In this case, the M first layers and the M second layers may be alternately positioned. The first layer and the second layer may be formed of inorganic layers such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0246] The third capping layer CAP3 may be located on the second capping layer CAP2, the light transmissive layer TPL, the first light conversion layer QDL1, and the second light conversion layer QDL2. The third capping layer CAP3 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The light transmissive layer TPL, the first light conversion layer QDL1, and the second light conversion layer QDL2 may be encapsulated by the first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3. The refractive index of the third capping layer CAP3 may be lower than the refractive index of the second capping layer CAP2. Furthermore, the refractive index of the third capping layer CAP3 may be lower than the refractive index of the fifth organic layer 193.

[0247] The fifth organic layer 193 may be located on the third capping layer CAP3. The fifth organic layer 193 may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0248] The color filter may be located on the fifth organic layer 193. The color filter may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. However, the embodiments are not limited thereto. For example, when the light-emitting element LE of the first sub-pixel SPX1 emits light of a first color, the light-emitting element LE of the second sub-pixel SPX2 emits light of a second color, and the light-emitting element LE of the third sub-pixel SPX3 emits light of a third color, the light-transmitting layer TPL, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light blocking layer BM may be omitted. In addition, in this case, the fifth organic layer 193 may be located on the first capping layer CAP1, and the color filter may be located on the fifth organic layer 193, or the color filter may be omitted.

[0249] The first color filter CF1 may be located in the first sub-pixel SPX1. The first color filter CF1 may transmit first light (e.g., light in a blue wavelength band). For example, the first color filter CF1 may transmit the first light emitted from the light-emitting element LE and passing through the light-transmitting layer TPL. Thus, the first sub-pixel SPX1 may emit the first light.

[0250] The second color filter CF2 may be located in the second sub-pixel SPX2. The second color filter CF2 may transmit second light (e.g., light in a green wavelength band) and may absorb or block the first light. For example, the second color filter CF2 may transmit the second light obtained by converting the first light emitted from the light-emitting element LE by the first light conversion layer QDL1, and may absorb or block the first light not converted by the first light conversion layer QDL1. Thus, the second sub-pixel SPX2 may emit the second light.

[0251] The third color filter CF3 may be located in the third sub-pixel SPX3. The third color filter CF3 may transmit third light (e.g., light in a red wavelength band) and may absorb or block the first light. For example, the third color filter CF3 may transmit the third light obtained by converting the first light emitted from the light-emitting element LE by the second light conversion layer QDL2, and may absorb or block the first light not converted by the second light conversion layer QDL2. Thus, the third sub-pixel SPX3 may emit the third light.

[0252] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may block external light incident from the outside. For example, the third color filter CF3 blocks the first light and the second light incident from the outside, where the first light is light in a blue wavelength band and the second light is light in a green wavelength band, thereby improving the color purity of the third light corresponding to the color in the red wavelength band.

[0253] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may overlap with the bank 190 and the light blocking layer BM in the third direction DR3.

[0254] The sixth organic layer 194 for planarization may be located on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The sixth organic layer 194 may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0255] Figure 15 is a plan view showing a sub-pixel according to one or more embodiments. Figure 16 is a cross-sectional view showing a display panel according to one or more embodiments. For example, Figure 16 shows along Figure 15 one or more embodiments of a cross-section of the display panel 100 taken along the line X2-X2'. Figure 15 and Figure 16 shows one or more embodiments that are different from the Figure 8 , Figure 13 and Figure 14 embodiments in terms of the pixel electrode PXE, the common electrode CE, and the light-emitting element LE.

[0256] In addition to Figures 1 to 14 also refer to Figure 15 and Figure 16 , the pixel electrode PXE and the common electrode CE of each of the sub-pixels SPX may overlap each other. For example, the pixel electrode PXE and the common electrode CE may overlap each other in the thickness direction (e.g., the third direction DR3) of the light-emitting element LE. In one or more embodiments, the pixel electrode PXE may be separately formed for each of the sub-pixels SPX, and the common electrode CE may be formed as one electrode shared by a plurality of sub-pixels SPX. For example, the Figures 8 to 14 shown first common electrode CE1, second common electrode CE2, and third common electrode CE3 may be integrated into one common electrode CE. The edge of each of the pixel electrodes PXE may be covered by the bank 190.

[0257] The light-emitting element LE of each in the sub-pixel SPX may be located between the pixel electrode PXE and the common electrode CE of the corresponding sub-pixel SPX. For example, the light-emitting element LE of each in the sub-pixel SPX may be located on the pixel electrode PXE of the corresponding sub-pixel SPX and may be covered by the common electrode CE. For example, the first light-emitting element LE1 and the second light-emitting element LE2 of the first sub-pixel SPX1 may be located on the first pixel electrode PXE1. The first light-emitting element LE1 and the second light-emitting element LE2 of the second sub-pixel SPX2 may be located on the second pixel electrode PXE2. The first light-emitting element LE1 and the second light-emitting element LE2 of the third sub-pixel SPX3 may be located on the third pixel electrode PXE3.

[0258] Each of the light-emitting elements LE may include a first semiconductor layer SEM1, a light-emitting layer EML, and a second semiconductor layer SEM2 that are sequentially positioned along a third direction DR3. For example, each of the light-emitting elements LE may be a vertical micro-LED extending in the third direction DR3. A vertical micro-LED may refer to an LED having a structure in which the first semiconductor layer SEM1, the light-emitting layer EML, and the second semiconductor layer SEM2 are sequentially located in the third direction DR3 as the vertical direction.

[0259] In one or more embodiments, the first semiconductor layer SEM1, the light-emitting layer EML, and the second semiconductor layer SEM2 of each of the light-emitting elements LE may have substantially the same or similar area, but are not limited thereto.

[0260] Each of the light-emitting elements LE may further include a passivation layer INS. The passivation layer INS may surround the side surfaces of the first semiconductor layer SEM1, the light-emitting layer EML, and the second semiconductor layer SEM2.

[0261] In one or more embodiments, each of the light-emitting elements LE may include a first contact electrode CTE1 connected to each of the pixel electrodes PXE. The first semiconductor layer SEM1, the light-emitting layer EML, and the second semiconductor layer SEM2 of each of the light-emitting elements LE may be sequentially located on the first contact electrode CTE1.

[0262] In one or more embodiments, each of the light-emitting elements LE may not include the second contact electrode CTE2 described in the foregoing embodiments. For example, the second semiconductor layer SEM2 may be directly connected to the common electrode CE.

[0263] In one or more embodiments, the common electrode CE may be entirely located on the light-emitting element LE of the sub-pixel SPX. As an example, the common electrode CE may be located on the light-emitting element LE of the sub-pixel SPX positioned in the display area DA and on the fourth organic layer 192, and may be entirely formed in the display area DA. In one or more embodiments, the common electrode CE may be directly located on the second semiconductor layer SEM2 of the light-emitting element LE.

[0264] The common electrode CE may be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) and indium zinc oxide (IZO) that can transmit light. The common electrode CE may be covered by the first capping layer CAP1.

[0265] Figure 17 FIG. is a diagram showing a virtual reality device including a display device according to one or more embodiments.

[0266] Reference Figure 17 , the virtual reality device 1 according to one or more embodiments may be a glasses-type device. The virtual reality device 1 according to one or more embodiments may include a display device 10_1, a left lens 10a, a right lens 10b, a support frame 20, temple arms 30a and 30b, a reflection member 40, and a display device housing 50.

[0267] Although Figure 17 FIG. shows the virtual reality device 1 including the temple arms 30a and 30b, the virtual reality device 1 according to one or more embodiments may be applied to a head-mounted display including a head-mounted strap that can be worn on the head, without the temple arms 30a and 30b. For example, the virtual reality device 1 according to one or more embodiments is not limited to Figure 17 the form shown in, and may be applied to various other electronic devices in various forms.

[0268] The display device housing 50 may accommodate the display device 10_1 and the reflection member 40. The image displayed on the display device 10_1 may be reflected by the reflection member 40 and may be provided to the right eye of the user through the right lens 10b. Thus, the user may view the virtual reality image displayed on the display device 10_1 through the right eye.

[0269] Although Figure 17The display device housing 50 is shown at the right end of the support frame 20, but the embodiment is not limited thereto. For example, the display device housing 50 may be located at the left end of the support frame 20, and in this case, the image displayed on the display device 10_1 may be reflected by the reflection member 40 and provided to the left eye of the user through the left lens 10a. Accordingly, the user may view the virtual reality image displayed on the display device 10_1 through the left eye. Alternatively, the display device housing 50 may be located at both the left end and the right end of the support frame 20. In this case, the user may view the virtual reality image displayed on the display device 10_1 through both the left eye and the right eye.

[0270] Figure 18 FIG. is a diagram showing a smart device including a display device according to one or more embodiments.

[0271] Reference Figure 18 , according to one or more embodiments, the display device 10_2 may be applied to the smart watch 2 which is one type of smart devices. The planar shape of the clock display unit of the smart watch 2 may follow the planar shape of the display device 10_2. For example, when the display device 10_2 according to one or more embodiments has a planar shape such as a circular shape or an oval shape, the clock display unit of the smart watch 2 may have a planar shape such as a circular shape or an oval shape. Alternatively, when the display device 10_2 according to one or more embodiments has a quadrilateral planar shape, the clock display unit of the smart watch 2 may have a quadrilateral planar shape. However, the embodiment is not limited thereto, and the clock display unit of the smart watch 2 may not follow the planar shape of the display device 10_2.

[0272] Figure 19 FIG. is a diagram showing an instrument panel and a center instrument panel of a vehicle including a display device according to one or more embodiments. Figure 19 Shows a vehicle to which the display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to one or more embodiments are applied.

[0273] Reference Figure 19 , according to one or more embodiments, the display devices 10_a, 10_b, and 10_c may be applied to the instrument panel of a vehicle, the center instrument panel of a vehicle, or the center information display (CID) of the instrument panel of a vehicle. Alternatively, the display devices 10_d and 10_e according to one or more embodiments may be applied to an interior mirror display instead of the side view mirror of a vehicle.

[0274] Figure 20 FIG. is a diagram showing a transparent display device including a display device according to one or more embodiments.

[0275] ReferenceFigure 20 According to one or more embodiments, the display device 10_3 can be applied to a transparent display device. The transparent display device can display an image IM and can also transmit light. Thus, in addition to the image IM displayed on the display device 10_3, a user located in front of the transparent display device can also view an object RS or a background located behind the transparent display device. When the display device 10_3 is applied to a transparent display device, the display panel 100 can include a light-transmitting portion capable of transmitting light, or can be formed on a substrate member made of a material capable of transmitting light.

[0276] At the end of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the embodiments without substantially departing from the aspects of the present disclosure. Therefore, the embodiments of the present disclosure are disclosed only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: A first pixel is in a display area and includes: a first pixel electrode; a first common electrode, spaced apart from the first pixel electrode; A first light emitting element connected between the first pixel electrode and the first common electrode; and The second light emitting element is connected in parallel with the first light emitting element between the first pixel electrode and the first common electrode and has a threshold voltage lower than a threshold voltage of the first light emitting element.

2. The display device according to claim 1, wherein: The size of the first light emitting element is different from the size of the second light emitting element.

3. The display device according to claim 2, wherein: The size of the first light emitting element is greater than the size of the second light emitting element.

4. The display device according to claim 1, wherein: The light emission efficiency of the first light emitting element is higher than the light emission efficiency of the second light emitting element.

5. The display device according to claim 1, wherein: The first pixel electrode and the first common electrode do not overlap each other in a thickness direction of the first light emitting element and the second light emitting element, wherein a portion of the first light emitting element and a portion of the second light emitting element are above the first pixel electrode, and Another portion of the first light emitting element and another portion of the second light emitting element are above the first common electrode.

6. The display device according to claim 1, wherein: The first pixel electrode and the first common electrode overlap each other in a thickness direction of the first light emitting element and the second light emitting element, wherein the first light emitting element and the second light emitting element are above the first pixel electrode, and Wherein, the first common electrode is above the first light-emitting element and the second light-emitting element.

7. The display device according to claim 1, wherein: The first pixel electrode includes a first sub-pixel electrode and a second sub-pixel electrode that are separated from each other and electrically connected to each other.

8. The display device according to claim 7, wherein: The first light emitting element and the second light emitting element are respectively above the first sub-pixel electrode and the second sub-pixel electrode.

9. The display device according to claim 7, wherein: The first common electrode includes a first sub-common electrode and a second sub-common electrode that are separated from each other and electrically connected to each other.

10. The display device according to claim 9, wherein: The first light emitting element includes a first portion above the first sub-pixel electrode and a second portion extending from the first portion and above the first sub-common electrode, and The second light emitting element includes a first portion above the second sub-pixel electrode and a second portion extending from the first portion of the second light emitting element and above the second sub-common electrode.

11. The display device according to claim 1, wherein: The first light emitting element and the second light emitting element include: a first contact electrode, above the first pixel electrode; a first semiconductor layer, above the first contact electrode; a light emitting layer, above the first semiconductor layer; and The second semiconductor layer is above the light emitting layer and is electrically connected to the first common electrode.

12. The display device according to claim 11, wherein: The first light emitting element and the second light emitting element further include a second contact electrode between the second semiconductor layer and the first common electrode.

13. The display device according to claim 1, wherein: The first pixel further includes a third light emitting element, the third light emitting element and the second light emitting element are connected in series between the first pixel electrode and the first common electrode, and Wherein, a threshold voltage of the third light-emitting element is lower than the threshold voltage of the first light-emitting element.

14. The display device according to claim 13, wherein: The threshold voltage of the third light emitting element is equal to the threshold voltage of the second light emitting element.

15. The display device according to claim 1, wherein: The first pixel further includes a fourth light emitting element, the fourth light emitting element and the first light emitting element are connected in series between the first pixel electrode and the first common electrode, and Wherein, a threshold voltage of the fourth light-emitting element is higher than the threshold voltage of the second light-emitting element.

16. The display device according to claim 15, wherein: The threshold voltage of the fourth light emitting element is equal to the threshold voltage of the first light emitting element.

17. The display device according to claim 1, further comprising a second pixel in the display area and including more light emitting elements than the first pixel, in, Two of the light emitting elements of the second pixel are connected in parallel and have different respective threshold voltages.

18. The display device according to claim 17, wherein: The first pixel and the second pixel are configured to emit light of different respective colors.

19. A pixel comprising: Pixel electrode; a common electrode, spaced apart from the pixel electrode; A first light emitting element connected between the pixel electrode and the common electrode; as well as The second light emitting element is connected in parallel with the first light emitting element between the pixel electrode and the common electrode and has a threshold voltage lower than a threshold voltage of the first light emitting element.

20. The pixel according to claim 19, further comprising a third light emitting element, the third light emitting element being connected in series with the second light emitting element between the pixel electrode and the common electrode, in, A threshold voltage of the third light emitting element is lower than the threshold voltage of the first light emitting element.

Images