Packaging body, lead frame structure and SOP packaging piece

Abstract

The invention relates to the technical field of IC manufacturing semiconductor packaging, in particular to a packaging body, a lead frame structure unit and an SOP packaging piece, according to the SOP packaging piece, a plurality of lead frames are arranged on a lead frame body in an array mode, one-to-one correspondence of the packaging body and the lead frames is achieved, the packaging body is in a pin arrangement mode different from an existing SOP8L, and the packaging body and the lead frame structure unit are arranged in an array mode. Wherein five common pins are arranged on one side of the colloid, one common pin and two wide pins are arranged on the other side of the colloid, the common pins and the wide pins are arranged on the lead frame structure unit, and the wide pins can conduct out heat transmitted from the surface of a chip to the inside of a plastic package body to play a role in heat dissipation. Through the one-to-one correspondence between the inner pins and the outer pins, the connection process of the packaging piece and the external equipment is simplified, and the reliability of a system is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of IC manufacturing semiconductor packaging, and specifically to a package body, a lead frame structure, and an SOP package. Background Art

[0002] For traditional SOP8L products, due to their relatively small package body size (specifically 4.9 mm in length × 3.9 mm in width × 1.4 mm in thickness), they are unable to cope when facing application scenarios with high power and high heat dissipation requirements. In order to better meet the urgent market demand for high-power and high-heat dissipation performance products, and to be customized according to the actual size and functional characteristics of the chip, designing and developing a new type of high-heat dissipation packaging device has become an important direction for the innovative development in the field of microelectronics assembly and packaging technology.

[0003] In the field of high-power and high-heat dissipation products, most products are realized by co-packaging an IC chip and a MOS chip. CN114050139A discloses a dual-base island dual-heat sink dual-drive chip SOP packaging structure and its lead frame. The lead frame includes a first base island and a second base island arranged adjacent to each other at intervals. Both the first base island and the second base island include heat sinks. The first base island and the second base island are respectively provided with more than three support rods that form a "zigzag" cross-section with the heat sinks at equal intervals on the edge except at the adjacent position of the two. Through the support rods, it is avoided that the heat sinks shrink and overflow glue unilaterally or at a single corner during mold clamping. The area of the dual-base island part is large enough for each of them to contain a heat sink, which improves the performance upper limit and application range of the SOP packaging product and realizes a breakthrough in the SOP packaging product.

[0004] As the heat dissipation requirements continue to increase, the size of the MOS chips used has gradually increased accordingly. Therefore, in order to effectively meet the actual market demand and further enhance the market competitiveness of products, it is particularly crucial and urgent to design and develop a brand-new package body size and a matching lead frame structure. Summary of the Invention

[0005] Aiming at the problem of incompatibility between heat dissipation and product size of SOP8L products in the prior art, the present invention provides a package body, a lead frame structure, and an SOP package.

[0006] The present invention is realized through the following technical solutions: An encapsulation body includes a colloid. Five outer pins with the same width are arranged on the side of the colloid, denoted as the first outer pin P1, the second outer pin P2, the third outer pin P3, the fourth outer pin P4, and the fifth outer pin P5. On the side of the colloid opposite to the first outer pin, a sixth outer pin P6, a seventh outer pin P7, and an eighth outer pin P8 are arranged. The width of the sixth outer pin P6 is less than the width of the seventh outer pin P7, and the width of the seventh outer pin P7 is the same as the width of the eighth outer pin P8.

[0007] Preferably, the five outer pins with the same width are arranged at equal intervals.

[0008] Preferably, the distance e1 between adjacent ordinary outer pins is 1.30 BSC.

[0009] Preferably, the pin width of the sixth outer pin P6 is 0.4 mm, and the pin widths of the seventh outer pin P7 and the eighth outer pin P8 are 1.52 mm.

[0010] Preferably, the center distance between the sixth outer pin P6 and the seventh outer pin P7 is greater than the center distance between the seventh outer pin P7 and the eighth outer pin P8.

[0011] Preferably, the center distance e3 between the sixth outer pin P6 and the seventh outer pin P7 is 2.6 mm, and the center distance e2 between the seventh outer pin P7 and the eighth outer pin P8 is 1.92 mm.

[0012] A lead frame structure unit, which is a double-carrier lead frame. Six ordinary inner pins and two wide pins are provided on the lead frame structure unit. The pin width of the wide pins is greater than the pin width of the ordinary inner pins; The six ordinary inner pins are respectively denoted as the first inner pin A1, the second inner pin A2, the third inner pin A3, the fourth inner pin A4, the fifth inner pin A5, and the sixth inner pin A6. A false connecting rib B3 is designed between the second inner pin A2 and the third inner pin A3. The false connecting rib B3, the right carrier connecting rib B1, and the fifth inner pin A5 are all connected to the right small carrier; The two wide pins are respectively denoted as the seventh inner pin A7 and the eighth inner pin A8. The seventh inner pin A7, the eighth inner pin A8, and the left carrier connecting rib B2 are all connected to the left small carrier.

[0013] Preferably, the pin width of the wide pins is 3.8 times the pin width of the ordinary inner pins.

[0014] Preferably, a square groove is provided between the seventh inner pin A7 and the eighth inner pin A8 and the base island.

[0015] An SOP package includes a lead frame body and a plurality of said packages. A plurality of said lead frame units are arranged in an array on the lead frame body. The packages correspond to the lead frame units one by one, and the outer pins and the inner pins correspond to each other one by one.

[0016] Compared with the prior art, the present invention has the following beneficial effects: An SOP package of the present invention is a new package with a package body size and outer pin arrangement different from those of the existing SOP8L. It is mainly a new type of high heat dissipation package designed according to the actual chip size and function.

[0017] A lead frame structure unit of the present invention has a pin arrangement different from that of the existing SOP8L. It is a double-carrier lead frame structure. The wide pins are connected to the carrier to form a heat conduction channel, which is more conducive to the conduction and dissipation of heat during chip operation, enabling the chip to work at a relatively low temperature and improving product reliability.

[0018] An SOP package of the present invention realizes the thinning of the package by introducing a package body and a lead frame structure unit with specific sizes, and meets the heat dissipation requirements by introducing the form of connecting wide pins to the carrier, thereby achieving performance breakthroughs in thinness and heat dissipation of SOP products. Description of the Drawings

[0019] Figure 1 It is a schematic diagram of a package body of the present invention; Figure 2 It is a schematic diagram of the lead frame structure body in the present invention; Figure 3 It is a schematic diagram of a double-carrier unit of the lead frame structure of the present invention; Figure 4 It is a schematic diagram of chip bonding and leads inside the lead frame structure of the present invention.

[0020] In the figure, 1, package body; 2, lead frame structure body; 3, square groove; 4, mold locking hole; P1, first outer pin; P2, second outer pin; P3, third outer pin; P4, fourth outer pin; P5, fifth outer pin; P6, sixth outer pin; P7, seventh outer pin; P8, eighth outer pin; A1, first inner pin; A2, second inner pin; A3, third inner pin; A4, fourth inner pin; A5, fifth inner pin; A6, sixth inner pin; A7, seventh inner pin; A8, eighth inner pin; B1, right connecting rib; B2, left connecting rib; B3, false connecting rib; 5, IC chip; 6, MOS chip; 7, lead from MOS chip to inner pin A6, 8, first lead; 9, second lead; 10, third lead. Detailed Embodiments

[0021] The present invention will be further described in detail below in conjunction with specific embodiments. The following is an explanation rather than a limitation of the present invention.

[0022] Referring to Figure 1 , the present invention discloses a package, including a colloid. Five outer pins with the same width are arranged on the side of the colloid, denoted as the first outer pin P1, the second outer pin P2, the third outer pin P3, the fourth outer pin P4, and the fifth outer pin P5. The five outer pins with the same width are arranged at equal intervals, and the distance e1 between adjacent outer pins is 1.30 BSC, and the width is 0.4 mm.

[0023] On the side of the colloid opposite to the first outer pin, a sixth outer pin P6, a seventh outer pin P7, and an eighth outer pin P8 are arranged. The width of the sixth outer pin P6 is less than the width of the seventh outer pin P7, and the width of the seventh outer pin P7 is the same as the width of the eighth outer pin P8. Specifically, the pin width of the sixth outer pin P6 is 0.4 mm, and the pin widths of the seventh outer pin P7 and the eighth outer pin P8 are 1.52 mm.

[0024] The center distance between the sixth outer pin P6 and the seventh outer pin P7 is greater than the center distance between the seventh outer pin P7 and the eighth outer pin P8. The center distance e3 between the sixth outer pin P6 and the seventh outer pin P7 is, and the center distance e2 between the seventh outer pin P7 and the eighth outer pin P8 is 1.92 mm.

[0025] That is, the size of the package is 6.2 mm in length, 3.9 mm in width, and 1.4 mm in thickness. The pins are arranged on both sides in the length direction of the colloid. On the side corresponding to the first outer pin, there are 5 ordinary outer pins P1 to P5 with a width of 0.4 mm, and the pitch e1 between the pins is 1.30 BSC. On the other side of the colloid, there are 3 outer pins with different widths. The width of the outer pin P6 is 0.4 mm, the pin widths of the outer pins P7 and P8 are 1.52 mm, and the pitch e2 is 1.92 mm.

[0026] The design size and outer pin arrangement of a package of the present invention are a new package different from the existing SOP8L. It is mainly a new type of high-heat-dissipation package designed according to the actual chip size and function, so as to increase the cross-sectional area of the package, thereby widening the heat conduction path and further improving the heat dissipation ability. Specifically, on one side of the colloid, there are 5 ordinary pins with a pin width of 0.4 mm arranged, on the other side, there is an ordinary pin with a pin width of 0.4 mm, and 2 wide pins with a width of 1.52 mm. By optimizing the pin settings, the flexibility and applicability of the package are improved.

[0027] The present invention discloses a lead frame structure unit, the thickness of the material is 0.203mm, the lead frame structure is a double-carrier lead frame, the lead frame structure unit is provided with six common inner pins and two wide pins, the pin width of the wide pins is greater than the pin width of the common inner pins, and the pin width of the wide pins is 3.8 times the pin width of the common inner pins. The six common inner pins are respectively recorded as the first inner pin A1, the second inner pin A2, the third inner pin A3, the fourth inner pin A4, the fifth inner pin A5 and the sixth inner pin A6. A dummy connecting rib B3 is designed between the second inner pin A2 and the third inner pin A3. The dummy connecting rib B3, the right carrier connecting rib B1 and the fifth inner pin A5 are all connected to the right small carrier. Compared with the ordinary SOP8L, the dummy connecting rib B3 ensures the coplanarity of the right base island, thereby ensuring the stability of the wire bonding process during the processing of the product and improving the reliability of the product. This is because the small base island on the right needs to carry the IC chip. The design of the false connecting rib B3 increases the coplanarity of the base island, so that the small base island on the right is supported by the false connecting rib B3 and the right carrier connecting rib B1, so as to ensure the coplanarity (plane consistency of the base island, avoid the tilt of the base island with one-sided connecting ribs, so that the bonding glue overflows evenly when the IC chip is bonded, and avoids the stratification between the bonding glue and the chip due to uneven overflow of glue. In addition, the IC chip has leads to the base island and the inner pins, and the wire bonding process needs to be stressed, which avoids the shaking of the base island when stressed, causing the welding wire to be unreliable, and the welding wire falls off during the transfer process, thereby improving product reliability.

[0028] The two wide pins are respectively recorded as the seventh inner pin A7 and the eighth inner pin A8. The seventh inner pin A7, the eighth inner pin A8 and the left carrier connecting rib B2 are all connected to the left small carrier. One purpose is to dissipate heat, and at the same time ensure the coplanarity of the left carrier, and also ensure the stability of the wire bonding process and improve product reliability.

[0029] A square groove is provided between the seventh inner pin A7 and the eighth inner pin A8 and the base island. The design of the square groove can strengthen the bonding strength between the plastic encapsulation body and the carrier. At the same time, the square groove reduces the force-bearing area of ​​the wide outer pins P7 and P8 during the encapsulation molding of the product, reduces the risk of product stratification, and improves the reliability of the product. Specifically, the plastic encapsulation material penetrates during the plastic encapsulation of the product, thereby wrapping the lead frame copper material in the middle. The through-hole design allows the plastic encapsulation material to be firmly combined together, avoiding stratification between the copper material and the plastic powder material, thereby improving product reliability. The outer pins need to be subjected to force during molding. The wide outer pins P7 and P8 are relatively wide and have a large force-bearing area. The square groove in the middle releases the gravitational force of the force, which can reduce the stratification between the plastic encapsulation material and the copper material caused by the force applied to the plastic encapsulation body.

[0030] Specifically, the width of the inner pins A1 to A6 is 0.4 mm, and the width of the inner pins A7 and A8 is 1.52 mm, so as to facilitate assembly with the package body.

[0031] The inner leads at the edge of the carrier are also designed with mold locking holes, which can strengthen the bonding strength between the plastic encapsulant and the carrier and improve the product reliability.

[0032] In the dual-carrier lead frame structure of the present invention, wide leads are connected to the carrier to form a heat conduction channel, which is more conducive to the conduction and dissipation of heat when the chip is working, enabling the chip to work at a relatively low temperature and improving the product reliability. At the same time, the right base island is supported jointly by the false connecting rib B3 and the right carrier connecting rib B1, ensuring the coplanarity of the base islands and solving problems such as uneven overflow of the die bonding adhesive and unreliable wire bonding caused by the inclination of the base islands.

[0033] The present invention also discloses an SOP package, which includes a lead frame body, a plurality of the above-mentioned lead frame structure units, a MOS chip, an IC chip, a first lead, a second lead, and a third lead. A plurality of the lead frame structure units are arranged in an array on the lead frame body, and the packages are in one-to-one correspondence with the lead frame structure units. The MOS chip is fixed on the left base island of the lead frame structure unit, the IC chip is fixed on the right base island of the lead frame structure unit, the first lead is the interconnection lead between the IC and the MOS chips, the second lead is the lead connecting the IC chip to the right base island, and the third lead is the lead from the IC chip to the inner leads A1, A2, A3, A4, A5, A6. The plastic package encapsulates all the components and leads.

[0034] Specifically, the designed length of the lead frame body is 250 mm, and the designed width is 79.5 mm. There are 28 columns on the lead frame body, and each column of the frame group is designed with 8 unit structures. The outer leads and the inner leads are in one-to-one correspondence, that is, the inner lead A1 corresponds to the outer lead P1, the inner lead A2 corresponds to the outer lead P2, the inner lead A3 corresponds to the outer lead P3, the inner lead A4 corresponds to the outer lead P4, the inner lead A5 corresponds to the outer lead P5, the inner lead A6 corresponds to the outer lead P6, the inner lead A7 corresponds to the outer lead P7, and the inner lead A8 corresponds to the outer lead P8.

[0035] In the SOP package of the present invention, a plurality of lead frame structure units are arranged in an array on the lead frame body, and the packages are in one-to-one correspondence with the lead frame structure units. The layout of the MOS chip and the IC chip takes into account both the functional requirements between the chips and the signal transmission path, which helps to optimize the circuit performance and reduce signal interference. The electrical connections between the various components are realized by using the first lead, the second lead, and the third lead. The inner leads and the outer leads are in one-to-one correspondence, forming a clear signal transmission path, facilitating the connection between the external device and the package, reducing the possibility of connection errors, and reducing the failure rate and maintenance cost, thereby improving the reliability of the system.

[0036] The above are only the preferred embodiments of the present invention, and are not intended to limit the technical solutions of the present invention. Those skilled in the art should understand that without departing from the spirit and principle of the present invention, the technical solutions can be subject to several simple modifications and substitutions, and these modifications and substitutions also fall within the protection scope covered by the claims.

Claims

1. A package, characterized in that: The invention comprises a colloid, and five external pins with the same width are arranged on the side of the colloid, which are denoted as the first external pin P1, the second external pin P2, the third external pin P3, the fourth external pin P4 and the fifth external pin P5. The sixth external pin P6, the seventh external pin P7 and the eighth external pin P8 are arranged on the side of the colloid opposite to the first external pin. The width of the sixth external pin P6 is smaller than the width of the seventh external pin P7, and the width of the seventh external pin P7 is the same as the width of the eighth external pin P8.

2. The package according to claim 1, characterized in that: The five outer pins of the same width are arranged at equal intervals.

3. The package according to claim 2, characterized in that: The distance e1 between adjacent common external pins is 1.30 BSC.

4. The package according to claim 1, characterized in that: The pin width of the sixth external pin P6 is 0.4 mm, and the pin widths of the seventh external pin P7 and the eighth external pin P8 are 1.52 mm.

5. The package according to claim 1, characterized in that: The center distance between the sixth external pin P6 and the seventh external pin P7 is greater than the width of the seventh external pin P7 and the center distance between the eighth external pin P8.

6. The package according to claim 1, characterized in that: The center distance e3 between the sixth outer pin P6 and the seventh outer pin P7 is 2.6 mm, and the center distance e2 between the width of the seventh outer pin P7 and the eighth outer pin P8 is 1.92 mm.

7. A lead frame structure unit, characterized in that: The lead frame structure is a dual-carrier lead frame, and is provided with six common inner pins and two wide pins, wherein the pin width of the wide pins is greater than the pin width of the common inner pins; The six common inner pins are respectively recorded as the first inner pin A1, the second inner pin A2, the third inner pin A3, the fourth inner pin A4, the fifth inner pin A5 and the sixth inner pin A6. A dummy connecting rib B3 is designed between the second inner pin A2 and the third inner pin A3. The dummy connecting rib B3, the right carrier connecting rib B1 and the fifth inner pin A5 are all connected to the right small carrier. The two wide pins are respectively recorded as the seventh inner pin A7 and the eighth inner pin A8. The seventh inner pin A7, the eighth inner pin A8 and the left carrier connecting rib B2 are all connected to the left small carrier.

8. The lead frame structure unit according to claim 7, characterized in that: The pin width of the wide pin is 3.8 times the pin width of the normal inner pin.

9. The lead frame structure unit according to claim 7, characterized in that: A square groove is provided between the seventh inner lead A7 and the eighth inner lead A8 and the base island.

10. A SOP package, characterized in that: It comprises a lead frame body and a plurality of packages as claimed in any one of claims 1 to 3, wherein a plurality of lead frame units as claimed in any one of claims 7 to 9 are arranged in an array on the lead frame body, the package body corresponds to the lead frame unit one by one, and the outer pins correspond to the inner pins one by one.

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