Display device

Abstract

The display device may include a sub-pixel having a first region and a second region. The sub-pixel may include: a pixel circuit component in the first region and including a transistor on the substrate; and an emission assembly in the second area and including a light emitting element; and first and second electrodes electrically connected to the light emitting element. The transistor may include an active pattern on a substrate, a source electrode connected to a first side of the active pattern, a drain electrode connected to a second side of the active pattern, and a gate electrode on the active pattern. The active pattern, the source electrode, the drain electrode, the first electrode, and the second electrode may be in the same layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0189931, filed with the Korean Intellectual Property Office on December 22, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0004] Recently, with the increasing interest in information display, research and development of display devices have been continuously carried out. Summary of the Invention

[0005] One or more embodiments of the present disclosure are directed to a display device having improved manufacturing efficiency and a method of manufacturing the display device.

[0006] One or more embodiments of the present disclosure may provide a display device including a sub - pixel, the sub - pixel including a first region and a second region. The sub - pixel may include: a pixel circuit component in the first region and including a transistor located on a substrate; and an emission component in the second region and including a light - emitting element and a first electrode and a second electrode electrically connected to the light - emitting element. The transistor may include an active pattern located on the substrate, a source electrode connected to a first side of the active pattern, a drain electrode connected to a second side of the active pattern, and a gate electrode located on the active pattern. The active pattern, the source electrode, the drain electrode, the first electrode, and the second electrode may be provided in the same layer.

[0007] In one or more embodiments, the active pattern may include an intrinsic semiconductor layer. Each of the source electrode, the drain electrode, the first electrode, and the second electrode may include a semiconductor layer containing impurities, the semiconductor layer being conductive.

[0008] In one or more embodiments, the first electrode and the second electrode may be spaced apart from the active pattern, the source electrode, and the drain electrode.

[0009] In one or more embodiments, each of the pixel circuit component and the emission component may have a multi - layer structure. At least one layer of the pixel circuit component and at least one layer of the emission component may be in the same layer.

[0010] In one or more embodiments, a pixel circuit assembly may include a bottom metal layer on a substrate, a first insulating layer on the bottom metal layer, an active pattern on the first insulating layer, source and drain electrodes, a gate electrode on the source electrode, drain electrode, and active pattern, and a source-drain conductive layer on the gate electrode. An emission assembly may include a first alignment electrode and a second alignment electrode on the substrate, a first insulating layer on the first alignment electrode and the second alignment electrode, a light-emitting element on the first insulating layer, a first electrode on the light-emitting element and connected to a first end of the light-emitting element, and a second electrode on the light-emitting element and connected to a second end of the light-emitting element.

[0011] In one or more embodiments, the bottom metal layer, the first alignment electrode, and the second alignment electrode may be in the same layer.

[0012] In one or more embodiments, the first alignment electrode and the second alignment electrode may be floating.

[0013] In one or more embodiments, the second region may include an emission region from which light is emitted and a non-emission region adjacent to the emission region. The emission assembly may include a first bank in the non-emission region and including an opening corresponding to the emission region.

[0014] In one or more embodiments, at least a portion of the first bank may overlap each of the first alignment electrode and the second alignment electrode.

[0015] In one or more embodiments, the sub-pixel may further include a storage capacitor including a lower electrode on the substrate and an upper electrode on the lower electrode and overlapping the lower electrode. The lower electrode may be in the same layer as the active pattern, the source electrode, the drain electrode, and the first and second electrodes.

[0016] In one or more embodiments, the sub-pixel may further include a first power line configured to receive a first driving voltage and a second power line configured to receive a second driving voltage different from the first driving voltage. The first electrode may be electrically connected to the upper electrode, and the second electrode may be electrically connected to the second power line.

[0017] In one or more embodiments, the first electrode may be an anode electrode, and the second electrode may be a cathode electrode.

[0018] In one or more embodiments, the sub-pixel may further include a bottom metal pattern configured by the bottom metal layer. The bottom metal pattern may extend from the first region to the second region.

[0019] In one or more embodiments, in a plan view, the bottom metal pattern may overlap the transistor and the storage capacitor.

[0020] In one or more embodiments, the first power line may include a first vertical power line configured by a bottom metal layer, a first horizontal power line configured by a source-drain conductive layer, and a first dummy power line that overlaps the first vertical power line and is configured by the source-drain conductive layer. The second power line may include a second vertical power line formed by the bottom metal layer, a second horizontal power line formed by the source-drain conductive layer, and a second dummy power line that is integrally formed with the second horizontal power line and extends in a different direction from the second horizontal power line.

[0021] In one or more embodiments, the first vertical power line, the first horizontal power line, and the first dummy power line may be electrically connected to each other. The second vertical power line, the second horizontal power line, and the second dummy power line may be electrically connected to each other.

[0022] In one or more embodiments, the sub-pixel may include: a second bank located above the first bank in the second region; a color conversion layer surrounded by the second bank and located above the light-emitting element; and a color filter located on the color conversion layer.

[0023] In one or more embodiments, the sub-pixel may further include: an insulating pattern in the second region and located on the remaining portion of the light-emitting element except for the opposite ends of the light-emitting element.

[0024] One or more embodiments of the present disclosure may provide a method of manufacturing a display device, including forming a sub-pixel including a first region and a second region on a substrate. Forming the sub-pixel may include: forming a bottom metal layer on the substrate in the first region; forming a first alignment electrode and a second alignment electrode on the substrate in the second region; forming an insulating layer on the bottom metal layer, the first alignment electrode, and the second alignment electrode; aligning a light-emitting element on the insulating layer in the second region; forming a transistor on the insulating layer in the first region, and forming a first electrode and a second electrode on the light-emitting element in the second region; and forming a connection pattern on the transistor, the connection pattern being electrically connected to the transistor and configured by a source-drain conductive layer. The transistor may include an active pattern located on the insulating layer, a source electrode connected to a first side of the active pattern, a drain electrode connected to a second side of the active pattern, and a gate electrode located on the active pattern. The active pattern, the source electrode, the drain electrode, the first electrode, and the second electrode may be in the same layer.

[0025] In one or more embodiments, the active pattern may include an intrinsic semiconductor layer. Each of the source electrode, the drain electrode, the first electrode, and the second electrode may include a semiconductor layer containing impurities and have conductivity. Description of the Drawings

[0026] Figure 1is a schematic perspective view showing a light-emitting element according to one or more embodiments.

[0027] Figure 2 is showing Figure 1 a schematic cross-sectional view of the light-emitting element.

[0028] Figure 3 is a schematic plan view showing a display device according to one or more embodiments.

[0029] Figure 4 is showing Figure 3 a schematic cross-sectional view of the display panel.

[0030] Figure 5 is a schematic circuit diagram showing the electrical connection relationship of components included in each of the pixels shown in Figure 3 the above.

[0031] Figure 6 is a schematic plan view showing a pixel according to one or more embodiments.

[0032] Figure 7 is showing Figure 6 a schematic plan view of the first sub-pixel.

[0033] Figure 8 is only showing Figure 6 a schematic plan view of the components included in the first conductive layer of the pixel.

[0034] Figure 9A is showing Figure 6 a schematic plan view of the alignment electrode, light-emitting element, and first bank in the pixel.

[0035] Figure 9B is showing Figure 9A a schematic plan view of the alignment line before removing the portion of the alignment electrode in the above.

[0036] Figure 10 is showing Figure 6 a schematic plan view of the transistor, first electrode, and second electrode in the pixel.

[0037] Figure 11 is only showing Figure 6 a schematic plan view of the components included in the fourth conductive layer of the pixel.

[0038] Figure 12 is a schematic cross-sectional view taken along line I-I' of Figure 7 the above.

[0039] Figure 13 is a schematic cross-sectional view taken along line II-II' of Figure 7 the above.

[0040] Figures 14 to 22 is a diagram for describing a method of manufacturing a first sub-pixel according to one or more embodiments, and is a schematic cross-sectional view corresponding to line I-I' of Figure 7 .

[0041] Figure 23 shows a first sub-pixel according to one or more embodiments, and is a schematic cross-sectional view corresponding to line I-I' of Figure 7 . DETAILED DESCRIPTION

[0042] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a specific practice mode, and it should be understood that all changes, equivalents, and alternatives that do not depart from the technical scope of the present disclosure are included in the present disclosure.

[0043] Throughout the present disclosure, like reference numerals refer to like components throughout the various drawings and embodiments of the present disclosure. For the sake of clarity, the dimensions of the elements in the drawings may be exaggerated. It will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0044] It will also be understood that when used in the present disclosure, terms such as "comprising", "including", "having", etc. specify the presence of the stated aspects, wholes, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other aspects, wholes, steps, operations, elements, components, and / or combinations thereof. Further, in a case where a first portion of, for example, a layer, film, region, or plate is located on a second portion, the first portion may not only be directly located on the second portion, but also a third portion may be interposed therebetween. Further, in a case where a first portion of, for example, a layer, film, region, or plate is formed on a second portion, the surface of the second portion on which the first portion is formed is not limited to the upper surface of the second portion, but may include other surfaces of the second portion such as side surfaces or lower surfaces. Conversely, in a case where a first portion of, for example, a layer, film, region, or plate is under a second portion, the first portion may not only be directly under the second portion, but also a third portion may be interposed therebetween.

[0045] It will be understood that when an element (e.g., a first element) is referred to as being (operatively or communicatively) "coupled" / "coupled to" / "connected" / "connected to" another element (e.g., a second element), the first element may be directly coupled or directly connected / directly coupled to or directly connected to the second element, or may be coupled or connected / coupled to or connected to the second element via another element (e.g., a third element). Conversely, it will be understood that when an element (e.g., a first element) is referred to as being "directly coupled" / "directly coupled to" / "directly connected" / "directly connected to" another element (e.g., a second element), no other element (e.g., a third element) is interposed between the element and the other element.

[0046] Embodiments and desired details of the present disclosure are described with reference to the accompanying drawings in order to describe the present disclosure in detail such that those of ordinary skill in the art to which the present disclosure pertains may practice the present disclosure. In addition, the singular form may include the plural form as long as it is not specifically mentioned in the sentence.

[0047] Figure 1 is a schematic perspective view showing a light-emitting element LD according to one or more embodiments. Figure 2 is showing Figure 1 a schematic cross-sectional view of the light-emitting element LD.

[0048] Referring to Figure 1 and Figure 2 , the light-emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may be implemented as an emission stack (or referred to as a "stack pattern") formed by continuously stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. The type and / or shape of the light-emitting element LD are not limited to Figure 1 the type and / or shape of the embodiments shown in

[0049] The light-emitting element LD may be formed in a shape extending in one direction. If the direction in which the light-emitting element LD extends is defined as the longitudinal direction, the light-emitting element LD may have a first end EP1 and a second end EP2 that are opposite to each other along the longitudinal direction. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be located at the first end EP1 of the light-emitting element LD, and the other semiconductor layer of the first semiconductor layer 11 and the second semiconductor layer 13 may be located at the second end EP2 of the light-emitting element LD. For example, the second semiconductor layer 13 may be located at the first end EP1 of the light-emitting element LD, and the first semiconductor layer 11 may be located at the second end EP2 of the light-emitting element LD.

[0050] The light-emitting element LD may be provided in various shapes. For example, as Figure 1 shown, the light-emitting element LD may have a rod shape, a bar shape, or a column shape that is long with respect to the longitudinal direction (for example, having an aspect ratio greater than 1). Optionally, the light-emitting element LD may have a rod shape, a bar shape, and / or a column shape that is short with respect to the longitudinal direction (for example, having an aspect ratio less than 1). As another alternative, the light-emitting element LD may have a rod shape, a bar shape, and / or a column shape with an aspect ratio of 1.

[0051] The light-emitting element LD may include a light-emitting diode (LED) manufactured to have ultra-small dimensions (for example, having a diameter D and / or a length L corresponding to a range from the nano-scale (or nanoscale) to the micro-scale (or microscale)).

[0052] When the light-emitting element LD is long with respect to the longitudinal direction (for example, having an aspect ratio greater than 1), the range of the diameter D of the light-emitting element LD may be approximately from about 0.5 μm to about 6 μm, and the range of the length L of the light-emitting element LD may be approximately from about 1 μm to about 10 μm. However, the diameter D and the length L of the light-emitting element LD are not limited thereto. The dimensions of the light-emitting element LD may be changed to meet the requirements (or design conditions) of the lighting device or the self-emitting display device to which the light-emitting element LD is applied.

[0053] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include an n-type semiconductor layer including at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductive dopant (or n-type dopant) such as Si, Ge, and / or Sn. However, the constituent material of the first semiconductor layer 11 is not limited thereto, and various other materials may be used to form the first semiconductor layer 11. The active layer 12 may be located on the first semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. For example, in the case where the active layer 12 has a multi-quantum well structure, the active layer 12 may be formed by periodically repeating the stacking of a barrier layer, a strain-enhanced layer, and / or a well layer as a unit. However, the structure of the active layer 12 is not limited to the structure of the foregoing embodiments.

[0054] The active layer 12 may emit light having a wavelength ranging from 400 nm to 900 nm and have a double heterostructure. In one or more embodiments, a cladding layer doped with a conductive dopant may be formed above or below the active layer 12 along the longitudinal direction of the light-emitting element LD. For example, the cladding layer may be formed of an AlGaN layer and / or an InAlGaN layer. In one or more embodiments, materials such as AlGaN and / or InAlGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0055] If an electric field having a certain voltage or higher voltage is applied to opposite ends of the light-emitting element LD, the light-emitting element LD may emit light through the recombination of electron-hole pairs in the active layer 12. Since the light emission of the light-emitting element LD can be controlled based on the foregoing aspects, the light-emitting element LD can be used as a light source (e.g., a light-emitting source) of various light-emitting devices and a pixel of a display device.

[0056] The second semiconductor layer 13 may be located on the second surface of the active layer 12 and include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer including at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant (or p-type dopant) such as Mg, Zn, Ca, Sr, and / or Ba. However, the material used to form the second semiconductor layer 13 is not limited thereto, and various other materials may be used to form the second semiconductor layer 13.

[0057] The first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses in the longitudinal direction of the light-emitting element LD. For example, with respect to the longitudinal direction of the light-emitting element LD, the first semiconductor layer 11 may have a thickness greater than that of the second semiconductor layer 13. Accordingly, the active layer 12 of the light-emitting element LD may be located at a position closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11.

[0058] Although Figure 1 and Figure 2 it is shown that each of the first semiconductor layer 11 and the second semiconductor layer 13 is formed of a single layer, the present disclosure is not limited thereto. In one or more embodiments, depending on the material of the active layer 12, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include at least one or more layers, such as a cladding layer and / or a tensile strain barrier reduction (TSBR) layer. The TSBR layer may be a strain relaxation layer located between semiconductor layers having different lattice structures and may thus be used as a buffer layer to reduce the difference in lattice constants. Although the TSBR layer may be formed of a p-type semiconductor layer such as p-GaInP, p-AlInP, or p-AlGaInP, the present disclosure is not limited thereto.

[0059] In one or more embodiments, in addition to including the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light-emitting element LD may further include a contact electrode (hereinafter referred to as the "first contact electrode") located above the second semiconductor layer 13. Further, in one or more embodiments, the light-emitting element LD may further include an additional contact electrode (hereinafter referred to as the "second contact electrode") located at one end of the first semiconductor layer 11.

[0060] Each of the first contact electrode and the second contact electrode may be an ohmic contact electrode, but the present disclosure is not limited thereto. In one or more embodiments, each of the first contact electrode and the second contact electrode may be a Schottky contact electrode. The first contact electrode and the second contact electrode may include a conductive material. For example, the first contact electrode and the second contact electrode may include an opaque metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni) used alone or in combination and / or their oxides or alloys, but the present disclosure is not limited thereto. In one or more embodiments, the first contact electrode and the second contact electrode may further include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), and / or indium tin zinc oxide (ITZO). Here, zinc oxide (ZnO x ) may be zinc oxide (ZnO) and / or zinc peroxide (ZnO2).

[0061] The materials included in the first contact electrode and the second contact electrode may be the same as or different from each other. The first contact electrode and the second contact electrode may be substantially transparent or translucent.

[0062] In one or more embodiments, the light-emitting element LD may further include an insulating layer 14. However, according to the embodiment, the insulating layer 14 may be omitted, or may be provided to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0063] The insulating layer 14 can prevent a short circuit of the active layer 12 caused by contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, the insulating layer 14 can reduce or minimize surface defects of the light-emitting element LD, thereby improving the lifespan and emission efficiency of the light-emitting element LD. In the case where a plurality of light-emitting elements LD are positioned in close contact with each other, the insulating layer 14 can prevent an undesired short circuit from occurring between the light-emitting elements LD. The presence or absence of the insulating layer 14 is not limited as long as it can prevent the active layer 12 from short-circuiting with an external conductive material.

[0064] The insulating layer 14 may be provided to surround the entire outer surface (e.g., the entire outer peripheral surface or circumferential surface) of the emission stack including the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0065] Although in the foregoing embodiments, the insulating layer 14 is described as surrounding the entire outer surface (e.g., the outer peripheral surface or circumferential surface) of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the present disclosure is not limited thereto. In one or more embodiments, in the case where the light-emitting element LD includes a first contact electrode, the insulating layer 14 may surround the entire outer surfaces (e.g., the outer peripheral surfaces or circumferential surfaces) of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first contact electrode. In one or more embodiments, the insulating layer 14 may not surround the entire outer surface (e.g., the outer peripheral surface or circumferential surface) of the first semiconductor layer 11, or may surround only a part of the outer surface (e.g., the outer peripheral surface or circumferential surface) of the first semiconductor layer 11 and not surround another part of the outer surface (e.g., the outer peripheral surface or circumferential surface) of the first semiconductor layer 11. In addition, in one or more embodiments, in the case where the first contact electrode is located at the first end EP1 of the light-emitting element LD and the second contact electrode is located at the second end EP2 of the light-emitting element LD, the insulating layer 14 allows at least one region of each of the first contact electrode and the second contact electrode to be exposed.

[0066] The insulating layer 14 may include a transparent insulating material. Various materials having insulating properties may be used as the material of the insulating layer 14.

[0067] The insulating layer 14 may have a single-layer structure or a multi-layer structure including a double-layer structure. For example, in the case where the insulating layer 14 is formed of a double-layer structure including a first layer and a second layer stacked successively, the first layer and the second layer may be made of different materials (or substances) and may be formed by different processes. According to an embodiment, the first layer and the second layer may include the same material and may be formed by a continuous process.

[0068] In one or more embodiments, the light-emitting element LD may be implemented as a light-emitting pattern having a core-shell structure.

[0069] The light-emitting element LD may be used as a light source for various display devices. The light-emitting element LD may be manufactured by a surface treatment process.

[0070] The emission assembly including the above-described light-emitting element LD may be used not only in a display device but also in various electronic devices that require a light source.

[0071] Figure 3 is a schematic plan view showing a display device DD according to one or more embodiments. Figure 4 is showing Figure 3 a schematic cross-sectional view of the display panel DP.

[0072] In Figure 3 and Figure 4 for convenience, the display device DD is exemplarily shown centered on the display area DA for displaying an image, for example, the structure of the display panel DP provided in the display device DD is shown.

[0073] Referring to Figures 1 to 4 , the display device DD may include a substrate SUB, pixels PXL provided on the substrate SUB and each including at least one light-emitting element LD, a driver provided on the substrate SUB and configured to drive the pixels PXL, and / or a line assembly provided to connect the pixels PXL to the driver.

[0074] The display device DD may be classified into a passive matrix type display device and / or an active matrix type display device according to the method of driving the light-emitting element LD. For example, in the case where the display device DD is implemented as an active matrix type, each of the pixels PXL may include a driving transistor configured to control the amount of current to be provided to the light-emitting element LD and a switching transistor configured to transmit a data signal to the driving transistor.

[0075] The display panel DP (or display device DD) may include a substrate SUB and pixels PXL disposed on the substrate SUB. Each of the pixels PXL may include at least one light-emitting element LD.

[0076] The substrate SUB may include a transparent insulating material that allows light transmission. The substrate SUB may be a rigid substrate and / or a flexible substrate.

[0077] For example, the rigid substrate may be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystallized glass substrate.

[0078] The flexible substrate may be a film substrate or a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of the following: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate.

[0079] An area on the substrate SUB may be provided as a display area DA in which the pixels PXL are located, and another area on the substrate SUB may be provided as a non-display area NDA. For example, the substrate SUB may include a display area DA and a non-display area NDA. The display area DA includes a plurality of pixel areas PXA on which the corresponding pixels PXL are located, and the non-display area NDA is located around the edge or outer edge of the display area DA (or adjacent to the display area DA).

[0080] The non-display area NDA may be provided on at least one side of the display area DA. The non-display area NDA may surround the outer edge (or edge) of the display area DA. In the non-display area NDA, a part of a line assembly connected to the pixels PXL and a driver connected to the line assembly and configured to drive the pixels PXL may be provided.

[0081] The non-display area NDA may be an area in which certain lines (e.g., fan-out lines LP), pads PD, and / or internal circuit components electrically connected to the pixels PXL are provided to drive the pixels PXL.

[0082] In one or more embodiments, the non-display area NDA may include a fan-out area FTA and a pad area PDA.

[0083] The pad region PDA can be a region of the non-display region NDA where the pad assembly PDP is located, and can be positioned at a location closest to the outer edge (or margin) of the non-display region NDA. The fan-out region FTA can be another region of the non-display region NDA where the fan-out lines LP, which are part of the line assembly, are located, and can be positioned adjacent to the display region DA within the non-display region NDA. For example, the fan-out region FTA can be a region of the non-display region NDA that is located between the pad region PDA and the display region DA. In one or more embodiments, the non-display region NDA can include an antistatic circuit region where an antistatic circuit is located, the antistatic circuit being electrically connected to a signal line located in the display region DA and configured to prevent the occurrence of static electricity. The antistatic circuit region can be a region of the non-display region NDA between the display region DA and the fan-out region FTA, but is not limited thereto.

[0084] The pad assembly PDP can be located in the pad region PDA. The fan-out lines LP, which are part of the line assembly, can be located in the fan-out region FTA.

[0085] The fan-out lines LP can be electrically connected to the pixels PXL such that certain signals applied from the driver can be transmitted to the pixels PXL. The fan-out lines LP can be located in the fan-out region FTA and electrically connect the driver to the pixels PXL.

[0086] The pad assembly PDP can include a plurality of pads PD. The pads PD can provide (or transmit) driving power voltages and signals for driving the pixels PXL and / or internal circuits provided in the display region DA. In one or more embodiments, when the driver is mounted in the non-display region NDA of the substrate SUB, the pad assembly PDP can overlap with the output pads of the driver and can be provided with signals output from the driver.

[0087] Each of the pixels PXL can be located in the pixel region PXA. In one or more embodiments, the pixels PXL can be arranged in a stripe arrangement or the like in the display region DA, but the present disclosure is not limited thereto.

[0088] Each of the pixels PXL can include a pixel circuit layer PCL, a display element layer DPL, and a packaging layer ENC located on the substrate SUB.

[0089] A pixel circuit provided on the substrate SUB and including a plurality of transistors (refer to Figure 5The "PXC"), the signal line electrically connected to the transistor, and the plurality of insulating layers may be located in the pixel circuit layer PCL (or pixel circuit assembly). Each of the transistors has a structure in which, for example, a semiconductor pattern, a gate electrode, a first terminal, and a second terminal are successively stacked and an insulating layer is interposed therebetween. The semiconductor pattern may include amorphous silicon, polysilicon, low-temperature polysilicon, and / or an organic semiconductor and / or an oxide semiconductor. Although each of the gate electrode, the first terminal (or source electrode), and the second terminal (or drain electrode) may include one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), the present disclosure is not limited thereto.

[0090] The display element layer DPL may include a light-emitting element layer LDL and an optical layer LCL.

[0091] The light-emitting element layer LDL (or emission assembly) may be located on the substrate SUB. In one or more embodiments, the light-emitting element layer LDL may be on the same surface as the pixel circuit layer PCL and may be spaced apart from the pixel circuit layer PCL without overlapping the pixel circuit layer PCL. The emission assembly (refer to Figure 5 the "EMU") including the light-emitting element LD configured to emit light may be located in the light-emitting element layer LDL. The first electrode (refer to Figure 5 the "PE1") and the second electrode (refer to Figure 5 the "PE2") electrically connected to the light-emitting element LD may be located in the emission assembly EMU.

[0092] The optical layer LCL may convert the light emitted from the light-emitting element layer LDL and traveling in the upward direction (or third direction DR3) of the substrate SUB into light having excellent color reproducibility, and then emit the converted light. The optical layer LCL may include a color filter layer and a color conversion layer.

[0093] The encapsulation layer ENC may be located on the display element layer DPL (or optical layer LCL). The encapsulation layer ENC may reduce the step difference caused by the components located thereunder (e.g., the optical layer LCL), and may prevent external air, water, etc. from penetrating the display element layer DPL. The encapsulation layer ENC may include a material capable of absorbing and / or blocking light to prevent external light from being introduced into the display element layer DPL. For example, the encapsulation layer ENC may include a black matrix, but is not limited thereto.

[0094] Figure 5 is a schematic circuit diagram showing Figure 3 the electrical connection relationship of the components included in each of the pixels PXL shown in

[0095] For example, Figure 5Shows the electrical connection relationship of components included in a pixel PXL that can be applied to an active matrix display device. Here, the connection relationship of the components of each pixel PXL is not limited to this.

[0096] For ease of description, Figure 5 Shows a pixel PXL (or sub-pixel) located at the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj, where i and j are natural numbers greater than 0.

[0097] Referring Figures 1 to 5 , the pixel PXL (or sub-pixel) may include an emission component EMU (or emission unit) configured to generate light having a luminance corresponding to a data signal. In addition, the pixel PXL may optionally further include a pixel circuit PXC (or pixel circuit component) configured to drive the emission component EMU.

[0098] In one or more embodiments, the emission component EMU may include a plurality of light-emitting elements LD connected in parallel between a first power line PL1 to which a first driving voltage VDD is applied and a second power line PL2 to which a second driving voltage VSS is applied. For example, the emission component EMU may include a first electrode PE1 (or first pixel electrode) connected to the pixel circuit PXC and the first power line PL1, a second electrode PE2 (or second pixel electrode) connected to the second power line PL2 to receive the second driving voltage VSS, and a plurality of light-emitting elements LD connected in parallel to each other in the same direction between the first pixel electrode and the second pixel electrode. In one or more embodiments, the first electrode PE1 may be an anode, and the second electrode PE2 may be a cathode.

[0099] The first driving voltage VDD and the second driving voltage VSS may have different potentials. Here, during the emission period of the pixel PXL, the potential difference between the first driving voltage VDD and the second driving voltage VSS may be set to be equal to or greater than the threshold voltage of the light-emitting element LD.

[0100] Each of the light-emitting elements LD may include a first end EP1 (e.g., p-type end) connected to at least one electrode (e.g., the first electrode PE1) and the pixel circuit PXC and / or the first power line PL1, and a second end EP2 (e.g., n-type end) connected to at least one additional electrode (e.g., the second electrode PE2) and the second power line PL2. In other words, the light-emitting element LD may be connected in the forward direction between the first driving voltage (power supply) VDD and the second driving voltage (power supply) VSS. The light-emitting element LD connected in the forward direction may form an effective light source of the emission component EMU.

[0101] The light-emitting element LD of the emission assembly EMU can emit light having a luminance corresponding to the drive current supplied thereto through the pixel circuit PXC. For example, during each frame period, a drive current corresponding to the gray-scale value of the corresponding frame data of the pixel circuit PXC can be supplied to the emission assembly EMU. The drive current supplied to the emission assembly EMU can be divided into a plurality of portions flowing into the respective light-emitting elements LD. Accordingly, each of the light-emitting elements LD can emit light having a luminance corresponding to the current applied thereto, such that the emission assembly EMU can emit light having a luminance corresponding to the drive current.

[0102] Although embodiments in which the opposite ends EP1 and EP2 of the light-emitting element LD are connected in the same direction between the first drive voltage (power supply) VDD and the second drive voltage (power supply) VSS have been described, the present disclosure is not limited thereto. In one or more embodiments, in addition to including the light-emitting element LD forming the respective effective light sources, the emission assembly EMU may further include at least one ineffective light source (e.g., a reverse light-emitting element LDr). The reverse light-emitting element LDr and the light-emitting element LD forming the effective light source may be connected in parallel with each other between the first electrode PE1 and the second electrode PE2. Here, the reverse light-emitting element LDr may be connected between the first electrode PE1 and the second electrode PE2 in a direction opposite to that of the light-emitting element LD. Even when a drive voltage (e.g., a forward drive voltage) is applied between the first electrode PE1 and the second electrode PE2, the reverse light-emitting element LDr remains disabled. Accordingly, current substantially does not flow through the reverse light-emitting element LDr.

[0103] In the case where the pixel PXL is located on the i-th pixel row and the j-th pixel column in the display area DA, the pixel circuit PXC of the pixel PXL can be electrically connected to the i-th scan line Si and the j-th data line Dj. In addition, the pixel circuit PXC can be electrically connected to the i-th control line CLi and the j-th sensing line SENj.

[0104] The pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst.

[0105] The first transistor T1 may be a driving transistor configured to control a driving current to be applied to the emission assembly EMU, and may be connected between a first driving power supply VDD and the emission assembly EMU. Specifically, a first terminal of the first transistor T1 may be electrically connected to a first power line PL1. A second terminal of the first transistor T1 may be electrically connected to a second node N2. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 may control an amount of driving current to be applied from the first power line PL1 to the emission assembly EMU through the second node N2 in response to a voltage applied to the first node N1. In one or more embodiments, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode, and the present disclosure is not limited thereto. In one or more embodiments, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0106] The second transistor T2 may be a switching transistor configured to select and activate a pixel PXL in response to a scan signal, and may be electrically connected between a j-th data line Dj and the first node N1. A first terminal of the second transistor T2 may be electrically connected to the j-th data line Dj. A second terminal of the second transistor T2 may be electrically connected to the first node N1. A gate electrode of the second transistor T2 may be electrically connected to an i-th scan line Si. The first terminal and the second terminal of the second transistor T2 are different terminals, and for example, if the first terminal is a drain electrode, the second terminal may be a source electrode.

[0107] In a case where a scan signal providing a gate conduction voltage (e.g., a high-level voltage) is provided from the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the j-th data line Dj to the first node N1. The first node N1 may be a point where the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are electrically connected to each other. The second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0108] The third transistor T3 can obtain a sensing signal through the j-th sensing line SENj by electrically connecting the first transistor T1 to the j-th sensing line SENj, and can use the sensing signal to detect characteristics of the pixel PXL such as the threshold voltage of the first transistor T1. Information about the characteristics of the pixel PXL can be used to convert image data, thereby compensating for characteristic deviations between pixels PXL. The second terminal of the third transistor T3 can be electrically connected to the second terminal of the first transistor T1. The first terminal of the third transistor T3 can be electrically connected to the j-th sensing line SENj. The gate electrode of the third transistor T3 can be electrically connected to the i-th control line CLi. In addition, the first terminal of the third transistor T3 can be electrically connected to an initialization power line to which an initialization voltage is applied. The third transistor T3 can be an initialization transistor configured to initialize the second node N2, and can be turned on when a sensing control signal is provided thereto from the i-th control line CLi, thereby transmitting the initialization voltage to the second node N2.

[0109] The storage capacitor Cst can include a lower electrode LE (or first capacitor electrode) and an upper electrode UE (or second capacitor electrode). The lower electrode LE of the storage capacitor Cst can be electrically connected to the first node N1. The upper electrode UE of the storage capacitor Cst can be electrically connected to the second node N2. The storage capacitor Cst can be charged with a data voltage corresponding to a data signal to be provided to the first node N1 during one frame period.

[0110] Figure 6 is a schematic plan view showing a pixel PXL according to one or more embodiments. Figure 7 is a schematic plan view showing Figure 6 the first sub-pixel SPX1 of Figure 8 is a schematic plan view showing only Figure 6 the components included in the first conductive layer C1 in the pixel PXL of Figure 9A is a schematic plan view showing Figure 6 the alignment electrode ALE, the light-emitting element LD, and the first bank BNK1 in the pixel PXL of Figure 9B is a schematic plan view showing the alignment line before removing the portion of the alignment electrode in Figure 9A Figure 10 is a schematic plan view showing Figure 6 the transistor, the first electrode PE1, and the second electrode PE2 in the pixel PXL of Figure 11 is a schematic plan view showing only Figure 6 the components included in the fourth conductive layer C4 in the pixel PXL of

[0111] In Figures 6 to 11In the definition of the term "pixel PXL", it may include not only the components included in the pixel PXL, but also the region in which the components are disposed (or located).

[0112] Reference Figures 1 to 11 , according to one or more embodiments, the pixel PXL may be located in the pixel region PXA. The pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0113] The first sub-pixel SPX1 may be located in the first sub-pixel region SPXA1 of the pixel region PXA. The second sub-pixel SPX2 may be located in the second sub-pixel region SPXA2 of the pixel region PXA. The third sub-pixel SPX3 may be located in the third sub-pixel region SPXA3 of the pixel region PXA.

[0114] Each of the first sub-pixel region SPXA1 to the third sub-pixel region SPXA3 may include a first region A1 and a second region A2. For example, each of the first sub-pixel region SPXA1 to the third sub-pixel region SPXA3 may include a first region A1 and a second region A2 that are separated from each other in the second direction DR2. The pixel circuit PXC (or pixel circuit components) of each of the first sub-pixel SPX1 to the third sub-pixel SPX3 may be located in the first region A1. The emission component EMU of each of the first sub-pixel SPX1 to the third sub-pixel SPX3 may be located in the second region A2. In addition, the second region A2 in which the emission component EMU is located may include the emission region of the corresponding sub-pixel. For example, the second region A2 of the first sub-pixel SPX1 may include a first emission region EMA1. The second region A2 of the second sub-pixel SPX2 may include a second emission region EMA2. The second region A2 of the third sub-pixel SPX3 may include a third emission region EMA3.

[0115] The pixel region PXA may include a non-emission region NEA adjacent to (or located around) the first emission region EMA1, a non-emission region NEA adjacent to (or located around the edge or outer edge of) the second emission region EMA2, and a non-emission region NEA adjacent to (or located around) the third emission region EMA3.

[0116] The signal lines electrically connected to the pixel circuit PXC of each of the first sub-pixel SPX1 to the third sub-pixel SPX3 may be located in the pixel region PXA. For example, the initialization power line IPL, the data lines D1, D2, and D3, the power line PL, the scan line SC, etc. may be located in the pixel region PXA, but the present disclosure is not limited thereto.

[0117] The scan line SC can be selectively provided with a scan signal and a sensing control signal. The scan line SC can extend in the first direction DR1. The scan line SC can be configured by a fourth conductive layer C4. The fourth conductive layer C4 (or source-drain conductive layer) can be formed as a single-layer or multi-layer structure formed of molybdenum, copper, aluminum, chromium, gold, silver, titanium, nickel, neodymium, indium, tin, and / or their oxides and / or their alloys.

[0118] The scan line SC can be electrically connected to a second transistor T2 in a pixel circuit PXC included in each of the first sub-pixel SPX1 to the third sub-pixel SPX3. For example, the scan line SC can be electrically connected to a second gate electrode GE2 of the second transistor T2 in each of the first sub-pixel SPX1 to the third sub-pixel SPX3 through a corresponding contact hole CH. In addition, the scan line SC can be electrically connected to a third transistor T3 in a pixel circuit PXC included in each of the first sub-pixel SPX1 to the third sub-pixel SPX3. For example, the scan line SC can be electrically connected to a third gate electrode GE3 of the third transistor T3 in each of the first sub-pixel SPX1 to the third sub-pixel SPX3 through a corresponding contact hole CH.

[0119] The second gate electrode GE2 and the third gate electrode GE3 can be configured by a third conductive layer C3. The third conductive layer C3 (or gate conductive layer) can include the same material as the fourth conductive layer C4, or can include one or more suitable (or selected) materials from the constituent materials exemplified for the fourth conductive layer C4, but the present disclosure is not limited thereto.

[0120] The scan line SC can provide a scan signal to the second transistor T2 of the pixel circuit PXC in each of the first sub-pixel SPX1 to the third sub-pixel SPX3 during the driving period of the light-emitting element LD, and can provide a sensing control signal to the third transistor T3 of the pixel circuit PXC during the sensing period.

[0121] The data lines D1, D2, and D3 can include a first data line D1, a second data line D2, and a third data line D3 that extend in a second direction DR2 and are arranged along the first direction DR1. A data signal can be applied to each of the first data line D1, the second data line D2, and the third data line D3.

[0122] The first data line D1 can be electrically connected to the second transistor T2 of the pixel circuit PXC of the first sub-pixel SPX1. The second data line D2 can be electrically connected to the second transistor T2 of the pixel circuit PXC of the second sub-pixel SPX2. The third data line D3 can be electrically connected to the second transistor T2 of the pixel circuit PXC of the third sub-pixel SPX3. Each of the first data line D1, the second data line D2, and the third data line D3 can be formed of the first conductive layer C1. The first conductive layer C1 (or the bottom metal layer) can include the same material as that of the fourth conductive layer C4, or can include one or more suitable materials from the constituent materials exemplified as the fourth conductive layer C4, but the present disclosure is not limited thereto.

[0123] The power line PL can include a first power line PL1 and a second power line PL2.

[0124] The first power line PL1 can be supplied with a first driving voltage VDD. The first power line PL1 can include a first vertical power line PL1a, a first horizontal power line PL1b, and a first dummy power line PL1c.

[0125] The first vertical power line PL1a can extend in the second direction DR2 and can be formed of the first conductive layer C1. The first horizontal power line PL1b can extend in the first direction DR1 and can be formed of the fourth conductive layer C4. The first dummy power line PL1c can be formed of the fourth conductive layer C4 and can overlap with the first vertical power line PL1a.

[0126] The first vertical power line PL1a formed of the first conductive layer C1 and the first dummy power line PL1c formed of the fourth conductive layer C4 can be electrically connected to each other through corresponding contact holes. In one or more embodiments, the first vertical power line PL1a and the first horizontal power line PL1b can be electrically connected to each other. The mutually electrically connected first vertical power line PL1a, first horizontal power line PL1b, and first dummy power line PL1c can have a grid structure in the pixel region PXA.

[0127] The first dummy power line PL1c can be electrically connected to a first additional conductive pattern ACP1 located in a different layer through a corresponding contact hole CH. The first additional conductive pattern ACP1 can be formed of the third conductive layer C3 and extends in the second direction DR2 to overlap with the first dummy power line PL1c. The first dummy power line PL1c can be electrically connected to a first additional conductive pattern ACP1 located in a different layer through a corresponding contact CNT. In addition, the first additional conductive pattern ACP1 can be electrically connected to the first vertical power line PL1a formed of the first conductive layer C1 through a corresponding contact CNT.

[0128] In a plan view, the first vertical power line PL1a, the first additional conductive pattern ACP1, and the first dummy power line PL1c may overlap with each other. Since the first vertical power line PL1a formed by the first conductive layer C1, the first additional conductive pattern ACP1 formed by the third conductive layer C3, and the first dummy power line PL1c formed by the fourth conductive layer C4 are electrically connected to each other, the line resistance of the first power line PL1 can be reduced.

[0129] The second power line PL2 may be supplied with a second driving voltage VSS. The second power line PL2 may include a second vertical power line PL2a, a second horizontal power line PL2b, and a second dummy power line PL2c.

[0130] The second vertical power line PL2a may extend in the second direction DR2 and may be formed by the first conductive layer C1. The second horizontal power line PL2b may extend in the first direction DR1 and may be formed by the fourth conductive layer C4. The second dummy power line PL2c may be formed by the fourth conductive layer C4, may extend in the second direction DR2, and may overlap with the second vertical power line PL2a. The second dummy power line PL2c may be a region of the second horizontal power line PL2b. In one or more embodiments, the second horizontal power line PL2b may be arranged in a shape extending (or protruding) from the second dummy power line PL2c in the first direction DR1.

[0131] The second vertical power line PL2a formed by the first conductive layer C1 and the second dummy power line PL2c (or the second horizontal power line PL2b) formed by the fourth conductive layer C4 may be electrically connected to each other through corresponding contact holes CH. Accordingly, the second vertical power line PL2a, the second dummy power line PL2c, and the second horizontal power line PL2b may be electrically connected to each other. The second vertical power line PL2a, the second horizontal power line PL2b, and the second dummy power line PL2c that are electrically connected to each other may have a grid structure.

[0132] The second dummy power line PL2c may be electrically connected through a corresponding contact hole CH to a second additional conductive pattern ACP2 located in a different layer. The second additional conductive pattern ACP2 may be formed by the third conductive layer C3 and extends in the second direction DR2 to overlap with the second dummy power line PL2c. Since the second dummy power line PL2c is electrically connected to the second additional conductive pattern ACP2 located in a different layer, the line resistance of the second dummy power line PL2c can be reduced.

[0133] The second vertical power line PL2a can be electrically connected to a third additional conductive pattern ACP3 located in a different layer through a corresponding contact CNT. The third additional conductive pattern ACP3 can be formed by a third conductive layer C3 and can overlap with a part of the second vertical power line PL2a. The third additional conductive pattern ACP3 can be electrically connected to a dummy electrode DME through a corresponding contact hole CH. The dummy electrode DME can be formed by a fourth conductive layer C4 and can overlap with a part of the third additional conductive pattern ACP3 and a region of the second vertical power line PL2a. The dummy electrode DME can be electrically connected to the second vertical power line PL2a through a corresponding contact hole CH. The second vertical power line PL2a can be electrically connected to the third additional conductive pattern ACP3 and the dummy electrode DME located in different layers, thereby forming a multilayer structure (for example, see Figure 13 ). Therefore, the line resistance of the second vertical power line PL2a can be reduced.

[0134] The initialization power line IPL can extend in the second direction DR2. The initialization power line IPL can be located in each of the first sub-pixel region SPXA1 to the third sub-pixel region SPXA3 and can be positioned to be separated from the corresponding data line. The initialization power line IPL can be formed by a first conductive layer C1. The initialization power line IPL can be the j-th sensing line SENj described in Figure 5 . The initialization power line IPL can be provided with an initialization voltage. The initialization power line IPL in each of the first sub-pixel SPX1 to the third sub-pixel SPX3 can be electrically connected to the third transistor T3 of the pixel circuit PXC through a fourth connection pattern CNP4.

[0135] The fourth connection pattern CNP4 can be formed by a fourth conductive layer C4 and can be electrically connected to the initialization power line IPL through a corresponding contact hole CH. The fourth connection pattern CNP4 can be electrically connected to the third transistor T3 of each of the first sub-pixel SPX1 to the third sub-pixel SPX3 through a corresponding contact hole CH.

[0136] The initialization power line IPL, the first data line D1, the second data line D2, the third data line D3, the first vertical power line PL1a, and the second vertical power line PL2a can be located in both the first region A1 and the second region A2.

[0137] Each of the first sub-pixel SPX1 to the third sub-pixel SPX3 can include a pixel circuit PXC. The pixel circuit PXC can include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0138] The pixel circuits PXC of the first sub-pixel SPX1, the pixel circuits PXC of the second sub-pixel SPX2, and the pixel circuits PXC of the third sub-pixel SPX3 may have substantially the same or similar structures. Hereinafter, as a representative example, the pixel circuit PXC of the first sub-pixel SPX1 will be described. The description of the pixel circuit PXC of the first sub-pixel SPX1 will substitute for the descriptions of the pixel circuits PXC of the second sub-pixel SPX2 and the third sub-pixel SPX3.

[0139] The pixel circuit PXC of the first sub-pixel SPX1 may be located in the first region A1 of the first sub-pixel region SPXA1. For example, the first transistor T1 to the third transistor T3 and the storage capacitor Cst may be located in the first region A1 of the first sub-pixel region SPXA1.

[0140] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1 (or a first source region), and a first drain electrode DE1 (or a first drain region).

[0141] The first gate electrode GE1 may be electrically connected to the first connection pattern CNP1 through a contact hole. The first gate electrode GE1 may be formed of a third conductive layer C3.

[0142] The first connection pattern CNP1 may be formed of a fourth conductive layer C4. One end of the first connection pattern CNP1 may be electrically connected to the first gate electrode GE1 through a corresponding contact hole CH. The remaining end of the first connection pattern CNP1 may be electrically connected to the second source electrode SE2 of the second transistor T2 through a corresponding contact hole CH. The first gate electrode GE1 and the second source electrode SE2 may be electrically connected to each other through the first connection pattern CNP1.

[0143] The first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed of a semiconductor layer SCL. For example, the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be configured through a semiconductor layer SCL formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed of an undoped and / or impurity-doped semiconductor layer SCL. For example, each of the first source electrode SE1 and the first drain electrode DE1 may be doped with impurities and have conductivity. The first active pattern ACT1 may be formed of an intrinsic semiconductor layer without doping impurities.

[0144] The first active pattern ACT1 may be located under the first gate electrode GE1 formed of the third conductive layer C3 and may overlap with the first gate electrode GE1. The first active pattern ACT1 may form the channel region of the first transistor T1.

[0145] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. The first source electrode SE1 may be doped with impurities during an impurity doping process performed after forming the third conductive layer C3 and may thus have conductivity. The first source electrode SE1 may be electrically connected to the second connection pattern CNP2 through a corresponding contact hole CH.

[0146] The second connection pattern CNP2 may be formed of the fourth conductive layer C4. A part of the second connection pattern CNP2 may be electrically connected to the first source electrode SE1 through a corresponding contact hole CH. Another part of the second connection pattern CNP2 may be electrically connected to the third source electrode SE3 of the third transistor T3 through a corresponding contact hole CH. Another part of the second connection pattern CNP2 may be electrically connected to the bottom metal pattern BML through a corresponding contact hole CH. The first source electrode SE1, the third source electrode SE3, and the bottom metal pattern BML (e.g., formed of the first conductive layer C1) may be electrically connected to each other through the second connection pattern CNP2.

[0147] In one or more embodiments, the second connection pattern CNP2 may be electrically connected to the emission component EMU of the first sub-pixel SPX1 through a corresponding contact hole CH. For example, the second connection pattern CNP2 may be electrically connected to the first electrode PE1 through a corresponding contact hole CH.

[0148] The bottom metal pattern BML may be formed of the first conductive layer C1. The bottom metal pattern BML may be electrically connected to the second connection pattern CNP2 through a corresponding contact hole CH. The bottom metal pattern BML may be electrically connected to the first source electrode SE1 through the second connection pattern CNP2.

[0149] The bottom metal pattern BML may extend from the first region A1 to the second region A2. In the first region A1, the bottom metal pattern BML may overlap with the first transistor T1. In the second region A2, the bottom metal pattern BML may overlap with the storage capacitor Cst. The bottom metal pattern BML may shield the first transistor T1 and the storage capacitor Cst from its lower side.

[0150] In one or more embodiments, the bottom metal pattern BML positioned in the second region A2 (or extending into the second region A2) may be electrically connected to the upper electrode UE of the storage capacitor Cst through a corresponding contact hole CH. Thus, the bottom metal pattern BML and the upper electrode UE may be provided with the same signal. The bottom metal pattern BML positioned in the second region A2 may overlap with the lower electrode LE of the storage capacitor Cst, thereby further increasing the capacitance of the storage capacitor Cst.

[0151] The first drain electrode DE1 may be connected to the remaining end of the first active pattern ACT1. The first drain electrode DE1 may be electrically connected to the first horizontal power line PL1b through a corresponding contact hole CH.

[0152] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2, and a second drain electrode DE2.

[0153] The second gate electrode GE2 may be electrically connected to the scan line SC through a corresponding contact hole CH. The second gate electrode GE2 may overlap with the second active pattern ACT2.

[0154] Each of the second active pattern ACT2, the second source electrode SE2 (or the second source region), and the second drain electrode DE2 (or the second drain region) may be formed of a semiconductor layer SCL. For example, the second active pattern ACT2, the second source electrode SE2 (or the second source region), and the second drain electrode DE2 (or the second drain region) may be configured through a semiconductor layer SCL formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. Each of the second source electrode SE2 and the second drain electrode DE2 may be doped with impurities and have conductivity. The second active pattern ACT2 may be formed of an intrinsic semiconductor layer not doped with impurities.

[0155] The second active pattern ACT2 may be located under the second gate electrode GE2 formed of the third conductive layer C3 and may overlap with the second gate electrode GE2. The second active pattern ACT2 may form the channel region of the second transistor T2.

[0156] The second source electrode SE2 may be connected to one end of the second active pattern ACT2. The second source electrode SE2 may be doped with impurities during an impurity doping process performed after using a separate mask or using the third conductive layer C3 as a mask, so as to have conductivity. The second source electrode SE2 may be electrically connected to the first connection pattern CNP1 through a corresponding contact hole CH.

[0157] The second drain electrode DE2 may be connected to the remaining end of the second active pattern ACT2. The second drain electrode DE2 may be doped with impurities during an impurity doping process performed after using a separate mask or using the third conductive layer C3 as a mask, so as to have conductivity. The second drain electrode DE2 may be electrically connected to the third connection pattern CNP3 through a corresponding contact hole CH.

[0158] The third connection pattern CNP3 may be formed of the fourth conductive layer C4. One end of the third connection pattern CNP3 may be electrically connected to the second drain electrode DE2 through a corresponding contact hole CH. The remaining end of the third connection pattern CNP3 may be electrically connected to the first data line D1 formed of the first conductive layer C1 through a corresponding contact hole CH. The second drain electrode DE2 and the first data line D1 may be electrically connected to each other through the third connection pattern CNP3.

[0159] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source electrode SE3, and a third drain electrode DE3.

[0160] The third gate electrode GE3 may be electrically connected to the scan line SC through a corresponding contact hole CH. The third gate electrode GE3 may overlap with the third active pattern ACT3 and may be formed of the third conductive layer C3.

[0161] The third active pattern ACT3, the third source electrode SE3 (or the third source region), and the third drain electrode DE3 (or the third drain region) may be formed of the semiconductor layer SCL. For example, the third active pattern ACT3, the third source electrode SE3, and the third drain electrode DE3 may be configured through a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. Each of the third source electrode SE3 and the third drain electrode DE3 may be doped with impurities and have conductivity. The third active pattern ACT3 may be formed of an intrinsic semiconductor layer not doped with impurities.

[0162] The third active pattern ACT3 may be located under the third gate electrode GE3 formed of the third conductive layer C3 and may overlap with the third gate electrode GE3. The third active pattern ACT3 may form the channel region of the third transistor T3.

[0163] The third source electrode SE3 may be connected to one end of the third active pattern ACT3. The third source electrode SE3 may be doped with impurities during an impurity doping process performed after using a separate mask or using the third conductive layer C3 as a mask, thereby having conductivity. The third source electrode SE3 may be electrically connected to the second connection pattern CNP2 through a corresponding contact hole CH.

[0164] The third drain electrode DE3 may be connected to the remaining end of the third active pattern ACT3. The third drain electrode DE3 may be doped with impurities after using a separate mask or using the third conductive layer C3 as a mask, thereby having conductivity. The third drain electrode DE3 may be electrically connected to the fourth connection pattern CNP4 through a corresponding contact hole CH.

[0165] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE.

[0166] The lower electrode LE can be configured to extend from the second source electrode SE2 to the second region A2. In one or more embodiments, the lower electrode LE can be integrally formed with the second source electrode SE2. The lower electrode LE can be configured by a semiconductor layer SCL. For example, the lower electrode LE can be configured by a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc., and can have conductivity after being doped with impurities.

[0167] The upper electrode UE can be formed of a fourth conductive layer C4 and can extend in the second direction DR2 in the second region A2. The upper electrode UE can be positioned to overlap with the lower electrode LE and can be electrically connected to the bottom metal pattern BML through a corresponding contact hole CH. The upper electrode UE can be electrically connected to the first electrode PE1 of the emission assembly EMU through a second connection pattern CNP2 that is electrically connected to the bottom metal pattern BML.

[0168] The emission assembly EMU of each of the first sub-pixel SPX1 to the third sub-pixel SPX3 can include a light-emitting element LD located in the second region A2 of the corresponding sub-pixel. In addition, the emission assembly EMU can include an electrode PE (or pixel electrode) electrically connected to the light-emitting element LD and an alignment electrode ALE overlapping with the light-emitting element LD. The first bank BNK1 can be located in the non-emission region NEA of each of the first sub-pixel SPX1 to the third sub-pixel SPX3.

[0169] The first bank BNK1 can be a structure that defines a first emission region EMA1, a second emission region EMA2, and a third emission region EMA3, and can be a pixel defining layer. For example, the first bank BNK1 can be a structure that defines the emission regions of each of the adjacent sub-pixels. The first bank BNK1 can define the supply position of the light-emitting element LD during the process of supplying (or introducing) the light-emitting element LD to each of the first sub-pixel SPX1 to the third sub-pixel SPX3. For example, since the first emission region EMA1 to the third emission region EMA3 are separated (or defined) by the first bank BNK1, a mixed solution (e.g., ink) including a target amount and / or type of light-emitting element LD can be supplied (or input) to the corresponding emission regions.

[0170] In one or more embodiments, the first bank BNK1 may include at least one light-blocking material and / or a reflective material (or a scattering material) to prevent light leakage defects in which light (or light rays) leaks between adjacent sub-pixels. In one or more embodiments, the first bank BNK1 may include a transparent material (or substance). The transparent material may include, for example, a polyamide resin, a polyimide resin, etc., but the present disclosure is not limited thereto. In one or more embodiments, in order to enhance the efficiency of light emitted from each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, a separate reflective material layer may be provided and / or formed on the first bank BNK1.

[0171] The first bank BNK1 may include an opening OP in the pixel region PXA through which components located thereunder are exposed. In one or more embodiments, each of the first emission region EMA1 to the third emission region EMA3 may correspond to the opening OP of the first bank BNK1.

[0172] The first bank BNK1 may be located in the non-emission region NEA between the first emission region EMA1 to the third emission region EMA3. Accordingly, the provision (or input) region of the light-emitting element LD in the pixel region PXA may be determined. In this case, in the step of providing the light-emitting element LD to the pixel PXL, it is possible to prevent the light-emitting element LD from being provided to an undesired region, and the light-emitting element LD may be effectively provided to each of the first emission region EMA1 to the third emission region EMA3. Accordingly, unnecessary waste of the light-emitting element LD may be prevented. The manufacturing cost of the display device DD (or the pixel PXL) may be reduced.

[0173] In a plan view, the first bank BNK1 may be provided in a shape surrounding the light-emitting element LD. The first bank BNK1 may overlap at least some of the alignment electrodes ALE.

[0174] The emission components EMU of the first sub-pixel SPX1, the emission components EMU of the second sub-pixel SPX2, and the emission components EMU of the third sub-pixel SPX3 may have substantially the same or similar structures. Hereinafter, the emission component EMU of the first sub-pixel SPX1 will be described as a representative example. The description of the emission component EMU of the first sub-pixel SPX1 will replace the description of the emission components EMU of the second sub-pixel SPX2 and the third sub-pixel SPX3.

[0175] The emission component EMU of the first sub-pixel SPX1 may include at least an electrode PE located in the first emission region EMA1, a light-emitting element LD electrically connected to the electrode PE, and an alignment electrode ALE disposed at a position corresponding to the electrode PE. For example, the emission component EMU may include a first electrode PE1 (or a first pixel electrode), a second electrode PE2 (or a second pixel electrode), a light-emitting element LD, and a first alignment electrode ALE1 and a second alignment electrode ALE2 located at least in the first emission region EMA1. The number, shape, size, arrangement structure, etc. of each of the electrode PE and the alignment electrode ALE may be changed in various ways according to the structure of the first sub-pixel SPX1.

[0176] In one or more embodiments, the alignment electrode ALE, the light-emitting element LD, and the electrode PE may be arranged in the listed order based on one surface of the substrate SUB on which the first sub-pixel SPX1 is located. This will be described below with reference to Figure 12 and Figure 13 for the stacked structure (or cross-sectional structure) of the first sub-pixel SPX1.

[0177] The alignment electrode ALE may be located at least in the first emission region EMA1, may be spaced apart from each other in the first emission region EMA1 with respect to the first direction DR1, and each may extend in the second direction DR2. In one or more embodiments, the alignment electrode ALE may include a first alignment electrode ALE1 and a second alignment electrode ALE2 spaced apart from each other in the first direction DR1.

[0178] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed by removing a part of the alignment line in the first emission region EMA1 after aligning the light-emitting element LD during the process of manufacturing the display device DD (or the pixel PXL). As shown in Figure 9B , before the alignment of the light-emitting element LD, the first alignment electrode ALE1 may be a region of the first alignment line ALL1 whose part is not removed, and the second alignment electrode ALE2 may be a region of the second alignment line ALL2 whose part is not removed.

[0179] The first alignment line ALL1 and the second alignment line ALL2 are formed in the pixel region PXA. The first alignment signal can be applied to the first alignment line ALL1 through the first alignment pad. The second alignment signal can be applied to the second alignment line ALL2 through the second alignment pad. The first alignment signal and the second alignment signal can be signals having a voltage difference and / or a phase difference that enable the light-emitting element LD to be aligned between the first alignment line ALL1 and the second alignment line ALL2. After the light-emitting element LD is aligned, the first alignment electrode ALE1 can be formed by removing a part of the first alignment line ALL1, and the second alignment electrode ALE2 can be formed by removing a part of the second alignment line ALL2.

[0180] In one or more embodiments, the first alignment electrode ALE1 and the second alignment electrode ALE2 can be formed of the second conductive layer C2. The first alignment electrode ALE1 and the second alignment electrode ALE2 can be substantially located in the second region A2. The second conductive layer C2 can include the same material as the fourth conductive layer C4, or can include one or more suitable (or selected) materials from the constituent materials exemplified by the fourth conductive layer C4, but the present disclosure is not limited thereto.

[0181] Each of the first alignment electrode ALE1 and the second alignment electrode ALE2 can be provided in the form of a bar having a constant width in the first emission region EMA1, but the present disclosure is not limited thereto.

[0182] In one or more embodiments, each of the first alignment electrode ALE1 and the second alignment electrode ALE2 can be floating and not connected to any electrode. In this case, during the process of driving the light-emitting element LD, the electrical effects of the first alignment electrode ALE1 and the second alignment electrode ALE2 on the first electrode PE1 and the second electrode PE2 can be reduced or prevented.

[0183] The light-emitting element LD can be aligned and / or disposed in the first emission region EMA1 (or the first sub-pixel region SPXA1).

[0184] The light-emitting element LD can be located between the first alignment electrode ALE1 and the second alignment electrode ALE2. In a plan view, each of the light-emitting elements LD can include a first end EP1 and a second end EP2 that are located at the respective opposite ends (or opposite to each other) of the light-emitting element LD in its longitudinal direction (e.g., in the first direction DR1). In one or more embodiments, the second semiconductor layer including the p-type semiconductor layer (refer to Figure 1 "13") can be located on the first end EP1 (or the p-type end), and the first semiconductor layer including the n-type semiconductor layer (refer to Figure 1The “11”) may be located on the second end EP2 (or the n-type end). The light-emitting elements LD may be electrically connected in parallel to each other between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0185] The light-emitting elements LD may be located at positions spaced apart from each other and be substantially aligned parallel to each other. The distance by which the light-emitting elements LD are spaced apart from each other is not particularly limited. In one or more embodiments, a plurality of light-emitting elements LD may be positioned adjacent to each other to form a group, and a plurality of other light-emitting elements LD may be spaced apart from each other at regular intervals to form a group. The light-emitting elements LD may be aligned in one direction with non-uniform density.

[0186] The light-emitting elements LD may be input (or provided) into the first emission area EMA1 (or the opening OP of the first bank BNK1) by an inkjet printing scheme, a slot coating scheme, and / or various other schemes. For example, the light-emitting elements LD may be mixed with a volatile solvent and then input (or provided) into the first emission area EMA1 by an inkjet printing scheme or a slot coating scheme.

[0187] The first end EP1 of each of the light-emitting elements LD may be electrically connected to the first electrode PE1. The second end EP2 of each of the light-emitting elements LD may be electrically connected to the second electrode PE2. The light-emitting elements LD may be connected in parallel between the first electrode PE1 and the second electrode PE2.

[0188] The electrodes PE may be provided in at least the first emission area EMA1, and each may be provided at a position corresponding to at least one alignment electrode ALE and the light-emitting element LD. For example, each of the electrodes PE may be formed on the corresponding alignment electrode ALE and the light-emitting element LD to overlap with the corresponding alignment electrode ALE and the light-emitting element LD, and thus be electrically connected to at least the light-emitting element LD.

[0189] The electrodes PE may include the first electrode PE1 and the second electrode PE2 spaced apart from each other.

[0190] The first electrode PE1 (referred to as the “first pixel electrode” or “anode”) may be formed on one side of the first alignment electrode ALE1 and the corresponding first end EP1 of the light-emitting element LD, and thus be electrically connected to the corresponding first end EP1 of the light-emitting element LD. The first electrode PE1 may have a bar shape with a constant width in its extending direction (e.g., the second direction DR2).

[0191] The second electrode PE2 (also referred to as the "second pixel electrode" or "cathode") may be formed on the corresponding second ends EP2 of the second alignment electrode ALE2 and the light-emitting element LD, and is thus electrically connected to the corresponding second ends EP2 of the light-emitting element LD. The second electrode PE2 may have a bar shape with a constant width in its extending direction (e.g., the second direction DR2).

[0192] The first electrode PE1 and the second electrode PE2 may be positioned to be spaced apart from each other in the first emission region EMA1. In one or more embodiments, the first electrode PE1 and the second electrode PE2 may be formed of a semiconductor layer SCL. For example, the first electrode PE1 and the second electrode PE2 may be configured by a semiconductor layer SCL formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The first electrode PE1 and the second electrode PE2 may be doped with impurities during an impurity doping process performed after using a separate mask or using a third conductive layer C3 as a mask, so as to have conductivity.

[0193] In one or more embodiments, the first electrode PE1 and the second electrode PE2 may be provided in the same layer as the first active pattern ACT1 to the third active pattern ACT3, the first source electrode SE1 to the third source electrode SE3, the first drain electrode DE1 to the third drain electrode DE3, and the lower electrode LE. For example, the first electrode PE1 and the second electrode PE2 may be formed by the same process as the first active pattern ACT1 to the third active pattern ACT3, the first source electrode SE1 to the third source electrode SE3, the first drain electrode DE1 to the third drain electrode DE3, and the lower electrode LE, and may be provided in the same layer.

[0194] The first electrode PE1 may extend to the first region A1 and may be electrically connected to the second connection pattern CNP2 through a corresponding contact hole CH. The contact hole CH may be formed by opening a part of at least one insulating layer located between the first electrode PE1 configured by the semiconductor layer SCL and the second connection pattern CNP2 configured by the fourth conductive layer C4. A part of the first electrode PE1 may be exposed through the contact hole CH.

[0195] The second electrode PE2 may be electrically connected to the second horizontal power line PL2b through a corresponding contact hole CH. The contact hole CH may be formed by opening a part of at least one insulating layer located between the second electrode PE2 configured by the semiconductor layer SCL and the second horizontal power line PL2b configured by the fourth conductive layer C4. A part of the second electrode PE2 may be exposed through the contact hole CH.

[0196] In one or more embodiments, the first electrode PE1 may be the anode of the emission component EMU of the first sub-pixel SPX1. The second electrode PE2 may be the cathode of the emission component EMU.

[0197] In the following, reference will be mainly made to Figure 12 and Figure 13 to describe the stacked structure (or cross-sectional structure) of the first sub-pixel SPX1 according to the foregoing embodiment.

[0198] Figure 12 is a schematic cross-sectional view taken along line I-I' of Figure 7 . Figure 13 is a schematic cross-sectional view taken along line II-II' of Figure 7 .

[0199] Although Figure 12 and Figure 13 simply show the stacked structure of the first sub-pixel SPX1. For example, it shows that each electrode is formed of an electrode having a single layer, and each insulating layer is formed of a single insulating layer, but the present disclosure is not limited thereto.

[0200] Referring to Figures 7 to 13 , the first sub-pixel SPX1 according to one or more embodiments may be located in a first sub-pixel region SPXA1 provided in a substrate SUB. The first sub-pixel region SPXA1 may include a first region A1 and a second region A2.

[0201] Circuit elements of a pixel circuit PXC for forming the first sub-pixel SPX1 and signal lines electrically connected to the circuit elements may be located in the first region A1.

[0202] A light-emitting element layer (refer to "LDL" of Figure 4 ) forming an emission assembly EMU of the first sub-pixel SPX1 may be located in the second region A2. In addition, signal lines extending to the first region A1 may be located in the second region A2. The second region A2 may include a first emission region EMA1, and light may be emitted from the first emission region EMA1.

[0203] At least one or more insulating layers may be located on the substrate SUB. For example, a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, and a fourth insulating layer INS4 successively stacked in a third direction DR3 (e.g., the thickness direction of the substrate SUB) may be located on the substrate SUB. At least one or more conductive layers may be located on the substrate SUB. For example, the conductive layers may include a first conductive layer C1 and a second conductive layer C2 located on the substrate SUB, a third conductive layer C3 located on the second insulating layer INS2, and a fourth conductive layer C4 located on the third insulating layer INS3. A semiconductor layer SCL may be located on the first insulating layer INS1.

[0204] The first conductive layer C1 (or bottom metal layer) may include a first vertical power line PL1a, a second vertical power line PL2a, an initialization power line IPL, first to third data lines D1 to D3, and a bottom metal pattern BML.

[0205] The second conductive layer C2 (or alignment electrode conductive layer) may include a first alignment electrode ALE1 and a second alignment electrode ALE2.

[0206] The third conductive layer C3 (or gate conductive layer) may include first to third gate electrodes GE1 to GE3 and first to third additional conductive patterns ACP1 to ACP3. The gate electrodes GE1 to GE3 may be located on source electrodes SE1 to SE3, drain electrodes DE1 to DE3, and active patterns ACT1 to ACT3.

[0207] The fourth conductive layer C4 (or source-drain conductive layer) may include a first horizontal power line PL1b, a first dummy power line PL1c, a second horizontal power line PL2b, a second dummy power line PL2c, first to fourth connection patterns CNP1 to CNP4, an upper electrode UE, a dummy electrode DME, and a scan line SC. The semiconductor layer SCL may include first to third active patterns ACT1 to ACT3, first to third source electrodes SE1 to SE3, first to third drain electrodes DE1 to DE3, a lower electrode LE, a first electrode PE1, and a second electrode PE2.

[0208] The substrate SUB may include a transparent insulating material that allows light transmission. The substrate SUB may be a rigid substrate and / or a flexible substrate.

[0209] The first insulating layer INS1 (or buffer layer) may be located on the entire surface of the substrate SUB and the first conductive layer C1 and the second conductive layer C2. The first insulating layer INS1 may prevent impurities from diffusing into the first to third transistors T1 to T3 included in the pixel circuit PXC. The first insulating layer INS1 may be an inorganic insulating layer including an inorganic material. The first insulating layer INS1 may include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and / or such as aluminum oxide (AlO x) or at least one of the metal oxides. Although the first insulating layer INS1 may have a single-layer structure, the first insulating layer INS1 may have a multi-layer structure having at least two or more layers. In the case where the first buffer layer (e.g., the first insulating layer INS1) has a multi-layer structure, the corresponding layers may be formed of the same material and / or different materials. The first insulating layer INS1 may be omitted depending on the material or process conditions of the substrate SUB.

[0210] The second insulating layer INS2 (or gate insulating layer) may be located on the first insulating layer INS1 and the semiconductor layer SCL. The second insulating layer INS2 may include the same material as the first insulating layer INS1, or may include a suitable (or selected) material from the materials exemplified as the constituent materials of the first insulating layer INS1. For example, the second insulating layer INS2 may include an inorganic insulating layer containing an inorganic material. In one or more embodiments, the second insulating layer INS2 may be partially located on the first insulating layer INS1. For example, the second insulating layer INS2 may be etched together with the base material of the third conductive layer C3 during the process of manufacturing the third conductive layer C3, such that the second insulating layer INS2 is only located under the third conductive layer C3.

[0211] The third insulating layer INS3 (or interlayer insulating layer) may be provided and / or formed on the entire surface of the second insulating layer INS2 and the third conductive layer C3. The third insulating layer INS3 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials from the materials exemplified as the constituent materials of the first insulating layer INS1. For example, the third insulating layer INS3 may be formed of an inorganic insulating layer including an inorganic material.

[0212] The fourth insulating layer INS4 (or passivation layer) may be provided and / or formed on the entire surface of the third insulating layer INS3. The fourth insulating layer INS4 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials from the materials exemplified as the constituent materials of the first insulating layer INS1. For example, the fourth insulating layer INS4 may be an inorganic insulating layer including an inorganic material, but the present disclosure is not limited thereto. In one or more embodiments, the fourth insulating layer INS4 may be formed of an organic insulating layer including an organic material.

[0213] The pixel circuit PXC may include a first transistor T1 to a third transistor T3 and a storage capacitor Cst located on the first insulating layer INS1. The first transistor T1 to the third transistor T3 may be located in the first region A1. The storage capacitor Cst may be located in the second region A2.

[0214] The first transistor T1 may include a first active pattern ACT1 located on a first insulating layer INS1, a first source electrode SE1 and a first drain electrode DE1, and a first gate electrode GE1 located on a second insulating layer INS2. A bottom metal pattern BML may be located on a substrate SUB under the first transistor T1.

[0215] The second transistor T2 may include a second active pattern ACT2 located on the first insulating layer INS1, a second source electrode SE2 and a second drain electrode DE2, and a second gate electrode GE2 located on the second insulating layer INS2.

[0216] The third transistor T3 may include a third active pattern ACT3 located on the first insulating layer INS1, a third source electrode SE3 and a third drain electrode DE3, and a third gate electrode GE3 located on the second insulating layer INS2.

[0217] The storage capacitor Cst may include a lower electrode LE located on the first insulating layer INS1 and an upper electrode UE located on a third insulating layer INS3. The lower electrode LE may be integrally formed with the second source electrode SE2 and thus connected to the second source electrode SE2, and may have conductivity. The upper electrode UE may be formed of a fourth conductive layer C4 and may be electrically connected to the bottom metal pattern BML through corresponding contact holes CH passing through the third insulating layer INS3, the second insulating layer INS2, and the first insulating layer INS1.

[0218] A fourth insulating layer INS4 may be provided and / or formed on the pixel circuit PXC.

[0219] The emission component EMU may include a first alignment electrode ALE1 and a second alignment electrode ALE2 located on the substrate SUB, a light-emitting element LD located on the first insulating layer INS1, a first electrode PE1 located on a first end EP1 of the light-emitting element LD, and a second electrode PE2 located on a second end EP2 of the light-emitting element LD.

[0220] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be configured by the second conductive layer C2 and are located on the substrate SUB at a position spaced apart from the first conductive layer C1. After the first conductive layer C1 is formed, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed by a continuous process with a spacing distance from the first conductive layer C1. In this case, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be in the same layer as the components of the first conductive layer C1. For example, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be provided in the same layer as the bottom metal pattern BML. Here, the present disclosure is not limited to the foregoing embodiments. In one or more embodiments, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed after performing a process of forming an additional insulating layer on the first conductive layer C1 to more reliably ensure electrical separation from the first conductive layer C1. In this case, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be in different layers from the components of the first conductive layer C1.

[0221] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed of a reflective material to allow the light emitted from the light-emitting element LD to travel in the image display direction (or the front direction or the third direction DR3) of the display device DD. For example, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed of a conductive material (or substance). The conductive material may include an opaque metal suitable for reflecting the light emitted from the light-emitting element LD in the image display direction (e.g., the third direction DR3) of the display device DD.

[0222] Each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may have a single-layer structure, but is not limited thereto. In one or more embodiments, each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be provided and / or formed as a multi-layer structure formed by stacking at least two or more materials from metals, alloys, conductive oxides, and conductive polymers.

[0223] In the case where the first alignment electrode ALE1 and the second alignment electrode ALE2 are formed of a reflective conductive material, the light emitted from the first end EP1 and the second end EP2 of each of the light-emitting elements LD may more reliably travel in the image display direction (e.g., the third direction DR3) of the display device DD.

[0224] The first insulating layer INS1 may be located on the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0225] The first bank BNK1 may be located on the first insulating layer INS1 substantially in the non-emission area NEA of the second area A2. However, in one or more embodiments, a portion of the first bank BNK1 may be located in the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3 (e.g., see Figures 9A to 9B ).

[0226] The first bank BNK1 may be located on the first insulating layer INS1 in at least the second area A2, but the present disclosure is not limited thereto. The first bank BNK1 may be formed between adjacent sub-pixels to surround the first emission area EMA1, so that a pixel defining layer for separating (or defining) the first emission area EMA1 may be formed. In an operation of providing the light-emitting element LD to the first emission area EMA1, the first bank BNK1 may be a dam structure configured to prevent a solution (or ink) mixed with the light-emitting element LD from being sucked into the second emission area and the third emission area (refer to Figure 6 's "EMA2" and "EMA3") or control the amount of the solution so that a constant amount of the solution is provided to each of the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3.

[0227] In the second area A2, the light-emitting element LD may be aligned (or positioned) in the first emission area EMA1 of the first insulating layer INS1 and the first bank BNK1. For example, the light-emitting element LD may be provided (or input) to the first emission area EMA1 by an inkjet printing scheme or the like. The light-emitting element LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2 by an electric field formed by alignment signals respectively applied to the first alignment electrode ALE1 and the second alignment electrode ALE2. For example, the light-emitting element LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2 on the first insulating layer INS1.

[0228] Each of the light-emitting elements LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2, and may include a first end EP1 overlapping with the first alignment electrode ALE1 and a second end EP2 overlapping with the second alignment electrode ALE2.

[0229] The insulating pattern INSP may be located on the light-emitting element LD. The insulating pattern INSP may be located on the light-emitting element LD to partially cover an outer surface (e.g., an outer peripheral surface or a circumferential surface) of each of the light-emitting elements LD, so that the first end EP1 and the second end EP2 of each of the light-emitting elements LD are exposed to the outside.

[0230] The insulating pattern INSP may include an inorganic insulating layer and / or an organic insulating layer including an inorganic material. For example, the insulating pattern INSP may include an inorganic insulating layer suitable for protecting the active layer 12 in each of the light-emitting elements LD from external oxygen, water, etc. However, the present disclosure is not limited thereto. The insulating pattern INSP may be formed of an organic insulating layer including an organic material according to design conditions of the display device DD (or display panel DP) to which the light-emitting elements LD are applied. The insulating pattern INSP may be formed of a single layer or multiple layers.

[0231] Since the insulating pattern INSP is formed on the light-emitting elements LD that have been fully aligned in the first emission region EMA1, the light-emitting elements LD can be prevented from being removed from the aligned positions.

[0232] The first electrode PE1 and the second electrode PE2 may be formed on the first end EP1 and the second end EP2 of the light-emitting element LD not covered by the insulating pattern INSP. For example, the first electrode PE1 may be formed on the first end EP1 of the light-emitting element LD. The second electrode PE2 may be formed on the second end EP2 of the light-emitting element LD.

[0233] In one or more embodiments, the first electrode PE1 and the second electrode PE2 may be formed in the same layer. The first electrode PE1 and the second electrode PE2 may be formed concurrently (e.g., simultaneously), and the insulating pattern INSP may be interposed between the first electrode PE1 and the second electrode PE2. For example, the first electrode PE1 may be positioned adjacent to the first side surface (e.g., left side surface) of the insulating pattern INSP in each of the light-emitting elements LD, and the second electrode PE2 may be positioned adjacent to the second side surface (e.g., right side surface) of the insulating pattern INSP in each of the light-emitting elements LD. The first electrode PE1 may directly contact the first end EP1 in each of the light-emitting elements LD and may be electrically connected to the light-emitting elements LD. The second electrode PE2 may directly contact the second end EP2 of the light-emitting element LD and may be electrically connected to the light-emitting elements LD. As described above, when the first electrode PE1 and the second electrode PE2 are in the same layer and are formed concurrently (e.g., simultaneously), the process of manufacturing the first sub-pixel SPX1 (or display device DD) can be facilitated, and its manufacturing efficiency can be improved.

[0234] Each of the first electrode PE1 and the second electrode PE2 may be formed of various transparent conductive materials. For example, each of the first electrode PE1 and the second electrode PE2 may include at least one of various transparent conductive materials and may be substantially transparent or semi-transparent to provide a suitable transmittance, wherein the transparent conductive materials include indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and / or gallium tin oxide. Thus, the light emitted from the first end EP1 and the second end EP2 of the light-emitting element LD may pass through the first electrode PE1 and the second electrode PE2 and may then be emitted from the display device DD (or display panel DP).

[0235] The second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 may be located on the first electrode PE1 and the second electrode PE2.

[0236] In one or more embodiments, an optical layer (refer to Figure 4 “LCL” in Figure 23 ) may be selectively located on the first electrode PE1 and the second electrode PE2. For example, the optical layer LCL may include a color conversion layer and / or a color filter layer that can convert the light emitted from the light-emitting element LD into light having excellent color reproducibility and emit the converted light. A detailed description of the optical layer LCL will be made with reference to

[0237] As described above, each of the pixel circuit PXC and the emission assembly EMU may be configured as a multilayer structure including at least one or more conductive layers and at least one or more insulating layers provided and / or formed on one surface of the substrate SUB. At least one layer of the pixel circuit layer PCL and at least one layer of the display element layer DPL may be provided in the same layer, may have the same material, and / or may be formed by the same process. For example, the first electrode PE1 and the second electrode PE2 of the emission assembly EMU may be provided in the same layer as the first active pattern ACT1 to the third active pattern ACT3, the first source electrode SE1 to the third source electrode SE3, the first drain electrode DE1 to the third drain electrode DE3, and the lower electrode LE of the pixel circuit PXC, may include the same material, and / or may be formed by the same process.

[0238] According to the foregoing embodiments, the components included in the pixel circuit PXC and the components included in the emission assembly EMU are formed by the same process. Therefore, compared with the conventional display device in which the pixel circuit PXC and the emission assembly EMU are formed by corresponding separate processes, the number of masks can be reduced. Thus, a display device DD with improved manufacturing efficiency can be provided.

[0239] According to the foregoing embodiments, the light-emitting elements LD are densely aligned in a desired region (e.g., the second region A2 of each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3), such that the alignment distribution of the light-emitting elements LD in each sub-pixel and the alignment distribution of the light-emitting elements LD in adjacent sub-pixels can be uniform. In this case, the display device DD can have a uniform light output distribution over its entire region, thereby enhancing the reliability of the display device DD.

[0240] According to the foregoing embodiments, in the case where the light-emitting elements LD are densely aligned in a desired region, the number of misaligned light-emitting elements LD can be reduced. Accordingly, the loss of the light-emitting elements LD can be reduced or minimized, thereby preventing or reducing the occurrence of abnormal alignment defects in which the light-emitting elements LD are aligned in an undesired region.

[0241] According to the foregoing embodiments, the emission module EMU including the light-emitting elements LD and the pixel circuit PXC including circuit elements (e.g., the first transistor T1 to the third transistor T3 and the storage capacitor Cst) can be located on the same substrate SUB. Accordingly, compared with a conventional display device including a sub-pixel in which the emission module is positioned above the pixel circuit such that the pixel circuit and the emission module overlap each other, a display device DD that is more conducive to implementing a thin structure can be provided.

[0242] Figures 14 to 22 is a diagram for describing a method of manufacturing the first sub-pixel SPX1 according to one or more embodiments, and is a schematic cross-sectional view corresponding to the line I-I' of Figure 7

[0243] Hereinafter, reference will be made to Figures 14 to 22 to sequentially describe a method of manufacturing the first sub-pixel SPX1 (or the display device) according to one or more embodiments.

[0244] In one or more embodiments, a case where operations of manufacturing the first sub-pixel (or the display device) are sequentially performed according to a cross-sectional view is shown. However, without changing the technical scope of the present disclosure, some operations shown as being sequentially performed may be performed concurrently (e.g., simultaneously), the order of the operations may be changed, some operations may be skipped, or additional operations may be included between the operations.

[0245] Reference will be made to Figures 14 to 22 for a description that focuses on differences from the above-described embodiments to avoid redundant description.

[0246] Reference will be made to Figures 7 to 14, a first conductive layer C1 is formed on a substrate SUB. The first conductive layer C1 may include first vertical power lines PL1a, second vertical power lines PL2a, an initialization power line IPL, first data lines D1 to third data lines D3, and a bottom metal pattern BML. The first conductive layer C1 may be located in a first region A1 and a second region A2.

[0247] Reference Figures 7 to 15 , a second conductive layer C2 is formed on the substrate SUB. The second conductive layer C2 may be formed by a continuous process after the first conductive layer C1 is formed, and may be located on the substrate SUB at a position spaced apart from the first conductive layer C1. The second conductive layer C2 may include a first alignment line (Reference Figure 9B “ALL1”) (or a first alignment electrode ALE1) and a second alignment line (Reference Figure 9B “ALL2”) (or a second alignment electrode ALE2). The first alignment line ALL1 may be integrally formed with a first alignment pad positioned in a non-display region (Reference Figure 3 “NDA”). The second alignment line ALL2 may be integrally formed with a second alignment pad positioned in the non-display region NDA.

[0248] A first insulating layer INS1 may be formed on the entire surfaces of the substrate SUB, the first conductive layer C1, and the second conductive layer C2. The first insulating layer INS1 may be located on the substrate SUB, the first conductive layer C1, and the second conductive layer C2 in the first region A1 and the second region A2. In one or more embodiments, the first insulating layer INS1 may include an inorganic insulating layer containing an inorganic material. For example, the first insulating layer INS1 may include an inorganic insulating layer including a first layer formed of silicon nitride (SiN x ) and a second layer formed of silicon oxide (SiO x ).

[0249] Reference Figures 1 to 16 , a first bank BNK1 is formed in the second region A2 on the first insulating layer INS1. The first bank BNK1 may define a first emission region EMA1 of a first sub-pixel SPX1. The first bank BNK1 may be substantially located in a non-emission region NEA of each sub-pixel.

[0250] Reference Figures 1 to 17 , the first alignment line ALL1 electrically connected to the first alignment pad and the second alignment line ALL2 electrically connected to the second alignment pad are respectively provided with corresponding alignment signals, such that an electric field is formed between the first alignment line ALL1 and the second alignment line ALL2.

[0251] Ink including the light-emitting element LD is input into the second region A2 by an inkjet printing scheme or the like. For example, at least one inkjet nozzle can be positioned in the second region A2 on the first insulating layer INS1 in the first bank BNK1 including the opening OP, and the ink mixed with a plurality of light-emitting elements LD can be input into the second region A2 through the inkjet nozzle. Self-alignment of the light-emitting element LD can be induced between the first alignment line ALL1 and the second alignment line ALL2 on the first insulating layer INS1.

[0252] After self-aligning the light-emitting element LD, the solvent contained in the ink can be removed by a volatilization scheme and / or other schemes.

[0253] Reference Figures 7 to 18 , an insulating pattern INSP is formed on the light-emitting element LD. The insulating pattern INSP allows the first end EP1 and the second end EP2 of each of the light-emitting elements LD to be exposed.

[0254] After forming the insulating pattern INSP, the first alignment electrode ALE1 and the second alignment electrode ALE2 can be formed by removing corresponding portions of the first alignment line ALL1 and the second alignment line ALL2 in the first region A1. The first alignment electrode ALE1 and the second alignment electrode ALE2 can be located only in the second region A2. Thus, the first alignment electrode ALE1 and the second alignment electrode ALE2 provided in the first sub-pixel SPX1 can be electrically separated and physically separated from the first alignment electrode ALE1 and the second alignment electrode ALE2 of adjacent sub-pixels arranged in the same pixel column in the second direction DR2.

[0255] Reference Figures 7 to 19 , a semiconductor layer SCL is formed on the first insulating layer INS1 and the light-emitting element LD. The semiconductor layer SCL can include a first active pattern ACT1 to a third active pattern ACT3, a first source electrode SE1 to a third source electrode SE3, a first drain electrode DE1 to a third drain electrode DE3, a lower electrode LE, and a first electrode PE1 and a second electrode PE2. In one or more embodiments, the first active pattern ACT1 to the third active pattern ACT3, the first source electrode SE1 to the third source electrode SE3, and the first drain electrode DE1 to the third drain electrode DE3 can be located in the first region A1. The lower electrode LE, the first electrode PE1, and the second electrode PE2 can be located in the second region A2.

[0256] Each of the first active pattern ACT1 to the third active pattern ACT3 can be an intrinsic semiconductor not doped with impurities. The first source electrode SE1 to the third source electrode SE3, the first drain electrode DE1 to the third drain electrode DE3, the lower electrode LE, and the first electrode PE1 and the second electrode PE2 can be doped with impurities to have conductivity, and thus can be used as conductive patterns.

[0257] After forming a semiconductor layer SCL including at least one of polysilicon, amorphous silicon, and an oxide semiconductor on a first insulating layer INS1 and a light-emitting element LD, a separate mask is positioned over locations where a first active pattern ACT1 to a third active pattern ACT3 are to be formed, and then the semiconductor layer SCL is doped with impurities. Regions of the semiconductor layer SCL doped with impurities to have conductivity can be formed as a first source electrode SE1 to a third source electrode SE3, a first drain electrode DE1 to a third drain electrode DE3, a lower electrode LE, and a first electrode PE1 and a second electrode PE2.

[0258] Reference Figures 7 to 20 , a second insulating layer INS2 is formed on the first active pattern ACT1 to the third active pattern ACT3, the first source electrode SE1 to the third source electrode SE3, the first drain electrode DE1 to the third drain electrode DE3, the lower electrode LE, and the first electrode PE1 and the second electrode PE2. The second insulating layer INS2 may include an inorganic insulating layer containing an inorganic material.

[0259] A third conductive layer C3 is formed on the second insulating layer INS2. For example, the third conductive layer C3 may be provided as a bilayer structure stacked in the order of titanium and / or copper, but the present disclosure is not limited thereto. The third conductive layer C3 may include a first gate electrode GE1 to a third gate electrode GE3 and a first additional conductive pattern ACP1 to a third additional conductive pattern ACP3.

[0260] Reference Figures 7 to 21 , a third insulating layer INS3 is formed on the entire surface of the third conductive layer C3. The third insulating layer INS3 may be located on the third conductive layer C3 and the second insulating layer INS2 in a first region A1 and a second region A2. The third insulating layer INS3 may be formed of an inorganic insulating layer including an inorganic material. For example, the third insulating layer INS3 may include an inorganic insulating layer containing silicon oxynitride (SiO x N y ).

[0261] The third insulating layer INS3 may be patterned to include a plurality of contact holes CH through which some of the components located thereunder are exposed.

[0262] Reference Figures 7 to 22 , a fourth conductive layer C4 is formed on the third insulating layer INS3. The fourth conductive layer C4 may be located in the first region A1 and the second region A2. For example, the fourth conductive layer C4 may be provided as a multilayer structure stacked in the order of titanium, copper, and / or indium tin oxide, but the present disclosure is not limited thereto.

[0263] The fourth conductive layer C4 may include a first horizontal power line PL1b, a first dummy power line PL1c, a second horizontal power line PL2b, a second dummy power line PL2c, first to fourth connection patterns CNP1 to CNP4, an upper electrode UE, a dummy electrode DME, and a scan line SC.

[0264] A fourth insulating layer INS4 as described above may be formed over the fourth conductive layer C4. Figure 12

[0265] In the first sub-pixel SPX1 (or display device DD) formed by the foregoing manufacturing method, the substrate SUB is partitioned into a first region A1 in which the pixel circuit PXC (or pixel circuit layer (refer to Figure 4 "PCL")) is located and a second region A2 in which the emission component EMU (or light-emitting element layer (refer to Figure 4 "LDL")) is located, and some components of the pixel circuit PXC and some components of the emission component EMU are formed by the same process. Therefore, manufacturing efficiency can be improved.

[0266] Figure 23 FIG. shows a first sub-pixel SPX1 according to one or more embodiments and is a schematic cross-sectional view taken along line I-I' of Figure 7

[0267] Regarding Figure 23 the embodiments, the following description will focus on the differences from the description of the foregoing embodiments to avoid redundant explanations.

[0268] Refer to Figure 7 and Figure 23 , the first sub-pixel SPX1 may further include an upper substrate U_SUB located over the fourth conductive layer C4 and the fourth insulating layer INS4.

[0269] The upper substrate U_SUB may include a base layer BSL, an optical layer LCL, a fifth insulating layer INS5, a sixth insulating layer INS6, and a second bank BNK2. The optical layer LCL may include a color filter layer CFL and a color conversion layer CCL.

[0270] The base layer BSL may be a rigid substrate and / or a flexible substrate, and its material or properties are not particularly limited. The base layer BSL may be formed of the same material as the substrate SUB or may be formed of a material different from that of the substrate SUB.

[0271] ​​The color filter layer CFL may be located on one surface of the base layer BSL in a direction opposite to the third direction DR3 to face the first electrode PE1 and the second electrode PE2. The color filter layer CFL may include a color filter CF corresponding to the first emission area EMA1. For example, the color filter layer CFL may include a first color filter CF1 located on the color conversion layer CCL of the first sub-pixel SPX1, a second color filter CF2 located on the color conversion layer of the second sub-pixel (refer to Figure 6 "SPX2") adjacent to the first sub-pixel SPX1, and a third color filter CF3 located on the color conversion layer of the third sub-pixel (refer to Figure 6 "SPX3") adjacent to the second sub-pixel SPX2.

[0272] The first color filter CF1 of the color filter layer CFL may be located on one surface of the base layer BSL to correspond to the light-emitting element LD in the first emission area EMA1. The first color filter CF1, the second color filter CF2, and the third color filter CF3 of the color filter layer CFL may be positioned to overlap each other in the non-emission area NEA, thereby serving as a light-blocking component.

[0273] A fifth insulating layer INS5 may be positioned on the color filter layer CFL. The fifth insulating layer INS5 may be located on the color filter layer CFL and cover the color filter layer CFL to protect the color filter layer CFL. The fifth insulating layer INS5 may be an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material.

[0274] A second bank BNK2 and a color conversion layer CCL may be positioned on one surface of the fifth insulating layer INS5 in a direction opposite to the third direction DR3.

[0275] The second bank BNK2 may be positioned on the first bank BNK1 in the non-emission area NEA and overlap the first bank BNK1 in the third direction DR3. The color conversion layer CCL may be positioned on the first electrode PE1, the second electrode PE2, and the light-emitting element LD in the first emission area EMA1 and overlap the first electrode PE1, the second electrode PE2, and the light-emitting element LD.

[0276] The second bank BNK2 may be a dam structure that surrounds the first sub-pixel SPX1 and defines the position where the color conversion layer CCL is to be provided, thereby ultimately defining the first emission area EMA1. The second bank BNK2 may include a light-blocking material. For example, the second bank BNK2 may be a black matrix, but the present disclosure is not limited thereto. In one or more embodiments, the second bank BNK2 may include at least one light-blocking material and / or a reflective material, and allow the light emitted from the color conversion layer CCL to travel more reliably in the image display direction (e.g., the third direction DR3) of the display device DD, thereby enhancing the light output efficiency of the color conversion layer CCL.

[0277] The color conversion layer CCL may include color conversion particles QD corresponding to a specific color. For example, the color conversion layer CCL may include color conversion particles QD that convert the light of the first color emitted from the light-emitting element LD into the light of the second color (light of a specific color or light having excellent color reproducibility).

[0278] In the case where the first sub-pixel SPX1 is a red sub-pixel, the color conversion layer CCL of the first sub-pixel SPX1 may include color conversion particles QD formed of red quantum dots that convert the light of the first color emitted from the light-emitting element LD into the light of the second color (e.g., red light).

[0279] In the case where the first sub-pixel SPX1 is a green sub-pixel, the color conversion layer CCL of the first sub-pixel SPX1 may include color conversion particles QD formed of green quantum dots that convert the light of the first color emitted from the light-emitting element LD into the light of the second color (e.g., green light).

[0280] In the case where the first sub-pixel SPX1 is a blue sub-pixel, the color conversion layer CCL of the first sub-pixel SPX1 may include color conversion particles QD formed of blue quantum dots that convert the light of the first color emitted from the light-emitting element LD into the light of the second color (e.g., blue light). In the case where the first sub-pixel SPX1 is a blue sub-pixel, according to an embodiment, a light-scattering layer including light-scattering particles SCT may be provided instead of the color conversion layer CCL including color conversion particles QD. For example, in the case where the light-emitting element LD emits blue-based light, the first sub-pixel SPX1 may include a light-scattering layer including light-scattering particles SCT. According to an embodiment, the light-scattering layer may be omitted. In the case where the first sub-pixel SPX1 is a blue sub-pixel, according to an embodiment, a transparent polymer may be provided instead of the color conversion layer CCL.

[0281] The sixth insulating layer INS6 may be located on the entire surfaces of the second bank BNK2 and the color conversion layer CCL.

[0282] The sixth insulating layer INS6 may be formed of an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The sixth insulating layer INS6 may be located on the color conversion layer CCL and protect the color conversion layer CCL from external water and / or moisture, thereby further improving the reliability of the color conversion layer CCL.

[0283] In the first sub-pixel SPX1 according to the foregoing embodiment, the color conversion layer CCL and the color filter layer CFL may be located on the light-emitting element LD, so that light with excellent light reproducibility may be emitted through the color conversion layer CCL and the color filter layer CFL, thereby improving the light output efficiency.

[0284] According to one or more embodiments, the pixel circuit assembly and the emission assembly may be located on one surface of the same (e.g., identical) substrate, so that a display device having a thin structure with a reduced thickness may be realized.

[0285] In addition, according to one or more embodiments, the components included in the pixel circuit assembly and the components included in the emission assembly may be formed by the same process, thereby improving the manufacturing efficiency of the display device.

[0286] Aspects of the present disclosure are not limited by the foregoing, and various other aspects are contemplated herein.

[0287] Although various embodiments have been described above, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the spirit or scope of the present disclosure.

[0288] Therefore, the embodiments disclosed in the present disclosure are only for exemplary purposes and do not limit the technical spirit of the present disclosure. The scope of the present disclosure may be defined by the appended claims and their equivalents.

Claims

1. A display device, comprising a sub-pixel, wherein the sub-pixel comprises a first region and a second region, and the sub-pixel comprises: a pixel circuit component in the first region and including a transistor on the substrate; as well as an emitting component in the second region and comprising a light emitting element and a first electrode and a second electrode electrically connected to the light emitting element, The transistor includes an active pattern on the substrate, a source electrode connected to a first side of the active pattern, a drain electrode connected to a second side of the active pattern, and a gate electrode on the active pattern, and The active pattern, the source electrode, the drain electrode, the first electrode, and the second electrode are disposed in the same layer.

2. The display device according to claim 1, in, The active pattern includes an intrinsic semiconductor layer, and Each of the source electrode, the drain electrode, the first electrode and the second electrode includes a semiconductor layer containing impurities, and the semiconductor layer is conductive.

3. The display device according to claim 2, wherein: The first electrode and the second electrode are spaced apart from the active pattern, the source electrode, and the drain electrode.

4. The display device according to claim 1, in, Each of the pixel circuit component and the emission component has a multi-layer structure, and Wherein, at least one layer of the pixel circuit component and at least one layer of the emission component are in the same layer.

5. The display device according to claim 4, in, The pixel circuit assembly includes a bottom metal layer on the substrate, a first insulating layer on the bottom metal layer, the active pattern on the first insulating layer, the source electrode and the drain electrode, the gate electrode on the source electrode, the drain electrode and the active pattern, and a source-drain conductive layer on the gate electrode, and Wherein, the emitting component includes a first alignment electrode and a second alignment electrode located on the substrate, the first insulating layer located on the first alignment electrode and the second alignment electrode, the light-emitting element located on the first insulating layer, the first electrode located on the light-emitting element and connected to the first end of the light-emitting element, and the second electrode located on the light-emitting element and connected to the second end of the light-emitting element.

6. The display device according to claim 5, wherein: The bottom metal layer, the first alignment electrode, and the second alignment electrode are in the same layer.

7. The display device according to claim 5, in, The second region includes an emission region from which light is emitted and a non-emission region adjacent to the emission region, wherein the emission assembly comprises a first dam, the first dam is in the non-emission area and comprises an opening corresponding to the emission area, and Wherein, at least a portion of the first bank overlaps with each of the first alignment electrode and the second alignment electrode.

8. The display device according to claim 5, in, The sub-pixel further includes a storage capacitor including a lower electrode on the substrate and an upper electrode on and overlapping the lower electrode. wherein the lower electrode is in the same layer as the active pattern, the source electrode, the drain electrode, the first electrode and the second electrode, The sub-pixel further includes a first power line configured to receive a first driving voltage and a second power line configured to receive a second driving voltage different from the first driving voltage, and Wherein, the first electrode is electrically connected to the upper electrode, and the second electrode is electrically connected to the second power line.

9. The display device according to claim 8, in, The first power line includes a first vertical power line configured by the bottom metal layer, a first horizontal power line configured by the source-drain conductive layer, and a first dummy power line overlapping the first vertical power line and configured by the source-drain conductive layer, and The second power line includes a second vertical power line formed by the bottom metal layer, a second horizontal power line formed by the source-drain conductive layer, and a second dummy power line formed integrally with the second horizontal power line and extending in a different direction from the second horizontal power line.

10. The display device according to claim 9, in, The first vertical power line, the first horizontal power line, and the first dummy power line are electrically connected to each other, and The second vertical power line, the second horizontal power line and the second dummy power line are electrically connected to each other.

Images