Display device

Abstract

The invention relates to a display device. According to one embodiment, a display device includes: a substrate having a display region and a peripheral region; an organic insulating layer disposed in the display region and the peripheral region; a plurality of display elements disposed in the display region, each of the plurality of display elements including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a first partition wall disposed in the display region and disposed between adjacent display elements; a second partition wall disposed in the peripheral region and connected to the first partition wall; and a dam portion disposed in the peripheral region and surrounding the organic insulating layer and the second partition wall. The first partition wall and the second partition wall include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. In addition, an end portion of the second partition wall is located above the organic insulating layer and is separated from the dam portion.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-215593 filed on December 21, 2023, and incorporates by reference all the descriptions recited in the Japanese application. Technical Field

[0003] Embodiments of the present invention relate to a display device. Background Art

[0004] In recent years, a display device using an organic light-emitting diode (OLED) as a display element has been put into practical use. In such a display device, technologies capable of improving the yield and enhancing the reliability are required. Summary of the Invention

[0005] Generally, according to an embodiment, a display device includes: a substrate having a display area for displaying an image and a peripheral area around the display area; an organic insulating layer disposed in the display area and the peripheral area; a plurality of display elements disposed in the display area, each of the plurality of display elements including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to the application of a voltage; a first partition wall disposed in the display area and between adjacent display elements; a second partition wall disposed in the peripheral area and connected to the first partition wall; and a dam portion disposed in the peripheral area and surrounding the organic insulating layer and the second partition wall. The first partition wall and the second partition wall include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. Further, the end portion of the second partition wall is located above the organic insulating layer and separated from the dam portion.

[0006] According to such a configuration, a display device capable of improving the yield or enhancing the reliability can be provided. Brief Description of the Drawings

[0007] Figure 1 is a diagram showing a configuration example of a display device according to an embodiment.

[0008] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels.

[0009] Figure 3 is along Figure 2 a schematic cross-sectional view of the display device taken along line III-III in

[0010] Figure 4 is a schematic plan view of the display device for explaining the structure of the peripheral area.

[0011] Figure 5 An enlarged top view of a part of the peripheral area.

[0012] Figure 6 Is along Figure 5 A schematic cross-sectional view of the display device taken along line VI-VI in

[0013] Figure 7 Is a schematic cross-sectional view of an enlarged part of Figure 6 .

[0014] Figure 8A Is a schematic cross-sectional view showing an example of the manufacturing process of the display device.

[0015] Figure 8B Is a schematic cross-sectional view showing the process following Figure 8A .

[0016] Figure 8C Is a schematic cross-sectional view showing the process following Figure 8B .

[0017] Figure 8D Is a schematic cross-sectional view showing the process following Figure 8C .

[0018] Figure 8E Is a schematic cross-sectional view showing the process following Figure 8D .

[0019] Figure 8F Is a schematic cross-sectional view showing the process following Figure 8E .

[0020] Figure 8G Is a schematic cross-sectional view showing the process following Figure 8F .

[0021] Figure 8H Is a schematic cross-sectional view showing the process following Figure 8G .

[0022] Figure 8I Is a schematic cross-sectional view showing the process following Figure 8H .

[0023] Figure 9 Is a schematic cross-sectional view of the peripheral area of the comparative example.

[0024] Figure 10 Is a schematic top view of the display device of the modified example. Detailed Description of the Invention

[0025] Several embodiments will be described with reference to the accompanying drawings.

[0026] The disclosed content is merely an example, and appropriate modifications that can be easily conceived by those skilled in the art to maintain the gist of the invention are of course included in the scope of the present invention. Additionally, regarding the drawings, for the sake of clearer explanation, the width, thickness, shape, etc. of each part may be schematically shown compared to the actual manner, but this is merely an example and does not limit the interpretation of the present invention. Further, in this specification and each figure, for components that perform the same or similar functions as components described in the accompanying drawings that have already appeared, there are cases where the same reference numerals are marked and repeated detailed descriptions are appropriately omitted.

[0027] It should be noted that for ease of understanding, the X-axis, Y-axis, and Z-axis orthogonal to each other are depicted in the drawings as needed. The direction along the X-axis is referred to as the X direction, the direction along the Y-axis is referred to as the Y direction, and the direction along the Z-axis is referred to as the Z direction. The Z direction is the normal direction of the plane including the X direction and the Y direction. Additionally, observing various elements parallel to the Z direction is referred to as a top view.

[0028] The display device of each embodiment is an organic electroluminescent display device having an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as a television, a personal computer, a vehicle-mounted device, a tablet terminal, a smartphone, and a mobile phone terminal.

[0029] Figure 1 It is a diagram showing a configuration example of the display device DSP of one embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 can be glass or a flexible resin film.

[0030] In the present embodiment, the shapes of the substrate 10 and the display area DA when observed from above are circular. However, the shapes of the substrate 10 and the display area DA when observed from above are not limited to circular, and can also be other shapes such as rectangular, square, or oval.

[0031] The display area DA includes a plurality of pixels PX arranged in a matrix in the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, it is assumed that the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, the pixel PX can also include other color sub-pixels SP such as white together with or instead of any one of the sub-pixels SP1, SP2, and SP3.

[0032] The display device DSP further includes a terminal portion T disposed in the peripheral area SA. The terminal portion T is connected to, for example, a flexible circuit board that supplies a voltage and signals for driving the display device DSP.

[0033] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switch elements formed of thin film transistors, for example.

[0034] In the display area DA, a plurality of scan lines GL for supplying scan signals to the pixel circuits 1 of the respective sub-pixels SP, a plurality of signal lines SL for supplying video signals to the pixel circuits 1 of the respective sub-pixels SP, and a plurality of power supply lines PL are arranged. In Figure 1 this example, the scan lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0035] The gate electrode of the pixel switch 2 is connected to the scan line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power supply line PL and the capacitor 4, and the other is connected to the display element DE.

[0036] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0037] Figure 2 is a schematic plan view showing an example of the layout of the sub-pixels SP1, SP2, and SP3. In Figure 2 this example, the sub-pixels SP2 and SP3 are arranged in the X direction with respect to the sub-pixel SP1, respectively. In addition, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the Y direction.

[0038] When the sub-pixels SP1, SP2, and SP3 have such a layout, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the Y direction and columns in which a plurality of sub-pixels SP1 are repeatedly arranged in the Y direction are formed in the display area DA. These columns are alternately arranged in the X direction. It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 this example.

[0039] A rib layer 5 is arranged in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. In Figure 2 this example, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the sub-pixels SP1, SP2, and SP3, the sub-pixel SP1 has the largest aperture ratio, and the sub-pixel SP3 has the smallest aperture ratio.

[0040] The sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that respectively overlap with the pixel aperture AP1. The sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that respectively overlap with the pixel aperture AP2. The sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that respectively overlap with the pixel aperture AP3.

[0041] The portions of the lower electrode LE1, the upper electrode UE1, and the organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the sub-pixel SP1. The portions of the lower electrode LE2, the upper electrode UE2, and the organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the sub-pixel SP2. The portions of the lower electrode LE3, the upper electrode UE3, and the organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cover layer described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3 respectively.

[0042] Above the rib layer 5, a conductive partition wall 6A (first partition wall) is disposed. The partition wall 6A overlaps with the rib layer 5 as a whole and has the same planar shape as the rib layer 5. That is, the partition wall 6A has openings in the sub-pixels SP1, SP2, and SP3 respectively. From another perspective, the rib layer 5 and the partition wall 6A are in a lattice shape in a top view and surround the sub-pixels SP1, SP2, and SP3 respectively. The partition wall 6A functions as a wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3.

[0043] Figure 3 It is along Figure 2 a schematic cross-sectional view of the display device DSP along the line III-III in. Above the substrate 10, a circuit layer 11 is disposed. The circuit layer 11 includes Figure 1 various circuits and wirings such as the pixel circuit 1, the scan line GL, the signal line SL, and the power line PL shown. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarization film for planarizing the unevenness generated by the circuit layer 11.

[0044] The lower electrodes LE1, LE2, and LE3 are disposed above the organic insulating layer 12. The rib layer 5 is disposed above the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the Figure 3 cross-section, the lower electrodes LE1, LE2, and LE3 are respectively connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0045] The partition wall 6A includes a lower portion 61 disposed above the rib layer 5 and having conductivity, and an upper portion 62 disposed above the lower portion 61. The upper portion 62 has a larger width than the lower portion 61. Accordingly, both end portions of the upper portion 62 protrude beyond the sides of the lower portion 61. Such a shape of the partition wall 6A is referred to as a cantilever shape.

[0046] In Figure 3 the example of, the lower portion 61 includes a bottom layer 63 disposed above the rib layer 5 and a shaft layer 64 disposed above the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Additionally, in Figure 3 the example of, both end portions of the bottom layer 63 protrude beyond the sides of the shaft layer 64.

[0047] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the sides of the lower portion 61 of the partition wall 6A.

[0048] The display element DE1 includes a cover layer CP1 disposed above the upper electrode UE1. The display element DE2 includes a cover layer CP2 disposed above the upper electrode UE2. The display element DE3 includes a cover layer CP3 disposed above the upper electrode UE3. The cover layers CP1, CP2, and CP3 each serve as an optical adjustment layer for improving the light extraction efficiency of the light emitted from the organic layers OR1, OR2, and OR3.

[0049] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cover layer CP3 is referred to as the stacked film FL3.

[0050] A part of the stacked film FL1 is located above the upper portion 62. This part is separated from the part of the stacked film FL1 that is located around the partition wall 6A (the part constituting the display element DE1). Similarly, a part of the stacked film FL2 is located above the upper portion 62, and this part is separated from the part of the stacked film FL2 that is located around the partition wall 6A (the part constituting the display element DE2). Further, a part of the stacked film FL3 is located above the upper portion 62, and this part is separated from the part of the stacked film FL3 that is located around the partition wall 6A (the part constituting the display element DE3).

[0051] Sealing layers SE11, SE12, and SE13 are respectively disposed in sub-pixels SP1, SP2, and SP3. The sealing layer SE11 continuously covers the cover layer CP1 and the partition wall 6A around the sub-pixel SP1. The sealing layer SE12 continuously covers the cover layer CP2 and the partition wall 6A around the sub-pixel SP2. The sealing layer SE13 continuously covers the cover layer CP3 and the partition wall 6A around the sub-pixel SP3.

[0052] In Figure 3 this example, the stacked film FL1 and the sealing layer SE11 on the partition wall 6A between the sub-pixels SP1 and SP2 are separated from the stacked film FL2 and the sealing layer SE12 on the partition wall 6A. In addition, the stacked film FL1 and the sealing layer SE11 on the partition wall 6A between the sub-pixels SP1 and SP3 are separated from the stacked film FL3 and the sealing layer SE13 on the partition wall 6A.

[0053] The sealing layers SE11, SE12, and SE13 (the first sealing layer) are covered by a resin layer RS1 (the first resin layer). The resin layer RS1 is covered by a sealing layer SE2 (the second sealing layer). The sealing layer SE2 is covered by a resin layer RS2 (the second resin layer). The resin layers RS1, RS2, and the sealing layer SE2 are at least continuously provided over the entire display area DA, and a part thereof also reaches the peripheral area SA.

[0054] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass can be further disposed above the resin layer RS2. Such a cover member can be bonded to the resin layer RS2 by means of an adhesive layer such as an OCA (Optical Clear Adhesive).

[0055] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as an epoxy resin or an acrylic resin.

[0056] The lower electrodes LE1, LE2, and LE3 have a reflective layer formed of, for example, silver and a pair of conductive oxide layers covering the upper surface and the lower surface of the reflective layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0057] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), for example. For example, the lower electrodes LE1, LE2, and LE3 correspond to anodes, and the upper electrodes UE1, UE2, and UE3 correspond to cathodes.

[0058] The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in the Z direction in sequence. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of light-emitting layers.

[0059] The cover layers CP1, CP2, and CP3 have a stacked structure in which a plurality of transparent layers overlap, for example. These transparent layers may include a layer formed of an inorganic material and a layer formed of an organic material. In addition, these transparent layers have different refractive indices from each other. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the refractive indices of the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the cover layers CP1, CP2, and CP3 may be omitted.

[0060] The bottom layer 63 and the shaft layer 64 of the partition wall 6A are formed of a metal material. As the metal material for the bottom layer 63, for example, molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used. As the metal material for the shaft layer 64, for example, aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used. It should be noted that the shaft layer 64 may also be formed of an insulating material.

[0061] For example, the upper portion 62 of the partition wall 6A has a stacked structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. As the metal material for forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide for forming the upper layer, for example, ITO or IZO can be used. It should be noted that the upper portion 62 may have a single-layer structure of a metal material. In addition, the upper portion 62 may include a layer formed of an insulating material.

[0062] A common voltage is supplied to the partition wall 6A. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3 that are in contact with the side surface of the lower portion 61, respectively. Pixel voltages corresponding to the video signals of the signal lines SL are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0063] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, if a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength region. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength region. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength region.

[0064] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer into light corresponding to the sub-pixels SP1, SP2, and SP3. Additionally, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layer to generate light corresponding to the sub-pixels SP1, SP2, and SP3.

[0065] Figure 4 is a schematic top view of the display device DSP for explaining the structure of the peripheral region SA. The display device DSP includes a dam structure DS disposed in the peripheral region SA. In Figure 4 the example, the dam structure DS includes annular dam portions DM1, DM2, DM3, and DM4.

[0066] The dam portion DM1 surrounds the display region DA. The dam portion DM2 surrounds the dam portion DM1. The dam portion DM3 surrounds the dam portion DM2. The dam portion DM4 surrounds the dam portion DM3.

[0067] Each of the dam portions DM1, DM2, DM3, and DM4 has an arc-shaped curved portion CV and straight portions ST connected to both ends of the curved portion CV. The curved portion CV is, for example, concentric with the display region DA. The straight portion ST is, for example, located between the display region DA and the terminal portion T and extends parallel to the X direction.

[0068] It should be noted that the shapes of the dam portions DM1, DM2, DM3, and DM4 are not limited to Figure 4 the example. Additionally, the number of dam portions included in the dam structure DS may be 3 or less, or may be 5 or more.

[0069] Figure 5 is an enlarged top view of a part of the peripheral region SA. The above-mentioned organic insulating layer 12 is also disposed in the peripheral region SA. The organic insulating layer 12 is disposed inside the dam portion DM1. That is, the dam portion DM1 surrounds the organic insulating layer 12. The end portion E0 of the organic insulating layer 12 is separated from the dam portion DM1.

[0070] In the peripheral region SA, a partition wall 6B is further disposed. The partition wall 6B is formed byFigure 2 and Figure 3 formed by the same process as the partition wall 6A shown and having the same structure as the partition wall 6A.

[0071] For example, the partition wall 6B surrounds the display area DA together with the dams DM1, DM2, DM3, and DM4. The partition wall 6B is connected to the above-mentioned partition wall 6A. That is, a common voltage is applied to the partition wall 6B. As shown in the figure, the partition wall 6B may have a plurality of openings A. The openings A are arranged at regular intervals in the X direction and the Y direction.

[0072] The partition wall 6B entirely overlaps the organic insulating layer 12 in a plan view. That is, the end portion E1 of the partition wall 6B is located above the organic insulating layer 12.

[0073] In Figure 5 the example of, a stacked film FL and a sealing layer SE1 are disposed in the peripheral area SA. The stacked film FL is Figure 3 any one of the stacked films FL1, FL2, and FL3 shown. The sealing layer SE1 is Figure 3 any one of the sealing layers SE11, SE12, and SE13 shown. Similar to the partition wall 6B, the stacked film FL and the sealing layer SE1 entirely overlap the organic insulating layer 12 in a plan view.

[0074] The partition wall 6B, the stacked film FL, and the sealing layer SE1 are disposed inside the dam DM1. That is, the dam DM1 surrounds the partition wall 6B, the stacked film FL, and the sealing layer SE1. The end portion E1 of the partition wall 6B is separated from the dam DM1. Similarly, the end portions E2 of the stacked film FL and the sealing layer SE1 are separated from the dam DM1. The end portion E2 is located between the end portion E1 and the dam DM1, and more specifically, between the end portion E1 and the end portion E0.

[0075] In Figure 5 the example of, the end portions E0, E1, and E2 are in the same arc shape as the dam DM1. For example, the end portions E0, E1, and E2 may also have an outer shape in which the distance from the dam DM1 is substantially constant over the entire circumference.

[0076] Figure 6 is a schematic cross-sectional view of the display device DSP along the line VI-VI in Figure 5 . Figure 7 is a schematic cross-sectional view obtained by magnifying a part of Figure 6 . Figure 3The illustrated circuit layer 11 has inorganic insulating layers 31, 32, 33 formed of an inorganic insulating material, an organic insulating layer 34 formed of an organic insulating material, and metal layers 41, 42, 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is disposed over the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is disposed over the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is disposed over the organic insulating layer 34 and is covered by the organic insulating layer 12.

[0077] The dam portions DM1, DM2, DM3, DM4 all protrude from above the substrate 10. In Figure 6 the example, the dam portion DM1 is formed of the organic insulating layers 12, 34. The dam portions DM2, DM3, DM4 are also formed of the organic insulating layers 12, 34 in the same manner. That is, in the present embodiment, the dam portions DM1, DM2, DM3, DM4 are formed of the same material as the organic insulating layers 12, 34 in the same layer as the organic insulating layers 12, 34. It should be noted that the dam portions DM2, DM3, DM4 may not include the organic insulating layer 34.

[0078] A power supply line PW to which a common voltage is applied is disposed below the dam portions DM1, DM2. The power supply line PW has a first wiring W1 formed of the metal layer 42 and a second wiring W2 formed of the metal layer 43.

[0079] In Figure 6 the example, the first wiring W1 and the second wiring W2 are in contact with each other at a contact portion CN0 located between the dam portions DM1, DM2. In each of the dam portions DM1, DM2, a part of the second wiring W2 is located between the organic insulating layers 12, 34.

[0080] A conductive relay layer RL that connects the partition wall 6B and the power supply line PW is further disposed in the peripheral area SA and a rib layer 5. The relay layer RL is formed of, for example, the same material as the lower electrodes LE1, LE2, LE3 described above and by the same process.

[0081] The relay layer RL is located on the display area DA side (left side in the figure) with respect to the dam portion DM1 and covers the organic insulating layer 12. The rib layer 5 continuously covers the relay layer RL and the dam portions DM1, DM2, DM3, DM4. The end of the rib layer 5 is located outside the dam portion DM4.

[0082] The partition wall 6B is disposed over the rib layer 5. The partition wall 6B is in contact with the relay layer RL at a contact portion CN1 (first contact portion) that overlaps the organic insulating layer 12 in a plan view. The rib layer 5 has an opening at the contact portion CN1.

[0083] The relay layer RL contacts the second wiring W2 of the power supply line PW at the contact portion CN2 (the second contact portion). The contact portion CN2 is located between the end E0 of the organic insulating layer 12 and the dam portion DM1 when viewed from above.

[0084] The partition wall 6B is covered with the laminated film FL. The laminated film FL is covered with the sealing layer SE1. As Figure 7 shown, the partition wall 6B includes the same lower portion 61 and upper portion 62 as the partition wall 6A. In addition, the lower portion 61 of the partition wall 6B includes the bottom layer 63 and the shaft layer 64. In the partition wall 6B, the upper portion 62 protrudes from the side surface of the shaft layer 64. That is, the end E1 of the partition wall 6B is Figure 3 in the same cantilever shape as the partition wall 6A shown.

[0085] Therefore, as Figure 6 and Figure 7 shown, the laminated film FL is partitioned near the end E1 of the partition wall 6B. The sealing layer SE1 continuously covers the partitioned laminated film FL. By partitioning the laminated film FL in this way, the moisture intrusion path through the laminated film FL can be cut off.

[0086] Above the sealing layer SE1, there are arranged Figure 3 the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown. The resin layer RS1 covers the sealing layer SE1 and the rib layer 5. The ends E2 of the laminated film FL and the sealing layer SE1 are covered by the resin layer RS1. The dam portions DM1 and DM2 function to intercept the resin layer RS1 before curing when manufacturing the display device DSP.

[0087] In Figure 6 the example, the end Er1 of the resin layer RS1 is located above the dam portion DM2. However, the position of the end Er1 is not limited to this example.

[0088] The sealing layer SE2 covers the end Er1 of the resin layer RS1. The sealing layer SE2 contacts the rib layer 5 in a region outside (the right side in the figure) of the end Er1. In Figure 6 the example, the end Es of the sealing layer SE2 is located above the dam portion DM4. The resin layer RS1 is surrounded by the sealing layer SE1, the rib layer 5, and the sealing layer SE2. Thereby, the intrusion of moisture into the resin layer RS1 is suppressed.

[0089] The resin layer RS2 covers the sealing layer SE2. The dam portions DM3 and DM4 function to intercept the resin layer RS2 before curing when manufacturing the display device DSP. In the present embodiment, the end Er2 of the resin layer RS2 is located between the end Er1 of the resin layer RS1 and the end Es of the sealing layer SE2. More specifically, the end Er2 is located above the dam portion DM4. The resin layer RS2 covers the sealing layer SE2 above the dam portion DM3. It should be noted that the position of the end Er2 is not limited toFigure 6 Example

[0090] As Figure 7 shown, the organic insulating layer 12 includes a first portion P1 having a thickness T1 and a second portion P2 having a thickness T2. The thickness T2 is less than the thickness T1 (T2 < T1). The second portion P2 is formed on the periphery of the first portion P1. That is, the second portion P2 surrounds the first portion P1 in a plan view.

[0091] In Figure 7 the example, an organic insulating layer 34 is disposed below the first portion P1. Near an end E3 of the organic insulating layer 34, a step portion 12a is generated in the organic insulating layer 12. For example, a boundary B between the first portion P1 and the second portion P2 is located at a lower end of the step portion 12a.

[0092] The relay layer RL covers the first portion P1, the second portion P2, and the step portion 12a. Assuming that the second portion P2 is not provided in the organic insulating layer 34, the step portion 12a becomes steeper. If the relay layer RL is formed in a manner to cover such a steep step portion 12a, an abnormal shape of the relay layer RL may be generated. In contrast, in the case where the second portion P2 is provided, the step portion 12a can be alleviated and the relay layer RL can be formed well.

[0093] An end E1 of the partition wall 6B is located above the first portion P1. In addition, an end E2 of the stacked film FL and the sealing layer SE1 is also located above the first portion P1. The end E1 corresponds to an end of an upper portion 62 of the partition wall 6B. Both the ends E1 and E2 are located on the display area DA side (left side in the figure) with respect to the end E3 of the organic insulating layer 34.

[0094] Here, a distance D1 between the ends E1 and E2 in a plan view is defined as D1, a distance D2 between the ends E2 and E3 in a plan view is defined as D2, and a distance D3 between the ends E3 and the boundary B in a plan view is defined as D3. In Figure 7 the example, the distance D1 is greater than the distances D2 and D3 (D1 > D2, D3). In addition, the distance D2 is less than the distance D3 (D2 < D3). In one example, the distance D1 is 6 μm, the distance D2 is 2 μm, and the distance D3 is 4 μm.

[0095] In the present embodiment, a distance D (D1 + D2 + D3) from the boundary B to the end E1 in a plan view is equal to or greater than the thickness T1 of the first portion P1 (D ≥ T1). The distance D is preferably 4 μm or more, and more preferably 10 μm.

[0096] Note that Figure 6 and Figure 7The cross-sectional structure shown can also be applied to any position in the peripheral region SA. In one example, the peripheral region SA has Figure 6 and Figure 7 the cross-sectional structure shown. However, for example, the cross-sectional structure near the terminal portion T may be different from that of other regions of the peripheral region SA.

[0097] Next, an example of a manufacturing method of the display device DSP will be described. Figures 8A to 8I is a schematic cross-sectional view showing the manufacturing process of the display device DSP. In Figures 8A to 8I , the display region DA is mainly focused on, and elements below the organic insulating layer 12 are omitted.

[0098] When forming the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10. Next, as Figure 8A shown, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12.

[0099] Next, as Figure 8B shown, a rib layer 5 covering the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3 is formed. The rib layer 5 can be formed, for example, by CVD (Chemical Vapor Deposition).

[0100] In addition, as Figure 8C shown, a partition wall 6A is formed on the rib layer 5. Specifically, first, a layer serving as a base for the bottom layer 63, the shaft layer 64, and the upper portion 62 is formed, and these layers are patterned by etching. It should be noted that Figures 5 to 7 the partition wall 6B shown is formed by the same process as the partition wall 6A.

[0101] After forming the partition walls 6A and 6B, as Figure 8D shown, pixel openings AP1, AP2, and AP3 are formed in the rib layer 5 by dry etching. It should be noted that in addition to this process, the rib layer 5 is also subjected to dry etching multiple times. For example, these dry etchings include etching for forming an opening of the contact portion CN1 in the rib layer 5 in the peripheral region SA.

[0102] After forming the rib layer 5 and the partition walls 6A and 6B, a process for forming the display elements DE1, DE2, and DE3 is performed. In the present embodiment, it is assumed that the display element DE1 is formed first, then the display element DE2 is formed, and finally the display element DE3 is formed. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0103] When forming the display element DE1, first, as Figure 8EAs shown, a stacked film FL1 and a sealing layer SE11 are formed. As Figure 3 shown, the stacked film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 that covers the organic layer OR1, and a cover layer CP1 that covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cover layer CP1 are formed by evaporation. In addition, the sealing layer SE11 is formed by CVD.

[0104] The stacked film FL1 and the sealing layer SE11 are formed not only in the display area DA but also in the peripheral area SA. The stacked film FL1 is partitioned into a plurality of parts by the cantilever-shaped partitions 6A and 6B. The sealing layer SE11 continuously covers the partitioned parts of the stacked film FL1 and the partitions 6A and 6B.

[0105] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, as Figure 8F shown, a resist R is disposed on the sealing layer SE11. The resist R covers the sub-pixel SP1 and a part of the surrounding partition 6A.

[0106] Then, by etching using the resist R as a mask, as Figure 8G shown, the portions of the stacked film FL1 and the sealing layer SE11 that are exposed from the resist R are removed. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are left, and the other portions are removed. Thus, a display element DE1 is formed in the sub-pixel SP1. This etching may include wet etching and dry etching sequentially performed on the sealing layer SE11, the cover layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R is removed.

[0107] The display element DE2 is formed in the same steps as the display element DE1. That is, when forming the display element DE2, the stacked film FL2 and the sealing layer SE12 are formed over the entire display area DA and the peripheral area SA. As Figure 3 shown, the stacked film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 that covers the organic layer OR2, and a cover layer CP2 that covers the upper electrode UE2.

[0108] The organic layer OR2, the upper electrode UE2, and the cover layer CP2 are formed by evaporation. In addition, the sealing layer SE12 is formed by CVD. The stacked film FL2 is partitioned into a plurality of parts by the cantilever-shaped partitions 6A and 6B. The sealing layer SE12 continuously covers the partitioned parts of the stacked film FL2 and the partitions 6A and 6B. By patterning such a stacked film FL2 and the sealing layer SE2, as Figure 8H shown, a display element DE2 is formed in the sub-pixel SP2.

[0109] The display element DE3 is formed by the same steps as the display elements DE1 and DE2. That is, when forming the display element DE3, the stacked film FL3 and the sealing layer SE13 are formed over the entire display area DA and the peripheral area SA. As Figure 3 shown, the stacked film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 that covers the organic layer OR3, and a cover layer CP3 that covers the upper electrode UE3.

[0110] The organic layer OR3, the upper electrode UE3, and the cover layer CP3 are formed by vapor deposition. In addition, the sealing layer SE13 is formed by CVD. The stacked film FL3 is partitioned into a plurality of parts by the cantilever-shaped partition walls 6A and 6B. The sealing layer SE13 continuously covers the partitioned parts of the stacked film FL3 and the partition walls 6A and 6B. By patterning such a stacked film FL3 and the sealing layer SE13, as Figure 8I shown, the display element DE3 is formed in the sub-pixel SP3.

[0111] After forming the display elements DE1, DE2, and DE3, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in Figure 3 sequence are formed.

[0112] Figures 5 to 7 The stacked film FL shown in is, for example, the stacked film FL1 that is formed first among the stacked films FL1, FL2, and FL3. Similarly, the sealing layer SE1 is the sealing layer SE11 that is formed first among the sealing layers SE11, SE12, and SE13. Thus, when the initially formed sealing layer SE11 remains in the peripheral area SA, the peripheral area SA can be protected from the influence of etching when forming the display elements DE2 and DE3.

[0113] As another example, the stacked film FL may be the stacked film FL3 that is formed last among the stacked films FL1, FL2, and FL3. Similarly, the sealing layer SE1 may be the sealing layer SE13 that is formed last among the sealing layers SE11, SE12, and SE13.

[0114] Sometimes, the adhesion between the stacked films FL1, FL2, and FL3 formed by vapor deposition and the substrate is poor. Therefore, when manufacturing the display device DSP, the stacked films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 that cover them may peel off from the substrate.

[0115] The above peeling is likely to occur when the stacked films FL1, FL2, and FL3 are continuously and widely formed. In the display area DA, the stacked films FL1, FL2, and FL3 are finely partitioned by the partition walls 6A. Therefore, the above peeling is suppressed.

[0116] In addition, in the present embodiment, a partition wall 6B having a plurality of openings A is disposed in the peripheral region SA. As a result, in the peripheral region SA, the laminated films FL1, FL2, and FL3 are also finely partitioned, and the above-described peeling is suppressed.

[0117] In addition, if it is Figure 7 the configuration shown, the effects described below can be obtained, for example.

[0118] Figure 9 is a schematic cross-sectional view of the peripheral region SA of a comparative example of the present embodiment. In the example of this figure, compared with the example of Figure 7 , the end E1 of the partition wall 6B is located near the dam portion DM1. Specifically, the end E1 is located between the end E0 of the organic insulating layer 12 and the dam portion DM1 and faces the side surface of the dam portion DM1.

[0119] If such a configuration is adopted, for example, when forming the pixel openings AP1, AP2, and AP3 in the rib layer 5, it is difficult to fill the narrow region between the end E1 and the dam portion DM1 with the resist. If a void is generated due to insufficient filling of the resist in this region, there is a possibility that the void expands and the resist breaks when the resist is dried in a reduced-pressure environment. If such an abnormal shape of the resist occurs, the rib layer 5 cannot be etched normally.

[0120] In addition, when the stripping liquid for stripping the resist flows in the narrow region between the end E1 and the dam portion DM1, stress is likely to concentrate on the end E1. As a result, at the end E1, the upper portion 62 is pressed upward, and the upper portion 62 may be peeled off from the shaft layer 64. Thus, if an abnormal shape occurs at the end E1 of the partition wall 6B, it is likely to cause peeling of the subsequently formed laminated film FL and the sealing layer SE1.

[0121] In contrast, in the present embodiment, as shown in Figure 7 , the end E1 is located above the organic insulating layer 12 and is separated from the dam portion DM1. If such a configuration is adopted, it is easy to fill the resist in the region between the end E1 and the dam portion DM1. In addition, since stress concentration of the stripping liquid as in the comparative example is not likely to occur, an abnormal shape of the end E1 is also suppressed. As a result, peeling of the laminated film FL and the sealing layer SE1 can also be suppressed.

[0122] It should be noted that, from the viewpoint of forming a well-shaped end E1, it is preferable that the upper surface of the organic insulating layer 12 serving as the base of the end E1 is flat. Regarding this point, as used Figure 7As described, if the distance D is greater than or equal to the thickness T1 of the first part P1 of the organic insulating layer 12 or greater than or equal to 4 μm, the end portion E1 can be formed on the flat upper surface while avoiding the influence of the step portion 12a.

[0123] Thus, according to the present embodiment, peeling of the stacked film FL in the peripheral region SA and abnormal shapes of the resist can be suppressed, and the yield of the display device DSP can be improved. In addition, intrusion of moisture into the interior of the display device DSP can be suppressed, and the reliability of the display device DSP can be enhanced.

[0124] Figure 10 FIG. is a schematic plan view of a display device DSP according to a modified example of the present embodiment. In the example of this figure, the substrate 10, the display region DA, and the dam portions DM1, DM2, DM3, and DM4 are rectangular. Thus, even when the substrate 10 and the display region DA are other than circular, the configuration shown can be applied to the peripheral region SA. Figures 5 to 7 as shown.

[0125] As described above, based on the display device described as an embodiment of the present invention, all display devices that can be implemented by those skilled in the art through appropriate design changes also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0126] Within the scope of the idea of the present invention, various modified examples can be conceived by those skilled in the art, and these modified examples should also be understood to fall within the scope of the present invention. For example, a solution obtained by appropriately adding, deleting, or changing the design of the constituent elements in the above-described embodiments, or a solution obtained by adding, omitting, or changing the conditions of the process also falls within the scope of the present invention as long as it conforms to the gist of the present invention.

[0127] In addition, with regard to other effects brought about by the solutions described in the above embodiments, effects that can be clearly understood from the description of this specification or technical effects that can be appropriately conceived by those skilled in the art should of course be understood as effects brought about by the present invention.

Claims

1. A display device comprising: A substrate having a display area for displaying an image and a peripheral area around the display area; An organic insulating layer, which is arranged in the display area and the peripheral area; A plurality of display elements arranged in the display area, each of the plurality of display elements comprising a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a first partition wall disposed in the display region and disposed between adjacent display elements; a second partition wall disposed in the peripheral region and connected to the first partition wall; and a dam portion disposed in the peripheral region and surrounding the organic insulating layer and the second partition wall, The first partition wall and the second partition wall include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. An end portion of the second partition wall is located above the organic insulating layer and is separated from the dam portion.

2. The display device according to claim 1, wherein: The second partition wall surrounds the display area together with the dam portion.

3. The display device according to claim 1, wherein: The dam portion is formed of the same material as the organic insulating layer.

4. The display device according to claim 1, wherein: The organic insulating layer comprises: Part 1; and The second portion is formed on the periphery of the first portion and is thinner than the first portion.

5. The display device according to claim 4, wherein: The end portion of the second partition wall is located above the first portion.

6. The display device according to claim 5, wherein: A distance from a boundary between the first portion and the second portion to the end portion of the second partition wall in a plan view is equal to or greater than a thickness of the first portion.

7. The display device according to claim 5, wherein: A distance from a boundary between the first portion and the second portion to the end of the second partition wall in a plan view is 4 μm or more.

8. The display device according to claim 1, further comprising a rib layer, the rib layer being formed of an inorganic insulating material and being located below the second partition wall. The rib layer covers the dam portion.

9. The display device according to claim 8, further comprising a first sealing layer covering a laminated film including the organic layer and the upper electrode, The laminated film and a portion of the first sealing layer are disposed in the peripheral region.

10. The display device according to claim 9, wherein: The ends of the laminated film and the first sealing layer are located between the end of the second partition wall and the dam portion.

11. The display device according to claim 10, wherein: The end portions of the stacked film and the first sealing layer are located above the organic insulating layer.

12. The display device according to claim 10, wherein: The laminated film is partitioned by the end portion of the second partition wall.

13. The display device according to claim 12, further comprising a first resin layer, wherein the first resin layer covers the first sealing layer. The end portions of the laminated film and the first sealing layer are covered with the first resin layer.

14. The display device according to claim 13, further comprising a second sealing layer, wherein the second sealing layer covers the first resin layer. The second sealing layer is in contact with the rib layer in a region outside an end portion of the first resin layer. 15 . The display device according to claim 14 , further comprising a second resin layer, wherein the second resin layer covers the second sealing layer.

16. The display device according to claim 1, further comprising: a power supply line disposed in the peripheral area; and A conductive relay layer is disposed in the peripheral region and connects the second partition wall and the power supply line.

17. The display device according to claim 16, wherein: The second partition wall is in contact with the relay layer at a first contact portion overlapping with the organic insulating layer in a plan view.

18. The display device according to claim 17, wherein: The relay layer contacts the power supply line at a second contact portion located between an end portion of the organic insulating layer and the dam portion in a plan view.

19. The display device according to any one of claims 1 to 18, wherein: The display area is circular. The dam portion has an arc-shaped curved portion along the display area.

20. The display device according to claim 19, further comprising a terminal portion arranged in the peripheral area, The dam portion further includes a straight line portion connecting both ends of the curved portion. The straight line portion is located between the display area and the terminal portion in a plan view.

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