Display device and method for manufacturing same

Abstract

The invention relates to a display device and a method for manufacturing the same. The display device according to an embodiment includes: a substrate; a first bottom electrode disposed on the substrate and having a first end portion; a first insulating layer disposed on the first bottom electrode; a second bottom electrode disposed on the first insulating layer and overlapping the first bottom electrode in a plan view; a second insulating layer disposed on the second bottom electrode; and a transistor including an active layer disposed on the second insulating layer, the transistor further including a gate electrode overlapping the active layer, in which the second bottom electrode overlaps the active layer in a plan view and has a second end adjacent to the first end, and the first end and the second end do not overlap in the plan view.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0188785, filed with the Korean Intellectual Property Office on December 21, 2023, the entire contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device and a method of manufacturing the same. Background art

[0004] With the development of the information - oriented society, there is an increasing demand for display devices for displaying images in various ways. Along with this trend, various types of display devices including light - emitting display devices are being developed. A display device may include transistors for controlling the operation of pixels. Summary of the invention

[0005] Aspects of the present disclosure provide a display device and a method of manufacturing the same that can improve the operating characteristics of transistors.

[0006] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other embodiments of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to an aspect of the present disclosure, a display device may be provided, which may include: a substrate; a first bottom electrode disposed on the substrate and having a first end; a first insulating layer disposed on the first bottom electrode; a second bottom electrode disposed on the first insulating layer, the second bottom electrode overlapping the first bottom electrode in a plan view; a second insulating layer disposed on the second bottom electrode; and a transistor including an active layer disposed on the second insulating layer, the transistor may include a gate electrode overlapping the active layer in a plan view. The second bottom electrode may overlap the active layer in a plan view, and may have a second end adjacent to the first end, and the first end and the second end may not overlap in a plan view.

[0008] In an embodiment, the first end and the second end may be spaced apart from each other by at least about 0.6 μm in a plan view.

[0009] In an embodiment, a part of the second bottom electrode may overlap the first end, and the second end may extend from a part of the second bottom electrode to the outside of the first end.

[0010] In an embodiment, a part of the first bottom electrode may overlap the second end, and the first end may extend from a part of the first bottom electrode to the outside of the second end.

[0011] In an embodiment, the first bottom electrode may include a first metal layer containing aluminum (Al) and a second metal layer disposed on the first metal layer, and the second metal layer may contain titanium (Ti).

[0012] In an embodiment, the first bottom electrode may further include a third metal layer disposed under the first metal layer, and the third metal layer may contain titanium (Ti).

[0013] In an embodiment, the second metal layer may completely cover the top surface of the first metal layer, and the third metal layer may completely cover the bottom surface of the first metal layer.

[0014] In an embodiment, the second bottom electrode may include a first metal layer containing aluminum (Al) and a second metal layer disposed on the first metal layer, and the second metal layer may contain titanium (Ti).

[0015] In an embodiment, the second bottom electrode may further include a third metal layer disposed under the first metal layer, and the third metal layer may contain titanium (Ti).

[0016] In an embodiment, the second metal layer may completely cover the top surface of the first metal layer, and the third metal layer may completely cover the bottom surface of the first metal layer.

[0017] In an embodiment, the second insulating layer may include a first layer containing silicon nitride and a second layer disposed on the first layer, and the second layer may contain silicon oxide or silicon oxynitride.

[0018] In an embodiment, the thickness of the first layer may be greater than the thickness of the second layer.

[0019] In an embodiment, the first layer may have a thickness in the range of about to about

[0020] In an embodiment, the active layer may contain an oxide semiconductor.

[0021] In an embodiment, the display device may further include a gate insulating layer disposed between the active layer and the gate electrode, the gate insulating layer may cover a part of the active layer including a part overlapping with the gate electrode, and expose another part of the active layer.

[0022] In an embodiment, the transistor may further include a source electrode disposed on the third insulating layer, the third insulating layer may be disposed on the gate electrode, and the second bottom electrode may be electrically connected to the source electrode.

[0023] ​In an embodiment, the third insulating layer may include a first layer containing silicon oxide or silicon oxynitride and a second layer provided on the first layer, and the second layer may contain silicon nitride.

[0024] In an embodiment, the display device may further include a light-emitting element electrically connected to the transistor.

[0025] According to an aspect of the present disclosure, a method for manufacturing a display device may be provided, the method including: forming a first bottom electrode on a substrate, the first bottom electrode may have a first end; forming a first insulating layer on the first bottom electrode, forming a second bottom electrode on the first insulating layer, the second bottom electrode may overlap the first bottom electrode in a plan view, and the second bottom electrode may have a second end adjacent to the first end; forming a second insulating layer on the second bottom electrode; and forming a transistor on the second insulating layer, the transistor may include an active layer overlapping the second bottom electrode in a plan view, wherein the first end and the second end may not overlap in the plan view.

[0026] In an embodiment, the first end and the second end may be spaced apart from each other by at least about 0.6 μm in the plan view.

[0027] According to the display device and the method for manufacturing the display device according to an embodiment, it may be possible to prevent or block hydrogen from being introduced into the active layer of the transistor. Accordingly, the operating characteristics of the transistor may be improved, and the image quality of the display device may be improved.

[0028] However, the effects according to the embodiments of the present disclosure are not limited to the effects of the above examples, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0030] Figure 1 is a plan view showing a display device according to an embodiment;

[0031] Figure 2 is a plan view showing Figure 1 of the display panel;

[0032] Figure 3 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment;

[0033] Figure 4 is a schematic cross-sectional view showing a display panel according to an embodiment;

[0034] Figure 5 is a detailed schematic cross-sectional view showing Figure 4 region A of;

[0035] Figure 6 is a schematic cross-sectional view showing in detail Figure 4 region A;

[0036] Figure 7 is a schematic cross-sectional view showing a display panel according to an embodiment;

[0037] Figure 8 is a schematic cross-sectional view showing in detail Figure 7 region C;

[0038] Figure 9 is a schematic cross-sectional view showing in detail Figure 7 region C; and

[0039] Figures 10 to 18 is a schematic cross-sectional view showing a method for manufacturing a display device according to an embodiment. Detailed Embodiments

[0040] In the following description, for the purpose of illustration, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable terms that are non-limiting examples of the devices or methods disclosed herein. However, it will be apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, the various embodiments are not necessarily exclusive and do not limit the present disclosure. For example, the specific shapes, configurations, and characteristics of an embodiment can be used or implemented in another embodiment.

[0041] Unless otherwise specified, the illustrated embodiments are to be understood as providing features of the present disclosure. Thus, unless otherwise specified, without departing from the inventive concept, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments can be otherwise combined, separated, interchanged, and / or rearranged.

[0042] The use of cross-hatching and / or shading in the figures is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, scale, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements. In addition, in the figures, for clarity and / or descriptive purposes, the dimensions and relative dimensions of the elements may be exaggerated. When the embodiments can be implemented differently, the specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously, or in an order opposite to the described order. In addition, like reference numerals and / or reference signs denote like elements.

[0043] When an element such as a layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there can be intervening elements or layers. However, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. For this reason, the term “connected” can refer to physical connection, electrical connection, and / or fluid connection with or without intervening elements. In addition, the first direction D1, the second direction D2, and the third direction D3 are not limited to the directions corresponding to the three axes such as the x-axis, the y-axis, and the z-axis of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the first direction D1, the second direction D2, and the third direction D3 can be perpendicular to each other, or can be different directions that are not perpendicular to each other.

[0044] For the purposes of the present disclosure, “at least one of A and B” can be interpreted as only A, only B, or any combination of A and B. In addition, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term “and / or” includes any combination and all combinations of one or more of the associated listed items.

[0045] Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element.

[0046] For descriptive purposes, spatial relative terms such as "below", "beneath", "under", "lower", "above", "upper", "on", "over", "higher", "side" (e.g., as in "sidewall") may be used herein, and thereby to describe the relationship of one element to another(s) as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is turned over, an element described as "below" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the term "below" can encompass both an orientation of above and below. Further, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatial relative descriptors used herein should be interpreted accordingly.

[0047] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, when used in this specification, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and are thus used to interpret the inherent deviations in measured, calculated, and / or provided values that would be recognized by a person of ordinary skill in the art.

[0048] Various embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic illustrations of embodiments and / or intermediate structures. Accordingly, variations in the shape of the figures due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the particular shapes of regions shown, but should include, for example, shape deviations resulting from manufacturing. In this manner, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shape of regions of the device, and thus are not necessarily intended to be limiting.

[0049] As is customary in the art, for functional blocks, units, and / or modules, some embodiments are described and illustrated in the drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electrical circuits (or optical circuits) such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connectors, etc., which can be formed using semiconductor-based manufacturing technologies or other manufacturing technologies. In the case where the blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be selectively driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. Additionally, without departing from the scope of the inventive concept, each block, unit, and / or module in some embodiments can be physically separated into two or more interacting and discrete blocks, units, and / or modules. Further, without departing from the scope of the inventive concept, the blocks, units, and / or modules in some embodiments can be physically combined into more complex blocks, units, and / or modules.

[0050] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the relevant art and the context of this disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0051] Figure 1 is a plan view showing a display device 100 according to an embodiment. Figure 2 is showing Figure 1 of the display panel 110.

[0052] Reference Figure 1 and Figure 2, the display device 100 can be a device for displaying moving images or still images. The display device 100 can be used as various devices such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IoT) device, as well as a display screen for portable electronic devices such as a mobile phone, a smartphone, a tablet personal computer (PC), a smartwatch, a watch phone, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC). These are presented only as examples, and the display device 100 can be applied to various other types of electronic devices.

[0053] In an embodiment, the display device 100 can be a light-emitting display device such as an organic light-emitting display including an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or an ultra-small light-emitting display including ultra-small light-emitting diodes such as micro light-emitting diodes or nano light-emitting diodes (micro-LED or nano-LED), but is not limited thereto. For example, the display device 100 can be another type of display device other than a light-emitting display device. In the following, embodiments in which the display device 100 can be a light-emitting display device (e.g., an organic light-emitting display device) will be disclosed.

[0054] The display device 100 can include a display panel 110 that includes pixels PX and first and second drivers 120 and 130 configured to provide driving signals to the pixels PX. The display device 100 can also include additional components. For example, the display device 100 can also include a power supply section for providing a power voltage to the pixels PX, the first driver 120, and the second driver 130, and a timing controller for controlling the operations of the first driver 120 and the second driver 130.

[0055] The display panel 110 can include a display area DA and a non-display area NDA. The display area DA can be an area including pixels PX for displaying an image. For example, the display area DA can include a pixel area where the pixels PX can be arranged. The non-display area NDA can be an area other than the display area DA, and an image can not be displayed in the non-display area NDA. In an embodiment, the non-display area NDA can be located around the display area DA and can surround the display area DA.

[0056] In Figure 1 and Figure 2 , a first direction D1, a second direction D2, and a third direction D3 can be defined. In an embodiment, the first direction D1 can be the horizontal direction of the display panel 110, and the second direction D2 can be the vertical direction of the display panel 110. The third direction D3 can be the thickness direction of the display panel 110.

[0057] In an embodiment, the display panel 110 may have a rectangular shape in a plan view. Although Figure 1 and Figure 2 the display panel 110 shown has a horizontal length longer than the vertical length, the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may have a shape with a vertical length longer than the horizontal length, a square shape, etc. The display panel 110 may include angled corners or rounded corners.

[0058] The planar shape of the display panel 110 is not limited to the shown quadrilateral shape, and it may be applied in other shapes. For example, the display panel 110 may have a non - quadrilateral polygon shape, a circular shape, an elliptical shape, an atypical shape, or other shapes in a plan view.

[0059] In an embodiment, the display panel 110 may be substantially flat on a plane defined by a first direction D1 and a second direction D2, and may have a uniform thickness in a third direction D3. In another example, the display panel 110 may be provided in a three - dimensional shape with a curved surface or the like.

[0060] The display panel 110 may be set as a rigid panel so as not to transform substantially, or set as a flexible panel that can be transformed into at least partially folded, bent, or curled. The display panel 110 may be provided to the display device 100 without being bent, or may be provided to the display device 100 while being partially bent.

[0061] The display panel 110 may include a substrate SUB and pixels PX provided on the substrate SUB. The pixels PX may be provided in a display area DA on the substrate SUB.

[0062] The substrate SUB, which can be a basic member for manufacturing or providing the display panel 110, may form the basic surface of the display panel 110. The substrate SUB may include a display area DA and a non - display area NDA around the display area DA.

[0063] According to an embodiment, the display area DA may have various shapes. For example, the display area DA may have a quadrilateral shape, a non - quadrilateral polygon shape, a circular shape, an elliptical shape, an atypical shape, or other shapes. In an embodiment, the display area DA may have a shape consistent with the shape of the display panel 110.

[0064] The pixels PX may be set and / or arranged in the display area DA. For example, the display area DA may include a plurality of pixel areas in which corresponding pixels PX can be set.

[0065] In an embodiment, the display device 100 may be a light-emitting display device, and each pixel PX may include a light-emitting element located in each emission region and a pixel circuit electrically connected to the light-emitting element. When describing the embodiment, the term "connected" may include electrical connection and / or physical connection. Each pixel circuit may include transistors (e.g., transistors including a driving transistor that generates a driving current corresponding to a data signal and at least one switching transistor) and at least one capacitor (e.g., a capacitor including a storage capacitor).

[0066] The non-display area NDA may include a pad area PA where pads PD may be provided. In an embodiment, the non-display area NDA may further include a driving circuit area located on at least one side of the display area DA. At least one driver, pads PD, and / or wirings may be provided in the non-display area NDA.

[0067] At least one driver or a part of the driver for driving the pixels PX may be provided in the driving circuit area. For example, circuit elements constituting the first driver 120 (e.g., driving transistors and driving capacitors of the stage circuits constituting the first driver 120) may be provided in the driving circuit area on the substrate SUB. In an embodiment, the circuit elements of the first driver 120 may be formed together with the pixels PX in the display panel 110. In an embodiment, the driving transistors provided in the first driver 120 may be transistors having a type and / or structure that is substantially the same as or similar to the type and / or structure of the transistors provided in the pixels PX, and may be formed simultaneously with the transistors of the pixels PX.

[0068] The pads PD may be provided in the pad area PA. At least one circuit board 140 may be provided and / or bonded in the pad area PA. In an embodiment, a plurality of circuit boards 140 electrically connected to different pads PD may be provided in the pad area PA. The pads PD may include signal pads and power pads for transmitting driving signals and power voltages required to drive the pixels PX and / or the first driver 120 into the display panel 110.

[0069] The first driver 120 and the second driver 130 can generate driving signals for controlling the operation timing, brightness, etc. of the pixel PX, and can supply the generated driving signals to the pixel PX. For example, the first driver 120 can be a gate driver including a scan driver and can be electrically connected to the pixel PX through a corresponding gate line. The first driver 120 can supply a corresponding gate signal (e.g., a control signal for controlling the driving timing of the pixel PX, including a scan signal and / or an emission control signal) to the pixel PX. The second driver 130 can be a data driver including a source driver circuit and can be electrically connected to the pixel PX through a corresponding data line. The second driver 130 can supply a corresponding data signal to the pixel PX.

[0070] In an embodiment, at least one of the first driver 120 and the second driver 130 or a part of at least one of the drivers can be embedded in the display panel 110. For example, the first driver 120 or a part of the first driver 120 can be disposed and / or formed in the non-display area NDA and disposed on the substrate SUB of the display panel 110.

[0071] Although Figure 1 it is shown that the first driver 120 can be formed on one side of the display area DA (e.g., in the non-display area NDA on the right side of the display area DA), the embodiment is not limited thereto. For example, the first driver 120 can be only located on the other side of the display area DA (e.g., in the non-display area NDA on the left side of the display area DA), or can be located on both sides of the display area DA (e.g., in the non-display areas NDA on the left and right sides of the display area DA). In other examples, a part of the first driver 120 can be located in the non-display area NDA, and another part of the first driver 120 can be located in a non-emission area inside the display area DA (e.g., an area between the emission areas of the pixels PX).

[0072] In an embodiment, the other driver or a part of the other driver of the first driver 120 and the second driver 130 can be disposed or formed outside the display panel 110 to be electrically connected to the display panel 110. For example, the second driver 130 can be implemented as a plurality of integrated circuit chips that can be disposed on a circuit board 140 electrically connected to the pixel PX of the display panel 110. The second driver 130 can be implemented as at least one integrated circuit chip and mounted in the non-display area NDA of the display panel 110.

[0073] The circuit board 140 can be electrically connected to the display panel 110 through the pads PD. In an embodiment, the circuit board 140 can be a flexible film such as a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a chip on film (COF), but is not limited thereto. In an embodiment, the circuit board 140 can be electrically connected to the timing controller and / or the power supply section through another circuit board, a connector, etc.

[0074] Figure 3 is a schematic diagram of an equivalent circuit of the pixel PX according to an embodiment. For example, Figure 3 shows a pixel PX including a light-emitting element ED of the light-emitting display device. In addition to Figure 3 the embodiments of, the type and / or structure of the pixel PX that can be included in the display device 100 can vary variously according to the embodiments.

[0075] In addition to Figure 1 and Figure 2 in addition to, referring to Figure 3 , the pixel PX can include a light-emitting element ED and a pixel circuit PC electrically connected to the light-emitting element ED. The light-emitting element ED can be a light source of the pixel PX, and it can be, for example, an organic light-emitting diode, but is not limited thereto. The pixel circuit PC can control the emission time point and brightness of the light-emitting element ED.

[0076] The pixel circuit PC can include a transistor T and at least one capacitor C. For example, the pixel circuit PC can include a first transistor T1 to a fifth transistor T5 and a first capacitor C1 and a second capacitor C2. Although Figure 3 shows an embodiment in which all the transistors T can be N-type transistors, the type of the transistor T is not limited thereto. For example, at least one transistor T can be formed of a P-type transistor.

[0077] The pixel circuit PC can provide a drive current Id to the light-emitting element ED in response to drive signals provided from the first driver 120 and the second driver 130. For example, the pixel circuit PC can provide a drive current Id to the light-emitting element ED in response to a corresponding gate signal GS provided from the first driver 120 through a corresponding gate line GL and a data signal DATA provided from the second driver 130 through a data line DL.

[0078] The first transistor T1 may be a driving transistor of the pixel PX whose magnitude of the drain-source current (e.g., driving current Id) can be determined according to the gate-source voltage. The second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be switching transistors that can be turned on or off according to corresponding gate-source voltages. According to the type (e.g., P-type or N-type) and / or operating conditions of each of the first transistor T1 to the fifth transistor T5, the first electrode of each of the first transistor T1 to the fifth transistor T5 may be a drain electrode (or drain region) or a source electrode (or source region), and its second electrode may be an electrode different from the first electrode. For example, in the case where the first electrode is a drain electrode, the second electrode may be a source electrode.

[0079] The pixel PX may be electrically connected to a first gate line GWL that transmits a first gate signal GW (e.g., a scan signal), a second gate line GIL that transmits a second gate signal GIN, a third gate line GRL that transmits a third gate signal GR, an emission control line ECL that transmits an emission control signal EM, and a data line DL that transmits a data signal DATA. In addition, the pixel PX may be electrically connected to a first power line VDL that transmits a first pixel voltage ELVDD (also referred to as "first pixel power voltage") and a second power line VSL that transmits a second pixel voltage ELVSS (also referred to as "second pixel power voltage"). In an embodiment, the pixel PX may also be electrically connected to an initialization power line VIL that transmits an initialization voltage VINT (also referred to as "third pixel power voltage") and a reference power line VRL that transmits a reference voltage VREF (also referred to as "fourth pixel power voltage").

[0080] In an embodiment, the first transistor T1 to the fifth transistor T5 may be located in each pixel region and may be oxide transistors (also referred to as "oxide semiconductor transistors") including an oxide semiconductor (e.g., an oxide semiconductor material). For example, the active layer of each of the first transistor T1 to the fifth transistor T5 may include an oxide semiconductor. However, the embodiment is not limited thereto. For example, at least one transistor T may be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polycrystalline silicon).

[0081] The oxide semiconductor may have a high carrier mobility and a low leakage current, such that even if the driving time of the oxide transistor increases, a significant voltage drop may not occur. For example, the pixel PX including the oxide transistor may be driven at a low frequency because even when driven at a low frequency, the change in the brightness and / or color of the image due to the voltage drop may not be significant. In the case where the first transistor T1 to the fifth transistor T5 are formed of oxide transistors, the leakage current of the pixel PX may be reduced or prevented, and the power consumption may be reduced.

[0082] Oxide semiconductors may be sensitive to light, such that the amount of electric current or the like can be changed due to external light. In an embodiment, a light-blocking pattern or a light-blocking electrode (e.g., a bottom electrode or a back gate electrode) may be provided under an active layer included in at least one transistor T to block external light. Accordingly, the operating characteristics of the transistor T can be stabilized.

[0083] The first transistor T1 may include a gate electrode electrically connected to a first node N1, a first electrode (e.g., a drain electrode) electrically connected to a second node N2, and a second electrode (e.g., a source electrode) electrically connected to a third node N3. The first electrode of the first transistor T1 may be electrically connected to a first power line VDL via a fifth transistor T5, and its second electrode may be electrically connected to a light-emitting element ED. The first transistor T1 may control the magnitude (e.g., the amount of electric current) of a driving current Id flowing to the light-emitting element ED to correspond to a data signal DATA transmitted to the first node N1.

[0084] In an embodiment, the first transistor T1 may further include a bottom electrode BE (e.g., Figure 4 the second bottom electrode BE2 in ) electrically connected to the third node N3. In a case where the first transistor T1 may be formed of a transistor having a double gate structure by connecting the bottom electrode BE of the first transistor T1 to the third node N3 (e.g., a double gate transistor having a source synchronous structure), the operating characteristics of the first transistor T1 can be improved.

[0085] The second transistor T2 may include a gate electrode electrically connected to a first gate line GWL, a first electrode electrically connected to a data line DL, and a second electrode electrically connected to the first node N1. The second transistor T2 may be turned on by a first gate signal GW (e.g., a first gate signal GW of a gate conduction voltage) transmitted to the first gate line GWL to connect the data line DL and the first node N1. Accordingly, the data signal DATA transmitted through the data line DL can be sent to the first node N1.

[0086] The third transistor T3 may include a gate electrode electrically connected to a third gate line GRL, a first electrode electrically connected to a reference power line VRL, and a second electrode electrically connected to the first node N1. The third transistor T3 may be turned on by a third gate signal GR transmitted through the third gate line GRL and transmit a reference voltage VREF transmitted to the reference power line VRL to the first node N1.

[0087] The fourth transistor T4 may include a gate electrode electrically connected to the second gate line GIL, a first electrode electrically connected to the third node N3, and a second electrode electrically connected to the initialization power line VIL. The fourth transistor T4 may be turned on by a second gate signal GIN transmitted through the second gate line GIL, and transmit an initialization voltage VINT transmitted to the initialization power line VIL to the third node N3.

[0088] The fifth transistor T5 may include a gate electrode electrically connected to the emission control line ECL, a first electrode electrically connected to the first power line VDL, and a second electrode electrically connected to the second node N2 (or the first electrode of the first transistor T1). The fifth transistor T5 may be turned on by an emission control signal EM (e.g., an emission control signal EM of a gate turn-on voltage) transmitted to the emission control line ECL to control the emission time point of the pixel PX.

[0089] Each of the second transistor T2 to the fifth transistor T5 may or may not include a bottom electrode. In an embodiment, at least one switching transistor among the second transistor T2 to the fifth transistor T5 may include a bottom electrode, and the bottom electrode of at least one switching transistor may be electrically connected to the gate electrode of the corresponding switching transistor. In the case where the bottom electrode of the switching transistor is electrically connected to the gate electrode, it may be possible to improve the cutoff characteristics and switching speed of the switching transistor, ensure an additional voltage tolerance range, reduce leakage current, and improve voltage stability. For example, since the switching transistor formed of an oxide transistor having a short channel length may be formed in a double gate structure such as a gate synchronous structure, the operating characteristics of the switching transistor may be improved.

[0090] The first capacitor C1 may be electrically connected between the first node N1 and the third node N3. The first capacitor C1 may be a storage capacitor of the pixel PX, and may store the threshold voltage of the first transistor T1 and a voltage (e.g., a data voltage) corresponding to the data signal DATA therein.

[0091] The second capacitor C2 may be electrically connected between the first power line VDL and the third node N3. In an embodiment, the capacitance of the second capacitor C2 may be smaller than the capacitance of the first capacitor C1.

[0092] The light-emitting element ED can be electrically connected between the third node N3 and the second power line VSL. For example, the light-emitting element ED can include a first electrode (e.g., an anode electrode) electrically connected to the third node N3, a second electrode (e.g., a cathode electrode) facing the first electrode and electrically connected to the second power line VSL, and a light-emitting layer disposed between the first electrode and the second electrode. In an embodiment, the first electrode of the light-emitting element ED can be an individual electrode separately provided in each pixel PX, and the second electrode of the light-emitting element ED can be a common electrode shared by the pixels PX. During a period in which the drive current Id can be provided from the pixel circuit PC, the light-emitting element ED can emit light having a luminance corresponding to the drive current Id.

[0093] Figure 4 is a schematic cross-sectional view showing a display panel 110 according to an embodiment. For example, Figure 4 shows a part of the display area DA of the display panel 110. Figure 4 shows a light-emitting display panel including a light-emitting element ED (e.g., an organic light-emitting diode) as an example of the display panel 110 to which the embodiment can be applied.

[0094] In addition to Figures 1 to 3 other than, referring to Figure 4 , the display panel 110 can include a substrate SUB (or a base layer), a panel circuit layer PCL (or a thin-film transistor layer), a light-emitting element layer LEL, and a packaging layer ENL. The panel circuit layer PCL, the light-emitting element layer LEL, and the packaging layer ENL can be provided to overlap each other on the substrate SUB. For example, with respect to the display area DA, the panel circuit layer PCL, the light-emitting element layer LEL, and the packaging layer ENL can be sequentially provided on the substrate SUB in the third direction D3. The positions of the panel circuit layer PCL, the light-emitting element layer LEL, and / or the packaging layer ENL can be changed according to the embodiment.

[0095] In an embodiment, the display panel 110 can further include additional elements disposed above and / or below the packaging layer ENL. For example, the display panel 110 can further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a passivation layer (e.g., a passivation film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and the passivation layer can be provided above the packaging layer ENL, or can be provided between the light-emitting element layer LEL and the packaging layer ENL.

[0096] The substrate SUB, which can be a base member for forming the display panel 110, can be a rigid or flexible substrate (or film). In an embodiment, the substrate SUB can be a substrate including an insulating material such as glass and having rigid characteristics, and may not be bendable. In another example, the substrate SUB can be a flexible substrate including polyimide or another insulating material, and can be transformed into a bent, folded, or curled shape, and may or may not be bendable. The type and / or material of the substrate SUB can vary according to the embodiment.

[0097] In an embodiment, the display panel 110 may also optionally include a barrier layer BR disposed between the substrate SUB and the panel circuit layer PCL. For example, the barrier layer BR can be disposed on the substrate SUB, and the panel circuit layer PCL can be disposed on the barrier layer BR, or the panel circuit layer PCL can be disposed (e.g., directly) on the substrate SUB without the barrier layer BR.

[0098] The barrier layer BR can include at least one inorganic insulating layer containing an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials). The barrier layer BR can protect the pixels PX from moisture penetration through the substrate SUB that may be vulnerable to moisture penetration. The material of the barrier layer BR can vary variously according to the embodiment.

[0099] The panel circuit layer PCL can be disposed on the surface of the substrate SUB where the barrier layer BR can be disposed. The panel circuit layer PCL can include circuit elements such as transistors T and capacitors C that include the pixels PX and wirings (e.g., signal lines and power lines). In an embodiment, the panel circuit layer PCL can also include circuit elements of the first driver 120 (e.g., driving transistors and / or driving capacitors disposed in the first driver 120) and / or additional conductive patterns (e.g., bridging patterns).

[0100] Figure 4 The transistor T and the capacitor C disposed in any one pixel region PXA are shown as examples of circuit elements that can be disposed in the panel circuit layer PCL. Figure 4 The transistor T can be a driving transistor or a switching transistor disposed in the pixel circuit PC of the corresponding pixel PX. For example, Figure 4 The transistor T can be Figure 3 The first transistor T1. Figure 4 The capacitor C can be any one capacitor C disposed in the pixel circuit PC of the corresponding pixel PX. For example, Figure 4 The capacitor C can be Figure 3 The first capacitor C1. In an embodiment, Figure 3The second capacitor C2 can be formed around the first transistor T1. For example, the second capacitor C2 can be formed by a first bottom electrode BE1 and a second bottom electrode BE2 under the transistor T.

[0101] The panel circuit layer PCL can include a conductive layer and a semiconductor layer SCL on which circuit elements and wirings can be provided. Electrodes of circuit elements (e.g., the transistor T and the capacitor C) constituting the panel circuit layer PCL and conductive patterns (e.g., the bridge electrode BRE and / or wirings) electrically connected to the electrodes and / or wirings can be provided in the conductive layer. The active layer ACT of the transistor T provided in the panel circuit layer PCL can be provided in the semiconductor layer SCL.

[0102] In an embodiment, the panel circuit layer PCL can include a first conductive layer CDL1 (also referred to as the "first lower conductive layer" or "first bottom conductive layer"), a second conductive layer CDL2 (also referred to as the "second lower conductive layer" or "second bottom conductive layer"), a semiconductor layer SCL, a third conductive layer CDL3 (also referred to as the "gate conductive layer"), and a fourth conductive layer CDL4 (also referred to as the "first source-drain conductive layer" or "first data conductive layer") that can be sequentially provided on the substrate SUB in a third direction D3. In an embodiment, the panel circuit layer PCL can further include a fifth conductive layer CDL5 (also referred to as the "second source-drain conductive layer" or "second data conductive layer") provided on the fourth conductive layer CDL4. For example, the first conductive layer CDL1 and the second conductive layer CDL2 can be provided below the semiconductor layer SCL (e.g., between the substrate SUB and the semiconductor layer SCL), and the third conductive layer CDL3, the fourth conductive layer CDL4, and the fifth conductive layer CDL5 can be provided above the semiconductor layer SCL (e.g., between the semiconductor layer SCL and the light-emitting element layer LEL).

[0103] The corresponding electrodes, conductive patterns, and / or wirings provided on the conductive layers of the panel circuit layer PCL can include at least one conductive material. For example, the electrodes, conductive patterns, and / or wirings provided in each of the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3, the fourth conductive layer CDL4, and the fifth conductive layer CDL5 can include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, their alloys, or other conductive materials. In an embodiment, the electrodes, conductive patterns, and / or wirings provided on the same conductive layer can be formed simultaneously using the same conductive material.

[0104] In an embodiment, each of the electrodes, conductive patterns, and / or wirings provided in the conductive layer of the panel circuit layer PCL may have a single-layer or multi-layer structure. For example, the electrodes, conductive patterns, and / or wirings provided in the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3, the fourth conductive layer CDL4, and the fifth conductive layer CDL5 may have a single-layer or multi-layer structure. In an embodiment, the electrodes, conductive patterns, and / or wirings provided on the same conductive layer may be formed simultaneously using the same material.

[0105] The panel circuit layer PCL may further include a plurality of insulating layers and / or insulating patterns provided on the substrate SUB. For example, the panel circuit layer PCL may include a first insulating layer IL1, a second insulating layer IL2, a gate insulating layer GI, a third insulating layer IL3, a fourth insulating layer IL4, and a fifth insulating layer IL5 that may be sequentially provided on the substrate SUB in the third direction D3.

[0106] The first insulating layer IL1 may be provided between the first conductive layer CDL1 and the second conductive layer CDL2 and may cover the first conductive layer CDL1. For example, the first insulating layer IL1 may be provided on the substrate SUB and on the electrodes (e.g., the first bottom electrode BE1 and the first electrode E1 of the capacitor C), wirings, and / or conductive patterns provided in the first conductive layer CDL1.

[0107] The second insulating layer IL2 may be provided between the second conductive layer CDL2 and the semiconductor layer SCL and may cover the second conductive layer CDL2. For example, the second insulating layer IL2 may be provided on the first insulating layer IL1 and on the electrodes (e.g., the second bottom electrode BE2 and the second electrode E2 of the capacitor C), wirings, and / or conductive patterns provided in the second conductive layer CDL2.

[0108] In an embodiment, the second insulating layer IL2 may be a double-layer or multi-layer insulating layer. For example, the second insulating layer IL2 may include a first layer IL2a provided on the second conductive layer CDL2 and a second layer IL2b provided on the first layer IL2a.

[0109] The gate insulating layer GI may be provided on the second insulating layer IL2 and the semiconductor layer SCL. For example, the gate insulating layer GI may be provided between the second insulating layer IL2 and the semiconductor layer SCL and the third conductive layer CDL3. The gate insulating layer GI may cover a part of each of the second insulating layer IL2 and the semiconductor layer SCL.

[0110] The third insulating layer IL3 may be disposed on the second insulating layer IL2. For example, the third insulating layer IL3 may be disposed between the third conductive layer CDL3 and the fourth conductive layer CDL4. The third insulating layer IL3 may cover the semiconductor layer SCL, the gate insulating layer GI, and the third conductive layer CDL3. For example, the third insulating layer IL3 may be disposed on the active layer ACT provided in the semiconductor layer SCL, the insulating patterns (e.g., the first gate insulating layer GI1 and the second gate insulating layer GI2 that may be integral with each other or separated from each other) provided in the gate insulating layer GI, and the electrodes (e.g., the gate electrode GE of the transistor T and the third electrode E3 of the capacitor C), wirings, and / or conductive patterns provided in the third conductive layer CDL3.

[0111] In an embodiment, the third insulating layer IL3 may be a double-layer or multi-layer insulating layer. For example, the third insulating layer IL3 may include a first layer IL3a disposed on the third conductive layer CDL3 and a second layer IL3b disposed on the first layer IL3a.

[0112] The fourth insulating layer IL4 may be disposed between the fourth conductive layer CDL4 and the fifth conductive layer CDL5, and may cover the fourth conductive layer CDL4. For example, the fourth insulating layer IL4 may be disposed on the third insulating layer IL3 and on the electrodes (e.g., the source electrode SE and the drain electrode DE of the transistor T and the fourth electrode E4 and the fifth electrode E5 of the capacitor C), wirings, and / or conductive patterns provided in the fourth conductive layer CDL4. In an embodiment, the fourth insulating layer IL4 may be a single-layer or multi-layer insulating layer including an organic insulating layer. The fourth insulating layer IL4 may include an inorganic insulating layer or may not include an inorganic insulating layer.

[0113] The fifth insulating layer IL5 may be disposed between the fifth conductive layer CDL5 and the light-emitting element layer LEL, and may cover the fifth conductive layer CDL5. For example, the fifth insulating layer IL5 may be disposed on the fourth insulating layer IL4, and may cover the electrodes (e.g., the bridging electrode BRE electrically connected to the transistor T and the sixth electrode E6 of the capacitor C), wirings, and / or conductive patterns provided in the fifth conductive layer CDL5. In an embodiment, the fifth insulating layer IL5 may be a single-layer or multi-layer insulating layer including an organic insulating layer. The fifth insulating layer IL5 may include an inorganic insulating layer or may not include an inorganic insulating layer.

[0114] In an embodiment, each of the first insulating layer IL1, the second insulating layer IL2, the gate insulating layer GI, and the third insulating layer IL3 may include at least one inorganic insulating layer containing an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, another inorganic insulating material, or a combination thereof). For example, each of the first insulating layer IL1, the second insulating layer IL2, the gate insulating layer GI, and the third insulating layer IL3 may be a single-layer or multi-layer inorganic insulating layer.

[0115] In an embodiment, the first layer IL2a of the second insulating layer IL2 may include silicon nitride, and the second layer IL2b of the second insulating layer IL2 may include silicon oxide or silicon oxynitride. Since the second insulating layer IL2 includes the first layer IL2a and the second layer IL2b made of different materials, the insulating properties of the second insulating layer IL2 can be improved or ensured. For example, by providing at least a double-layer second insulating layer IL2 between the second bottom electrode BE2 and the active layer ACT that overlap each other and the second insulating layer IL2 is disposed therebetween, the second bottom electrode BE2 and the active layer ACT can be stably insulated and defects such as short-circuit defects can be prevented.

[0116] Furthermore, by covering the second conductive layer CDL2 with the first layer IL2a containing silicon nitride having an excellent hydrogen barrier effect, it is possible to effectively block hydrogen from being introduced from the first conductive layer CDL1 and / or the second conductive layer CDL2 into the semiconductor layer SCL. For example, it is possible to block hydrogen from being introduced from at least one of the first bottom electrode BE1 and the second bottom electrode BE2 into the active layer ACT disposed above the first bottom electrode BE1 and the second bottom electrode BE2. Therefore, a change in the characteristics of the transistor T can be prevented, and the operating characteristics of the transistor T can be improved or stabilized. Therefore, defects such as bright spots or dark spots that may occur in the display panel 110 due to deterioration of the operating characteristics of the transistor T can be prevented.

[0117] In an embodiment, the thickness of the first layer IL2a of the second insulating layer IL2 may be greater than the thickness of the second layer IL2b of the second insulating layer IL2. In an embodiment, the first layer IL2a of the second insulating layer IL2 may include silicon nitride, and may be formed with a thickness of at least about to effectively block hydrogen diffusion. For example, the first layer IL2a of the second insulating layer IL2 may be a silicon nitride layer formed with a thickness in the range of about to about . Thus, it is possible to ensure the insulating properties without forming a too thick second insulating layer IL2, and at the same time appropriately block hydrogen from being introduced or diffused into the active layer ACT. Therefore, the active layer ACT can be protected, and the operating characteristics of the transistor T can be improved or ensured.

[0118] In an embodiment, the first layer IL3a of the third insulating layer IL3 may include silicon oxide or silicon oxynitride, and the second layer IL3b of the third insulating layer IL3 may include silicon nitride. By first covering the active layer ACT with the first layer IL3a containing silicon oxide or silicon oxynitride, it may be possible to prevent or reduce the introduction or diffusion of hydrogen from the second layer IL3b of the third insulating layer IL3 into the active layer ACT. In addition, by covering the first layer IL3a with the second layer IL3b containing silicon nitride, it may be possible to block the introduction or diffusion of hydrogen from other surrounding conductive layers, insulating layers, etc. into the active layer ACT. Therefore, the active layer ACT can be stably protected, and the operating characteristics of the transistor T can be improved or ensured.

[0119] In an embodiment, the thickness of the first layer IL3a of the third insulating layer IL3 may be greater than the thickness of the second layer IL3b of the third insulating layer IL3. For example, the first layer IL3a of the third insulating layer IL3 may be formed to have a thickness of at least about For example, the first layer IL3a of the third insulating layer IL3 may be formed to have a thickness in the range of about to about Thus, by ensuring the separation distance between the second layer IL3b of the third insulating layer IL3 and the active layer ACT, it may be possible to prevent or reduce the introduction of hydrogen from the second layer IL3b of the third insulating layer IL3 into the active layer ACT.

[0120] In an embodiment, each of the fourth insulating layer IL4 and the fifth insulating layer IL5 may include at least one organic insulating layer containing an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating materials). The surface (e.g., top surface) of the fourth insulating layer IL4 and the fifth insulating layer IL5 may be substantially flat.

[0121] In an embodiment, at least one insulating layer provided in the panel circuit layer PCL may be entirely provided in the display area DA. For example, the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 may be entirely provided in the display area DA.

[0122] In an embodiment, the gate insulating layer GI may be partially disposed only in each pixel region PXA and a portion of the display region DA including the pixel region PXA. In an embodiment, the gate insulating layer GI may include a first gate insulating layer GI1 (also referred to as a "first gate insulating pattern") disposed on a part of each active layer ACT provided in the semiconductor layer SCL, and a second gate insulating layer GI2 (also referred to as a "second gate insulating pattern") disposed on the second insulating layer IL2 without overlapping with the active layer ACT. For example, the first gate insulating layer GI1 may be disposed between a part of the active layer ACT including the channel region CH and the gate electrode GE, and the second gate insulating layer GI2 may be disposed between the third electrode E3 provided in the third conductive layer CDL3 of the capacitor C and the second insulating layer IL2. The first gate insulating layer GI1 and the second gate insulating layer GI2 may extend to each other to form an integrated insulating pattern, or may be separate insulating patterns that can be separated from each other in a plan view. However, the embodiment is not limited thereto. For example, the gate insulating layer GI may be completely disposed in the display region DA to completely cover the second insulating layer IL2 and the semiconductor layer SCL.

[0123] In an embodiment, the display panel 110 may further include a first bottom electrode BE1 disposed under the transistor T. As an example, the display panel 110 may further include a first bottom electrode BE1 disposed under the second bottom electrode BE2. In an embodiment, the first bottom electrode BE1 may be disposed in the first conductive layer CDL1 provided on the substrate SUB and the barrier layer BR. In an embodiment, the first bottom electrode BE1 may include a first end portion EP1 overlapping with the active layer ACT.

[0124] The first bottom electrode BE1 may overlap with the second bottom electrode BE2. Thus, a capacitor (e.g., Figure 3 the second capacitor C2 therein) may be formed between the first bottom electrode BE1 and the second bottom electrode BE2. For example, the first bottom electrode BE1 may constitute the third capacitor electrode CE3, and the second bottom electrode BE2 may constitute the fourth capacitor electrode. The third capacitor electrode CE3 and the fourth capacitor electrode may form Figure 3 the second capacitor C2. In another example, the first bottom electrode BE1 may be integrally formed with the first electrode E1 of the first capacitor electrode CE1 (e.g., formed of the same first conductive layer CDL1 as the first electrode E1 of the first capacitor electrode CE1) to form the first capacitor C1.

[0125] The transistor T may include an active layer ACT (also referred to as an "active pattern" or a "semiconductor pattern") and a gate electrode GE (e.g., a top gate electrode) disposed on a part of the active layer ACT. In an embodiment, the transistor T may further include at least one of a source electrode SE and a drain electrode DE. For example, the transistor T may further include a source electrode SE electrically connected to a source region SR of the active layer ACT and a drain electrode DE electrically connected to a drain region DR of the active layer ACT. In another example, the transistor T may not include a separate source electrode and / or a separate drain electrode, and the source region SR and / or the drain region DR of the active layer ACT may be electrically connected to another circuit element, wiring, and / or a conductive pattern to serve as the source electrode and / or the drain electrode of the transistor T.

[0126] In an embodiment, the transistor T may further include a second bottom electrode BE2 (or a bottom gate electrode) disposed under the active layer ACT. For example, the second bottom electrode BE2 may be electrically connected to an electrode of the transistor T and may serve as a back gate electrode BG for adjusting the characteristics of the transistor T. Since the second bottom electrode BE2 may be disposed under the active layer ACT, it may be possible to block external light from incident on a channel region CH of the active layer ACT and stabilize the operating characteristics of the transistor T.

[0127] Figure 4 Embodiments are disclosed in which the transistor T may be formed in a double-gate structure including a second bottom electrode BE2 and a gate electrode GE that overlap each other in a plan view, and the active layer ACT is disposed between the gate electrode GE and the second bottom electrode BE2, but the embodiments are not limited thereto. For example, the transistor T may include only one of the second bottom electrode BE2 and the gate electrode GE. As an example, the transistor T may be formed in a top-gate structure including a single gate electrode GE disposed above the active layer ACT, or may also be formed in a bottom-gate structure including a second bottom electrode BE2 disposed under the active layer ACT.

[0128] In an embodiment, the transistor T may be an N-type transistor. For example, the transistor T may be an N-type oxide transistor.

[0129] The second bottom electrode BE2 may be disposed in a second conductive layer CDL2 disposed on a first insulating layer IL1. The second conductive layer CDL2 may be disposed between the first insulating layer IL1 and a second insulating layer IL2. The second bottom electrode BE2 may overlap the active layer ACT and the gate electrode GE in a plan view. For example, the second bottom electrode BE2 may be disposed under the active layer ACT to overlap at least a part of the active layer ACT including the channel region CH, and may face the gate electrode GE, and the active layer ACT is disposed between the second bottom electrode BE2 and the gate electrode GE.

[0130] In an embodiment, the first bottom electrode BE1 and the second bottom electrode BE2 may include corresponding end portions overlapping with the active layer ACT, and these end portions may not overlap in the thickness direction of the substrate SUB. For example, the first bottom electrode BE1 may include a first end portion EP1 overlapping with the active layer ACT, and the second bottom electrode BE2 may include a second end portion EP2 overlapping with the active layer ACT and adjacent to the first end portion EP1 of the first bottom electrode BE1. The first end portion EP1 of the first bottom electrode BE1 and the second end portion EP2 of the second bottom electrode BE2 may not overlap with each other in the thickness direction of the substrate SUB (e.g., the third direction D3) (or in a plan view). For example, when observed in a plan view defined by the first direction D1 and the second direction D2, the first end portion EP1 and the second end portion EP2 may be disposed at positions spaced apart from each other.

[0131] In an embodiment, the second bottom electrode BE2 may be electrically connected to the source electrode SE or the gate electrode GE of the transistor T. For example, the transistor T may be a driving transistor of the pixel PX, and the second bottom electrode BE2 of the transistor T may be electrically connected to the source electrode SE of the transistor T through a first contact hole CNT1 penetrating the second insulating layer IL2 and the third insulating layer IL3. In another example, the transistor T may be a switching transistor of the pixel PX, and the second bottom electrode BE2 of the transistor T may be electrically connected to the gate electrode GE of the transistor T.

[0132] The active layer ACT may be disposed in the semiconductor layer SCL. The semiconductor layer SCL may be disposed on the second insulating layer IL2 covering the second conductive layer CDL2, and may be covered by the gate insulating layer GI and the third insulating layer IL3.

[0133] The active layer ACT may include a channel region CH, a source region SR, and a drain region DR. The source region SR and the drain region DR are spaced apart from each other, and the channel region CH is disposed between the source region SR and the drain region DR. For example, the source region SR and the drain region DR may be located on both sides of the channel region CH. The channel region CH may be a region that maintains semiconductor characteristics without becoming conductive. The source region SR and the drain region DR, which may be regions that have become conductive, may have a carrier concentration (e.g., electron concentration) higher than that of the channel region CH.

[0134] The active layer ACT may overlap with the second bottom electrode BE2 and the gate electrode GE. For example, a portion of the active layer ACT including the channel region CH may overlap with the second bottom electrode BE2 and the gate electrode GE.

[0135] In an embodiment, the active layer ACT may include an oxide semiconductor. For example, the active layer ACT may include an oxide semiconductor containing at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf), or other oxide semiconductors. In an embodiment, the active layer ACT may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO or In2O3), titanium oxide (TiO or TiO2), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium tin gallium zinc oxide (ITGZO), or other oxide semiconductors.

[0136] In an embodiment, the active layer ACT may be formed of a high-mobility oxide semiconductor (e.g., an oxide semiconductor material having a mobility of about 20 cm 2 / Vs or at least about 30 cm 2 / Vs). For example, the active layer ACT may be formed of indium gallium zinc oxide (IGZO) or indium tin gallium zinc oxide (ITGZO) and may have a mobility of at least about 20 cm 2 / Vs. In the case where the active layer ACT is formed of a high-mobility oxide semiconductor, the conductivity of the source region SR and the drain region DR can be appropriately and / or easily ensured without performing an additional doping process. Further, in the case where the active layer ACT is formed of a high-mobility oxide semiconductor, it is possible to form a transistor T having a fine size (e.g., a size including the active layer ACT having a width and / or length in the range of about several micrometers to about several tens of micrometers), and the mobility of the transistor T can be appropriately ensured.

[0137] The first gate insulating layer GI1 may be disposed on the active layer ACT. For example, the first gate insulating layer GI1 may be disposed between the active layer ACT and the gate electrode GE.

[0138] In an embodiment, the first gate insulating layer GI1 may cover a part of the active layer ACT including a portion overlapping with the gate electrode GE and expose another part of the active layer ACT. For example, the first gate insulating layer GI1 may be disposed on a part of the active layer ACT including the channel region CH and may expose the source region SR and the drain region DR of the active layer ACT.

[0139] Since the first gate insulating layer GI1 exposes the source region SR and the drain region DR, the source region SR and the drain region DR can become suitably and / or easily conductive during the manufacturing process of the display panel 110. For example, in the step of etching the gate insulating layer GI to expose at least a part of the source region SR and at least a part of the drain region DR, oxygen vacancies can occur in the source region SR and the drain region DR by an etching gas or the like. Therefore, the source region SR and the drain region DR can become suitably conductive in a subsequent process (e.g., a process of forming the third insulating layer IL3) without performing a separate doping process.

[0140] In an embodiment, in order to limit the carrier concentration of the source region SR and the drain region DR and / or the mobility of the active layer ACT to an appropriate range, an oxygen supply layer can be formed between the first gate insulating layer GI1 and the gate electrode GE. For example, the transistor T can further include an oxygen supply layer disposed between the first gate insulating layer GI1 and the gate electrode GE and containing an oxide semiconductor. The active layer ACT and the oxygen supply layer of the transistor T can contain the same oxide semiconductor or different oxide semiconductors.

[0141] The gate electrode GE can be disposed on the first gate insulating layer GI1. The gate electrode GE can be disposed in the third conductive layer CDL3. The third conductive layer CDL3 can be disposed on the second insulating layer IL2 and the gate insulating layer GI and can be covered by the third insulating layer IL3.

[0142] The gate electrode GE can be disposed on the active layer ACT to overlap with the channel region CH. The gate electrode GE and the active layer ACT can be separated from each other and / or spaced apart from each other, and the first gate insulating layer GI1 is disposed between the gate electrode GE and the active layer ACT.

[0143] The third insulating layer IL3 can be disposed on the gate electrode GE. The third insulating layer IL3 can cover the active layer ACT, the gate insulating layer GI, and the gate electrode GE.

[0144] The source electrode SE and the drain electrode DE can be disposed on the third insulating layer IL3. The source electrode SE and the drain electrode DE can be disposed in the fourth conductive layer CDL4. The fourth conductive layer CDL4 can be disposed between the third insulating layer IL3 and the fourth insulating layer IL4. In an embodiment, each of the patterns of the fourth conductive layer CDL4 can be formed of a bilayer (e.g., a bilayer including a lower layer containing aluminum (Al) and an upper layer containing titanium (Ti)), or can be formed of a trilayer (e.g., a trilayer of aluminum (Al) / titanium (Ti) / aluminum (Al)).

[0145] The source electrode SE can be electrically connected to a part of the active layer ACT. For example, the source electrode SE can be electrically connected to the source region SR of the active layer ACT through the second contact hole CNT2 that penetrates the third insulating layer IL3. In an embodiment, the source electrode SE can be electrically connected to the second bottom electrode BE2 through the first contact hole CNT1.

[0146] The drain electrode DE can be electrically connected to another part of the active layer ACT. For example, the drain electrode DE can be electrically connected to the drain region DR of the active layer ACT through the third contact hole CNT3 that penetrates the third insulating layer IL3.

[0147] In an embodiment, at least one transistor T disposed in each pixel region PXA can be electrically connected to a light-emitting element ED disposed on the transistor T. For example, at least one transistor T (e.g., the first transistor T1) disposed in each pixel region PXA can be electrically connected to a bridging electrode BRE disposed on a fourth insulating layer IL4 covering a fourth conductive layer CDL4. For example, the source electrode SE (or drain electrode DE) of the first transistor T1 disposed in each pixel region PXA can be electrically connected to the bridging electrode BRE on the fourth insulating layer IL4 through a seventh contact hole CNT7 that penetrates the fourth insulating layer IL4. At least one transistor T can be electrically connected to the light-emitting element ED disposed on a fifth insulating layer IL5 through the bridging electrode BRE.

[0148] The bridging electrode BRE can be disposed in a fifth conductive layer CDL5. The bridging electrode BRE can be electrically connected to a first electrode ET1 of the light-emitting element ED disposed in a light-emitting element layer LEL through a ninth contact hole CNT9 that penetrates the fifth insulating layer IL5.

[0149] The fifth conductive layer CDL5 can be disposed between the fourth insulating layer IL4 and the fifth insulating layer IL5. For example, the fifth conductive layer CDL5 can be disposed on the fourth insulating layer IL4 and covered by the fifth insulating layer IL5. In an embodiment, each of the patterns of the fifth conductive layer CDL5 can be formed of a double layer (e.g., a double layer including a lower layer containing aluminum (Al) and an upper layer containing titanium (Ti)), or can be formed of a triple layer (e.g., a triple layer of aluminum (Al) / titanium (Ti) / aluminum (Al)).

[0150] The capacitor C can include capacitor electrodes that form an electrostatic capacitance. For example, Figure 3 the first capacitor C1 can include a first capacitor electrode CE1 and a second capacitor electrode CE2. In an embodiment, the first capacitor C1 can have a multilayer structure including multilayer electrodes (or sub-electrodes). Therefore, the capacitance of the first capacitor C1 can be appropriately ensured by effectively using the area of the pixel region PXA.

[0151] In an embodiment, the first capacitor C1 may include a first electrode E1 disposed in the first conductive layer CDL1, a second electrode E2 disposed in the second conductive layer CDL2, a third electrode E3 disposed in the third conductive layer CDL3, and a fourth electrode E4 disposed in the fourth conductive layer CDL4. In an embodiment, the first capacitor C1 may further include at least one of a fifth electrode E5 disposed in the fourth conductive layer CDL4 and spaced apart from the fourth electrode E4 and a sixth electrode E6 disposed in the fifth conductive layer CDL5.

[0152] In an embodiment, the fourth electrode E4 may overlap with the first electrode E1 and may be electrically connected to the first electrode E1 through a fourth contact hole CNT4 penetrating the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3. In an embodiment, the fourth electrode E4 may also overlap with the third electrode E3 and may be electrically connected to the third electrode E3 through a fifth contact hole CNT5 penetrating the third insulating layer IL3. For example, the fourth electrode E4 may be electrically connected to the first electrode E1 and the third electrode E3 separately and / or in parallel through the fourth contact hole CNT4 and the fifth contact hole CNT5, respectively. The first electrode E1 and the third electrode E3 may be electrically connected to each other through the fourth electrode E4. The first electrode E1, the third electrode E3, and the fourth electrode E4 may form a first capacitor electrode CE1 of the first capacitor C1.

[0153] In an embodiment, the third electrode E3 may be electrically connected to a gate electrode GE of a first transistor T1 located in each pixel region PXA. For example, the third electrode E3 in the third conductive layer CDL3 and the gate electrode GE of the first transistor T1 may be integrated with each other. For example, when observed in a plan view defined by a first direction D1 and a second direction D2, the third electrode E3 and the gate electrode GE of the first transistor T1 may be electrically connected to each other to form an integrated electrode. A first gate insulating layer GI1 located under the gate electrode GE of the first transistor T1 and a second gate insulating layer GI2 located under the third electrode E3 may extend to each other to form an integrated insulating pattern.

[0154] The second electrode E2 may overlap with at least one of the first electrode E1, the third electrode E3, and the fourth electrode E4 and may form a capacitance between itself and the at least one electrode. The second electrode E2 may constitute a second capacitor electrode CE2.

[0155] In an embodiment, the second electrode E2 may be electrically connected to a source electrode SE of a first transistor T1 located in each pixel region PXA. For example, the second electrode E2 and a second bottom electrode BE2 of the first transistor T1 may be disposed in the second conductive layer CDL2 and may be integrated with each other, and may be electrically connected to the source electrode SE of the first transistor T1 through a first contact hole CNT1.

[0156] The fifth electrode E5 may overlap with the second electrode E2 and may be connected (e.g., directly electrically connected) to the second electrode E2 through a sixth contact hole CNT6 that penetrates the second insulating layer IL2 and the third insulating layer IL3. The fifth electrode E5 and the second electrode E2 may together form the second capacitor electrode CE2. The fifth electrode E5 located in each pixel region PXA and the source electrode SE of the first transistor T1 may be integral with each other or may be formed separately from each other.

[0157] The sixth electrode E6 may overlap with the fifth electrode E5 and may be connected (e.g., directly electrically connected) to the fifth electrode E5 through an eighth contact hole CNT8 that penetrates the fourth insulating layer IL4. The sixth electrode E6, the second electrode E2, and the fifth electrode E5 may together form the second capacitor electrode CE2. The sixth electrode E6 located in each pixel region PXA and the bridging electrode BRE may be integral with each other or may be formed separately from each other.

[0158] In an embodiment, the display panel 110 may include multilayer wirings that include sub-wirings provided in at least two conductive layers provided in the panel circuit layer PCL, similar to the first capacitor electrode CE1 and / or the second capacitor electrode CE2. For example, at least one of the wirings provided in the display panel 110 may have a multilayer structure that includes at least two sub-wirings among a first sub-wiring provided in the first conductive layer CDL1, a second sub-wiring provided in the second conductive layer CDL2, a third sub-wiring provided in the third conductive layer CDL3, a fourth sub-wiring provided in the fourth conductive layer CDL4, and a fifth sub-wiring provided in the fifth conductive layer CDL5. Accordingly, the resistance of the wiring can be reduced.

[0159] The light-emitting element layer LEL may be provided on the panel circuit layer PCL. For example, the light-emitting element layer LEL may be provided on the fifth insulating layer IL5 and may be at least located in the display area DA.

[0160] The light-emitting element layer LEL may include a light-emitting element ED for each of the pixels PX. For example, the light-emitting element layer LEL may include a pixel defining layer PDL (also referred to as a "bank") that separates the emission regions of the pixels PX and the light-emitting elements ED located in each emission region. In an embodiment, the light-emitting element layer LEL may further include a spacer SPC provided on a part of the pixel defining layer PDL.

[0161] Each light-emitting element ED may include a first electrode ET1 located in each emission region, and a light-emitting layer EML and a second electrode ET2 sequentially disposed on the first electrode ET1. The first electrode ET1 of the light-emitting element ED may be electrically connected to at least one transistor (e.g., the first transistor T1) included in the corresponding pixel PX.

[0162] The first electrode ET1 of the light-emitting element ED may be a single-layer or multi-layer electrode including at least one conductive material. In an embodiment, the display panel 110 may be a top-emission type display panel, and the first electrode ET1 may include a reflective electrode layer having a high reflectivity.

[0163] The light-emitting layer EML of the light-emitting element ED may include a polymer material or a low-molecular material. The light emitted from the light-emitting layer EML may contribute to image display.

[0164] The second electrode ET2 of the light-emitting element ED may include a conductive material. In an embodiment, the second electrode ET2 may be a common layer formed across the entire display area DA to cover the light-emitting layer EML and the pixel defining layer PDL. In an embodiment, the display panel 110 may be a top-emission type display panel, and the second electrode ET2 may include a transparent electrode layer or a semi-transparent electrode layer.

[0165] The pixel defining layer PDL may have openings corresponding to each emission region and may surround the emission region. For example, the pixel defining layer PDL may be formed to cover the edge of the first electrode ET1 of the light-emitting element ED and may include an opening exposing the remaining portion of the first electrode ET1. The region where the exposed first electrode ET1 and the light-emitting layer EML overlap may be the emission region of each pixel PX. In an embodiment, the pixel defining layer PDL may include at least one organic insulating layer containing an organic insulating material.

[0166] The spacer SPC may be disposed on a part of the pixel defining layer PDL. The spacer SPC may include at least one organic insulating layer containing an organic insulating material. The spacer SPC and the pixel defining layer PDL may include the same material or may include different materials. The pixel defining layer PDL and the spacer SPC may be sequentially formed by separate mask processes, or may be formed simultaneously and / or integrally using a halftone mask.

[0167] The encapsulation layer ENL may be disposed on the light-emitting element layer LEL. The encapsulation layer ENL may cover the light-emitting element layer LEL in the display area DA and may extend to the non-display area NDA to contact the panel circuit layer PCL. The encapsulation layer ENL may block oxygen or moisture from penetrating into the light-emitting element layer LEL and may reduce the electrical and / or physical effects on the panel circuit layer PCL and the light-emitting element layer LEL.

[0168] In an embodiment, the encapsulation layer ENL may include a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 that are sequentially disposed on the light-emitting element layer LEL. Each of the first encapsulation layer ENL1 and the third encapsulation layer ENL3 may be an inorganic encapsulation layer containing an inorganic material. The second encapsulation layer ENL2 may be an organic encapsulation layer containing an organic material.

[0169] Figure 5 is a schematic cross-sectional view Figure 4 detailing region A. Figure 6 is a schematic cross-sectional view Figure 4 detailing region A. Figure 5 and Figure 6 show different embodiments with respect to the first bottom electrode BE1 and the second bottom electrode BE2.

[0170] Except for Figure 4 , referring to Figure 5 and Figure 6 , the first bottom electrode BE1 and the second bottom electrode BE2 may be formed of at least a double-layer electrode. For example, the first bottom electrode BE1 and the second bottom electrode BE2 may be formed of a three-layer electrode including each of the first metal layers ML1a and ML1b, each of the second metal layers ML2a and ML2b disposed above the first metal layers ML1a and ML1b, and each of the third metal layers ML3a and ML3b disposed below the first metal layers ML1a and ML1b, as shown in Figure 5 . In another example, the first bottom electrode BE1 and the second bottom electrode BE2 may be formed of a double-layer electrode including each of the first metal layers ML1a and ML1b and each of the second metal layers ML2a and ML2b disposed above the first metal layers ML1a and ML1b, as shown in Figure 6 .

[0171] In an embodiment, each of the first metal layers ML1a and ML1b of the first bottom electrode BE1 and the second bottom electrode BE2 may include aluminum (Al) having a relatively low resistance. Each of the first metal layers ML1a and ML1b of the first bottom electrode BE1 and the second bottom electrode BE2 may include a low-resistance metal other than aluminum (Al). Each of the first metal layers ML1a and ML1b of the first bottom electrode BE1 and the second bottom electrode BE2 may have a relatively large thickness compared to the second metal layers ML2a and ML2b and the third metal layers ML3a and ML3b.

[0172] Each of the second metal layers ML2a and ML2b of the first bottom electrode BE1 and the second bottom electrode BE2 may include titanium (Ti) that can block the ion diffusion of each of the first metal layers ML1a and ML1b into the periphery. Each of the second metal layers ML2a and ML2b of the first bottom electrode BE1 and the second bottom electrode BE2 may include a capping metal in addition to titanium (Ti). In an embodiment, the second metal layer ML2a of the first bottom electrode BE1 may completely cover the top surface of the first metal layer ML1a of the first bottom electrode BE1, and the second metal layer ML2b of the second bottom electrode BE2 may completely cover the top surface of the first metal layer ML1b of the second bottom electrode BE2.

[0173] The second metal layers ML2a and ML2b of the first bottom electrode BE1 and the second bottom electrode BE2 respectively cap the top surfaces of the first metal layers ML1a and ML1b of the first bottom electrode BE1 and the second bottom electrode BE2, so that voids or seams can be suppressed from appearing on the top surfaces or their peripheries (e.g., the first insulating layer IL1 and the second insulating layer IL2) of the first metal layers ML1a and ML1b. In addition, the second metal layers ML2a and ML2b can block the diffusion of hydrogen from the first metal layers ML1a and ML1b in the upward direction (e.g., in the third direction D3).

[0174] Each of the third metal layers ML3a and ML3b of the first bottom electrode BE1 and the second bottom electrode BE2 may include titanium (Ti). Each of the third metal layers ML3a and ML3b of the first bottom electrode BE1 and the second bottom electrode BE2 may include a capping metal in addition to titanium (Ti). In an embodiment, the third metal layer ML3a of the first bottom electrode BE1 may completely cover the bottom surface of the first metal layer ML1a of the first bottom electrode BE1, and the third metal layer ML3b of the second bottom electrode BE2 may completely cover the bottom surface of the first metal layer ML1b of the second bottom electrode BE2.

[0175] The first metal layers ML1a and ML1b of the first bottom electrode BE1 and the second bottom electrode BE2 may be formed on the third metal layers ML3a and ML3b of the first bottom electrode BE1 and the second bottom electrode BE2, so that voids or seams can be suppressed from appearing on the bottom surfaces or their peripheries of the first metal layers ML1a and ML1b. In addition, the third metal layers ML3a and ML3b can block the diffusion of hydrogen in the third direction D3. For example, it may be possible to block the diffusion of hydrogen from the first metal layers ML1a and ML1b into the periphery, or block the diffusion of hydrogen from the lower portions of the first bottom electrode BE1 and the second bottom electrode BE2 into the first bottom electrode BE1, the second bottom electrode BE2, etc.

[0176] The first bottom electrode BE1 and the second bottom electrode BE2 may include a first end portion EP1 and a second end portion EP2 that overlap with the active layer ACT and may be adjacent to each other. The first metal layers ML1a and ML1b of the first bottom electrode BE1 and the second bottom electrode BE2 may be exposed at the first end portion EP1 and the second end portion EP2.

[0177] At the first end portion EP1 and the second end portion EP2 where the first metal layers ML1a and ML1b are exposed, voids or seams may occur in the first bottom electrode BE1, the second bottom electrode BE2, and / or their peripheries. For example, in a portion where the first metal layers ML1a and ML1b are exposed (such as Figure 5 and Figure 6 region B in) or in the insulating layer (e.g., the first insulating layer IL1 and / or the second insulating layer IL2) of its periphery, voids or seams may occur. The voids or seams may form a path for hydrogen movement or diffusion.

[0178] In an embodiment, the first bottom electrode BE1 and the second bottom electrode BE2 may be arranged to mitigate voids or seams and increase the length of the hydrogen movement path. Thus, the diffusion of hydrogen between the layers of the display panel 110 can be prevented or reduced, and the active layer ACT can be appropriately protected.

[0179] For example, the first end portion EP1 and the second end portion EP2 may not overlap with each other in the third direction D3 (or in a plan view). When observed in a plan view perpendicular to the third direction D3 (e.g., a plane defined by the first direction D1 and the second direction D2), the first end portion EP1 and the second end portion EP2 may be spaced apart from each other by at least a first distance d1 (e.g., at least a predetermined or optional distance). In an embodiment, the first end portion EP1 and the second end portion EP2 may be spaced apart from each other by at least a distance (e.g., at least a predetermined or optional distance) in each of the first direction D1 and the second direction D2.

[0180] In an embodiment, the first end portion EP1 and the second end portion EP2 may be spaced apart from each other by at least about 0.6 μm in a plan view. For example, the first end portion EP1 and the second end portion EP2 may be spaced apart from each other by at least about 0.6 μm in each of the first direction D1 and the second direction D2.

[0181] In an embodiment, a portion of the second bottom electrode BE2 may overlap with the first end portion EP1 of the first bottom electrode BE1. In addition, the second end portion EP2 of the second bottom electrode BE2 may extend from a portion of the second bottom electrode BE2 to the outside of the first end portion EP1 (or may not overlap with the first end portion EP1). For example, in a plan view, the second end portion EP2 of the second bottom electrode BE2 may be located outside the first end portion EP1.

[0182] According to an embodiment, the first end portion EP1 and the second end portion EP2 may be arranged to be spaced apart from each other by at least a distance (e.g., at least a predetermined or optional distance), such that the second insulating layer IL2 may be formed in a shape having step portions corresponding to the first end portion EP1 and the second end portion EP2. Accordingly, a separation distance between the first end portion EP1 and the second end portion EP2 and the active layer ACT provided on the second insulating layer IL2 can be appropriately ensured. For example, since the second insulating layer IL2 may be formed to have step portions corresponding to the first end portion EP1 and the second end portion EP2, as shown by the dashed arrows in Figure 5 and Figure 6 , it is possible to increase the distance of the movement path of hydrogen that can diffuse or be introduced into the active layer ACT from the second end portion EP2 or the like. A portion of the second bottom electrode BE2 including the second end portion EP2 may be provided between the first end portion EP1 and the active layer ACT, such that it is possible to block hydrogen from diffusing from the first end portion EP1 or the like into the active layer ACT.

[0183] Furthermore, according to an embodiment, although seams in the form of connection voids appear around the first end portion EP1 and / or the second end portion EP2, it is possible to prevent the seams from extending to an area close to the active layer ACT. For example, a seam that appears around the first end portion EP1 may be blocked by the second bottom electrode BE2 and may no longer extend, and a seam that appears around the first end portion EP1 and a seam that appears around the second end portion EP2 may not extend to each other. Accordingly, seams that may occur between the first bottom electrode BE1 and the second bottom electrode BE2 and the active layer ACT can be alleviated or reduced, and it is possible to block or reduce hydrogen diffusion or introduction into the active layer ACT.

[0184] Figure 7 is a schematic cross-sectional view showing a display panel 110 according to an embodiment. Figure 8 is a schematic cross-sectional view showing in detail Figure 7 region C of Figure 9 is a schematic cross-sectional view showing in detail Figure 7 region C of Figures 7 to 9 shows an embodiment different from Figures 4 to 6 with respect to the arrangement of the first bottom electrode BE1 and the second bottom electrode BE2.

[0185] Refer to Figures 7 to 9, a portion of the first bottom electrode BE1 may overlap with the second end portion EP2 of the second bottom electrode BE2. In addition, the first end portion EP1 of the first bottom electrode BE1 may extend from a portion of the first bottom electrode BE1 to the outside of the second end portion EP2 (or may not overlap with the second end portion EP2). For example, in a plan view, the first end portion EP1 of the first bottom electrode BE1 may be positioned outside the second end portion EP2. Therefore, the first end portion EP1 and the second end portion EP2 may not overlap each other in the third direction D3.

[0186] The first end portion EP1 and the second end portion EP2 may be spaced apart from each other by a second distance d2 in a plan view. In an embodiment, the second distance d2 may be at least about 0.6 μm. For example, the first end portion EP1 and the second end portion EP2 may be spaced apart from each other by at least about 0.6 μm in each of the first direction D1 and the second direction D2.

[0187] According to an embodiment, the first end portion EP1 and the second end portion EP2 may be arranged to be spaced apart from each other by a distance (e.g., a predetermined or optional distance) such that the second insulating layer IL2 may be formed in a shape having a stepped portion corresponding to the first end portion EP1 and the second end portion EP2. Therefore, a separation distance can be appropriately ensured between the first end portion EP1 and the second end portion EP2 and the active layer ACT, and it is possible to block or reduce the diffusion of hydrogen from the first end portion EP1, the second end portion EP2, etc. into the active layer ACT. For example, since the second insulating layer IL2 may be formed in a shape having a stepped portion corresponding to the first end portion EP1 and the second end portion EP2, as Figure 8 and Figure 9 shown by the dashed arrows in, it is possible to increase the distance of the movement path of hydrogen that can be diffused or introduced from the first end portion EP1, the second end portion EP2, etc. into the active layer ACT. In addition, according to an embodiment, seams that may occur between the first bottom electrode BE1 and the second bottom electrode BE2 and the active layer ACT can be alleviated or reduced, and it is possible to block or reduce the diffusion or introduction of hydrogen into the active layer ACT.

[0188] Figures 10 to 18 is a schematic cross-sectional view showing a method for manufacturing the display device 100 according to an embodiment. For example, Figures 10 to 18 successively shows the step of forming a panel circuit layer PCL including a transistor T and a capacitor C among the steps of manufacturing Figure 4 the display panel 110. Except for possibly partially changing the relative dimensions and / or positions, etc. of the first bottom electrode BE1 and the second bottom electrode BE2, Figure 7 the display panel 110 can be manufactured in substantially the same manner as Figure 4 the display panel 110.

[0189] Except forFigures 1 to 9 In addition, referring to Figure 10 , a substrate SUB including a display area DA can be prepared, and a barrier layer BR can be selectively formed on the substrate SUB. The display area DA can include a pixel area PXA.

[0190] Hereinafter, a first conductive layer CDL1 including a first bottom electrode BE1 and a first electrode E1 can be formed on the barrier layer BR (or the substrate SUB). The first bottom electrode BE1 can include a first end portion EP1.

[0191] A pattern (e.g., an electrode, a conductive pattern, and / or at least one wiring provided in the first conductive layer CDL1) of the first conductive layer CDL1 including the first bottom electrode BE1 and the first electrode E1 can be formed by a film-forming process (e.g., a deposition process) of a conductive film using at least one of the conductive materials exemplified above and a patterning process of the conductive film (e.g., an etching process using a mask). In an embodiment, each of the patterns in the first conductive layer CDL1 can be formed of a double layer including a first metal layer ML1a and a second metal layer ML2a, or can be formed of a triple layer including a first metal layer ML1a, a second metal layer ML2a, and a third metal layer ML3a.

[0192] Referring to Figure 11 , a first insulating layer IL1 covering the first conductive layer CDL1 can be formed on the substrate SUB. For example, the first insulating layer IL1 can be formed on a pattern of the first conductive layer CDL1 including the first bottom electrode BE1 and the first electrode E1. The first insulating layer IL1 can be formed by a film-forming process of an insulating film using at least one of the insulating materials exemplified above (e.g., an inorganic insulating material).

[0193] Referring to Figure 12 , a second conductive layer CDL2 including a second bottom electrode BE2 and a second electrode E2 can be formed on the first insulating layer IL1. The second bottom electrode BE2 can include a second end portion EP2 adjacent to the first end portion EP1 of the first bottom electrode BE1.

[0194] In an embodiment, the first bottom electrode BE1 and the second bottom electrode BE2 can be formed such that the first end portion EP1 and the second end portion EP2 do not overlap in the thickness direction (e.g., the third direction D3) of the substrate SUB or in a plan view. In an embodiment, when observed in a plan view (e.g., a plane defined by a first direction D1 and a second direction D2 perpendicular to the third direction D3), the first end portion EP1 and the second end portion EP2 can be spaced apart from each other by a distance of at least about 0.6 μm. For example, the first end portion EP1 and the second end portion EP2 can be spaced apart from each other by a distance of at least about 0.6 μm in each of the first direction D1 and the second direction D2.

[0195] The pattern of the second conductive layer CDL2 including the second bottom electrode BE2 and the second electrode E2 (e.g., electrodes, conductive patterns, and / or at least one wiring provided in the second conductive layer CDL2) can be formed by a film-forming process (e.g., a deposition process) of a conductive film using at least one of the conductive materials in the above examples and a patterning process of the conductive film (e.g., an etching process using a mask). In an embodiment, each of the patterns in the second conductive layer CDL2 can be formed of a bilayer including a first metal layer ML1b and a second metal layer ML2b, or can be formed of a trilayer including a first metal layer ML1b, a second metal layer ML2b, and a third metal layer ML3b.

[0196] Reference Figure 13 , a second insulating layer IL2 covering the second conductive layer CDL2 can be formed on the first insulating layer IL1. For example, the second insulating layer IL2 can be formed on the pattern of the second conductive layer CDL2 including the second bottom electrode BE2 and the second electrode E2. The second insulating layer IL2 can be formed by a film-forming process of an insulating film using at least one of the insulating materials in the above examples (e.g., an inorganic insulating material).

[0197] In an embodiment, the second insulating layer IL2 can be formed of at least a bilayer including a first layer IL2a and a second layer IL2b. As an example, a first layer IL2a including silicon nitride and a second layer IL2b including silicon oxide or silicon oxynitride can be sequentially formed on the first insulating layer IL1 and the second conductive layer CDL2 so that a bilayer second insulating layer IL2 can be formed.

[0198] Reference Figures 14 to 17 , a transistor T can be formed on the second insulating layer IL2. For example, first, as shown in Figure 14 , a semiconductor layer SCL including an active layer ACT can be formed on the second insulating layer IL2. The active layer ACT can be formed in each transistor region.

[0199] The active layer ACT can be formed to overlap with the second bottom electrode BE2. In an embodiment, the active layer ACT can be formed of an oxide semiconductor. For example, the active layer ACT can be formed by a film-forming process and a patterning process (e.g., an etching process using a mask) of a semiconductor layer using at least one of the oxide semiconductors in the above examples.

[0200] Thereafter, as shown in Figure 15 , a gate insulating layer GI and a third conductive layer CDL3 can be formed on the second insulating layer IL2. The gate insulating layer GI can include a first gate insulating layer GI1 and a second gate insulating layer GI2, and the third conductive layer CDL3 can include a gate electrode GE and a third electrode E3.

[0201] The gate insulating layer GI can be formed by a film forming process and a patterning process (e.g., an etching process using a mask) of an insulating film using at least one of the insulating materials in the above examples (e.g., an inorganic insulating material such as silicon oxide). The third conductive layer CDL3 can be formed by a film forming process (e.g., a deposition process) of a conductive film using at least one of the conductive materials mentioned above and a patterning process of patterning the conductive film (e.g., an etching process using a mask).

[0202] In an embodiment, the third conductive layer CDL3 and the gate insulating layer GI can be etched sequentially or substantially simultaneously by an etching process using a mask. For example, the gate insulating layer GI can be etched by using the mask used in the etching process of the third conductive layer CDL3 or by using the third conductive layer CDL3 as a mask. Therefore, the gate insulating layer GI can be patterned into a shape corresponding to the third conductive layer CDL3. For example, the pattern of the gate insulating layer GI can have a shape and / or size corresponding to the pattern of the third conductive layer CDL3.

[0203] The first gate insulating layer GI1 and the gate electrode GE can be formed on a part of the active layer ACT. The second gate insulating layer GI2 and the third electrode E3 can be formed on a part of the second insulating layer IL2 where the active layer ACT may not be provided.

[0204] In the process of etching the gate insulating layer GI, the properties of the active layer ACT can be changed so that a part of the active layer ACT has different characteristics. Therefore, the active layer ACT can be divided into multiple regions with different characteristics.

[0205] For example, at a part that does not overlap with the gate electrode GE and the first gate insulating layer GI1, oxygen vacancies may appear in the oxide semiconductor forming the active layer ACT due to an etching gas or the like. Therefore, the active layer ACT can be divided into multiple regions with different characteristics (e.g., a channel region CH, a source region SR, and a drain region DR). In an embodiment, oxygen vacancies can appear at a part of the active layer ACT that does not overlap with the gate electrode GE and the first gate insulating layer GI1 (e.g., the source region SR and the drain region DR), and can diffuse to a part of the region that overlaps with the gate electrode GE and / or the first gate insulating layer GI1.

[0206] Thereafter, as Figure 16As shown, a third insulating layer IL3 can be formed on the second insulating layer IL2 to cover the semiconductor layer SCL, the gate insulating layer GI, and the third conductive layer CDL3. For example, the third insulating layer IL3 can be formed on the active layer ACT, the first gate insulating layer GI1, the second gate insulating layer GI2, the gate electrode GE, and the third electrode E3. The third insulating layer IL3 can be formed by a film-forming process of an insulating film using at least one of the insulating materials in the above examples (e.g., an inorganic insulating material).

[0207] In an embodiment, the third insulating layer IL3 can be formed of at least a double layer including a first layer IL3a and a second layer IL3b. For example, the first layer IL3a including silicon oxide or silicon oxynitride and the second layer IL3b including silicon nitride can be sequentially formed on the second insulating layer IL2, the semiconductor layer SCL, the gate insulating layer GI, and the third conductive layer CDL3, so that the double-layer third insulating layer IL3 can be formed.

[0208] In the process of forming the third insulating layer IL3 and / or in the heat treatment process before and after this process, hydrogen can be introduced into the active layer ACT. Since hydrogen can be introduced into the active layer ACT, a part of the active layer ACT can become conductive (e.g., conductive to N-type) at a part containing a large amount of oxygen vacancies. For example, the source region SR and the drain region DR can become conductive.

[0209] After the third insulating layer IL3 is formed, a plurality of contact holes can be formed in the third insulating layer IL3. For example, the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, the fourth contact hole CNT4, the fifth contact hole CNT5, and the sixth contact hole CNT6 can be formed by an etching process using a mask. In an embodiment, the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, the fourth contact hole CNT4, the fifth contact hole CNT5, and the sixth contact hole CNT6 can be formed substantially simultaneously by a single mask process, but the embodiment is not limited thereto.

[0210] Thereafter, as Figure 17 shown, a fourth conductive layer CDL4 can be formed on the third insulating layer IL3. The fourth conductive layer CDL4 can include a source electrode SE, a drain electrode DE, a fourth electrode E4, and a fifth electrode E5. In an embodiment, when at least one of the source electrode SE and the drain electrode DE is replaced by at least one of the source region SR and the drain region DR, at least one of the source electrode SE and the drain electrode DE may not be formed.

[0211] A pattern of a fourth conductive layer CDL4 including a source electrode SE, a drain electrode DE, a fourth electrode E4, and / or a fifth electrode E5 (e.g., an electrode, a conductive pattern, and / or a wiring provided in the fourth conductive layer CDL4) can be formed by a film-forming process (e.g., a deposition process) of a conductive film using at least one of the conductive materials in the above examples and a patterning process of the conductive film (e.g., an etching process using a mask).

[0212] Reference Figure 18 , a fourth insulating layer IL4, a fifth conductive layer CDL5, and a fifth insulating layer IL5 can be sequentially formed on the third insulating layer IL3. In the case of manufacturing a display panel 110 that does not include the fifth conductive layer CDL5, the forming processes of the fifth conductive layer CDL5 and the fifth insulating layer IL5 (or the fourth insulating layer IL4) can be omitted.

[0213] The fourth insulating layer IL4 can be formed on the third insulating layer IL3 by a film-forming process of an insulating film using at least one of the organic insulating materials in the above examples. A plurality of contact holes can be formed in the fourth insulating layer IL4. For example, a seventh contact hole CNT7 and an eighth contact hole CNT8 can be formed in the fourth insulating layer IL4.

[0214] The fifth conductive layer CDL5 can be formed on the fourth insulating layer IL4. The fifth conductive layer CDL5 can include a bridging electrode BRE and a sixth electrode E6. In an embodiment, when the second capacitor electrode CE2 does not include the sixth electrode E6, the sixth electrode E6 can be not formed.

[0215] A pattern of the fifth conductive layer CDL5 including the bridging electrode BRE and / or the sixth electrode E6 (e.g., an electrode, a conductive pattern, and / or at least one wiring provided in the fifth conductive layer CDL5) can be formed by a film-forming process (e.g., a deposition process) of a conductive film using at least one of the conductive materials in the above examples and a patterning process of the conductive film (e.g., an etching process using a mask).

[0216] The fifth insulating layer IL5 can be formed on the fourth insulating layer IL4 and the fifth conductive layer CDL5. The fifth insulating layer IL5 can be formed by a film-forming process of an insulating film using at least one of the organic insulating materials in the above examples. A ninth contact hole CNT9 exposing the bridging electrode BRE (or the source electrode SE) can be formed in the fifth insulating layer IL5.

[0217] Through the processes described above, a panel circuit layer PCL of the display panel 110 can be formed. As in Figure 4 and Figure 7In an embodiment, when the display panel 110 includes a light-emitting element layer LEL and a encapsulation layer ENL, the light-emitting element layer LEL and the encapsulation layer ENL may be sequentially formed on the panel circuit layer PCL. Through the processes described above, the display panel 110 according to the embodiment and the display device 100 including the display panel 110 may be manufactured.

[0218] As described above, according to the display device 100 and the method of manufacturing the display device 100 according to the embodiment, the first end portion EP1 of the first bottom electrode BE1 and the second end portion EP2 of the second bottom electrode BE2 disposed below the active layer ACT may not overlap each other in the thickness direction of the substrate SUB. For example, the first end portion EP1 of the first bottom electrode BE1 and the second end portion EP2 of the second bottom electrode BE2 may be spaced apart from each other by at least about 0.6 μm in a plan view.

[0219] According to the embodiment, voids or seams that may occur around the first bottom electrode BE1, the second bottom electrode BE2, etc. may be reduced or alleviated, and the paths (e.g., the moving distance of hydrogen) through which hydrogen can be introduced from the first bottom electrode BE1, the second bottom electrode BE2, etc. into the active layer ACT may be increased. Accordingly, hydrogen diffusing into the active layer ACT may be prevented or reduced, and the operating characteristics of the transistor T may be improved or stabilized. As a result, the operating characteristics of the transistor T and the pixel PX including the transistor T may be improved, and the image quality of the display device 100 may be improved.

[0220] In some embodiments, the first bottom electrode BE1 and the second bottom electrode BE2 may include first metal layers ML1a and ML1b containing aluminum (Al), and may include second metal layers ML2a and ML2b containing titanium (Ti) and respectively covering the top surfaces of the first metal layers ML1a and ML1b. In the embodiment, the first bottom electrode BE1 and the second bottom electrode BE2 may further include third metal layers ML3a and ML3b containing titanium (Ti) and respectively covering the bottom surfaces of the first metal layers ML1a and ML1b. As an example, each of the first bottom electrode BE1 and the second bottom electrode BE2 may be formed of three layers of aluminum (Al) / titanium (Ti) / aluminum (Al).

[0221] According to the embodiment, the top surfaces and / or the bottom surfaces of the first metal layers ML1a and ML1b of the first bottom electrode BE1 and the second bottom electrode BE2 may be respectively covered by the second metal layers ML2a and ML2b and / or the third metal layers ML3a and ML3b, so that voids or seams that may occur around the first bottom electrode BE1, the second bottom electrode BE2, etc. may be suppressed, and hydrogen diffusion in directions such as the third direction D3 may be blocked. Accordingly, hydrogen introduced into the active layer ACT may be more effectively prevented or reduced.

[0222] In some embodiments, the second insulating layer IL2 disposed between the second bottom electrode BE2 and the active layer ACT may include a first layer IL2a containing silicon nitride and a second layer IL2b containing silicon oxide or silicon oxynitride.

[0223] According to an embodiment, the insulating property of the second insulating layer IL2 can be improved, and it may be possible to block hydrogen from diffusing from the lower portion of the second insulating layer IL2 into the upper portion of the second insulating layer IL2. Accordingly, it may be possible to more effectively prevent or reduce hydrogen from being introduced into the active layer ACT.

[0224] Upon concluding the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the embodiments without substantially departing from the principles of the disclosure. Accordingly, the disclosed embodiments of the disclosure are used only in a general and descriptive sense and not for purposes of limitation.

Claims

1. A display device, comprising: substrate; A first bottom electrode, disposed on the substrate and having a first end; A first insulating layer, disposed on the first bottom electrode; a second bottom electrode, disposed on the first insulating layer, wherein the second bottom electrode overlaps with the first bottom electrode in a plan view; a second insulating layer, disposed on the second bottom electrode; as well as a transistor including an active layer disposed on the second insulating layer, the transistor including a gate electrode overlapping the active layer in a plan view, wherein the second bottom electrode overlaps the active layer in a plan view and has a second end adjacent to the first end, and The first end portion and the second end portion do not overlap in a plan view.

2. The display device according to claim 1, wherein: The first end portion and the second end portion are spaced apart from each other by a distance of at least 0.6 μm in a plan view.

3. The display device according to claim 1, wherein: A portion of the second bottom electrode overlaps the first end portion, and The second end portion extends from the portion of the second bottom electrode to an outer side of the first end portion.

4. The display device according to claim 1, wherein: A portion of the first bottom electrode overlaps the second end portion, and The first end portion extends from the portion of the first bottom electrode to an outer side of the second end portion.

5. The display device according to claim 1, wherein: The first bottom electrode includes a first metal layer containing aluminum and a second metal layer disposed on the first metal layer, and The second metal layer contains titanium.

6. The display device according to claim 5, wherein: The first bottom electrode further includes a third metal layer disposed below the first metal layer, and The third metal layer contains titanium.

7. The display device according to claim 6, wherein: The second metal layer completely covers the top surface of the first metal layer, and the third metal layer completely covers the bottom surface of the first metal layer.

8. The display device according to claim 1, wherein: The second bottom electrode includes a first metal layer containing aluminum and a second metal layer disposed on the first metal layer, and The second metal layer contains titanium.

9. The display device according to claim 8, wherein: The second bottom electrode further includes a third metal layer disposed below the first metal layer, and The third metal layer contains titanium.

10. The display device according to claim 9, wherein: The second metal layer completely covers the top surface of the first metal layer, and the third metal layer completely covers the bottom surface of the first metal layer.

11. The display device according to claim 1, wherein: The second insulating layer includes a first layer containing silicon nitride and a second layer disposed on the first layer, and The second layer contains silicon oxide or silicon oxynitride.

12. The display device according to claim 11, wherein: The thickness of the first layer is greater than the thickness of the second layer.

13. The display device according to claim 11, wherein: The first layer has to The thickness is within the range of .

14. The display device according to claim 1, wherein: The active layer contains an oxide semiconductor.

15. The display device according to claim 14, further comprising: A gate insulating layer is disposed between the active layer and the gate electrode, the gate insulating layer covers a portion of the active layer including a portion overlapping the gate electrode and exposes another portion of the active layer.

16. The display device according to claim 1, wherein: The transistor further includes a source electrode disposed on the third insulating layer, The third insulating layer is disposed on the gate electrode, and The second bottom electrode is electrically connected to the source electrode.

17. The display device according to claim 16, wherein: The third insulating layer includes a first layer including silicon oxide or silicon oxynitride and a second layer provided on the first layer, and the second layer includes silicon nitride.

18. The display device according to claim 1, further comprising: The light emitting element is electrically connected to the transistor.

19. A method for manufacturing a display device, comprising: forming a first bottom electrode on a substrate, wherein the first bottom electrode has a first end; forming a first insulating layer on the first bottom electrode; forming a second bottom electrode on the first insulating layer, the second bottom electrode overlapping the first bottom electrode in a plan view, and the second bottom electrode having a second end adjacent to the first end; forming a second insulating layer on the second bottom electrode; as well as forming a transistor on the second insulating layer, the transistor including an active layer overlapping the second bottom electrode in a plan view, The first end portion and the second end portion do not overlap in a plan view.

20. The method according to claim 19, wherein: The first end portion and the second end portion are spaced apart from each other by a distance of at least 0.6 μm in a plan view.

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