Display device

Abstract

A display device is provided. The display device includes a light emitting element, a first transistor including a first semiconductor layer connected to a first power supply line and the light emitting element, and a first gate electrode on the first semiconductor layer and connected to a first node, a second transistor including a second semiconductor layer connected to a second node, the second transistor includes a second semiconductor layer connected to the first node and a second node to which the data line is connected, a 2-1 gate electrode on the second semiconductor layer, and a 2-2 gate electrode under the second semiconductor layer. And the third transistor includes a third semiconductor layer connected to the second node and the light emitting element, a (3-1) th gate electrode on the third semiconductor layer, and a (3-2) th gate electrode under the third semiconductor layer, where the (2-2) th gate electrode and the (3-2) th gate electrode are on a layer above the first gate electrode and on different layers.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2023 - 0182710, filed with the Korean Intellectual Property Office on December 15, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] Aspects of some embodiments of the present disclosure relate to a display device. Background art

[0004] Generally, electronic devices (such as smartphones, digital cameras, laptop computers, automotive navigation units, and smart TVs) that display images to users include a display device for displaying images. The display device generates an image and provides the generated image to the user through a display screen.

[0005] The display device includes a display panel including a plurality of pixels for generating an image, a scan driver for applying a scan signal to the pixels, and a data driver for applying a data voltage to the pixels. The pixels receive the data voltage in response to the scan signal and use the data voltage to generate an image.

[0006] Recently, high - resolution display devices have been favored by consumers. The display panel generally includes a display area and a non - display area surrounding the display area, and the pixels are in the display area. As the number of pixels in the display area increases, the resolution of the display device increases. To increase the number of pixels in the display area, it may be desirable to develop a technology for relatively reducing the size of the pixels.

[0007] The above information disclosed in this background art section is only for enhancing the understanding of the background, and thus the information discussed in this background art section does not necessarily constitute prior art. Summary of the invention

[0008] Aspects of some embodiments of the present disclosure include a display device capable of achieving high resolution by relatively reducing the size of pixels.

[0009] Aspects of some embodiments of the present disclosure include a display device, which includes a light-emitting element, a first transistor, a second transistor, a data line, and a third transistor. The first transistor includes a first semiconductor layer connected to a first power supply line and the light-emitting element, and a first gate electrode on the first semiconductor layer and connected to a first node. The second transistor includes a second semiconductor layer connected to the first node and a second node, a 2-1 gate electrode on the second semiconductor layer, and a 2-2 gate electrode under the second semiconductor layer. The data line is connected to the second node. The third transistor includes a third semiconductor layer connected to the second node and the light-emitting element, a 3-1 gate electrode on the third semiconductor layer, and a 3-2 gate electrode under the third semiconductor layer. Among them, the 2-2 gate electrode and the 3-2 gate electrode are on a layer above the first gate electrode and on different layers (or in different layers).

[0010] According to some embodiments of the present disclosure, a display device includes a light-emitting element, a first transistor, a second transistor, a data line, and a third transistor. The first transistor includes a first semiconductor layer connected to a first power supply line and the light-emitting element, and a first gate electrode on the first semiconductor layer and connected to a first node. The second transistor includes a second semiconductor layer connected to the first node and a second node, a 2-1 gate electrode on the second semiconductor layer, and a 2-2 gate electrode under the second semiconductor layer. The data line is connected to the second node. The third transistor includes a third semiconductor layer connected to the second node and the light-emitting element, a 3-1 gate electrode on the third semiconductor layer, and a 3-2 gate electrode under the third semiconductor layer. Among them, the 2-2 gate electrode and the 3-2 gate electrode are on a layer above the first gate electrode, and the 2-2 gate electrode is on a layer above the 3-2 gate electrode.

[0011] According to some embodiments of the present disclosure, a display device includes a light-emitting element, a first transistor, an insulating layer, a second transistor, a data line, and a third transistor. The first transistor includes a first semiconductor layer connected to a first power supply line and the light-emitting element, and a first gate electrode on the first semiconductor layer and connected to a first node. The insulating layer is on the first transistor. The second transistor includes a second semiconductor layer on the insulating layer and connected to the first node and a second node, a 2-1 gate electrode on the second semiconductor layer, and a 2-2 gate electrode under the second semiconductor layer. The data line is connected to the second node. The third transistor includes a third semiconductor layer on the insulating layer and connected to the second node and the light-emitting element, a 3-1 gate electrode on the third semiconductor layer, and a 3-2 gate electrode under the third semiconductor layer. Among them, the 2-2 gate electrode and the 3-2 gate electrode are on the insulating layer and on different layers (or in different layers). Description of the Drawings

[0012] The accompanying drawings are included to provide a further understanding of embodiments in accordance with the present disclosure, and the accompanying drawings are incorporated in and constitute a part of this specification. The accompanying drawings illustrate aspects of some embodiments of the present disclosure and, together with the description, are used to explain aspects of some embodiments of the present disclosure. In the accompanying drawings:

[0013] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure;

[0014] Figure 2 shows a Figure 1 cross-sectional view of the display device shown in;

[0015] Figure 3 shows a Figure 2 cross-sectional view of the display panel shown in;

[0016] Figure 4 is a Figure 2 planar view of the display panel shown in according to some embodiments of the present disclosure;

[0017] Figure 5 is a view showing a display device according to some embodiments of the present disclosure;

[0018] Figure 6 is a Figure 5 exploded perspective view of the display device shown in according to some embodiments of the present disclosure;

[0019] Figure 7 is a view showing Figure 4 an equivalent circuit of one of the pixels shown in according to some embodiments of the present disclosure;

[0020] Figure 8 is a Figure 7 timing diagram of signals for operating the pixel shown in according to some embodiments of the present disclosure;

[0021] Figure 9 is schematically showing Figure 7 a cross-sectional view of the first transistor and the light-emitting element shown in according to some embodiments of the present disclosure;

[0022] Figure 10 is schematically showing Figure 7 a planar configuration view of the second transistor and the third transistor shown in according to some embodiments of the present disclosure;

[0023] Figure 11 is a Figure 10 cross-sectional view taken along line I-I' shown in according to some embodiments of the present disclosure;

[0024] Figure 12 is a cross-sectional view schematically showing a connection structure for a first transistor and a second transistor according to some embodiments of the present disclosure;

[0025] Figure 13 is a cross-sectional view schematically showing a connection structure for a first transistor and a third transistor according to some embodiments of the present disclosure;

[0026] Figure 14 is a view schematically showing a planar arrangement of a second transistor and a third transistor of a pixel according to a comparative example of the present disclosure; and

[0027] Figures 15 to 18 is a view schematically showing a cross-sectional arrangement of a second transistor and a third transistor according to some embodiments of the present disclosure. Detailed Description

[0028] In this specification, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on", "connected to", or "coupled to" another element, it can be directly positioned on, directly connected or coupled to the other element, or an intervening element may be positioned therebetween.

[0029] Similar reference numerals or symbols always refer to similar elements. Also, in the drawings, the thickness, ratio, and size of elements are exaggerated for effective description of the technical content.

[0030] The term "and / or" includes all combinations of one or more of the associated listed elements.

[0031] Although terms such as first, second, etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the spirit and scope of the embodiments according to the present disclosure, the first element may also be referred to as the second element, and similarly, the second element may be referred to as the first element. Unless the context clearly indicates otherwise, the singular form also includes the plural form.

[0032] Moreover, for description, terms such as "below", "under", "above", "on", and similar words may be used to describe the relationship between one element and another element shown in the drawings. It will be understood that the terms have relative concepts and are described based on the orientation depicted in the drawings.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Also, unless expressly defined herein, terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0034] It will be understood that the terms "includes" or "comprises", when used in this specification, specify the presence of the stated feature, integer, step, operation, element, component, or combination thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0035] Hereinafter, aspects of some embodiments of the disclosure will be described in more detail with reference to the accompanying drawings.

[0036] Figure 1 is a perspective view of a display device according to some embodiments of the present disclosure.

[0037] Referring to Figure 1 , a display device DD according to some embodiments of the present disclosure may have a rectangular shape in a plan view including a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, the embodiments according to the present disclosure are not limited thereto, and the display device DD may have various shapes such as a circular, oval, or polygonal shape in a plan view.

[0038] Hereinafter, a direction perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In this specification, the phrase "when viewed on a plane" or "in a plan view" may refer to the case when viewed from the third direction DR3.

[0039] The upper surface of the display device DD may be defined as a display surface DS and have a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the display device DD through the display surface DS may be provided to a user in the third direction DR3.

[0040] The display surface DS may include a display area DA and a non-display area NDA around the display area DA (e.g., outside the periphery of the display area DA or outside the covering area of the display area DA). The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and define a boundary of the display device DD printed in a color (e.g., a set or predetermined color).

[0041] The display device DD can be used in large electronic devices such as televisions, monitors, or outdoor billboards. Additionally, the display device DD can be used in small and medium-sized devices such as personal computers (e.g., laptop computers, tablet computers), personal digital terminals, automotive navigation units, gaming consoles, smart phones, or cameras. However, these are presented only as examples, and the display device DD can also be adopted in other electronic devices without departing from the spirit and scope of the embodiments according to the present disclosure.

[0042] Figure 2 A cross-sectional view of the display device according to some embodiments of the present disclosure is shown. Figure 1 as shown in.

[0043] For example, Figure 2 shows a cross-section of the display device DD when viewed in the first direction DR1.

[0044] Referring to Figure 2 , the display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and a first adhesive layer AL1 and a second adhesive layer AL2.

[0045] The display panel DP may be a flexible display panel. The display panel DP according to some embodiments of the present disclosure may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots, quantum rods, and the like. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0046] The input sensing unit ISP may be directly positioned on the display panel DP. The input sensing unit ISP may include a plurality of sensor units for capacitively sensing an external input. When manufacturing the display device DD, the input sensing unit ISP may be directly manufactured on the display panel DP. However, the embodiments according to the present disclosure are not limited thereto. The input sensing unit ISP may be manufactured separately as a panel and then attached to the display panel DP via an adhesive layer.

[0047] The anti-reflection layer RPL may be positioned on the input sensing unit ISP. When manufacturing the display device DD, the anti-reflection layer RPL may be directly manufactured on the input sensing unit ISP. However, the embodiments according to the present disclosure are not limited thereto. The anti-reflection layer RPL may be manufactured separately as a panel and then attached to the input sensing unit ISP via an adhesive layer.

[0048] The antireflection layer RPL can be defined as an external light antireflection film. The antireflection layer RPL can relatively reduce the reflectance of external light entering the display panel DP from above the display device DD. Due to the antireflection layer RPL, the external light may not be observable by the user.

[0049] When the external light traveling toward the display panel DP is reflected at the display panel DP and re-provided to the external user, the external light may be observable by the user, just like being reflected from a mirror. To prevent or relatively reduce this phenomenon, the antireflection layer RPL can include, for example, a plurality of color filters that display the same color as the pixels of the display panel DP.

[0050] The color filters can filter the external light of the same color as the pixels. In this case, the external light may be invisible to the user. However, the embodiments according to the present disclosure are not limited thereto, and the antireflection layer RPL can include a retarder and / or a polarizer for relatively reducing the reflectance of external light.

[0051] The window WIN can be positioned on the antireflection layer RPL. The window WIN can protect the display panel DP, the input sensing unit ISP, and the antireflection layer RPL from external scratches and impacts.

[0052] The panel protective film PPF can be positioned below the display panel DP. The panel protective film PPF can protect the lower part of the display panel DP. The panel protective film PPF can include a flexible plastic material such as polyethylene terephthalate (PET).

[0053] The first adhesive layer AL1 can be positioned between the display panel DP and the panel protective film PPF, and the display panel DP and the panel protective film PPF can be joined to each other via the first adhesive layer AL1. The second adhesive layer AL2 can be positioned between the window WIN and the antireflection layer RPL, and the window WIN and the antireflection layer RPL can be joined to each other via the second adhesive layer AL2.

[0054] Figure 3 A cross-sectional view of a display panel according to some embodiments of the present disclosure is shown. Figure 2 as shown in

[0055] For example, Figure 3 a cross-section of the display panel DP when observed in the first direction DR1 is shown.

[0056] Referring to Figure 3 , the display panel DP can include a substrate SUB, a circuit element layer DP-CL positioned on the substrate SUB, a display element layer DP-OLED positioned on the circuit element layer DP-CL, and a thin film encapsulation layer TFE positioned on the display element layer DP-OLED.

[0057] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The substrate SUB may include glass or a flexible plastic material (such as polyimide (PI)). The display element layer DP-OLED may be positioned at the display area DA.

[0058] A plurality of pixels may be positioned in the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel may include a transistor positioned in the circuit element layer DP-CL and a light-emitting element positioned in the display element layer DP-OLED and connected to the transistor.

[0059] The thin film encapsulation layer TFE may be positioned on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixels from contaminants such as moisture, oxygen, and external foreign substances.

[0060] Figure 4 Yes Figure 2 is a plan view of the display panel shown in.

[0061] Referring to Figure 4 , the display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, and a plurality of pads PD.

[0062] The display panel DP may have a rectangular shape in a plan view, including a long side extending in a first direction DR1 and a short side extending in a second direction DR2. However, the shape of the display panel DP is not limited thereto. The display panel DP may include a display area DA and a non-display area NDA around the display area DA.

[0063] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a control line CSL, a first power supply line PL1 and a second power supply line PL2, and a connection line CNL. m and n are natural numbers greater than 0.

[0064] The pixels PX may be positioned in the display area DA. The pixels PX may be arranged in a matrix form, but the arrangement form of the pixels PX is not limited thereto.

[0065] The scan driver SDV may be positioned in the non-display area NDA adjacent to one of the long sides of the display panel DP. In a plan view, the scan driver SDV may be adjacent to the left side of the display panel DP.

[0066] The data driver DDV may be positioned in the non-display area NDA adjacent to one of the short sides of the display panel DP. In a plan view, the data driver DDV may be adjacent to the lower end of the display panel DP.

[0067] The scan lines SL1 to SLm may extend in the second direction DR2 to be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the first direction DR1 to be connected to the pixels PX and the data driver DDV.

[0068] The first power supply line PL1 may extend in the first direction DR1 and may be positioned in the non-display area NDA. The first power supply line PL1 may be adjacent to the long side of the display panel DP where the scan driver SDV is not positioned.

[0069] The connection line CNL may extend in the second direction DR2 and may be arranged in the first direction DR1 to be connected to the first power supply line PL1 and the pixel PX. The first voltage may be applied to the pixel PX via the first power supply line PL1 and the connection line CNL connected to each other.

[0070] The second power supply line PL2 may be positioned in the non-display area NDA and extend along the long side of the display panel DP and the other short side of the display panel DP where the data driver DDV is not positioned. The second power supply line PL2 may be further positioned outside the scan driver SDV.

[0071] According to some embodiments, the second power supply line PL2 may extend toward the display area DA to be connected to the pixel PX. The second voltage may be applied to the pixel PX via the second power supply line PL2.

[0072] The control line CSL may be connected to the scan driver SDV and extend toward the lower end of the display panel DP. The control signal for controlling the operation of the scan driver SDV may be provided to the scan driver SDV via the control line CSL.

[0073] The pad PD may be positioned in the non-display area NDA adjacent to the lower end of the display panel DP, and may be adjacent to the lower end of the display panel DP closer than the data driver DDV. The data driver DDV, the first power supply line PL1, the second power supply line PL2, and the control line CSL may be connected to the pad PD. The data lines DL1 to DLn may be connected to the data driver DDV, and the data driver DDV may be connected to the pad PD corresponding to the data lines DL1 to DLn.

[0074] According to some embodiments, the display device DD may further include a timing controller for controlling the operations of the scan driver SDV and the data driver DDV, and a voltage generator for generating the first voltage and the second voltage. The timing controller and the voltage generator may be mounted on a printed circuit board and connected to the pad PD via the printed circuit board.

[0075] The scan driver SDV can generate a plurality of scan signals, and the scan signals can be applied to the pixels PX via the scan lines SL1 to SLm. The data driver DDV can generate a plurality of data voltages, and the data voltages can be applied to the pixels PX via the data lines DL1 to DLn.

[0076] The pixel PX can receive the data voltage in response to the scan signal. The pixel PX can display an image by emitting light having a luminance corresponding to the data voltage.

[0077] According to some embodiments of the present disclosure, the size of the pixel PX of the display panel DP can be relatively reduced, and the structure of the pixel PX will be described in more detail below.

[0078] Figure 5 is a view showing a display device according to some embodiments of the present disclosure.

[0079] Referring to Figure 5 , the display device DD' according to some embodiments of the present disclosure can be defined as a head-mounted display device. The display device DD' can be worn on the head of the user USR.

[0080] The display device DD' can provide an image to the user USR by blocking the peripheral vision of the user USR. The display device DD' can provide virtual reality to the user USR.

[0081] The display device DD' can include a housing portion CAS, a cushion portion CUP, and strap portions STP1 and STP2 (herein, the strap portions STP1 and STP2 can refer to the portions of the strap indicated by the reference numerals STP1 and STP2). The housing portion CAS can be worn on the user USR. A display panel DP for displaying an image (e.g., referring to Figure 6 ), an acceleration sensor, etc. can be accommodated inside the housing portion CAS. The display panel DP can be the Figure 4 display panel DP shown in

[0082] The acceleration sensor can detect the movement of the user USR and transmit a signal (e.g., a set or predetermined signal) to the display panel DP. Accordingly, the display panel DP can provide an image corresponding to a change in the gaze of the user USR. As a result, the user USR can experience virtual reality as if it were real reality.

[0083] The cushion portion CUP can be positioned between the housing portion CAS and the user USR. The cushion portion CUP can include a freely deformable material. For example, the cushion portion CUP can include a polymer resin (e.g., polyurethane, polycarbonate, polypropylene, and polyethylene). Additionally, the cushion portion CUP can include a sponge obtained by foaming a rubber solution, a urethane-based material, or an acrylic-based material.

[0084] The cushion part CUP enables the housing part CAS to be in close contact with the user USR, thereby improving the wearing comfort for the user USR. The cushion part CUP may be detachable from the housing part CAS.

[0085] The strap parts STP1 and STP2 are connected to the housing part CAS, which enables the housing part CAS to be easily worn by the user USR. The strap parts STP1 and STP2 may include a first strap STP1 and a second strap STP2.

[0086] The first strap STP1 may be worn along the head circumference of the user USR. The first strap STP1 may fix the housing part CAS to the user USR so that the housing part CAS can be in close contact with the user USR's head.

[0087] The second strap STP2 may connect the housing part CAS and the first strap STP1 along the top of the user USR's head. The second strap STP2 may prevent or relatively reduce the situation where the housing part CAS drops downward.

[0088] Figure 6 Yes Figure 5 The exploded perspective view of the display device shown in

[0089] Referring to Figure 6 , the housing part CAS may include a first housing CAS1 and a second housing CAS2. The first housing CAS1 and the second housing CAS2 may be separated from each other.

[0090] The display panel DP may be positioned between the first housing CAS1 and the second housing CAS2. The first housing CAS1 and the second housing CAS2 are coupled to each other, and the display panel DP may be accommodated inside the housing part CAS. For example, the display panel DP may provide a left-eye image and a right-eye image to the user. Accordingly, the display panel DP may display a three-dimensional image to the user.

[0091] The optical system OTP may be positioned inside the first housing CAS1. The optical system OTP may magnify the image provided from the display panel DP. The optical system OTP may be positioned between the display panel DP and the eyes of the user USR (e.g., referring to Figure 5 ). The optical system OTP may include a left-eye optical system OTP1 and a right-eye optical system OTP2. The left-eye optical system OTP1 may magnify the image to be provided to the left pupil of the user USR and provide it to the user USR, and the right-eye optical system OTP2 may magnify the image to be provided to the right pupil of the user USR and provide it to the user USR.

[0092] Figure 7 Is a view showing Figure 4 One of the pixels shown in Figure 7Various components are shown, but embodiments according to the present disclosure are not limited thereto. For example, in some embodiments, without departing from the spirit and scope of embodiments according to the present disclosure, the circuit of a pixel may include additional components or fewer components.

[0093] For example, Figure 7 A pixel PXij connected to the i-th scan line SLi and the j-th data line DLj is shown. i and j are natural numbers greater than 0. Hereinafter, for convenience of description, the terms "the i-th" and "the j-th" are omitted.

[0094] Referring to Figure 7 , the pixel PXij may include a first transistor T1, a second transistor T2, a third transistor T3, a light-emitting element OLED, and a capacitor CST.

[0095] The scan line SLi may include a write scan line GWLi and a compensation scan line GCLi. The write scan line GWLi may receive a write scan signal GWi, and the compensation scan line GCLi may receive a compensation scan signal GCi.

[0096] A parasitic capacitor CPR may be inadvertently formed between the data line DLj and a second node N2 between the second transistor T2 and the third transistor T3. However, since the parasitic capacitor CPR is not a component of the pixel PXij, the description of the parasitic capacitor CPR will be omitted when the operation of the pixel PXij is shown.

[0097] The first transistor T1 may be a PMOS transistor. The second transistor T2 and the third transistor T3 may be NMOS transistors. The first transistor T1, the second transistor T2, and the third transistor T3 may each include a source electrode, a drain electrode, and a gate electrode. Hereinafter, in Figure 7 , for convenience, one of the source electrode and the drain electrode is defined as a first electrode, and the other is defined as a second electrode. Additionally, the gate electrode is defined as a control electrode.

[0098] The first transistor T1 may be defined as a driving transistor, and the second transistor T2 may be defined as a switching transistor. The third transistor T3 may be defined as a compensating transistor.

[0099] The first transistor T1 may be connected to a first power supply line PL1 and the light-emitting element OLED, and may be switched according to the voltage of the first node N1. The first power supply line PL1 may receive a first voltage ELVDD.

[0100] The first transistor T1 may include a first electrode connected to the first power supply line PL1, a second electrode connected to the anode of the light-emitting element OLED, and a control electrode connected to the first node N1. The first transistor T1 may be turned on by the voltage of the first node N1. The first node N1 may be defined by the control electrode of the first transistor T1.

[0101] The second transistor T2 may be connected to the first node N1 and the second node N2, and may be switched by the write scan signal GWi. The second transistor T2 may include a first electrode connected to the first node N1, a second electrode connected to the second node N2, and a control electrode connected to the write scan line GWLi. The second transistor T2 may be turned on by the write scan signal GWi applied via the write scan line GWLi.

[0102] The third transistor T3 may be connected to the second node N2 and the light-emitting element OLED, and is switched by the compensation scan signal GCi. The third transistor T3 may include a first electrode connected to the second node N2, a second electrode connected to the anode of the light-emitting element OLED, and a control electrode connected to the compensation scan line GCLi. The third transistor T3 may be turned on by the compensation scan signal GCi applied via the compensation scan line GCLi.

[0103] The second transistor T2 may be turned on by the active write scan signal GWi. The third transistor T3 may be turned on by the active compensation scan signal GCi. Since the second transistor T2 and the third transistor T3 are NMOS transistors, the active write scan signal GWi and the active compensation scan signal GCi may be defined as high-level signals.

[0104] The data line DLj may be connected to the second node N2. Accordingly, the data line DLj may be connected to the second electrode of the second transistor T2 and the first electrode of the third transistor T3. The data line DLj may receive the data signal DATA.

[0105] The anode of the light-emitting element OLED may be connected to the first power supply line PL1 via the first transistor T1, and the cathode of the light-emitting element OLED may be connected to the second power supply line PL2. The second power supply line PL2 may receive the second voltage ELVSS.

[0106] The capacitor CST may include a first electrode connected to the initialization line VIL and a second electrode connected to the first node N1. The initialization line VIL may receive the initialization voltage VINT.

[0107] The write scan signal GWi applied to the control electrode of the second transistor T2 may be a global clock signal for simultaneous (or synchronous) emission driving. For example, when the display device DD (e.g., refer to Figure 4)When operating in a simultaneous (or synchronous) emission driving mode, the write scan signal GWi, which is a global clock signal, can be commonly applied to the pixels PX.

[0108] Figure 8 is for operating Figure 7 is a timing diagram of the signals for the pixels shown in

[0109] Referring to Figure 7 and Figure 8 , the operation section of the pixel PXij can include a turn-on bias section OP, an initialization section IP, a compensation section CP, a data write section DWP, and an emission section EMP.

[0110] The pixel PXij can perform a turn-on bias operation in the turn-on bias section OP and an initialization operation in the initialization section IP. The pixel PXij can perform a threshold voltage compensation operation in the compensation section CP, a data write operation in the data write section DWP, and an emission operation in the emission section EMP.

[0111] In the turn-on bias section OP, the first voltage ELVDD can have a high voltage level, the second voltage ELVSS can have a high voltage level, and the initialization voltage VINT can have a low voltage level. In the turn-on bias section OP, the write scan signal GWi and the compensation scan signal GCi can each have a low level (e.g., a disabled level), and the data signal DATA can have a reference voltage VR with a preset level.

[0112] In this case, a turn-on bias operation is performed on the pixel PXij, and thus the voltage characteristic curve of the first transistor T1 can be initialized to the turn-on bias state, regardless of the data signal DATA supplied in the previous frame. As a result, the pixel PXij can generate a desired luminance, regardless of the data signal DATA supplied in the previous frame.

[0113] In the turn-on bias section OP, the initialization voltage VINT having a low voltage level is sent to the gate terminal of the first transistor T1. However, both the first voltage ELVDD and the second voltage ELVSS have high voltage levels, and thus the first transistor T1 may not conduct. The second transistor T2 and the third transistor T3 can be turned off according to the disabled write scan signal GWi and the compensation scan signal GCi.

[0114] Thereafter, in the initialization section IP, the first voltage ELVDD can have a low voltage level, the second voltage ELVSS can have a high voltage level, and the initialization voltage VINT can have a low voltage level. In the initialization section IP, the write scan signal GWi can be converted from a low level to a high level (e.g., an active level), the compensation scan signal GCi can have a high level (e.g., an active level), and the data signal DATA can have a reference voltage VR.

[0115] Accordingly, the second transistor T2 can be turned off first and then turned on, and the third transistor T3 can be turned on. Since the second transistor T2 and the third transistor T3 are turned on, the first node N1 can be connected to the second node N2, and the second node N2 can be connected to the anode of the light-emitting element OLED. According to the initialization voltage VINT, the first node (i.e., the control electrode of the first transistor T1) can be initialized, the second node N2 connected to the first node N1 can be initialized, and the anode of the light-emitting element OLED connected to the second node N2 can be initialized.

[0116] Thereafter, in the compensation section CP, the first voltage ELVDD can have a high voltage level, the second voltage ELVSS can have a high voltage level, and the initialization voltage VINT can have a high voltage level. In the compensation section CP, the write scan signal GWi can have a high level, the compensation scan signal GCi can have a high level, and the data signal DATA can have the reference voltage VR.

[0117] The first transistor T1, the second transistor T2, and the third transistor T3 can be connected in diode form. In this case, the voltage reflecting the threshold voltage of the first transistor T1 is stored in the first node N1, and thus the characteristic deviation according to the threshold voltage of the first transistor T1 can be eliminated. The operation of connecting the first transistor T1 in diode form can be defined as a threshold voltage compensation operation.

[0118] Thereafter, in the data write section DWP, the first voltage ELVDD can have a low voltage level, and the second voltage ELVSS can have a high voltage level. In the data write section DWP, when a certain period of time (e.g., a set or predetermined time) has elapsed after the initialization voltage VINT has been converted from a high voltage level to a low voltage level, the initialization voltage VINT can be converted from a low voltage level to a high voltage level.

[0119] In the data write section DWP, when a certain period of time (e.g., a set or predetermined time) (e.g., the data write operation time) has elapsed after the write scan signal GWi has been converted from a low level to a high level, the write scan signal GWi can be converted from a high level to a low level. In the data write section DWP, the compensation scan signal GCi can have a low level, and the data signal DATA can have a data voltage VD corresponding to the gray level (e.g., a set or predetermined gray level).

[0120] During the section (e.g., high level) in which the write scan signal GWi is activated, the second transistor T2 can be turned on, and the third transistor T3 can be turned off. During the data write operation time when the second transistor T2 is turned on, the data signal DATA can be stored in the capacitor CST.

[0121] Thereafter, in the emission-stage EMP, the first voltage ELVDD may have a high voltage level, the second voltage ELVSS may have a low voltage level, and the initialization voltage VINT may have a high voltage level. The write scan signal GWi may have a low level, the compensation scan signal GCi may have a low level, and the data signal DATA may have the reference voltage VR.

[0122] In this case, the first transistor T1 may be turned on based on the data signal DATA stored in the capacitor CST. Accordingly, current flows to the light-emitting element OLED, and thus the light-emitting element OLED may emit light.

[0123] Figure 9 is schematically shown Figure 7 a cross-sectional view of the first transistor and the light-emitting element shown in

[0124] Referring to Figure 9 , the light-emitting element OLED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and a light-emitting layer EML. The first electrode AE may be Figure 7 the anode shown in Figure 7 , and the second electrode CE may be

[0125] the cathode shown in Figure 4 . The second electrode CE may be positioned on the first electrode AE, and the hole control layer HCL, the electron control layer ECL, and the light-emitting layer EML may be positioned between the first electrode AE and the second electrode CE.

[0126] The buffer layer BFL may be positioned on the substrate SUB. The first semiconductor layers S1, A1, and D1 of the first transistor T1 (herein, the first semiconductor layers S1, A1, and D1 may refer to the portions in the first semiconductor layer indicated by the reference numerals S1, A1, and D1) may be positioned on the buffer layer BFL. The first semiconductor layers S1, A1, and D1 may include polysilicon. However, according to an embodiment of the present disclosure, this is not limited thereto, and the first semiconductor layers S1, A1, and D1 may include amorphous silicon.

[0127] The first semiconductor layers S1, A1, and D1 may be doped with an N-type dopant or a P-type dopant. The first semiconductor layers S1, A1, and D1 may include a heavily doped region and a lightly doped region. The conductivity of the heavily doped region is greater than that of the lightly doped region, and the heavily doped region may be used as the source electrode and the drain electrode of the first transistor T1. The lightly doped region may correspond to the active portion (or channel) of the first transistor T1.

[0128] The first semiconductor layers S1, A1, and D1 may include a first source region S1, a first channel region A1, and a first drain region D1. The first channel region A1 may be positioned between the first source region S1 and the first drain region D1. The first source region S1 may be the first electrode of the first transistor T1 described above. The first drain region D1 may be the second electrode of the first transistor T1 described above. Accordingly, the first semiconductor layers S1, A1, and D1 may be connected to the first power supply line PL1 and the light-emitting element OLED.

[0129] The first insulating layer INS1 may be positioned on the buffer layer BFL to cover the first semiconductor layers S1, A1, and D1. The first gate electrode G1 of the first transistor T1 may be positioned on the first insulating layer INS1. In a plan view, the first gate electrode G1 may overlap with the first channel region A1. The first gate electrode G1 may be connected to the first node N1 that is the control electrode of the first transistor T1 described above. According to some embodiments, the first gate electrode G1 may serve as the first node N1.

[0130] The second insulating layer INS2 may be positioned on the first insulating layer INS1 to cover the first gate electrode G1. The dummy electrode DME may be positioned on the second insulating layer INS2. The dummy electrode DME may form the capacitor CST described above together with the first gate electrode G1. The first gate electrode G1 may define the first electrode of the capacitor CST, and the dummy electrode DME may define the second electrode of the capacitor CST.

[0131] The third insulating layer INS3 may be positioned on the second insulating layer INS2 to cover the dummy electrode DME. The fourth insulating layer INS4 may be positioned on the third insulating layer INS3, the fifth insulating layer INS5 may be positioned on the fourth insulating layer INS4, and the sixth insulating layer INS6 may be positioned on the fifth insulating layer INS5. The buffer layer BFL and the first insulating layer INS1 to the sixth insulating layer INS6 may include inorganic layers. The fourth insulating layer INS4 and the sixth insulating layer INS6 may be thicker than the other insulating layers INS1 to INS3 and INS5.

[0132] The connection electrode CNE may be positioned between the first transistor T1 and the light-emitting element OLED. The connection electrode CNE may electrically connect the first transistor T1 and the light-emitting element OLED. The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 positioned on the first connection electrode CNE1.

[0133] The first connection electrode CNE1 may be positioned on the sixth insulating layer INS6 and may be connected to the first drain region D1 via a first contact hole CH1 defined in the first insulating layer INS1 to the sixth insulating layer INS6. The seventh insulating layer INS7 may be positioned on the sixth insulating layer INS6 to cover the first connection electrode CNE1.

[0134] The second connection electrode CNE2 may be positioned on the seventh insulating layer INS7. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a second contact hole CH2 defined in the seventh insulating layer INS7. The eighth insulating layer INS8 may be positioned on the seventh insulating layer INS7 to cover the second connection electrode CNE2.

[0135] The first connection electrode CNE1-1 may be positioned on the sixth insulating layer INS6. The first connection electrode CNE1-1 may be connected to the first source region S1 via a first contact hole CH1-1 defined in the first insulating layer INS1 to the sixth insulating layer INS6. The seventh insulating layer INS7 may be positioned on the sixth insulating layer INS6 to cover the first connection electrode CNE1-1.

[0136] The first power supply line PL1 may be positioned on the seventh insulating layer INS7. The first power supply line PL1 may be connected to the first connection electrode CNE1-1 via a second contact hole CH2-1 defined in the seventh insulating layer INS7. The eighth insulating layer INS8 may be positioned on the seventh insulating layer INS7 to cover the first power supply line PL1. According to this structure, the first semiconductor layers S1, A1, and D1 may be connected to the first power supply line PL1.

[0137] The first electrode AE may be positioned on the eighth insulating layer INS8. The first electrode AE may be electrically connected to the second connection electrode CNE2 via a third contact hole CH3 defined in the eighth insulating layer INS8. Accordingly, the first drain region D1 may be connected to the light-emitting element OLED via the connection electrode CNE. According to this structure, the first semiconductor layers S1, A1, and D1 may be connected to the light-emitting element OLED.

[0138] The pixel defining film PDL that exposes a portion (e.g., a set or predetermined portion) of the first electrode AE may be positioned on the first electrode AE and the eighth insulating layer INS8. An opening PX_OP for exposing a portion (e.g., a set or predetermined portion) of the first electrode AE may be defined in the pixel defining film PDL.

[0139] The hole control layer HCL may be positioned on the first electrode AE and the pixel defining film PDL. The hole control layer HCL may be commonly positioned in the light-emitting region LA and the non-light-emitting region NLEA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0140] The light-emitting layer EML may be positioned on the hole control layer HCL. The light-emitting layer EML may be positioned in a region corresponding to the opening PX_OP. The light-emitting layer EML may include an organic material and / or an inorganic material. The light-emitting layer EML may generate light having one color among red, green, and blue.

[0141] The electronic control layer ECL may be positioned over the light-emitting layer EML and the hole control layer HCL. The electronic control layer ECL may be commonly positioned in the light-emitting area LA and the non-light-emitting area NLEA. The electronic control layer ECL may include an electron transport layer and an electron injection layer.

[0142] The second electrode CE may be positioned over the electronic control layer ECL. The second electrode CE may be commonly positioned in a plurality of pixels PX (e.g., refer to Figure 4 ). That is, the second electrode CE may be commonly positioned over the light-emitting layer EML of a plurality of pixels PX.

[0143] The layer including the buffer layer BFL to the eighth insulating layer INS8 may be defined as a circuit element layer DP-CL (e.g., refer to Figure 3 ). The layer including the substrate SUB to the eighth insulating layer INS8 may be defined as a circuit element unit DE-CL. The layer in which the light-emitting element OLED is positioned may be defined as a display element layer DP-OLED.

[0144] The thin film encapsulation layer TFE may be positioned over the light-emitting element OLED. The thin film encapsulation layer TFE may include an inorganic layer, an organic layer, and an inorganic layer stacked in sequence. The inorganic layer may include an inorganic material and protect the pixel PX from moisture / oxygen. The organic layer may include an organic material and protect the pixel PX from foreign substances or contaminants (such as dust particles or moisture).

[0145] A first voltage ELVDD may be applied to the first electrode AE, and a second voltage ELVSS may be applied to the second electrode CE. The holes and electrons injected into the light-emitting layer EML recombine to form excitons, and the excitons transition to the ground state so that the light-emitting element OLED can emit light. The light-emitting element OLED emits light and thus can display an image.

[0146] Figure 10 is a view schematically showing Figure 7 the planar configuration of the second transistor and the third transistor shown in

[0147] Refer to Figure 10 , the second transistor T2 and the third transistor T3 may be arranged in a first direction DR1. The second transistor T2 and the third transistor T3 may each have a structure symmetric with respect to the first direction DR1.

[0148] The semiconductor pattern SMP may extend in a first direction DR1. The second semiconductor layers S2, A2, and D2 of the second transistor T2 (herein, the second semiconductor layers S2, A2, and D2 may refer to the portions in the second semiconductor layer indicated by reference numerals S2, A2, and D2) and the third semiconductor layers S3, A3, and D3 of the third transistor T3 (herein, the third semiconductor layers S3, A3, and D3 may refer to the portions in the third semiconductor layer indicated by reference numerals S3, A3, and D3) may be formed by the semiconductor pattern SMP.

[0149] The second semiconductor layers S2, A2, and D2 may include a second source region S2, a second channel region A2, and a second drain region D2. The second channel region A2 may be positioned between the second source region S2 and the second drain region D2.

[0150] The second source region S2 may be the first electrode of the second transistor T2 described above, and the second drain region D2 may be the second electrode of the second transistor T2 described above. Accordingly, the second semiconductor layers S2, A2, and D2 may be connected to a first node N1 (e.g., refer to Figure 7 ) and a second node N2 (e.g., refer to Figure 7 ). The second source region S2 may be connected to the first node N1, and the second drain region D2 may be connected to the second node N2.

[0151] The third semiconductor layers S3, A3, and D3 may include a third source region S3, a third channel region A3, and a third drain region D3. The third channel region A3 may be positioned between the third source region S3 and the third drain region D3.

[0152] The third source region S3 may be the first electrode of the third transistor T3 described above, and the third drain region D3 may be the second electrode of the third transistor T3 described above. Accordingly, the third semiconductor layers S3, A3, and D3 may be connected to the second node N2 (e.g., refer to Figure 7 ) and a light-emitting element OLED (e.g., refer to Figure 7 ). The third source region S3 may be connected to the second node N2, and the third drain region D3 may be connected to the light-emitting element OLED.

[0153] The second semiconductor layers S2, A2, and D2 and the third semiconductor layers S3, A3, and D3 may be integrally formed. For example, the third source region S3 may be formed by extending from the second drain region D2.

[0154] The gate electrode of the second transistor T2 may include a 2-1 gate electrode G2-1 and a 2-2 gate electrode G2-2. The 2-1 gate electrode G2-1 may extend in a second direction DR2. The 2-1 gate electrode G2-1 may extend to cross the second semiconductor layers S2, A2, and D2. A portion of the second semiconductor layers S2, A2, and D2 that overlaps with the 2-1 gate electrode G2-1 may be defined as a second channel region A2.

[0155] The 2-2 gate electrode G2-2 may have a T shape and extend to cross the second semiconductor layers S2, A2, and D2. To have a T shape, the 2-2 gate electrode G2-2 may extend in the second direction DR2, and a portion of the 2-2 gate electrode G2-2 may protrude in a first direction DR1. The 2-2 gate electrode G2-2 may partially overlap with the 2-1 gate electrode G2-1. In a plan view, the 2-2 gate electrode G2-2 may have an area larger than the area of the second channel region A2 so as to cover the second channel region A2.

[0156] The gate electrode of the third transistor T3 may include a 3-1 gate electrode G3-1 and a 3-2 gate electrode G3-2. The 3-1 gate electrode G3-1 may extend in the second direction DR2. The 3-1 gate electrode G3-1 may extend to cross the third semiconductor layers S3, A3, and D3. A portion of the third semiconductor layers S3, A3, and D3 that overlaps with the 3-1 gate electrode G3-1 may be defined as a third channel region A3.

[0157] The 3-2 gate electrode G3-2 may have a T shape and extend to cross the third semiconductor layers S3, A3, and D3. To have a T shape, the 3-2 gate electrode G3-2 may extend in the second direction DR2, and a portion of the 3-2 gate electrode G3-2 may protrude in the first direction DR1. A portion of the 2-2 gate electrode G2-2 that protrudes in the first direction DR1 and a portion of the 3-2 gate electrode G3-2 that protrudes in the first direction DR1 may face each other.

[0158] The 3-2 gate electrode G3-2 may have a shape symmetric to that of the 2-2 gate electrode G2-2. The 3-2 gate electrode G3-2 may partially overlap with the 3-1 gate electrode G3-1. In a plan view, the 3-2 gate electrode G3-2 may have an area larger than the area of the third channel region A3 so as to cover the third channel region A3.

[0159] According to the above structure, the second transistor T2 may include a second source region S2, a second channel region A2, a second drain region D2, a 2-1 gate electrode G2-1, and a 2-2 gate electrode G2-2. Moreover, the third transistor T3 may include a third source region S3, a third channel region A3, a third drain region D3, a 3-1 gate electrode G3-1, and a 3-2 gate electrode G3-2.

[0160] The second - second gate electrode G2 - 2 may be spaced apart from the third - second gate electrode G3 - 2 by a first distance DT1 in a first direction DR1. The first distance DT1 may be defined as the distance between the portion of the second - second gate electrode G2 - 2 protruding in the first direction DR1 and the portion of the third - second gate electrode G3 - 2 protruding in the first direction DR1. The first distance DT1 may be from about 0.5 μm to about 1.5 μm.

[0161] Figure 11 is a cross - sectional view taken along Figure 10 the line I - I' shown in

[0162] For example, in Figure 11 the cross - section of the light - emitting element OLED (for example, refer to Figure 7 ) is omitted.

[0163] Referring to Figure 11 , a buffer layer BFL, a first insulating layer INS1, and a second insulating layer INS2 may be positioned on a substrate SUB. The third - second gate electrode G3 - 2 may be positioned on the second insulating layer INS2. A third insulating layer INS3 may be positioned on the second insulating layer INS2 to cover the third - second gate electrode G3 - 2. The second - second gate electrode G2 - 2 may be positioned on the third insulating layer INS3. A fourth insulating layer INS4 may be positioned on the third insulating layer INS3 to cover the second - second gate electrode G2 - 2.

[0164] A second semiconductor layer S2, A2, and D2 and a third semiconductor layer S3, A3, and D3 may be positioned on the fourth insulating layer INS4. The second semiconductor layer S2, A2, and D2 and the third semiconductor layer S3, A3, and D3 may include an oxide semiconductor formed of a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0165] The second semiconductor layer S2, A2, and D2 and the third semiconductor layer S3, A3, and D3 may each include a plurality of regions differentiated according to whether the metal oxide is relatively reduced. The conductivity of the region where the metal oxide is relatively reduced (hereinafter referred to as the reduced region) is higher than the conductivity of the region where the metal oxide is not reduced (hereinafter referred to as the non - reduced region). The reduced region may be used as a source electrode or a drain electrode for each of the second transistor T2 and the third transistor T3. The non - reduced region may correspond to the active portion (or channel) of each of the second transistor T2 and the third transistor T3.

[0166] The third semiconductor layer S3, A3, and D3 may be formed by extending from the second semiconductor layer S2, A2, and D2. A second channel region A2 may be positioned between a second source region S2 and a second drain region D2, and a third channel region A3 may be positioned between a third source region S3 and a third drain region D3.

[0167] The second - second gate electrode G2 - 2 may have an area larger than the area of the second channel region A2, be positioned below the second channel region A2, and cover the second channel region A2. The third - second gate electrode G3 - 2 may have an area larger than the area of the third channel region A3, be positioned below the third channel region A3, and cover the third channel region A3.

[0168] The second - second gate electrode G2 - 2 may block light provided from below the substrate SUB toward the second channel region A2. The third - second gate electrode G3 - 2 may block light provided from below the substrate SUB toward the third channel region A3.

[0169] When light is provided to the second channel region A2 and the third channel region A3, the light may cause a change in the threshold voltage characteristics (e.g., threshold voltage shift) of the second transistor T2 and the third transistor T3. To prevent or relatively reduce this phenomenon, the second - second gate electrode G2 - 2 and the third - second gate electrode G3 - 2 may block light provided from below the substrate SUB toward the second channel region A2 and the third channel region A3.

[0170] The second node N2 may be defined between the second semiconductor layers S2, A2, and D2 and the third semiconductor layers S3, A3, and D3. The portion of the semiconductor layer between the third source region S3 and the second drain region D2 may be defined as the second node N2. That is, the second semiconductor layers S2, A2, and D2 and the third semiconductor layers S3, A3, and D3 may be connected to the second node N2. The fourth insulating layer INS4 may be positioned on the third insulating layer INS3 to cover the second semiconductor layers S2, A2, and D2 and the third semiconductor layers S3, A3, and D3. In this embodiment, the fifth insulating layer INS5 may be positioned on the fourth insulating layer INS4 to cover the second semiconductor layers S2, A2, and D2 and the third semiconductor layers S3, A3, and D3.

[0171] The second - first gate electrode G2 - 1 and the third - first gate electrode G3 - 1 may be positioned on the fourth insulating layer INS4. In this embodiment, the second - first gate electrode G2 - 1 and the third - first gate electrode G3 - 1 may be positioned on the fifth insulating layer INS5. In a plan view, the second - first gate electrode G2 - 1 may overlap with the second channel region A2. In a plan view, the third - first gate electrode G3 - 1 may overlap with the third channel region A3.

[0172] According to this structure, the second - first gate electrode G2 - 1 may be positioned on the second semiconductor layers S2, A2, and D2, and the second - second gate electrode G2 - 2 may be positioned below the second semiconductor layers S2, A2, and D2. The third - first gate electrode G3 - 1 may be positioned on the third semiconductor layers S3, A3, and D3, and the third - second gate electrode G3 - 2 may be positioned below the third semiconductor layers S3, A3, and D3.

[0173] The second gate electrode G2-2 and the third gate electrode G3-2 may be positioned on a layer above the first gate electrode G1 shown in Figure 9 . For example, the second insulating layer INS2 may be positioned on the first transistor T1, and specifically, the second insulating layer INS2 may be positioned on the first gate electrode G1. The second gate electrode G2-2 and the third gate electrode G3-2 may be positioned on the second insulating layer INS2 and, thus, on a layer above the first gate electrode G1.

[0174] The second gate electrode G2-2 and the third gate electrode G3-2 may be positioned on different layers (or in different positions). For example, the second gate electrode G2-2 may be positioned on a layer above the third gate electrode G3-2.

[0175] The sixth insulating layer INS6 may be positioned on the fifth insulating layer INS5 to cover the second gate electrode G2-1 and the third gate electrode G3-1. The first connection electrode CNE1-2 may be positioned on the sixth insulating layer INS6. The first connection electrode CNE1-2 may be connected to the second node N2 via a first contact hole CH1-2 defined in the sixth insulating layer INS6.

[0176] The seventh insulating layer INS7 may be positioned on the sixth insulating layer INS6 to cover the first connection electrode CNE1-2. The data line DLj may be positioned on the seventh insulating layer INS7. The data line DLj may be connected to the first connection electrode CNE1-2 via a second contact hole CH2-2 defined in the seventh insulating layer INS7. The eighth insulating layer INS8 may be positioned on the data line DLj and the seventh insulating layer INS7.

[0177] The write scan signal GWi described above may be applied to the second gate electrode G2-1 and the second gate electrode G2-2. When the second gate electrode G2-1 and the second gate electrode G2-2 are respectively positioned above and below the second semiconductor layers S2, A2, and D2, the electron mobility of the second transistor T2 may be increased.

[0178] The compensation scan signal GCi described above may be applied to the third gate electrode G3-1 and the third gate electrode G3-2. When the third gate electrode G3-1 and the third gate electrode G3-2 are respectively positioned above and below the third semiconductor layers S3, A3, and D3, the electron mobility of the third transistor T3 may be increased.

[0179] Table 1 below shows the driving characteristics of each of the second transistor T2 and the third transistor T3.

[0180] [Table 1]

[0181] TR type Vth (V) DR range (V) <![CDATA[Mobility(cm 2 / Vs)]]> Ion (μA) T2 -1.23 2.05 7.2 5.00 T3 -1.22 2.08 6.9 4.89

[0182] In Table 1, Vth represents the threshold voltage, and the DR range represents the change in gate voltage within a specific range of drain current in the transfer curve (Id-Vg) of the transistor. For example, the DR range can represent the change in gate voltage in which the drain current of the transfer curve has a range of approximately 1 μA to approximately 1 pA. The difference between the gate voltage corresponding to approximately 1 μA and the gate voltage corresponding to approximately 1 pA can be defined as the DR range, and its unit is volts (V). In Table 1, Mobility represents the electron mobility, and Ion represents the current flowing in the transistor.

[0183] As shown in Table 1, the second transistor T2 and the third transistor T3 can have similar driving characteristics. It can be seen that even if the 2-2 gate electrode G2-2 and the 3-2 gate electrode G3-2 are located on different layers (or in different positions), there is no significant difference in the driving characteristics of the second transistor T2 and the third transistor T3.

[0184] According to some embodiments of the present disclosure, the 2-2 gate electrode G2-2 can be located on a layer above the 3-2 gate electrode G3-2. Accordingly, the distance between the 2-2 gate electrode G2-2 and the second semiconductor layers S2, A2, and D2 can be shorter than the distance between the 3-2 gate electrode G3-2 and the third semiconductor layers S3, A3, and D3.

[0185] In this case, as shown in Table 1, the electron mobility (Mobility) and current (Ion) of the second transistor T2 can become larger. According to the writing operation of the second transistor T2 may be more important than the compensation operation according to the third transistor T3. Accordingly, the 2-2 gate electrode G2-2 is positioned closer to the second semiconductor layers S2, A2, and D2, and thus the electron mobility (Mobility) and current (Ion) of the second transistor T2 can be greater than the electron mobility (Mobility) and current (Ion) of the third transistor T3.

[0186] Figure 12 is a cross-sectional view schematically showing the connection structure for the first transistor and the second transistor. Figure 13 is a cross-sectional view schematically showing the connection structure for the first transistor and the third transistor.

[0187] For example, in Figure 12 and Figure 13 the cross-section of the eighth insulating layer INS8 (for example, refer to Figure 11 ) and the light-emitting element OLED (for example, refer to Figure 7 ) is omitted. For the convenience of description, in Figure 12The second semiconductor layers S2, A2, and D2 are shown, and the third semiconductor layers S3, A3, and D3 that extend continuously with the second semiconductor layers S2, A2, and D2 are omitted. Additionally, in Figure 13 the third semiconductor layers S3, A3, and D3 are shown, and the second semiconductor layers S2, A2, and D2 that extend continuously with the third semiconductor layers S3, A3, and D3 are omitted. Moreover, in Figure 12 and Figure 13 the dummy electrode DME (for example, refer to Figure 9 ) is omitted.

[0188] Refer to Figure 12 , the first connection electrodes CNE1-3 can be positioned on the sixth insulating layer INS6. The first transistor T1 and the second transistor T2 can be connected via the first connection electrodes CNE1-3.

[0189] The first connection electrodes CNE1-3 can be connected to the first gate electrode G1 of the first transistor T1 via the first contact holes CH1-3 defined in the second insulating layer INS2 to the sixth insulating layer INS6. The first connection electrodes CNE1-3 can be connected to the second source region S2 of the second transistor T2 via the first contact hole CH1-4 defined in the fifth insulating layer INS5 and the sixth insulating layer INS6. Since the first gate electrode G1 defines the first node N1 (for example, refer to Figure 7 ), the second source region S2 of the second transistor T2 can be connected to the first node N1.

[0190] Refer to Figure 13 , the first connection electrode CNE1 can be positioned on the sixth insulating layer INS6. The first transistor T1 can be connected to the third transistor T3 via the first connection electrode CNE1. The first connection electrode CNE1 can be Figure 9 the first connection electrode CNE1 shown in

[0191] The first connection electrode CNE1 can extend toward the third transistor T3 on the sixth insulating layer INS6. The first connection electrode CNE1 can be connected to the third drain region D3 of the third transistor T3 via the first contact hole CH1-5 defined in the fifth insulating layer INS5 and the sixth insulating layer INS6. As described in Figure 9 , the first connection electrode CNE1 can be connected to the light-emitting element OLED and the first transistor T1. According to this structure, the third transistor T3 can be connected to the light-emitting element OLED and the first transistor T1.

[0192] Figure 14 is a view schematically showing a planar configuration of a second transistor and a third transistor of a pixel according to a comparative example of the present disclosure.

[0193] For example, Figure 14shown as being associated with Figure 10 in a plan view, and hereinafter, the description of the configuration shown in Figure 14 will focus mainly on components different from those shown in Figure 10 Referring to

[0194] Referring to Figure 14 , the planar configuration of the second transistor T2' and the third transistor T3' may be the same as the planar configuration of the second transistor T2 and the third transistor T3. However, the 2-2 gate electrode G2-2' of the second transistor T2' and the 3-2 gate electrode G3-2' of the third transistor T3' may be positioned on the same layer (or in the same layer).

[0195] Based on the cross-section shown in Figure 11 , the 2-2 gate electrode G2-2' and the 3-2 gate electrode G3-2' may be positioned on the second insulating layer INS2. However, embodiments according to the present disclosure are not limited thereto, and the 2-2 gate electrode G2-2' and the 3-2 gate electrode G3-2' may be positioned on the third insulating layer INS3.

[0196] When the 2-2 gate electrode G2-2' and the 3-2 gate electrode G3-2' are formed on the same layer (or in the same layer), a process margin is required to prevent or relatively reduce defects such as short circuits. For example, the 2-2 gate electrode G2-2' and the 3-2 gate electrode G3-2' may not be short-circuited only when the 2-2 gate electrode G2-2' is spaced apart from the 3-2 gate electrode G3-2' by a certain distance or more.

[0197] For example, the 2-2 gate electrode G2-2' and the 3-2 gate electrode G3-2' may not be short-circuited only when the 2-2 gate electrode G2-2' is spaced apart from the 3-2 gate electrode G3-2' by a second distance DT2. However, the second distance DT2 may be greater than the first distance DT1. When the 2-2 gate electrode G2-2' is spaced apart from the 3-2 gate electrode G3-2' by a distance greater than the second distance DT2, the size of the pixel PX (e.g., referring to Figure 4 ) may become larger. When the size of the pixel PX increases, the number of pixels PX that can be positioned in the display area DA (e.g., referring to Figure 4 ) may decrease.

[0198] Referring to Figure 10 and Figure 11 , according to some embodiments of the present disclosure, the 2-2 gate electrode G2-2 and the 3-2 gate electrode G3-2 may be positioned on different layers (or in different layers) and may be insulated by the third insulating layer INS3. Accordingly, since the 2-2 gate electrode G2-2 and the 3-2 gate electrode G3-2 are less likely to be short-circuited, the 2-2 gate electrode G2-2 and the 3-2 gate electrode G3-2 may be positioned closer to each other at the first distance DT1.

[0199] The second gate electrode G2-2 and the third gate electrode G3-2 are positioned close to each other, and thus the size of the pixel PX (e.g., refer to Figure 4 ) can become smaller. When the size of the pixel PX decreases, the number of pixels PX that can be positioned in the display area DA (e.g., refer to Figure 4 ) can increase. Therefore, according to some embodiments of the present disclosure, a high-resolution display device DD (e.g., refer to Figure 1 ) can be achieved.

[0200] Figures 15 to 18 is a view schematically showing a cross-sectional configuration of a second transistor and a third transistor according to some embodiments of the present disclosure.

[0201] For example, Figures 15 to 18 shows a cross-section corresponding to Figure 11 , and hereinafter, the description of the configuration shown in Figures 15 to 18 will focus on components different from those shown in Figure 11 .

[0202] Referring to Figure 15 , the second transistor T2-1 may include a second semiconductor layer S2, A2, and D2, a 2-1 gate electrode G2-1 positioned on the second semiconductor layer S2, A2, and D2, and a 2-2 gate electrode G2-2 positioned below the second semiconductor layer S2, A2, and D2. The third transistor T3-1 may include a third semiconductor layer S3, A3, and D3, a 3-1 gate electrode G3-1 positioned on the third semiconductor layer S3, A3, and D3, and a 3-2 gate electrode G3-2 positioned below the third semiconductor layer S3, A3, and D3.

[0203] The 2-2 gate electrode G2-2 may be positioned on the second insulating layer INS2, and the 3-2 gate electrode G3-2 may be positioned on the third insulating layer INS3. Different from that shown in Figure 11 , the 3-2 gate electrode G3-2 may be positioned on a layer above the 2-2 gate electrode G2-2.

[0204] Referring to Figure 16 , the second transistor T2 and the third transistor T3 may have the same (or substantially the same) configuration as the second transistor T2 and the third transistor T3 shown in Figure 11 . However, the first dummy gate electrode DGE1 may be positioned below the 2-2 gate electrode G2-2.

[0205] The first dummy gate electrode DGE1 may be positioned at the same level as the first gate electrode G1 of the first transistor T1 (e.g., refer to Figure 9 ) (e.g., refer to Figure 9) on (or in) the same layer as the layer of (). For example, the first dummy gate electrode DGE1 may be positioned on the first insulating layer INS1, and the second insulating layer INS2 may be positioned on the first dummy gate electrode DGE1.

[0206] In a plan view, the first dummy gate electrode DGE1 may have an area larger than the area of the second channel region A2, be positioned below the second channel region A2, and cover the second channel region A2. The first dummy gate electrode DGE1 may block light provided from below the substrate SUB toward the second channel region A2 together with the 2-2 gate electrode G2-2.

[0207] Referring to Figure 17 , the second transistor T2 and the third transistor T3 may have the same (or substantially the same) configuration as the second transistor T2 and the third transistor T3 shown in Figure 11 . However, the second dummy gate electrode DGE2 may be positioned below the 3-2 gate electrode G3-2.

[0208] The second dummy gate electrode DGE2 may be positioned on (or in) the same layer as the layer of the first gate electrode G1 of the first transistor T1 described above. The second dummy gate electrode DGE2 may be positioned on the first insulating layer INS1, and the second insulating layer INS2 may be positioned on the second dummy gate electrode DGE2.

[0209] In a plan view, the second dummy gate electrode DGE2 may have an area larger than the area of the third channel region A3, be positioned below the third channel region A3, and cover the third channel region A3. The second dummy gate electrode DGE2 may block light provided from below the substrate SUB toward the third channel region A3 together with the 3-2 gate electrode G3-2.

[0210] Referring to Figure 18 , the second transistor T2 and the third transistor T3 may have the same (or substantially the same) configuration as the second transistor T2 and the third transistor T3 shown in Figure 11 . The first dummy gate electrode DGE1 may be positioned below the 2-2 gate electrode G2-2. The second dummy gate electrode DGE2 may be positioned below the 3-2 gate electrode G3-2.

[0211] The first dummy gate electrode DGE1 may block light provided from below the substrate SUB toward the second channel region A2 together with the 2-2 gate electrode G2-2. The second dummy gate electrode DGE2 may block light provided from below the substrate SUB toward the third channel region A3 together with the 3-2 gate electrode G3-2.

[0212] According to some embodiments of the present disclosure, the spacing between the second transistor (e.g., the gate electrode under the semiconductor layer in the second transistor) and the third transistor (e.g., the gate electrode under the semiconductor layer in the third transistor) in each pixel may be relatively reduced, thereby relatively reducing the size of the corresponding pixel. Accordingly, the number of pixels that can be positioned in the display area may be relatively increased, thereby implementing a high-resolution display device.

[0213] In the above content, descriptions have been made with reference to some embodiments of the present disclosure. However, those skilled in the art or ordinary technicians in the relevant technical field can understand that various modifications and changes can be made to the disclosed embodiments of the present disclosure without departing from the spirit and scope of the embodiments according to the present disclosure described in the appended claims. Additionally, the disclosed embodiments in the present disclosure are not intended to limit the technical spirit of the embodiments according to the present disclosure, and all technical ideas within the scope of the appended claims and their equivalents should be interpreted as being included within the scope of the embodiments according to the present disclosure.

Claims

1. A display device, comprising: Light emitting element; a first transistor including a first semiconductor layer connected to a first power supply line and the light emitting element and a first gate electrode on the first semiconductor layer and connected to a first node; a second transistor including a second semiconductor layer connected to the first node and the second node, a 2-1 gate electrode on the second semiconductor layer, and a 2-2 gate electrode under the second semiconductor layer; a data line connected to the second node; as well as a third transistor including a third semiconductor layer connected to the second node and the light emitting element, a 3-1 gate electrode on the third semiconductor layer, and a 3-2 gate electrode under the third semiconductor layer, The 2-2 gate electrode and the 3-2 gate electrode are on a layer above the first gate electrode and on different layers.

2. The display device according to claim 1, further comprising: an insulating layer, the insulating layer being on the first transistor, Wherein, the 2-2 gate electrode and the 3-2 gate electrode are on the insulating layer.

3. The display device according to claim 2, wherein: The 2-2nd gate electrode is on a layer above the 3-2nd gate electrode.

4. The display device according to claim 2, wherein: The 3-2nd gate electrode is on a layer above the 2-2nd gate electrode.

5. The display device according to claim 1, wherein: The first semiconductor layer includes polycrystalline silicon.

6. The display device according to claim 5, wherein: The second semiconductor layer and the third semiconductor layer each include an oxide semiconductor.

7. The display device according to claim 1, wherein: The first semiconductor layer comprises: a first source region connected to the first power supply line; a first drain region connected to the light emitting element; and a first channel region, the first channel region being between the first source region and the first drain region, and In a plan view, the first gate electrode overlaps the first channel region.

8. The display device according to claim 1, wherein: The second semiconductor layer comprises: a second source region, the second source region being connected to the first node; a second drain region connected to the second node; and a second channel region, the second channel region being between the second source region and the second drain region, and In a plan view, the 2-1th gate electrode overlaps with the second channel region.

9. The display device according to claim 8, wherein: In the plan view, the 2-2 gate electrode has an area larger than that of the second channel region, is below the second channel region, and covers the second channel region.

10. The display device according to claim 8, further comprising: A first dummy gate electrode is provided below the 2-2 gate electrode.

11. The display device according to claim 10, wherein: The first dummy gate electrode is at the same layer as the first gate electrode.

12. The display device according to claim 10, wherein: In the plan view, the first dummy gate electrode has an area larger than that of the second channel region, is below the second channel region, and covers the second channel region.

13. The display device according to claim 1, wherein: The third semiconductor layer comprises: a third source region, the third source region connected to the second node; a third drain region connected to the light emitting element; and a third channel region, the third channel region being between the third source region and the third drain region, and In a plan view, the 3-1st gate electrode overlaps with the third channel region.

14. The display device according to claim 13, wherein: In the plan view, the 3-2nd gate electrode has an area larger than that of the third channel region, is below the third channel region and covers the third channel region.

15. The display device according to claim 13, further comprising: A second dummy gate electrode is provided below the 3-2 gate electrode.

16. The display device according to claim 15, wherein: The second dummy gate electrode is at the same layer as the first gate electrode.

17. The display device according to claim 16, wherein: In the plan view, the second dummy gate electrode has an area larger than that of the third channel region, is below the third channel region, and covers the third channel region.

18. A display device comprising: Light emitting element; a first transistor including a first semiconductor layer connected to a first power supply line and the light emitting element and a first gate electrode on the first semiconductor layer and connected to a first node; a second transistor including a second semiconductor layer connected to the first node and the second node, a 2-1 gate electrode on the second semiconductor layer, and a 2-2 gate electrode under the second semiconductor layer; a data line connected to the second node; as well as a third transistor including a third semiconductor layer connected to the second node and the light emitting element, a 3-1 gate electrode on the third semiconductor layer, and a 3-2 gate electrode under the third semiconductor layer, The 2-2 gate electrode and the 3-2 gate electrode are on a layer above the first gate electrode, and the 2-2 gate electrode is on a layer above the 3-2 gate electrode.

19. The display device according to claim 18, further comprising: a first dummy gate electrode, wherein the first dummy gate electrode is below the 2-2 gate electrode; as well as A second dummy gate electrode is provided below the 3-2 gate electrode.

20. A display device, comprising: Light emitting element; a first transistor including a first semiconductor layer connected to a first power supply line and the light emitting element and a first gate electrode on the first semiconductor layer and connected to a first node; an insulating layer, the insulating layer being on the first transistor; a second transistor including a second semiconductor layer on the insulating layer and connected to the first node and the second node, a 2-1 gate electrode on the second semiconductor layer, and a 2-2 gate electrode under the second semiconductor layer; a data line connected to the second node; as well as a third transistor including a third semiconductor layer on the insulating layer and connected to the second node and the light emitting element, a 3-1 gate electrode on the third semiconductor layer, and a 3-2 gate electrode under the third semiconductor layer, The 2-2 gate electrode and the 3-2 gate electrode are on different layers on the insulating layer.

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