Display device and manufacturing method thereof

Abstract

A display device and a method of manufacturing the same are provided. The display device may include: a substrate; a driving circuit unit disposed on the substrate in the display area; a first insulating layer disposed on the driving circuit unit; a second insulating layer including a boss while surrounding at least one end of the first insulating layer; the light emitting diode is arranged on the convex part of the second insulating layer; and a third insulating layer including a recessed portion while surrounding an end portion of the first insulating layer or the second insulating layer, in which the protruding portion and the recessed portion at least partially overlap.

Description

Technical Field

[0001] The present disclosure relates to a display device and a manufacturing method thereof, and more particularly, for example but not limited to, to a display device using light emitting diodes (LEDs) and a manufacturing method thereof. Background Art

[0002] As display devices for computer monitors, televisions, or cellular phones, there are organic light emitting display (OLED) devices as self-luminous devices, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0003] The application range of display devices has diversified to personal mobile devices, computer monitors, and televisions, and even to vehicles, electrical appliances, and buildings, etc., and display devices with a larger display area and reduced volume and weight are being studied.

[0004] In addition, recently, display devices including light emitting diodes (LEDs) have attracted attention as next-generation display devices. Since LEDs are formed of inorganic materials rather than organic materials, they have excellent reliability, so their lifespan is longer than that of liquid crystal display devices or organic light emitting display devices. In addition, LEDs have a fast light emission speed, excellent light emission efficiency, and strong impact resistance, making them excellent in stability and capable of displaying images with high brightness.

[0005] The descriptions provided in the background art section should not be considered prior art merely because they are mentioned in or associated with the background art section. The background art section may include information describing one or more aspects of the subject technology. Summary of the Invention

[0006] An object to be achieved by the present disclosure is to provide a display device and a manufacturing method thereof, in which the display device improves the connection contact hole steps of light emitting diodes and power lines and drivers located below the light emitting diodes through a plurality of insulating films.

[0007] An object to be achieved by the present disclosure is to provide a display device and a manufacturing method thereof, in which the display device suppresses short circuits of connection lines and improves the reflectivity of the display device.

[0008] According to an aspect of the present disclosure, there is provided a display device. The display device includes: a substrate; a driving circuit unit disposed on the substrate in a display area; a first insulating layer disposed on the driving circuit unit; a second insulating layer including a convex portion while surrounding at least one end of the first insulating layer; a light emitting diode disposed on the convex portion of the second insulating layer; and a third insulating layer including a concave portion while surrounding an end of the first insulating layer or the second insulating layer, wherein the convex portion and the concave portion at least partially overlap.

[0009] According to one aspect of the present disclosure, a method of manufacturing a display device is provided. The method of manufacturing the display device includes: forming a driving circuit unit and a power line on a first substrate; forming a planarization layer on the driving circuit unit and the power line; forming a first contact hole exposing at least a part of a source electrode of the driving circuit unit and a second contact hole exposing at least a part of the power line on the planarization layer; forming a metal layer connected to the source electrode and a connection line connected to the power line on the planarization layer; forming a first insulating layer and a second insulating layer on the metal layer and the connection line; disposing a light-emitting diode on the second insulating layer; forming a contact hole overlapping with the second contact hole, a third contact hole exposing at least a part of the metal layer, and a protrusion formed by a region overlapping with the light-emitting diode on the first insulating layer and the second insulating layer; and forming a third insulating layer on the second insulating layer, wherein the third insulating layer includes a recess overlapping with the protrusion of the second insulating layer.

[0010] According to the present disclosure, the step of the contact hole is improved to suppress a short circuit of the connection line.

[0011] According to the present disclosure, a short circuit of the connection line is minimized to improve the reliability of the display device.

[0012] According to the present disclosure, a stepped area of a light-shielding layer is reduced or minimized to improve the reflectance of the display device.

[0013] The effects according to the present disclosure are not limited to the above-exemplified contents, and more various effects are included in the present specification.

[0014] It should be understood that the foregoing general description and the following detailed description are both exemplary and explanatory and are intended to provide further explanation of the claimed inventive concept. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. From the following detailed description in conjunction with the drawings, the above and other aspects, features and other advantages of the present disclosure will be more clearly understood, wherein:

[0016] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0017] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0018] Figure 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 3 is a plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figures 4A to 4F is a plan view showing a method of manufacturing a display device and Figure 3 the structure of a pixel region thereof; and

[0021] Figures 5A to 5E is a cross-sectional view showing a method of manufacturing a display device and the structure of a region taken along line A-A' of Figure 4F thereof.

[0022] Throughout the drawings and the detailed description, unless otherwise specified, the same reference numerals should be understood to represent the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes of these elements may be exaggerated and the description thereof. Detailed Embodiments

[0023] Now, embodiments of the present disclosure will be described in detail, examples of which can be shown in the drawings. In the following description, when a detailed description of a well-known function or configuration related to this document unnecessarily obscures the gist of the inventive concept, its detailed description will be omitted. The progress of the described processing steps and / or operations is only an example; however, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as known in the art, except for steps and / or operations that must occur in a specific order. The names of the respective elements used in the following description may only be selected for ease of writing the specification and may therefore be different from the names used in actual products.

[0024] Advantages and features of the present disclosure and methods of achieving these advantages and features will become apparent by referring to the exemplary embodiments described in detail below in conjunction with the drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure content of the present disclosure and the scope of the present disclosure.

[0025] The shapes (e.g., size, length, width, height, thickness, position, radius, diameter, and area), ratios, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having", "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may also include the plural unless otherwise expressly stated.

[0026] The term "exemplary" is used to denote an example or illustration. Aspects are exemplary aspects. Terms such as "embodiment", "example", "aspect", etc. should not be construed as being preferred or advantageous as compared to other implementations. Unless otherwise specified, an embodiment, an example, an exemplary embodiment, an aspect, etc. may refer to one or more embodiments, one or more examples, one or more exemplary embodiments, one or more aspects, etc. In addition, the term "may" encompasses all meanings of the term "can".

[0027] Components are interpreted to include a normal margin of error even if not explicitly stated.

[0028] When terms such as "above", "over", "below", "beside" are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used together with the terms "immediately" or "directly".

[0029] Terms such as "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between elements as shown in the drawings. It should be understood that these terms are spatially relative and based on the orientation depicted in the drawings.

[0030] When an element or layer is disposed "above" another element or layer, the one element or layer may be disposed directly above the other element or layer, or another element or layer may be interposed therebetween.

[0031] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first element, the second element, and the third element" encompasses the combination of all three listed elements, any combination of two of the three elements, and each individual element (i.e., the first element, the second element, or the third element).

[0032] Although terms such as "first", "second", "A", "B", "(a)", and "(b)" are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Thus, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0033] Throughout the specification, the same reference numerals generally denote the same elements.

[0034] For ease of description, the size and thickness of each component shown in the drawings are shown, and the present disclosure is not limited to the size and thickness of the components shown.

[0035] The features of the various embodiments of the present disclosure can be partially or fully combined or combined with each other, and can be interlocked and operated in various ways technically, and these embodiments can be implemented independently or in association with each other.

[0036] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] The exemplary embodiments of the present disclosure can be implemented independently of each other or in association with each other.

[0038] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure. In Figure 1 For ease of description, among the various components of the display device, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are schematically shown.

[0039] Referring to Figure 1 , the display device includes: a display panel PN including a plurality of sub-pixels SP; a gate driver GD and a data driver DD that provide various signals to the display panel PN; and a timing controller TC that controls the gate driver GD and the data driver DD.

[0040] The gate driver GD provides a plurality of scan signals to a plurality of scan lines SL according to a plurality of gate control signals provided from the timing controller TC. Although in Figure 1 one gate driver GD is shown as being spaced apart from one side of the display panel PN, the number and arrangement of the gate drivers GD are not limited thereto. As an example, two gate drivers GD may be provided on opposite sides of the display panel PN, but not limited thereto. As an example, two or more gate drivers GD may be provided on one side or more sides of the display panel PN, but not limited thereto.

[0041] The data driver DD converts the image data input from the timing controller TC into a data voltage using a reference gamma voltage according to a plurality of data control signals provided from the timing controller TC. The data driver DD may provide the converted data voltage to a plurality of data lines DL.

[0042] The timing controller TC arranges the image data input from the outside to provide the image data to the data driver DD. The timing controller TC can use the synchronization signals input from the outside (such as the dot clock signal, data enable signal, and horizontal / vertical synchronization signal) to generate a gate control signal and a data control signal. The timing controller TC provides the generated gate control signal and data control signal to the gate driver GD and the data driver DD respectively to control the gate driver GD and the data driver DD. Although the timing controller TC, the gate driver GD, and the data driver DD are shown as separate components, the implementation is not limited thereto. As an example, at least two of the timing controller TC, the gate driver GD, and the data driver DD can be integrated into one component. As an example, one or more additional components can also be included.

[0043] The display panel PN is a structure that displays an image to the user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL cross each other, and the plurality of sub-pixels SP are respectively connected to the scan lines SL and the data lines DL. In addition, although not shown in the figure, each of the plurality of sub-pixels SP can be connected to a high-potential power supply line, a low-potential power supply line, a reference line, etc.

[0044] In the display panel PN, a display area AA and a non-display area NA extending from the display area AA can be defined. As an example, the non-display area NA can partially or completely surround the display area AA.

[0045] The display area AA is an area for displaying an image in the display device. In the display area AA, a plurality of sub-pixels SP that make up a plurality of pixels PX and a circuit unit for driving the plurality of sub-pixels SP can be provided. The sub-pixel SP is the smallest unit that makes up the display area AA, and n sub-pixels SP can form one pixel PX. In each of the plurality of sub-pixels SP, a light-emitting diode, a circuit unit for driving the light-emitting diode, etc. can be provided. Depending on the type of the display panel PN, the plurality of light-emitting diodes can be defined in different ways. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting diode can be a light-emitting diode (LED) or a micro light-emitting diode (micro LED), but is not limited thereto.

[0046] In the display area AA, a plurality of wirings for transmitting various signals to a plurality of sub-pixels SP are provided. For example, the plurality of wirings may include a plurality of data lines DL for supplying a data voltage to each of the plurality of sub-pixels SP and a plurality of scan lines SL for supplying a scan signal to each of the plurality of sub-pixels SP. The plurality of scan lines SL extend in one direction in the display area AA to connect to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the display area AA to connect to the plurality of sub-pixels SP. In addition, in the display area AA, a low-potential power supply line, a high-potential power supply line, etc. may also be provided, but are not limited thereto.

[0047] The non-display area NA is an area where an image is not displayed, and thus the non-display area NA can be defined as an area extending from the display area AA. In the non-display area NA, link lines, pad electrodes, or driving ICs such as a gate driver IC or a data driver IC for transmitting signals to the sub-pixels SP in the display area AA can be provided.

[0048] However, the non-display area NA may be located on the rear surface of the display panel PN (i.e., the surface on which the sub-pixels SP are not provided) or may be omitted, and is not limited to that shown in the figure. As an example, the non-display area NA may be partially or completely bent toward the rear side of the display panel PN so as to be partially or completely invisible from the front side of the display panel, but is not limited thereto.

[0049] Meanwhile, drivers such as a gate driver GD, a data driver DD, and a timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be mounted in the non-display area NA in a gate-in-panel (GIP) manner or between a plurality of sub-pixels SP in the display area AA in a gate-in-array (GIA) manner. For example, the data driver DD and the timing controller TC are formed in a separate flexible film and printed circuit board. By bonding the flexible film and the printed circuit board to the pad electrodes formed in the non-display area NA of the display panel PN, the data driver DD and the timing controller TC can be electrically connected to the display panel PN. The embodiments are not limited thereto. As an example, the gate driver GD can be separately provided (for example, provided on a separate flexible film or printed circuit board) and then connected to the display panel PN by a tape automated bonding (TAB) method, a chip-on-glass (COG) method, a chip-on-panel (COP) method, or a chip-on-film (COF) method, but is not limited thereto.

[0050] If the gate driver GD is mounted in a gate-in-panel (GIP) manner and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrodes in the non-display area NA, the area of the non-display area NA for setting the gate driver GD and the pad electrodes must be greater than a predetermined level. Therefore, the bezel may increase.

[0051] In contrast, when the gate driver GD is installed in the display area AA in a gate-in-area (GIA) manner and the side line SRL that connects the signal lines (or pad electrodes) on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN is formed to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-display area NA can be reduced or minimized on the front surface of the display panel PN. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a substantially borderless zero bezel can be achieved.

[0052] Specifically, referring to Figure 2A and Figure 2B , in the non-display area NA of the display panel PN, a plurality of pad electrodes for transmitting various signals to the plurality of sub-pixels SP are provided. For example, in the non-display area NA on the front surface of the display panel PN, a plurality of first pad electrodes PAD1 for transmitting signals to the plurality of sub-pixels SP are provided. In the non-display area NA on the rear surface of the display panel PN, a plurality of second pad electrodes PAD2 electrically connected to driving components such as a flexible film and a printed circuit board are provided. That is, on the front surface of the display panel PN on which an image is displayed, only the pad area of the non-display area NA provided with the first pad electrodes PAD1 can be minimized.

[0053] In this case, although not shown in the figure, various signal lines (e.g., scan lines SL or data lines DL) connected to the plurality of sub-pixels SP extend from the display area AA to the non-display area NA to be electrically connected to the first pad electrodes PAD1.

[0054] The side line SRL is provided along the side surface of the display panel PN. The side line SRL can electrically connect the first pad electrodes PAD1 on the front surface of the display panel PN and the second pad electrodes PAD2 on the rear surface of the display panel PN. Therefore, signals from the driving components on the rear surface of the display panel PN can be transmitted to the plurality of sub-pixels SP through the second pad electrodes PAD2, the side line SRL, and the first pad electrodes PAD1. Thus, a signal transmission path from the front surface to the side surface and the rear surface of the display panel PN is formed to reduce or minimize the area of the non-display area NA on the front surface of the display panel PN.

[0055] Referring to Figure 2B , a tiled display device TD with a large screen size can be achieved by connecting a plurality of display devices 100. At this time, as Figure 2AAs shown, when a display device 100 with a reduced or minimized bezel is used to implement a tiled display device TD, the seam area between the display devices 100 where no image is displayed is reduced or minimized, thereby improving the display quality.

[0056] For example, a plurality of sub-pixels SP may form one pixel PX, and a first distance D1 between the outermost pixel PX of one display device 100 and the outermost pixel PX of another display device 100 adjacent to the one display device may be configured to be equal to a second distance D2 between the pixels PX in the one display device 100. Accordingly, the distances D1 and D2 between the pixels PX between the display devices 100 are constantly configured to reduce or minimize the seam area.

[0057] However, Figure 2A and Figure 2B For illustrative purposes, the display device 100 according to an exemplary embodiment of the present disclosure may be a general display device with a bezel, but is not limited thereto.

[0058] Figure 3 is a plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure.

[0059] Referring to Figure 3 , in the display panel PN, a plurality of pixels PX are formed on a substrate (e.g., an insulating substrate) to display an image. For example, the insulating substrate may be formed of glass or resin and may include a polymer or plastic, but is not limited thereto. In addition, the insulating substrate may be formed of a flexible plastic material. The embodiment is not limited thereto. As an example, the substrate may be a rigid substrate or a flexible substrate. As an example, the insulating substrate may be formed of polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polyimide (PI) film, etc., but is not limited thereto.

[0060] In the insulating substrate, a plurality of pixel regions UPA, a plurality of gate driving regions GA, and a plurality of pad regions PA1 and PA2 are provided. Among them, the plurality of pixel regions UPA and the plurality of gate driving regions GA may be included in the display area AA of the display panel PN.

[0061] First, the plurality of pixel regions UPA are regions where a plurality of pixels PX are provided. The plurality of pixel regions UPA may be provided while forming a plurality of rows and a plurality of columns. Each of the plurality of pixels PX provided in the plurality of pixel regions UPA includes a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a light-emitting diode and a pixel circuit to emit light (e.g., independently).

[0062] A plurality of gate driving regions GA are regions where gate drivers GD are provided. The gate driver GD can be installed in the display area AA in a manner of gate driving within the display area (GIA). For example, the gate driving regions GA can be formed between a plurality of pixel regions UPA along the row direction and / or the column direction. The gate driver GD formed in the gate driving region GA can supply scan signals to a plurality of scan lines SL.

[0063] The gate driver GD provided in the gate driving region GA can include a circuit for outputting scan signals. At this time, the gate driver GD can include, for example, a plurality of transistors and / or capacitors. Here, the active layers of the plurality of transistors can be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, polycrystalline silicon, compound semiconductor, organic semiconductor, etc., but are not limited thereto. The active layers of the plurality of transistors can be formed of the same material or different materials from each other. In addition, the active layers of the transistors of the gate driver can be formed of the same material as the active layers of various transistors of the pixel circuit, or of different materials from each other.

[0064] A plurality of pad regions are regions where a plurality of first pad electrodes PAD1 are provided. The plurality of first pad electrodes PAD1 can transmit various signals to various wirings extending in the column direction in the display area AA. For example, the plurality of first pad electrodes PAD1 include data pads DP, gate pads GP, high-potential power pads VP1, and / or low-potential power pads VP2, but are not limited thereto. The data pad DP transmits a data voltage to the data line DL, and the gate pad GP transmits a clock signal, a start signal, a gate low voltage, and a gate high voltage for driving the gate driver GD to the gate driver GD. The high-potential power pad VP1 transmits a high-potential power voltage to the high-potential power line VL1, and the low-potential power pad VP2 transmits a low-potential power voltage to the low-potential power line VL2.

[0065] The plurality of pad regions may include a first pad region PA1 and a second pad region PA2, or may include only one pad region or more than two pad regions. As an example, the plurality of pad regions may include a first pad region PA1 located at the upper edge of the display panel PN and a second pad region PA2 located at the lower edge of the display panel PN, but is not limited thereto. At this time, as an example, different types of first pad electrodes PAD1 may be provided in the first pad region PA1 and the second pad region PA2. For example, in the first pad region PA1, a data pad DP, a gate pad GP, and a high-potential power supply pad VP1 among the plurality of first pad electrodes PAD1 may be provided, and a low-potential power supply pad VP2 may be provided in the second pad region PA2. The embodiments are not limited thereto. As an example, the same type of first pad electrode PAD1 may be provided in the first pad region PA1 and the second pad region PA2. As an example, each of the data pad DP, the gate pad GP, the high-potential power supply pad VP1, and the low-potential power supply pad VP2 may be provided in one or both of the first pad region PA1 and the second pad region PA2, but is not limited thereto.

[0066] At this time, as an example, the plurality of first pad electrodes PAD1 may be formed to have different sizes respectively, but is not limited thereto. For example, the plurality of data pads DP (for example, one-to-one) connected to the plurality of data lines DL may have a smaller width, while the high-potential power supply pad VP1, the low-potential power supply pad VP2, and the gate pad GP may have a larger width. However, Figure 3 the widths of the data pad DP, the gate pad GP, the high-potential power supply pad VP1, and the low-potential power supply pad VP2 shown in are exemplary, and thus the first pad electrode PAD1 may be configured in various sizes, and is not limited thereto. As an example, at least some or all of the data pad DP, the gate pad GP, the high-potential power supply pad VP1, and the low-potential power supply pad VP2 may have the same size.

[0067] Meanwhile, in order to reduce the bezel of the display panel PN, as an example, the edge of the display panel PN may be cut to be removed, but is not limited thereto. The plurality of pixels PX, the plurality of wirings, and the plurality of first pad electrodes PAD1 are formed on an initial first substrate 110i which is an insulating substrate, and the edge portion of the initial first substrate 110i is polished to reduce the bezel area. During the polishing process, a part of the initial first substrate 110i is removed to form a first substrate 110 having a smaller size. At this time, a part of the plurality of first pad electrodes PAD1 and the wirings provided at the edge of the first substrate 110 may be removed. Therefore, only a part of the plurality of first pad electrodes PAD1 may remain on the first substrate 110.

[0068] Next, a plurality of data lines DL extending in the column direction are provided on the first substrate 110 of the display panel PN. The plurality of data lines DL can extend from a plurality of first pad electrodes PAD1 in the first pad region PA1 toward a plurality of pixel regions UPA. The plurality of data lines DL extend in the column direction and overlap with the plurality of pixel regions UPA. Accordingly, the plurality of data lines DL can transmit data voltages to the pixel circuits of each of the plurality of sub-pixels SP.

[0069] A plurality of high potential power supply lines VL1 extending in the column direction are provided on the first substrate 110 of the display panel PN. Some of the plurality of high potential power supply lines VL1 extend from the high potential power supply pad VP1 in the first pad region PA1 to the plurality of pixel regions UPA to transmit a high potential power supply voltage to the light emitting diodes of each of the plurality of sub-pixels SP. Other high potential power supply lines VL1 among the plurality of high potential power supply lines VL1 can be electrically connected to another high potential power supply line VL1 by an auxiliary high potential power supply line AVL1 described below. In Figure 3 order to facilitate description, although one high potential power supply line VL1 and one high potential power supply pad VP1 are shown provided, a plurality of high potential power supply lines VL1 and a plurality of high potential power supply pads VP1 can be provided.

[0070] A plurality of low potential power supply lines VL2 extending in the column direction are provided on the first substrate 110 of the display panel PN. At least some of the plurality of low potential power supply lines VL2 extend from the low potential power supply pad VP2 in the second pad region PA2 to the plurality of pixel regions UPA to transmit a low potential power supply voltage to the pixel circuits of each of the plurality of sub-pixels SP. Other low potential power supply lines among the plurality of low potential power supply lines VL2 can be electrically connected to another low potential power supply line VL2 by an auxiliary low potential power supply line AVL2 described below.

[0071] A plurality of scan lines SL extending in the row direction are provided on the first substrate 110 of the display panel PN. The plurality of scan lines SL extend in the row direction and can be provided across the plurality of pixel regions UPA and the plurality of gate driving regions GA. The plurality of scan lines SL can transmit scan signals from the gate driver GD to the pixel circuits of the plurality of sub-pixels SP.

[0072] A plurality of auxiliary high potential power supply lines AVL1 extending in the row direction are provided on the first substrate 110 of the display panel PN. The plurality of auxiliary high potential power supply lines AVL1 may be provided in a region between a plurality of pixel regions UPA. The plurality of auxiliary high potential power supply lines AVL1 extending in the row direction are electrically connected to a plurality of high potential power supply lines VL1 extending in the column direction through contact holes, and may form a mesh structure. Accordingly, the plurality of auxiliary high potential power supply lines AVL1 and the plurality of high potential power supply lines VL1 are configured to form a mesh structure to reduce or minimize voltage drop and voltage deviation.

[0073] A plurality of auxiliary low potential power supply lines AVL2 extending in the row direction are provided on the first substrate 110 of the display panel PN. The plurality of auxiliary low potential power supply lines AVL2 may be provided in a region between a plurality of pixel regions UPA. The plurality of auxiliary low potential power supply lines AVL2 extending in the row direction are electrically connected to a plurality of low potential power supply lines VL2 extending in the column direction through contact holes to form a mesh structure. Accordingly, the plurality of auxiliary low potential power supply lines AVL2 and the plurality of low potential power supply lines VL2 are configured to form a mesh structure to reduce the resistance of the wiring and reduce or minimize voltage deviation.

[0074] The plurality of auxiliary high potential power supply lines AVL1 and the plurality of auxiliary low potential power supply lines AVL2 may additionally be provided between a plurality of data lines DL extending in the column direction of the display panel PN.

[0075] A plurality of gate driving lines GVL extending in the row direction and the column direction are provided on the first substrate 110 of the display panel PN. Some of the plurality of gate driving lines GVL extend from a gate pad GP of the first pad region PA1 to a gate driving region GA to transmit signals to the gate driver GD. Other gate driving lines GVL among the plurality of gate driving lines GVL extend in the row direction and transmit signals to the gate drivers GD of a plurality of gate driving regions GA. Accordingly, various signals may be transmitted from the gate driving lines GVL to the gate driver GD to drive the gate driver GD.

[0076] The plurality of gate driving lines GVL may include wirings for transmitting a clock signal, a start signal, a gate high voltage, and a gate low voltage to the gate driver GD. Accordingly, various signals are transmitted from the gate driving lines GVL to the gate driver GD to drive the gate driver GD.

[0077] A plurality of alignment keys AK1 and AK2 are provided in a region between a plurality of pixel regions UPA in the display panel PN. The plurality of alignment keys AK1 and AK2 are used for alignment during the manufacturing process of the display panel PN. The plurality of alignment keys AK1 and AK2 include a first alignment key AK1 and a second alignment key AK2.

[0078] The first alignment key AK1 can be disposed in the gate driving region GA between a plurality of pixel regions UPA. The first alignment key AK1 can be used to check the alignment positions of a plurality of light emitting diodes EM. For example, the first alignment key AK1 can have a cross shape, but is not limited thereto.

[0079] The second alignment key AK2 can be disposed to overlap with the high potential power supply line VL1 between a plurality of pixel regions UPA. In the high potential power supply line VL1, as an example, a hole overlapping with the second alignment key AK2 is formed to divide the second alignment key AK2 and the high potential power supply line VL1, but is not limited thereto. The second alignment key AK2 can be used to align the display panel PN and the donor. Using the second alignment key AK2 to align the display panel PN and the donor, and a plurality of light emitting diodes EM of the donor can be transferred onto the display panel PN. For example, the second alignment key AK2 can have a circular ring shape, but is not limited thereto. The embodiments are not limited thereto. As an example, the display panel PN can include only one of the first alignment key AK1 and the second alignment key AK2, or can include one or more additional alignment keys in addition to the first alignment key AK1 and the second alignment key AK2. As an example, the first alignment key AK1 and the second alignment key AK2 can be disposed at various positions, and are not limited to Figure 3 the positions shown.

[0080] will be described with reference to Figures 4A to 4D and Figures 5A to 5E the pixel PX and the sub-pixel SP of the pixel region UPA in more detail.

[0081] The display area AA on the first substrate 110 can include a light emitting area and a non-light emitting area. The light emitting area is an area where light emitting diodes are disposed to emit light, and the non-light emitting area is an area where no light emitting diodes are disposed.

[0082] A plurality of sub-pixels SP forming one pixel PX are disposed in one pixel region UPA. For example, the plurality of sub-pixels SP can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 that emit different color lights. The embodiments are not limited thereto. As an example, the plurality of sub-pixels SP forming one pixel PX can include more than three sub-pixels. As an example, the more than three sub-pixels can emit different color lights, or at least some of the more than three sub-pixels can emit the same color light. As an example, one or more pixels PX can be disposed in one pixel region UPA.

[0083] As an example, a red light-emitting diode may be disposed in the first sub-pixel SP1, a green light-emitting diode may be disposed in the second sub-pixel SP2, and a blue light-emitting diode may be disposed in the third sub-pixel SP3, but is not limited thereto. Sub-pixels of colors other than red, green, and blue (e.g., cyan, magenta, yellow, etc.) may be alternatively or additionally included.

[0084] Referring to Figure 4A , as described above, wirings for supplying various signals to the plurality of sub-pixels SP1, SP2, and SP3 are provided in the plurality of pixels PX of the first substrate 110. For example, a plurality of data lines RDL, R’DL, GDL, and BDL extending in the column direction and a power line 121 for transmitting a signal of a low-potential power supply pad VP2 ( Figure 3 ) or a high-potential power supply pad VP1 ( Figure 3 ) may be provided on the first substrate 110.

[0085] The power line 121 transmits low-potential or high-potential power to each sub-pixel SP and transmits high-potential or low-potential power to the drive circuit unit to drive the light-emitting diode.

[0086] The power line 121 may be provided between the respective sub-pixels SP and may be formed wider than the plurality of data lines RDL, R’DL, GDL, and BDL, but is not limited thereto. As an example, the power line 121 may be formed as wide as possible to reduce or minimize the voltage drop and voltage deviation of the power supply voltage, but is not limited thereto.

[0087] Each of the sub-pixels SP1, SP2, or SP3 may include a drive circuit unit and include at least two light-emitting diodes, but is not limited thereto.

[0088] To drive at least two light-emitting diodes, the drive circuit unit of each of the sub-pixels SP1, SP2, or SP3 may include main light-emitting circuit units RDT, GDT, and BDT and auxiliary light-emitting circuit units R’DT, G’DT, and B’DT.

[0089] In the red sub-pixel SP1, the red main light-emitting circuit unit RDT and the red auxiliary light-emitting circuit unit R’DT respectively include a first red data line RDL and a second red data line R’DL. For the green sub-pixel SP2 and the blue sub-pixel SP3, signals are applied to the green main light-emitting circuit unit GDT and the green auxiliary light-emitting circuit unit G’DT, as well as the blue main light-emitting circuit unit BDT and the blue auxiliary light-emitting circuit unit B’DT through a green data line GDL and a blue data line BDL. The implementation is not limited to this. As an example, the red main light-emitting circuit unit RDT and the red auxiliary light-emitting circuit unit R’DT may include a single red data line RDL, while the green main light-emitting circuit unit GDT and the green auxiliary light-emitting circuit unit G’DT or the blue main light-emitting circuit unit BDT and the blue auxiliary light-emitting circuit unit B’DT may include a single data line, but this is not limited.

[0090] The driving circuit unit may include a first contact hole CH1 (or one or more contact holes) for electrically connecting the transistors and light-emitting diodes of the driving circuit unit.

[0091] As an example, the power line 121 has a width that varies for each region, and is set as wide as possible in regions other than the region where the driving circuit unit is provided and the contact regions to which the driving circuit unit and the lower wiring are connected.

[0092] The power line 121 includes a first region and a second region, and the width L1 of the first region and the width L2 of the second region are different. As an example, the width L1 of the first region is greater than the width L2 of the second region.

[0093] In addition, the power line 121 further includes a third region, and the width L3 of the third region may be greater than the width L2 of the second region and may be less than the width L1 of the first region.

[0094] As an example, the power line 121 (e.g., the low-potential power line) may be formed by the same process as the plurality of data lines RDL, R’DL, GDL, and BDL, or may be formed by a different process from the plurality of data lines RDL, R’DL, GDL, and BDL.

[0095] The power line 121 and the plurality of data lines RDL, R’DL, GDL, and BDL may be formed of the same or different conductive materials. As an example, the power line 121 and the plurality of data lines RDL, R’DL, GDL, and BDL may be formed of one or more of opaque metal materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), and chromium (Cr) or their alloys, but this is not limited.

[0096] In addition, a light-shielding layer BSM, a semiconductor layer ACT, and / or an insulating layer may be disposed under the power supply line 121 and the plurality of data lines RDL, R’DL, GDL, and BDL.

[0097] Referring to Figure 4B , a metal layer 122 may be disposed on the driving circuit unit and the power supply line 121. At this time, as an example, the metal layer 122 may be electrically connected to the driving circuit unit through a first contact hole CH1. A first connection electrode 121a is disposed on the power supply line 121 to transmit the signal of the power supply line 121 to the light-emitting diode through a third contact hole CH3.

[0098] The metal layer 122 overlaps with the electrode of the driving circuit unit to form a capacitor. The metal layer 122 may have a width that overlaps with the entire driving circuit unit to ensure sufficient capacitance.

[0099] The metal layer 122 may include a reflective material to reflect the light of the light-emitting diode upward. As an example, the metal layer 122 and the first connection electrode 121a may include one or more of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), and indium tin oxide (ITO) or an alloy thereof, but is not limited thereto. As an example, the metal layer 122 and the first connection electrode 121a may include the same material or different materials.

[0100] An alignment key may be formed by etching a part of the metal layer 122. The alignment key AK may be disposed in the region where the power supply line 121 overlaps with the metal layer 122, but is not limited thereto.

[0101] Referring to Figure 4C , an adhesive layer AD may be disposed on the metal layer 122, the first connection electrode 121a, and the substrate 110. The adhesive layer AD may include a second contact hole CH2 that exposes a part of the metal layer 122 to electrically connect the light-emitting diode and the metal layer 122, and a third contact hole CH3 that exposes a part of the first connection electrode 121a to electrically connect the light-emitting diode and the power supply line 121.

[0102] Light-emitting diodes REM, R’EM, GEM, G’EM, BEM, and B’EM may be disposed on the adhesive layer AD of each sub-pixel.

[0103] Referring to Figure 4D and Figure 4E , a third planarization layer 119 is provided to cover the top surface and the side surfaces of the light-emitting diodes REM, R’EM, GEM, G’EM, BEM, and B’EM.

[0104] The third planarization layer 119 is disposed on the top and side surfaces of the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM, and has a size larger than that of the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM. The fourth contact hole CH4 and the fifth contact hole CH5 are formed above the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM to expose a part of the first electrode layer 134 and the second electrode layer 135 of the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM.

[0105] The third planarization layer 119 is spaced apart from the second contact hole CH2 and the third contact hole CH3 disposed around it to prevent the depths of the second contact hole CH2 and the third contact hole CH3 from becoming deeper as much as the height of the third planarization layer 119.

[0106] In Figure 4E the third planarization layer 119 according to another exemplary embodiment of the present disclosure is provided. The third planarization layer 119 may be provided to surround the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM to fix each of the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM to the substrate 110. At this time, the third planarization layer is not separately provided to surround each of the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM, but may be provided to surround two or more of the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM, for example, the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM in the row direction or the column direction in the pixel PX. In this case, the third planarization layer may be provided between two or more light-emitting diodes, thereby improving the fixing strength of fixing the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM to the substrate.

[0107] Referring to Figure 4F , the first electrode 123 and the second electrode 124 may be provided on the substrate 110. The first electrode 123 may electrically connect the driving circuit units RDT, GDT, BDT, R'DT, G'DT, and B'DT of each of the sub-pixels SP1, SP2, and SP3 to the second electrode layer 135 of the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM.

[0108] The second electrode 124 may be provided on the entire substrate 110 except for the region where the first electrode 123 is provided, and may electrically connect the power supply line 121 and the light-emitting diodes REM, R'EM, GEM, G'EM, BEM, and B'EM, but is not limited thereto.

[0109] As an example, the first electrode 123 and the second electrode 124 may be formed on the same layer by the same process and spaced apart from each other at a predetermined interval. The embodiments are not limited thereto. As an example, the first electrode 123 and the second electrode 124 may be formed on different layers and / or by different processes. As an example, the first electrode 123 even overlaps a part of the second electrode 124.

[0110] Figures 5A to 5E is a cross-sectional view showing a method of manufacturing a display device and the structure of a region taken along line A-A’ Figure 4F thereof.

[0111] The display panel PN includes a first substrate 110. The first substrate 110 is a substrate that supports components disposed above the display panel PN, and may be, for example, an insulating substrate, but is not limited thereto. A plurality of pixels PX are formed on the first substrate 110 to display an image. For example, the first substrate 110 may be formed of glass or resin. In addition, the first substrate 110 may include a polymer or plastic. In some exemplary embodiments, the first substrate 110 may be formed of a flexible plastic material, but is not limited thereto.

[0112] The light-shielding layer BSM may be disposed on the first substrate 110. The light-shielding layer BSM blocks light incident on the active layer ACT of the plurality of transistors to reduce or minimize leakage current. For example, the light-shielding layer BSM is disposed below the active layer ACT of the driving transistor DT to block light incident on the active layer ACT.

[0113] If light irradiates the active layer ACT, leakage current is generated, which reduces the reliability of the transistor. Therefore, the light-shielding layer BSM that blocks light is disposed on the first substrate 110 to improve the reliability of the driving transistor DT. The light-shielding layer BSM may be made of an opaque material (e.g., an opaque conductive material) such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto. As an example, the light-shielding layer BSM may be made of an opaque insulating material, but is not limited thereto. As an example, the light-shielding layer BSM may be omitted according to the design.

[0114] The buffer layer 111 is disposed on the light-shielding layer BSM. The buffer layer 111 may reduce the penetration of moisture or impurities through the first substrate 110. For example, the buffer layer 111 may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of the first substrate 110 or the type of the thin film transistor, but is not limited thereto.

[0115] Although not shown, an additional buffer layer may be provided between the first substrate 110 and the light-shielding layer BSM. Similar to the buffer layer 111, the additional buffer layer may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx) to reduce the penetration of moisture or impurities through the first substrate 110.

[0116] A driving transistor DT including an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE is disposed on the buffer layer 111.

[0117] First, the active layer ACT of the driving transistor DT is disposed on the buffer layer 111. The active layer ACT may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, polycrystalline silicon, compound semiconductor, or organic semiconductor, but is not limited thereto. In addition, although not shown in the figure, other transistors such as a switching transistor, a sensing transistor, and a light-emitting control transistor may also be provided in addition to the driving transistor DT. The active layer of the transistor may also be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, polycrystalline silicon, compound semiconductor, or organic semiconductor, but is not limited thereto. The active layers of the transistors included in the pixel circuit (e.g., the driving transistor DT, the switching transistor, the sensing transistor, and the light-emitting control transistor) may be formed of the same material or different materials.

[0118] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer that electrically insulates the active layer ACT from the gate electrode GE, and may be composed of a single layer, a double layer, or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0119] The gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be composed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0120] A first interlayer insulating layer 113 and a second interlayer insulating layer 114 are disposed on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114, and the source electrode SE and the drain electrode DE are respectively connected to the active layer ACT through the contact holes. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers that protect the components therebelow, and may be composed of a single layer, a double layer, or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0121] The source electrode SE and the drain electrode DE electrically connected to the active layer ACT are disposed on the second interlayer insulating layer 114. The source electrode SE is connected to the second capacitor C2 and the first electrode 123 of the light-emitting diode EM, and the drain electrode DE is connected to another structure of the pixel circuit. The source electrode SE and the drain electrode DE may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0122] The power supply line 121 may be formed on the second interlayer insulating layer 114 using the same material through the same process as the source electrode SE and the drain electrode DE, but is not limited thereto. As an example, the power supply line 121 may be disposed on a layer different from the second interlayer insulating layer 114 (e.g., the buffer layer 111, the gate insulating layer 112, or the first interlayer insulating layer 113, etc.). As an example, the power supply line 121 may be formed of a different material from the source electrode SE and the drain electrode DE, and / or may be formed through a different process from the source electrode SE and the drain electrode DE, but is not limited thereto.

[0123] Next, the first capacitor C1 is disposed on the gate insulating layer 112. The first capacitor C1 includes a first capacitor electrode C1a and a second capacitor electrode C1b.

[0124] First, the first capacitor electrode C1a is disposed on the gate insulating layer 112. The first capacitor electrode C1a may be integrally formed with the gate electrode GE of the driving transistor DT, or may be separately formed from the gate electrode GE of the driving transistor DT.

[0125] The second capacitor electrode C1b is disposed on the first interlayer insulating layer 113. The second capacitor electrode C1b is disposed to overlap the first capacitor electrode C1a, and the first interlayer insulating layer 113 is located therebetween. The embodiment is not limited thereto. As an example, the second capacitor electrode C1b may be disposed on the second interlayer insulating layer 114, but is not limited thereto. As an example, the first capacitor C1 may be disposed on the first interlayer insulating layer 113 and may be connected to the gate electrode GE of the driving transistor DT, but is not limited thereto.

[0126] Therefore, the first capacitor C1 is connected to the gate electrode GE of the driving transistor DT to maintain the voltage of the gate electrode GE of the driving transistor DT for a predetermined period.

[0127] Next, a second capacitor C2 is disposed on the first substrate 110. As an example, the second capacitor C2 includes a 2-1 capacitor electrode C2a as a lower capacitor electrode, a 2-2 capacitor electrode C2b as an intermediate capacitor electrode, and a 2-3 capacitor electrode C2c as an upper capacitor electrode. The embodiment is not limited thereto. As an example, the second capacitor C2 may include only two capacitor electrodes. As an example, the second capacitor C2 may include two of the 2-1 capacitor electrode C2a, the 2-2 capacitor electrode C2b, and the 2-3 capacitor electrode C2c, but is not limited thereto.

[0128] As an example, the 2-1 capacitor electrode C2a may be disposed on the first substrate 110. As an example, the 2-1 capacitor electrode C2a may be disposed on the same layer as the light-shielding layer BSM and may be formed of the same material as the light-shielding layer BSM, but is not limited thereto.

[0129] As an example, the 2-2 capacitor electrode C2b may be disposed on the buffer layer 111 and the gate insulating layer 112. As an example, the 2-2 capacitor electrode C2b may be disposed on the same layer as the gate electrode GE and may be formed of the same material as the gate electrode GE, but is not limited thereto.

[0130] As an example, the 2-3 capacitor electrode C2c may be disposed on the first interlayer insulating layer 113. As an example, the 2-3 capacitor electrode C2c may be composed of a first layer C2c1 and a second layer C2c2, but is not limited thereto. As an example, the first layer C2c1 of the 2-3 capacitor electrode C2c may be formed of the same material as the 1-2 capacitor electrode C1b on the same layer, but is not limited thereto. The first layer C2c1 may be disposed to overlap the 2-1 capacitor electrode C2a and the 2-2 capacitor electrode C2b, and the first interlayer insulating layer 113 may be located therebetween.

[0131] The second layer C2c2 of the 2-3 capacitor electrode C2c may be disposed on the second interlayer insulating layer 114. The second layer C2c2 may be a portion extending from the source electrode SE of the driving transistor DT and may be connected to the first layer C2c1 through a contact hole in the second interlayer insulating layer 114, but is not limited thereto.

[0132] Therefore, the second capacitor C2 is electrically connected to the source electrode SE of the driving transistor DT and the light-emitting diode EM to increase the inherent capacitance of the light-emitting diode EM and allow the light-emitting diode EM to emit light with higher brightness.

[0133] The first passivation layer 115a is disposed on the driving transistor DT, the first capacitor C1, the second capacitor C2, and the power line 121. The first passivation layer 115a is an insulating layer that protects the components under the first passivation layer 115a, and may be formed of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0134] The first planarization layer 116a is disposed on the first passivation layer 115a. The first planarization layer 116a can planarize the upper portion of the pixel circuit including the driving transistor DT. The first planarization layer 116a may be composed of a single layer, a double layer, or multiple layers, and is formed of, for example, benzocyclobutene or acrylic organic material, but is not limited thereto.

[0135] The first contact hole CH1 and the third contact hole CH3 may be formed in the first passivation layer 115a and the first planarization layer 116a.

[0136] The first contact hole CH1 may expose a part of the electrode SE of the driving transistor DT or a part of the 2-3 capacitor electrode C2c of the second capacitor C2.

[0137] The third contact hole CH3 may expose a part of the power line 121.

[0138] As an example, the metal layer 122 and the first connection electrode 121a may be disposed on the first planarization layer 116a.

[0139] The plurality of metal layers 122 may be disposed to be spaced apart from each other in a predetermined region.

[0140] The metal layer 122 may electrically connect the light emitting diode LED to the power line VDD and the driving transistor DT. As an example, the metal layer 122 may be used as a reflector that reflects the light emitted from the light emitting diode to the top of the light emitting diode, but is not limited thereto. As an example, the plurality of metal layers 122 may be formed of a conductive material having excellent reflection characteristics to reflect the light emitted from the light emitting diode to the top of the light emitting diode, but is not limited thereto. As an example, at least some of the plurality of metal layers 122 may be formed of a conductive material having poor reflection characteristics.

[0141] The metal layer 122 may electrically connect the driving transistor DT and the light emitting diode EM. The metal layer 122 may be connected to the source electrode SE or the drain electrode DE of the driving transistor DT through the first contact hole CH1 formed in the first planarization layer 116a. The metal layer 122 may be electrically connected to the electrode and the semiconductor layer of the light emitting diode through the first electrode 123 to be described below.

[0142] The first connection electrode 121a is partially spaced apart from the metal layer 122 to form in the region of the third contact hole CH3, and the power line 121 and the light-emitting diode EM are electrically connected through the third contact hole CH3. Therefore, the resistance can be reduced in the electrical connection between the power line 121 and the light-emitting diode EM.

[0143] The first connection electrode 121a can electrically connect the power line 121 to the p-type electrode 134 and the p-type semiconductor layer 131 of the light-emitting diode EM through the second electrode 124 to be described below.

[0144] The passivation layer 117 is provided on the metal layer 122 and the first connection electrode 121a. In the passivation layer 117, a second contact hole CH2 for connecting the first electrode 123 to the metal layer 122 and a third contact hole CH3 for connecting the second electrode 124 to the light-emitting diode EM are formed. The passivation layer 117 is an insulating layer that protects the components below the passivation layer 117, and can be composed of a single layer, a double layer, or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0145] The third contact hole CH3 is formed on the passivation layer 117 and the first planarization layer 116a to connect the second electrode 124 and the power line 121. The hole formed in the first planarization layer 116a can be formed to have a smaller width than the hole formed in the passivation layer 117 to form a stepped shape, but is not limited thereto.

[0146] The adhesive layer AD is provided on the passivation layer 117 and the first planarization layer 116a. The adhesive layer AD is coated on the entire substrate 110 to fix the light-emitting diode EM provided thereon. The adhesive layer AD can be selected from any one of adhesive polymers, epoxy resins, UV resins, polyimides, acrylates, polyurethanes, and polydimethylsiloxane (PDMS), but is not limited thereto. The material constituting the above adhesive layer AD is an insulating material, so the adhesive layer can be called an insulating layer.

[0147] A plurality of light-emitting diodes EM are provided in each of the plurality of sub-pixels SP on the adhesive layer AD. The light-emitting diode EM is an element that emits light through current, and the plurality of light-emitting diodes EM can include light-emitting diodes EM that emit red, green, and blue light, and various colors of light including white are achieved through their combination. For example, the plurality of light-emitting diodes EM can be light-emitting diodes (LEDs) or micro-LEDs, but are not limited thereto.

[0148] The light-emitting diode EM includes a first n-type semiconductor layer 133, a first light-emitting layer 132, a first p-type semiconductor layer 131, a first n-type electrode 135, a first p-type electrode 134, and a first encapsulation film 136.

[0149] The first n-type semiconductor layer 133 is disposed on the adhesive layer AD, and the first p-type semiconductor layer 131 is disposed on the first n-type semiconductor layer 133. The first n-type semiconductor layer 133 and the first p-type semiconductor layer 131 can be formed by doping n-type and p-type impurities into a specific material. For example, the first n-type semiconductor layer 133 and the first p-type semiconductor layer 131 can be layers doped with n-type and p-type impurities in a material such as gallium nitride (GaN), aluminum indium phosphide (InAlP), or gallium arsenide (GaAs), but are not limited thereto. The p-type impurity can be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurity can be silicon (Si), germanium, tin (Sn), etc., but are not limited thereto.

[0150] The first light-emitting layer 132 is disposed between the first n-type semiconductor layer 133 and the first p-type semiconductor layer 131. The first light-emitting layer 132 is supplied with holes and electrons from the first n-type semiconductor layer 133 and the first p-type semiconductor layer 131 to emit light. The first light-emitting layer 132 can be formed of a single layer or a multi-quantum well (MQW) structure, and for example, can be formed of indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0151] Refer to Figure 5A , the first light-emitting layer 132 and the first p-type semiconductor layer 131 are disposed spaced apart from the first n-type electrode 135. The first n-type electrode 135 is spaced apart from the first light-emitting layer 132 and the first p-type semiconductor layer 131 to be disposed on one side or both sides of the first light-emitting layer 132 and the first p-type semiconductor layer 131, but is not limited thereto.

[0152] At least one or more first n-type electrodes 135 are disposed on the first n-type semiconductor layer 133. The first n-type electrode 135 is an electrode that electrically connects the driving transistor DT and the first n-type semiconductor layer 133. The first n-type electrode 135 can be disposed on the top surface of the first n-type semiconductor layer 133 that is exposed from the first light-emitting layer 132 and the first p-type semiconductor layer 131. For example, the first n-type electrode 135 can be disposed adjacent to one end or both ends of the top surface of the first n-type semiconductor layer 133 (which has a circular planar shape, for example), but is not limited thereto. The planar shape of the first n-type electrode 135 can be a circular and / or oval shape, or an angular shape, but is not limited thereto. The first n-type electrode 135 can be made of a conductive material (for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof), but is not limited thereto.

[0153] The first p-type electrode 134 is disposed on the first p-type semiconductor layer 131. The first p-type electrode 134 may be disposed on the top surface of the first p-type semiconductor layer 131. The planar shape of the first p-type electrode 134 may be a circular and / or oval shape, or an angular shape, but is not limited thereto. The first p-type electrode 134 is an electrode that electrically connects the power supply line 121 and the first p-type semiconductor layer 131. The first p-type electrode 134 may be formed of a conductive material (for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof), but is not limited thereto.

[0154] Next, a first encapsulation film 136 that surrounds the first n-type semiconductor layer 133, the first light-emitting layer 132, the first p-type semiconductor layer 131, the first n-type electrode 135, and the first p-type electrode 134 is provided. The first encapsulation film 136 is formed of an insulating material to protect the first n-type semiconductor layer 133, the first light-emitting layer 132, and the first p-type semiconductor layer 131. In the first encapsulation film 136, contact holes that expose the first n-type electrode 135 and the first p-type electrode 134 are formed to electrically connect the first electrode 123 and the second electrode 124 to the first n-type electrode 135 and the first p-type electrode 134, respectively.

[0155] Refer to Figure 5B , for example, the adhesive layer AD may be removed from the regions of the second contact hole CH2 and the third contact hole CH3 through an exposure process to form holes.

[0156] As an example, the second contact hole CH2 and the third contact hole CH3 of the adhesive layer AD are formed to be narrower than the second contact hole CH2 and the third contact hole CH3 formed in the passivation layer 117, such that the adhesive layer AD covers the ends of the passivation layer 117.

[0157] When the second contact hole CH2 and the third contact hole CH3 of the adhesive layer AD are formed to be wider than the second contact hole CH2 and the third contact hole CH3 formed in the passivation layer 117, the widths of the second contact hole CH2 and the third contact hole CH3 formed in the second planarization layer 118 formed on the adhesive layer AD, which will be described later, increase. Therefore, the area required for the holes in the display panel PN may increase.

[0158] The adhesive layer AD is coated on the substrate 110 to dispose the light-emitting diode EM, and then a photoresist is coated, and an exposure process is performed using a photographic device. Then, holes may be formed, for example, through a dry etching process, but are not limited thereto.

[0159] When the exposure process is performed, the adhesive layer AD is cured, such that the adhesive strength is reduced, so that the process of forming holes may be performed after the light-emitting diode EM is placed and bonded.

[0160] After dry etching, an ashing process for removing impurities on the photoresist and the adhesive layer AD using oxygen plasma is performed. When the ashing process is performed, the region where the adhesive layer AD is partially etched is exposed, such that the level of the adhesive layer AD in the region that does not overlap with the light-emitting diode EM is lower than the level of the adhesive layer AD in the region that overlaps with the light-emitting diode EM. Accordingly, a protrusion may be included in the region that overlaps with the light-emitting diode EM.

[0161] The adhesive layer AD that overlaps with the light-emitting diode EM may have a first height H1 from the top surface of the substrate 110 to the top surface of the adhesive layer AD. The adhesive layer AD in the region that does not overlap with the light-emitting layer 132 may have a second height H2 from the top surface of the substrate 110 to the top surface of the adhesive layer AD. The first height H1 may be greater than the second height H2.

[0162] The second planarization layer 118 may be disposed on the adhesive layer AD. The second planarization layer 118 may be disposed on the adhesive layer AD while surrounding the side surface of the light-emitting diode EM.

[0163] The adhesive layer AD has been dry-etched, and the end portion may have an inverted conical shape or a right-angled shape. When the first electrode 123 and the second electrode 124, which will be described below, are disposed at the end portion of the adhesive layer AD, the first electrode 123 and the second electrode 124 may be broken due to the shape of the end portion of the adhesive layer AD while the first electrode 123 and the second electrode 124 are being formed.

[0164] To suppress this situation, the second planarization layer 118 covers the end portion of the adhesive layer AD in the regions of the second contact hole CH2 and the third contact hole CH3 to form the second contact hole CH2 and the third contact hole CH3.

[0165] The second contact hole CH2 may be formed by the passivation layer 117, the adhesive layer AD, and the second planarization layer 118, and the third contact hole CH3 may be formed by the first planarization layer 116a, the passivation layer 117, the adhesive layer AD, and the second planarization layer 118.

[0166] The second planarization layer 118 may include a third height H3 and a fourth height H4. The third height H3 is the height from the top surface of the substrate 110 to the top surface of the second planarization layer 118 in the region adjacent to the light-emitting diode EM. The fourth height H4 is the height from the top surface of the substrate 110 to the top surface of the second planarization layer 118 in the region spaced apart from the light-emitting diode EM by a predetermined interval.

[0167] The third height H3 is different from the fourth height H4, and the fourth height H4 is higher than the third height H3, such that the second planarization layer 118 may include recessed cells in the region where the light-emitting diodes EM are disposed.

[0168] The region 118c of the recess of the second planarization layer 118 may overlap with the region of the protrusion of the adhesive layer AD.

[0169] The height of the second planarization layer 118 has a step such that the third planarization layer 119, which will be described later, may be disposed in the region of the third height H3 where the light-emitting diodes EM are disposed.

[0170] The second planarization layer 118 and the third planarization layer 119 may be composed of a single layer or a double layer, and are made of, for example, benzocyclobutene or acrylic organic materials, but are not limited thereto.

[0171] The third planarization layer 119 is disposed to surround the top and side surfaces of the light-emitting diodes EM to fix the light-emitting diodes EM to the substrate 110.

[0172] Refer to Figure 4D 、 Figure 4E and Figure 5C , the third planarization layer 119 only surrounds the light-emitting diodes EM and does not overlap with the second contact hole CH2 and the third contact hole CH3.

[0173] The height of the third planarization layer 119 may be formed to be high enough (for example, about 3 um to 10 um, but not limited thereto) to cover the top surface of the light-emitting diodes EM.

[0174] When the third planarization layer 119 is disposed in the regions of the second contact hole CH2 and the third contact hole CH3, the depths of the second contact hole CH2 and the third contact hole CH3 may increase by the height of the third planarization layer 119.

[0175] The greater the depths of the second contact hole CH2 and the third contact hole CH3, the higher and more tapered the contact holes are due to the adhesive layer AD, the second planarization layer 118, and the third planarization layer 119. Therefore, the connection stability between the first electrode 123 and the second electrode 124 and the underlying metal layer 122 and the power line 121 may be reduced.

[0176] The third planarization layer 119 may be disposed in an island shape surrounding each light-emitting diode EM, or may be disposed to surround one or more light-emitting diodes EM, but is not limited thereto.

[0177] The third planarization layer 119 may include openings that partially expose the first n-type electrode 135 and the first p-type electrode 134 of the light-emitting diode EM, and may be disposed between the first n-type electrode 135 and the first p-type electrode 134 partially above the light-emitting diode EM.

[0178] The first electrode 123 and the second electrode 124 may be disposed on the third planarization layer 119.

[0179] The first electrode 123 connects the first n-type electrode 135 of the light-emitting diode EM and the metal layer 122 to transmit a high-potential power signal from the driving transistor DT to the light-emitting diode EM.

[0180] The second electrode 124 connects the power line 121 to the first p-type electrode 134 of the light-emitting diode EM through the first connection electrode 121a to transmit a low-potential power signal to the light-emitting diode EM.

[0181] The first electrode 123 and the second electrode 124 may be formed by the same process and may be formed of the same material (e.g., a transparent conductive material), but are not limited thereto. For example, the first electrode 123 and the second electrode 124 may be formed of indium tin oxide (ITO) or indium zinc oxide (IZO), but are not limited thereto. As an example, the first electrode 123 and the second electrode 124 may be formed by different processes and / or may be formed of different materials.

[0182] When the first n-type electrode 135 of the light-emitting diode EM is connected to the first electrode 123 and the first p-type electrode 134 is connected to the driving circuit unit, the power line 121 connected to the second electrode 124 may transmit a high-potential voltage to the light-emitting diode EM, and the driving circuit unit may transmit a low-potential voltage to the light-emitting diode EM.

[0183] Referring to Figure 5E , the black matrix 130 may be disposed on the first electrode 123 and the second electrode 124.

[0184] The black matrix 130 is spaced apart from the light-emitting diode EM at a predetermined interval to be disposed on the entire substrate 110 except for the light-emitting region. This structure may prevent the transistors of the driving circuit unit from deteriorating due to an external light source.

[0185] The black matrix 130 may reflect upward the light emitted from the side surface of the light-emitting diode EM, or may prevent color mixing with the light-emitting diodes of other sub-pixels, and define the light-emitting region of the sub-pixel SP.

[0186] The black matrix 130 may be set to be lower than the top surface of the third planarization layer 119 on the top surface of the substrate. The black matrix 130 may be formed in the second contact hole CH2 and the third contact hole CH3, and may be formed to have a uniform thickness on the second contact hole CH2 and the third contact hole CH3, so that the change in the reflectance of external light due to the thickness of the black matrix 130 can be reduced.

[0187] The black matrix 130 may be formed of an opaque material, and may be formed of, for example, a black resin, but is not limited thereto.

[0188] The first protective layer 140 is disposed over the entire black matrix 130 and the entire substrate 110. The first protective layer 140 is a layer for protecting the components below the first protective layer 140, and may be constituted by, for example, a single layer, a double layer, or a multi-layer of a translucent epoxy resin, silicon oxide (SiOx), or silicon nitride (SiNx), but is not limited thereto.

[0189] The cover substrate 200 for protecting the respective layers and elements may be disposed on the first protective layer 140. The cover substrate may be configured in a single-layer or multi-layer structure using materials such as organic substances or polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, polyaryl compound, polysulfone, or cycloolefin copolymer, but is not limited thereto.

[0190] Touch electrodes for touch operations may be additionally disposed on the first protective layer 140. The touch electrodes may be electrically connected to the driving circuit unit and / or may be electrically connected to a touch driving circuit IC outside the display area AA. As an example, the touch electrodes may be omitted according to the design.

[0191] Color filters may also be disposed on the first protective layer 140 in a region overlapping with the light-emitting region, and / or optical films may also be disposed. The optical films may be functional films that achieve higher-quality images while protecting the display panel PN. For example, the optical films may include a diffusion prevention film, an antiglare film, an antireflection film, a low reflection film, an OLED transmittance controllable film, or a polarizer, but is not limited thereto. For example, the color filters and / or the optical films may be omitted according to the design.

[0192] An adhesive layer may be additionally disposed between the optical film and the first protective layer 140.

[0193] A second substrate 120 may also be disposed below the first substrate 110. The second substrate 120 is a substrate that supports components disposed below the display panel PN and may be an insulating substrate. For example, the second substrate 120 may be formed of glass or resin. In addition, the second substrate 120 may include polymers or plastics. The second substrate 120 may be formed of the same material as the first substrate 110 or may be formed of a different material from the first substrate 110. In some exemplary embodiments, the second substrate 120 may be formed of a flexible plastic material. The second substrate 120 may be omitted according to the design.

[0194] A bonding layer BL is disposed between the first substrate 110 and the second substrate 120. The bonding layer BL may be formed of a material cured by various curing methods to bond the first substrate 110 and the second substrate 120. The bonding layer BL may be disposed only in a partial area between the first substrate 110 and the second substrate 120 or may be disposed in the entire area between the first substrate 110 and the second substrate 120.

[0195] Referring to Figure 2A , a plurality of second pad electrodes PAD2 are disposed on the rear surface of the second substrate 120. The plurality of second pad electrodes PAD2 are electrodes that transmit signals from a driving component disposed on the rear surface of the second substrate 120 to a plurality of side lines SRL and a plurality of first pad electrodes PAD1 and a plurality of wirings on the first substrate 110. The plurality of second pad electrodes PAD2 are disposed at ends in the non-display area NA of the second substrate 120 to be electrically connected to the side lines SRL covering the ends of the second substrate 120.

[0196] A side insulating layer covering the plurality of side lines SRL may be additionally provided. The side insulating layer may be formed on the top surface of the first substrate 110, the side surface of the first substrate 110, the side surface of the second substrate 120, and the rear surface of the second substrate 120 to cover the side lines SRL.

[0197] Meanwhile, when the plurality of side lines SRL are formed of a metal material, there may be a problem that external light is reflected from the plurality of side lines SRL or light emitted from the light emitting diode EM is reflected from the plurality of side lines SRL and thus visually recognized by the user. Therefore, the side insulating layer may be configured to include a black material to suppress the reflection of external light, but is not limited thereto. For example, the side insulating layer may be formed by a pad printing method using an insulating material including a black material (e.g., black ink).

[0198] Although not shown in the figures, a driving assembly including a plurality of flexible films and a printed circuit board may be disposed on the rear surface of the second substrate 120. The plurality of flexible films are components on which various components such as data driver ICs are disposed on a stretchable base film to provide signals to a plurality of sub-pixels SP. The printed circuit board is a component electrically connected to the plurality of flexible films to provide signals to the driving IC. On the printed circuit board, various components for providing various signals to the driving IC may be disposed.

[0199] A board for supporting the display panel PN may be disposed on the rear surface of the second substrate 120 and located below the driving assembly.

[0200] Exemplary embodiments of the present disclosure may also be described as follows:

[0201] According to an aspect of the present disclosure, a display device is provided. The display device may include: a substrate; a driving circuit unit disposed on the substrate in a display area; a first insulating layer disposed on the driving circuit unit; a second insulating layer including a protruding portion while surrounding at least one end of the first insulating layer; a light-emitting diode disposed on the protruding portion of the second insulating layer; and a third insulating layer including a recessed portion while surrounding one end of the first insulating layer or the second insulating layer, wherein the protruding portion and the recessed portion at least partially overlap.

[0202] The display device may further include: a power line applying a power supply voltage to the light-emitting diode; and a planarization layer disposed on the power line, wherein at least one or more of the first insulating layer, the second insulating layer, or the third insulating layer are disposed on the planarization layer.

[0203] A first contact hole may be formed in the planarization layer and the first insulating layer, the second insulating layer, or the third insulating layer.

[0204] The display device may further include a connection line electrically connecting the light-emitting diode and the driving circuit unit on the planarization layer.

[0205] The first contact hole may expose at least a part of the connection line.

[0206] The third insulating layer may surround one end of the second insulating layer.

[0207] The display device may further include a fourth insulating layer disposed in the recessed portion of the third insulating layer, wherein the fourth insulating layer surrounds at least a part of a side surface and a top surface of the light-emitting diode.

[0208] The display device may further include a light-shielding layer disposed on the third insulating layer.

[0209] A first height from the top surface of the substrate to the top surface of the light-shielding layer may be higher than a second height from the top surface of the substrate to the top surface of the fourth insulating layer.

[0210] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Accordingly, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

[0211] Cross - reference to related applications

[0212] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0188162, filed with the Korean Intellectual Property Office on December 21, 2023, the disclosure of which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: substrate; a driving circuit unit, wherein the driving circuit unit is arranged on the substrate in the display area; a first insulating layer, wherein the first insulating layer is disposed above the driving circuit unit; A light emitting diode, wherein the light emitting diode is arranged on the first insulating layer; as well as a second insulating layer, the second insulating layer surrounding an end portion of the first insulating layer, Wherein, the light emitting diode is arranged on the first insulating layer.

2. The display device according to claim 1, further comprising: a power line, the power line applying a power supply voltage to the light emitting diode; as well as a planarization layer, the planarization layer being arranged on the power line, Wherein, the first insulating layer and the second insulating layer are arranged on the planarization layer.

3. The display device according to claim 2, wherein: A first contact hole is formed in the planarization layer.

4. The display device according to claim 3, further comprising: A connection line electrically connects the light emitting diode and the driving circuit unit through the first contact hole and is disposed on the planarization layer.

5. The display device according to claim 4, wherein: The first contact hole exposes at least a portion of an electrode of the driving circuit unit.

6. The display device according to claim 2, wherein: A first contact hole is formed in the planarization layer, the first insulating layer, and the second insulating layer to expose a portion of the power line.

7. The display device according to claim 6, wherein: An end portion of the second insulating layer adjacent to the first contact hole surrounds an end portion of the first insulating layer adjacent to the first contact hole.

8. The display device according to claim 7, further comprising: a first electrode, wherein the first electrode electrically connects the power line to the light emitting diode through the first contact hole; The first electrode extends across an end portion of the second insulating layer adjacent to the first contact hole.

9. The display device according to claim 7, wherein: An end portion of the first insulating layer adjacent to the first contact hole has an inverted tapered shape or a right angle shape.

10. The display device according to claim 2, further comprising a connection line on the planarization layer, wherein the connection line electrically connects the light emitting diode and the driving circuit unit. in, A first contact hole is formed in the first insulating layer and the second insulating layer to expose the connection line.

11. The display device according to claim 10, wherein: An end portion of the second insulating layer adjacent to the first contact hole surrounds an end portion of the first insulating layer adjacent to the first contact hole.

12. The display device according to claim 1, further comprising: a third insulating layer, the third insulating layer being disposed on the second insulating layer, The third insulating layer surrounds at least a portion of the top surface and the side surface of the light emitting diode.

13. The display device according to claim 12, further comprising: A light shielding layer is disposed on the second insulating layer.

14. The display device according to claim 13, wherein: A first height from the top surface of the substrate to the top surface of the light shielding layer is lower than a second height from the top surface of the substrate to the top surface of the third insulating layer.

15. The display device according to claim 13, wherein: A first contact hole is formed in the first insulating layer and the second insulating layer, and the light shielding layer is formed in the first contact hole and has a uniform thickness on the first contact hole.

16. The display device according to claim 1, wherein: The first insulating layer includes a protrusion, and the light emitting diode is arranged on the protrusion.

17. The display device according to claim 16, wherein: The second insulating layer includes a concave portion overlapping the convex portion.

18. The display device according to claim 16, wherein: The second insulating layer covers the side surface of the protrusion and the interface between the protrusion and the light emitting diode.

19. The display device according to claim 1, further comprising: a third insulating layer, the third insulating layer being arranged below the first insulating layer, The first insulating layer and the second insulating layer cover ends of the third insulating layer.

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